core/stdarch/crates/core_arch/src/arm_shared/neon/
generated.rs

1// This code is automatically generated. DO NOT MODIFY.
2//
3// Instead, modify `crates/stdarch-gen-arm/spec/` and run the following command to re-generate this file:
4//
5// ```
6// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec
7// ```
8#![allow(improper_ctypes)]
9
10#[cfg(test)]
11use stdarch_test::assert_instr;
12
13use super::*;
14
15#[doc = "CRC32 single round checksum for bytes (8 bits)."]
16#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32b)"]
17#[inline]
18#[target_feature(enable = "crc")]
19#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
20#[cfg_attr(test, assert_instr(crc32b))]
21#[cfg_attr(
22    target_arch = "arm",
23    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
24)]
25#[cfg_attr(
26    not(target_arch = "arm"),
27    stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
28)]
29pub fn __crc32b(crc: u32, data: u8) -> u32 {
30    unsafe extern "unadjusted" {
31        #[cfg_attr(
32            any(target_arch = "aarch64", target_arch = "arm64ec"),
33            link_name = "llvm.aarch64.crc32b"
34        )]
35        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32b")]
36        fn ___crc32b(crc: u32, data: u32) -> u32;
37    }
38    unsafe { ___crc32b(crc, data as u32) }
39}
40#[doc = "CRC32-C single round checksum for bytes (8 bits)."]
41#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cb)"]
42#[inline]
43#[target_feature(enable = "crc")]
44#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
45#[cfg_attr(test, assert_instr(crc32cb))]
46#[cfg_attr(
47    target_arch = "arm",
48    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
49)]
50#[cfg_attr(
51    not(target_arch = "arm"),
52    stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
53)]
54pub fn __crc32cb(crc: u32, data: u8) -> u32 {
55    unsafe extern "unadjusted" {
56        #[cfg_attr(
57            any(target_arch = "aarch64", target_arch = "arm64ec"),
58            link_name = "llvm.aarch64.crc32cb"
59        )]
60        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cb")]
61        fn ___crc32cb(crc: u32, data: u32) -> u32;
62    }
63    unsafe { ___crc32cb(crc, data as u32) }
64}
65#[doc = "CRC32-C single round checksum for quad words (64 bits)."]
66#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)"]
67#[inline]
68#[target_feature(enable = "crc")]
69#[cfg(target_arch = "arm")]
70#[cfg_attr(test, assert_instr(crc32cw))]
71#[cfg_attr(
72    target_arch = "arm",
73    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
74)]
75pub fn __crc32cd(crc: u32, data: u64) -> u32 {
76    let b: u32 = (data & 0xFFFFFFFF) as u32;
77    let c: u32 = (data >> 32) as u32;
78    unsafe extern "unadjusted" {
79        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cw")]
80        fn ___crc32cw(crc: u32, data: u32) -> u32;
81    }
82    unsafe { ___crc32cw(___crc32cw(crc, b), c) }
83}
84#[doc = "CRC32-C single round checksum for bytes (16 bits)."]
85#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32ch)"]
86#[inline]
87#[target_feature(enable = "crc")]
88#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
89#[cfg_attr(test, assert_instr(crc32ch))]
90#[cfg_attr(
91    target_arch = "arm",
92    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
93)]
94#[cfg_attr(
95    not(target_arch = "arm"),
96    stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
97)]
98pub fn __crc32ch(crc: u32, data: u16) -> u32 {
99    unsafe extern "unadjusted" {
100        #[cfg_attr(
101            any(target_arch = "aarch64", target_arch = "arm64ec"),
102            link_name = "llvm.aarch64.crc32ch"
103        )]
104        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32ch")]
105        fn ___crc32ch(crc: u32, data: u32) -> u32;
106    }
107    unsafe { ___crc32ch(crc, data as u32) }
108}
109#[doc = "CRC32-C single round checksum for bytes (32 bits)."]
110#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cw)"]
111#[inline]
112#[target_feature(enable = "crc")]
113#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
114#[cfg_attr(test, assert_instr(crc32cw))]
115#[cfg_attr(
116    target_arch = "arm",
117    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
118)]
119#[cfg_attr(
120    not(target_arch = "arm"),
121    stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
122)]
123pub fn __crc32cw(crc: u32, data: u32) -> u32 {
124    unsafe extern "unadjusted" {
125        #[cfg_attr(
126            any(target_arch = "aarch64", target_arch = "arm64ec"),
127            link_name = "llvm.aarch64.crc32cw"
128        )]
129        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cw")]
130        fn ___crc32cw(crc: u32, data: u32) -> u32;
131    }
132    unsafe { ___crc32cw(crc, data) }
133}
134#[doc = "CRC32 single round checksum for quad words (64 bits)."]
135#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)"]
136#[inline]
137#[target_feature(enable = "crc")]
138#[cfg(target_arch = "arm")]
139#[cfg_attr(test, assert_instr(crc32w))]
140#[cfg_attr(
141    target_arch = "arm",
142    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
143)]
144pub fn __crc32d(crc: u32, data: u64) -> u32 {
145    let b: u32 = (data & 0xFFFFFFFF) as u32;
146    let c: u32 = (data >> 32) as u32;
147    unsafe extern "unadjusted" {
148        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32w")]
149        fn ___crc32w(crc: u32, data: u32) -> u32;
150    }
151    unsafe { ___crc32w(___crc32w(crc, b), c) }
152}
153#[doc = "CRC32 single round checksum for bytes (16 bits)."]
154#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32h)"]
155#[inline]
156#[target_feature(enable = "crc")]
157#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
158#[cfg_attr(test, assert_instr(crc32h))]
159#[cfg_attr(
160    target_arch = "arm",
161    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
162)]
163#[cfg_attr(
164    not(target_arch = "arm"),
165    stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
166)]
167pub fn __crc32h(crc: u32, data: u16) -> u32 {
168    unsafe extern "unadjusted" {
169        #[cfg_attr(
170            any(target_arch = "aarch64", target_arch = "arm64ec"),
171            link_name = "llvm.aarch64.crc32h"
172        )]
173        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32h")]
174        fn ___crc32h(crc: u32, data: u32) -> u32;
175    }
176    unsafe { ___crc32h(crc, data as u32) }
177}
178#[doc = "CRC32 single round checksum for bytes (32 bits)."]
179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32w)"]
180#[inline]
181#[target_feature(enable = "crc")]
182#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
183#[cfg_attr(test, assert_instr(crc32w))]
184#[cfg_attr(
185    target_arch = "arm",
186    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
187)]
188#[cfg_attr(
189    not(target_arch = "arm"),
190    stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
191)]
192pub fn __crc32w(crc: u32, data: u32) -> u32 {
193    unsafe extern "unadjusted" {
194        #[cfg_attr(
195            any(target_arch = "aarch64", target_arch = "arm64ec"),
196            link_name = "llvm.aarch64.crc32w"
197        )]
198        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32w")]
199        fn ___crc32w(crc: u32, data: u32) -> u32;
200    }
201    unsafe { ___crc32w(crc, data) }
202}
203#[doc = "Signed Add and Accumulate Long Pairwise."]
204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s8)"]
205#[inline]
206#[target_feature(enable = "neon")]
207#[cfg(target_arch = "arm")]
208#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
209#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
210#[cfg_attr(
211    target_arch = "arm",
212    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
213)]
214fn priv_vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t {
215    unsafe extern "unadjusted" {
216        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v4i16.v8i8")]
217        fn _priv_vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t;
218    }
219    unsafe { _priv_vpadal_s8(a, b) }
220}
221#[doc = "Signed Add and Accumulate Long Pairwise."]
222#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s8)"]
223#[inline]
224#[target_feature(enable = "neon")]
225#[cfg(target_arch = "arm")]
226#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
227#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
228#[cfg_attr(
229    target_arch = "arm",
230    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
231)]
232fn priv_vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
233    unsafe extern "unadjusted" {
234        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v8i16.v16i8")]
235        fn _priv_vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t;
236    }
237    unsafe { _priv_vpadalq_s8(a, b) }
238}
239#[doc = "Signed Add and Accumulate Long Pairwise."]
240#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s16)"]
241#[inline]
242#[target_feature(enable = "neon")]
243#[cfg(target_arch = "arm")]
244#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
245#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
246#[cfg_attr(
247    target_arch = "arm",
248    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
249)]
250fn priv_vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t {
251    unsafe extern "unadjusted" {
252        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v2i32.v4i16")]
253        fn _priv_vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t;
254    }
255    unsafe { _priv_vpadal_s16(a, b) }
256}
257#[doc = "Signed Add and Accumulate Long Pairwise."]
258#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s16)"]
259#[inline]
260#[target_feature(enable = "neon")]
261#[cfg(target_arch = "arm")]
262#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
263#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
264#[cfg_attr(
265    target_arch = "arm",
266    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
267)]
268fn priv_vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
269    unsafe extern "unadjusted" {
270        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v4i32.v8i16")]
271        fn _priv_vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t;
272    }
273    unsafe { _priv_vpadalq_s16(a, b) }
274}
275#[doc = "Signed Add and Accumulate Long Pairwise."]
276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s32)"]
277#[inline]
278#[target_feature(enable = "neon")]
279#[cfg(target_arch = "arm")]
280#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
281#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
282#[cfg_attr(
283    target_arch = "arm",
284    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
285)]
286fn priv_vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t {
287    unsafe extern "unadjusted" {
288        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v1i64.v2i32")]
289        fn _priv_vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t;
290    }
291    unsafe { _priv_vpadal_s32(a, b) }
292}
293#[doc = "Signed Add and Accumulate Long Pairwise."]
294#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s32)"]
295#[inline]
296#[target_feature(enable = "neon")]
297#[cfg(target_arch = "arm")]
298#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
299#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
300#[cfg_attr(
301    target_arch = "arm",
302    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
303)]
304fn priv_vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
305    unsafe extern "unadjusted" {
306        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v2i64.v4i32")]
307        fn _priv_vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t;
308    }
309    unsafe { _priv_vpadalq_s32(a, b) }
310}
311#[doc = "Signed Add and Accumulate Long Pairwise."]
312#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u8)"]
313#[inline]
314#[target_feature(enable = "neon")]
315#[cfg(target_arch = "arm")]
316#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
317#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
318#[cfg_attr(
319    target_arch = "arm",
320    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
321)]
322fn priv_vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t {
323    unsafe extern "unadjusted" {
324        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v4i16.v8i8")]
325        fn _priv_vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t;
326    }
327    unsafe { _priv_vpadal_u8(a, b) }
328}
329#[doc = "Signed Add and Accumulate Long Pairwise."]
330#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u8)"]
331#[inline]
332#[target_feature(enable = "neon")]
333#[cfg(target_arch = "arm")]
334#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
335#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
336#[cfg_attr(
337    target_arch = "arm",
338    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
339)]
340fn priv_vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
341    unsafe extern "unadjusted" {
342        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v8i16.v16i8")]
343        fn _priv_vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t;
344    }
345    unsafe { _priv_vpadalq_u8(a, b) }
346}
347#[doc = "Signed Add and Accumulate Long Pairwise."]
348#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u16)"]
349#[inline]
350#[target_feature(enable = "neon")]
351#[cfg(target_arch = "arm")]
352#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
353#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
354#[cfg_attr(
355    target_arch = "arm",
356    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
357)]
358fn priv_vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t {
359    unsafe extern "unadjusted" {
360        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v2i32.v4i16")]
361        fn _priv_vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t;
362    }
363    unsafe { _priv_vpadal_u16(a, b) }
364}
365#[doc = "Signed Add and Accumulate Long Pairwise."]
366#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u16)"]
367#[inline]
368#[target_feature(enable = "neon")]
369#[cfg(target_arch = "arm")]
370#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
371#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
372#[cfg_attr(
373    target_arch = "arm",
374    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
375)]
376fn priv_vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
377    unsafe extern "unadjusted" {
378        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v4i32.v8i16")]
379        fn _priv_vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t;
380    }
381    unsafe { _priv_vpadalq_u16(a, b) }
382}
383#[doc = "Signed Add and Accumulate Long Pairwise."]
384#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u32)"]
385#[inline]
386#[target_feature(enable = "neon")]
387#[cfg(target_arch = "arm")]
388#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
389#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
390#[cfg_attr(
391    target_arch = "arm",
392    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
393)]
394fn priv_vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t {
395    unsafe extern "unadjusted" {
396        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v1i64.v2i32")]
397        fn _priv_vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t;
398    }
399    unsafe { _priv_vpadal_u32(a, b) }
400}
401#[doc = "Signed Add and Accumulate Long Pairwise."]
402#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u32)"]
403#[inline]
404#[target_feature(enable = "neon")]
405#[cfg(target_arch = "arm")]
406#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
407#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
408#[cfg_attr(
409    target_arch = "arm",
410    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
411)]
412fn priv_vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
413    unsafe extern "unadjusted" {
414        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v2i64.v4i32")]
415        fn _priv_vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t;
416    }
417    unsafe { _priv_vpadalq_u32(a, b) }
418}
419#[doc = "Absolute difference and accumulate (64-bit)"]
420#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s16)"]
421#[inline]
422#[target_feature(enable = "neon")]
423#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
424#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s16"))]
425#[cfg_attr(
426    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
427    assert_instr(saba)
428)]
429#[cfg_attr(
430    not(target_arch = "arm"),
431    stable(feature = "neon_intrinsics", since = "1.59.0")
432)]
433#[cfg_attr(
434    target_arch = "arm",
435    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
436)]
437pub fn vaba_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
438    unsafe { simd_add(a, vabd_s16(b, c)) }
439}
440#[doc = "Absolute difference and accumulate (64-bit)"]
441#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s32)"]
442#[inline]
443#[target_feature(enable = "neon")]
444#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
445#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s32"))]
446#[cfg_attr(
447    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
448    assert_instr(saba)
449)]
450#[cfg_attr(
451    not(target_arch = "arm"),
452    stable(feature = "neon_intrinsics", since = "1.59.0")
453)]
454#[cfg_attr(
455    target_arch = "arm",
456    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
457)]
458pub fn vaba_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
459    unsafe { simd_add(a, vabd_s32(b, c)) }
460}
461#[doc = "Absolute difference and accumulate (64-bit)"]
462#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s8)"]
463#[inline]
464#[target_feature(enable = "neon")]
465#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
466#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s8"))]
467#[cfg_attr(
468    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
469    assert_instr(saba)
470)]
471#[cfg_attr(
472    not(target_arch = "arm"),
473    stable(feature = "neon_intrinsics", since = "1.59.0")
474)]
475#[cfg_attr(
476    target_arch = "arm",
477    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
478)]
479pub fn vaba_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
480    unsafe { simd_add(a, vabd_s8(b, c)) }
481}
482#[doc = "Absolute difference and accumulate (64-bit)"]
483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u16)"]
484#[inline]
485#[target_feature(enable = "neon")]
486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
487#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u16"))]
488#[cfg_attr(
489    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
490    assert_instr(uaba)
491)]
492#[cfg_attr(
493    not(target_arch = "arm"),
494    stable(feature = "neon_intrinsics", since = "1.59.0")
495)]
496#[cfg_attr(
497    target_arch = "arm",
498    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
499)]
500pub fn vaba_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
501    unsafe { simd_add(a, vabd_u16(b, c)) }
502}
503#[doc = "Absolute difference and accumulate (64-bit)"]
504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u32)"]
505#[inline]
506#[target_feature(enable = "neon")]
507#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
508#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u32"))]
509#[cfg_attr(
510    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
511    assert_instr(uaba)
512)]
513#[cfg_attr(
514    not(target_arch = "arm"),
515    stable(feature = "neon_intrinsics", since = "1.59.0")
516)]
517#[cfg_attr(
518    target_arch = "arm",
519    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
520)]
521pub fn vaba_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
522    unsafe { simd_add(a, vabd_u32(b, c)) }
523}
524#[doc = "Absolute difference and accumulate (64-bit)"]
525#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u8)"]
526#[inline]
527#[target_feature(enable = "neon")]
528#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
529#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u8"))]
530#[cfg_attr(
531    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
532    assert_instr(uaba)
533)]
534#[cfg_attr(
535    not(target_arch = "arm"),
536    stable(feature = "neon_intrinsics", since = "1.59.0")
537)]
538#[cfg_attr(
539    target_arch = "arm",
540    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
541)]
542pub fn vaba_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
543    unsafe { simd_add(a, vabd_u8(b, c)) }
544}
545#[doc = "Signed Absolute difference and Accumulate Long"]
546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s8)"]
547#[inline]
548#[target_feature(enable = "neon")]
549#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
550#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s8"))]
551#[cfg_attr(
552    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
553    assert_instr(sabal)
554)]
555#[cfg_attr(
556    not(target_arch = "arm"),
557    stable(feature = "neon_intrinsics", since = "1.59.0")
558)]
559#[cfg_attr(
560    target_arch = "arm",
561    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
562)]
563pub fn vabal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
564    let d: int8x8_t = vabd_s8(b, c);
565    unsafe {
566        let e: uint8x8_t = simd_cast(d);
567        simd_add(a, simd_cast(e))
568    }
569}
570#[doc = "Signed Absolute difference and Accumulate Long"]
571#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s16)"]
572#[inline]
573#[target_feature(enable = "neon")]
574#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
575#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s16"))]
576#[cfg_attr(
577    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
578    assert_instr(sabal)
579)]
580#[cfg_attr(
581    not(target_arch = "arm"),
582    stable(feature = "neon_intrinsics", since = "1.59.0")
583)]
584#[cfg_attr(
585    target_arch = "arm",
586    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
587)]
588pub fn vabal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
589    let d: int16x4_t = vabd_s16(b, c);
590    unsafe {
591        let e: uint16x4_t = simd_cast(d);
592        simd_add(a, simd_cast(e))
593    }
594}
595#[doc = "Signed Absolute difference and Accumulate Long"]
596#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s32)"]
597#[inline]
598#[target_feature(enable = "neon")]
599#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
600#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s32"))]
601#[cfg_attr(
602    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
603    assert_instr(sabal)
604)]
605#[cfg_attr(
606    not(target_arch = "arm"),
607    stable(feature = "neon_intrinsics", since = "1.59.0")
608)]
609#[cfg_attr(
610    target_arch = "arm",
611    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
612)]
613pub fn vabal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
614    let d: int32x2_t = vabd_s32(b, c);
615    unsafe {
616        let e: uint32x2_t = simd_cast(d);
617        simd_add(a, simd_cast(e))
618    }
619}
620#[doc = "Unsigned Absolute difference and Accumulate Long"]
621#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u8)"]
622#[inline]
623#[target_feature(enable = "neon")]
624#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
625#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u8"))]
626#[cfg_attr(
627    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
628    assert_instr(uabal)
629)]
630#[cfg_attr(
631    not(target_arch = "arm"),
632    stable(feature = "neon_intrinsics", since = "1.59.0")
633)]
634#[cfg_attr(
635    target_arch = "arm",
636    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
637)]
638pub fn vabal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
639    let d: uint8x8_t = vabd_u8(b, c);
640    unsafe { simd_add(a, simd_cast(d)) }
641}
642#[doc = "Unsigned Absolute difference and Accumulate Long"]
643#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u16)"]
644#[inline]
645#[target_feature(enable = "neon")]
646#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
647#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u16"))]
648#[cfg_attr(
649    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
650    assert_instr(uabal)
651)]
652#[cfg_attr(
653    not(target_arch = "arm"),
654    stable(feature = "neon_intrinsics", since = "1.59.0")
655)]
656#[cfg_attr(
657    target_arch = "arm",
658    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
659)]
660pub fn vabal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
661    let d: uint16x4_t = vabd_u16(b, c);
662    unsafe { simd_add(a, simd_cast(d)) }
663}
664#[doc = "Unsigned Absolute difference and Accumulate Long"]
665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u32)"]
666#[inline]
667#[target_feature(enable = "neon")]
668#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
669#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u32"))]
670#[cfg_attr(
671    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
672    assert_instr(uabal)
673)]
674#[cfg_attr(
675    not(target_arch = "arm"),
676    stable(feature = "neon_intrinsics", since = "1.59.0")
677)]
678#[cfg_attr(
679    target_arch = "arm",
680    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
681)]
682pub fn vabal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
683    let d: uint32x2_t = vabd_u32(b, c);
684    unsafe { simd_add(a, simd_cast(d)) }
685}
686#[doc = "Absolute difference and accumulate (128-bit)"]
687#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s16)"]
688#[inline]
689#[target_feature(enable = "neon")]
690#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
691#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s16"))]
692#[cfg_attr(
693    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
694    assert_instr(saba)
695)]
696#[cfg_attr(
697    not(target_arch = "arm"),
698    stable(feature = "neon_intrinsics", since = "1.59.0")
699)]
700#[cfg_attr(
701    target_arch = "arm",
702    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
703)]
704pub fn vabaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
705    unsafe { simd_add(a, vabdq_s16(b, c)) }
706}
707#[doc = "Absolute difference and accumulate (128-bit)"]
708#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s32)"]
709#[inline]
710#[target_feature(enable = "neon")]
711#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
712#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s32"))]
713#[cfg_attr(
714    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
715    assert_instr(saba)
716)]
717#[cfg_attr(
718    not(target_arch = "arm"),
719    stable(feature = "neon_intrinsics", since = "1.59.0")
720)]
721#[cfg_attr(
722    target_arch = "arm",
723    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
724)]
725pub fn vabaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
726    unsafe { simd_add(a, vabdq_s32(b, c)) }
727}
728#[doc = "Absolute difference and accumulate (128-bit)"]
729#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s8)"]
730#[inline]
731#[target_feature(enable = "neon")]
732#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
733#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s8"))]
734#[cfg_attr(
735    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
736    assert_instr(saba)
737)]
738#[cfg_attr(
739    not(target_arch = "arm"),
740    stable(feature = "neon_intrinsics", since = "1.59.0")
741)]
742#[cfg_attr(
743    target_arch = "arm",
744    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
745)]
746pub fn vabaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
747    unsafe { simd_add(a, vabdq_s8(b, c)) }
748}
749#[doc = "Absolute difference and accumulate (128-bit)"]
750#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u16)"]
751#[inline]
752#[target_feature(enable = "neon")]
753#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
754#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u16"))]
755#[cfg_attr(
756    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
757    assert_instr(uaba)
758)]
759#[cfg_attr(
760    not(target_arch = "arm"),
761    stable(feature = "neon_intrinsics", since = "1.59.0")
762)]
763#[cfg_attr(
764    target_arch = "arm",
765    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
766)]
767pub fn vabaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
768    unsafe { simd_add(a, vabdq_u16(b, c)) }
769}
770#[doc = "Absolute difference and accumulate (128-bit)"]
771#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u32)"]
772#[inline]
773#[target_feature(enable = "neon")]
774#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
775#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u32"))]
776#[cfg_attr(
777    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
778    assert_instr(uaba)
779)]
780#[cfg_attr(
781    not(target_arch = "arm"),
782    stable(feature = "neon_intrinsics", since = "1.59.0")
783)]
784#[cfg_attr(
785    target_arch = "arm",
786    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
787)]
788pub fn vabaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
789    unsafe { simd_add(a, vabdq_u32(b, c)) }
790}
791#[doc = "Absolute difference and accumulate (128-bit)"]
792#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u8)"]
793#[inline]
794#[target_feature(enable = "neon")]
795#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
796#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u8"))]
797#[cfg_attr(
798    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
799    assert_instr(uaba)
800)]
801#[cfg_attr(
802    not(target_arch = "arm"),
803    stable(feature = "neon_intrinsics", since = "1.59.0")
804)]
805#[cfg_attr(
806    target_arch = "arm",
807    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
808)]
809pub fn vabaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
810    unsafe { simd_add(a, vabdq_u8(b, c)) }
811}
812#[doc = "Absolute difference between the arguments of Floating"]
813#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f16)"]
814#[inline]
815#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
816#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f16"))]
817#[cfg_attr(
818    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
819    assert_instr(fabd)
820)]
821#[target_feature(enable = "neon,fp16")]
822#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
823pub fn vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
824    unsafe extern "unadjusted" {
825        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4f16")]
826        #[cfg_attr(
827            any(target_arch = "aarch64", target_arch = "arm64ec"),
828            link_name = "llvm.aarch64.neon.fabd.v4f16"
829        )]
830        fn _vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
831    }
832    unsafe { _vabd_f16(a, b) }
833}
834#[doc = "Absolute difference between the arguments of Floating"]
835#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f16)"]
836#[inline]
837#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
838#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f16"))]
839#[cfg_attr(
840    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
841    assert_instr(fabd)
842)]
843#[target_feature(enable = "neon,fp16")]
844#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
845pub fn vabdq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
846    unsafe extern "unadjusted" {
847        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v8f16")]
848        #[cfg_attr(
849            any(target_arch = "aarch64", target_arch = "arm64ec"),
850            link_name = "llvm.aarch64.neon.fabd.v8f16"
851        )]
852        fn _vabdq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
853    }
854    unsafe { _vabdq_f16(a, b) }
855}
856#[doc = "Absolute difference between the arguments of Floating"]
857#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f32)"]
858#[inline]
859#[target_feature(enable = "neon")]
860#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
861#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))]
862#[cfg_attr(
863    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
864    assert_instr(fabd)
865)]
866#[cfg_attr(
867    not(target_arch = "arm"),
868    stable(feature = "neon_intrinsics", since = "1.59.0")
869)]
870#[cfg_attr(
871    target_arch = "arm",
872    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
873)]
874pub fn vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
875    unsafe extern "unadjusted" {
876        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v2f32")]
877        #[cfg_attr(
878            any(target_arch = "aarch64", target_arch = "arm64ec"),
879            link_name = "llvm.aarch64.neon.fabd.v2f32"
880        )]
881        fn _vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
882    }
883    unsafe { _vabd_f32(a, b) }
884}
885#[doc = "Absolute difference between the arguments of Floating"]
886#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f32)"]
887#[inline]
888#[target_feature(enable = "neon")]
889#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
890#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))]
891#[cfg_attr(
892    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
893    assert_instr(fabd)
894)]
895#[cfg_attr(
896    not(target_arch = "arm"),
897    stable(feature = "neon_intrinsics", since = "1.59.0")
898)]
899#[cfg_attr(
900    target_arch = "arm",
901    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
902)]
903pub fn vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
904    unsafe extern "unadjusted" {
905        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4f32")]
906        #[cfg_attr(
907            any(target_arch = "aarch64", target_arch = "arm64ec"),
908            link_name = "llvm.aarch64.neon.fabd.v4f32"
909        )]
910        fn _vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
911    }
912    unsafe { _vabdq_f32(a, b) }
913}
914#[doc = "Absolute difference between the arguments"]
915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s8)"]
916#[inline]
917#[target_feature(enable = "neon")]
918#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
919#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))]
920#[cfg_attr(
921    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
922    assert_instr(sabd)
923)]
924#[cfg_attr(
925    not(target_arch = "arm"),
926    stable(feature = "neon_intrinsics", since = "1.59.0")
927)]
928#[cfg_attr(
929    target_arch = "arm",
930    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
931)]
932pub fn vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
933    unsafe extern "unadjusted" {
934        #[cfg_attr(
935            any(target_arch = "aarch64", target_arch = "arm64ec"),
936            link_name = "llvm.aarch64.neon.sabd.v8i8"
937        )]
938        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v8i8")]
939        fn _vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
940    }
941    unsafe { _vabd_s8(a, b) }
942}
943#[doc = "Absolute difference between the arguments"]
944#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s8)"]
945#[inline]
946#[target_feature(enable = "neon")]
947#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
948#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))]
949#[cfg_attr(
950    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
951    assert_instr(sabd)
952)]
953#[cfg_attr(
954    not(target_arch = "arm"),
955    stable(feature = "neon_intrinsics", since = "1.59.0")
956)]
957#[cfg_attr(
958    target_arch = "arm",
959    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
960)]
961pub fn vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
962    unsafe extern "unadjusted" {
963        #[cfg_attr(
964            any(target_arch = "aarch64", target_arch = "arm64ec"),
965            link_name = "llvm.aarch64.neon.sabd.v16i8"
966        )]
967        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v16i8")]
968        fn _vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
969    }
970    unsafe { _vabdq_s8(a, b) }
971}
972#[doc = "Absolute difference between the arguments"]
973#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s16)"]
974#[inline]
975#[target_feature(enable = "neon")]
976#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
977#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))]
978#[cfg_attr(
979    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
980    assert_instr(sabd)
981)]
982#[cfg_attr(
983    not(target_arch = "arm"),
984    stable(feature = "neon_intrinsics", since = "1.59.0")
985)]
986#[cfg_attr(
987    target_arch = "arm",
988    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
989)]
990pub fn vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
991    unsafe extern "unadjusted" {
992        #[cfg_attr(
993            any(target_arch = "aarch64", target_arch = "arm64ec"),
994            link_name = "llvm.aarch64.neon.sabd.v4i16"
995        )]
996        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4i16")]
997        fn _vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
998    }
999    unsafe { _vabd_s16(a, b) }
1000}
1001#[doc = "Absolute difference between the arguments"]
1002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s16)"]
1003#[inline]
1004#[target_feature(enable = "neon")]
1005#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1006#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))]
1007#[cfg_attr(
1008    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1009    assert_instr(sabd)
1010)]
1011#[cfg_attr(
1012    not(target_arch = "arm"),
1013    stable(feature = "neon_intrinsics", since = "1.59.0")
1014)]
1015#[cfg_attr(
1016    target_arch = "arm",
1017    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1018)]
1019pub fn vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
1020    unsafe extern "unadjusted" {
1021        #[cfg_attr(
1022            any(target_arch = "aarch64", target_arch = "arm64ec"),
1023            link_name = "llvm.aarch64.neon.sabd.v8i16"
1024        )]
1025        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v8i16")]
1026        fn _vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
1027    }
1028    unsafe { _vabdq_s16(a, b) }
1029}
1030#[doc = "Absolute difference between the arguments"]
1031#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s32)"]
1032#[inline]
1033#[target_feature(enable = "neon")]
1034#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1035#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))]
1036#[cfg_attr(
1037    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1038    assert_instr(sabd)
1039)]
1040#[cfg_attr(
1041    not(target_arch = "arm"),
1042    stable(feature = "neon_intrinsics", since = "1.59.0")
1043)]
1044#[cfg_attr(
1045    target_arch = "arm",
1046    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1047)]
1048pub fn vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
1049    unsafe extern "unadjusted" {
1050        #[cfg_attr(
1051            any(target_arch = "aarch64", target_arch = "arm64ec"),
1052            link_name = "llvm.aarch64.neon.sabd.v2i32"
1053        )]
1054        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v2i32")]
1055        fn _vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
1056    }
1057    unsafe { _vabd_s32(a, b) }
1058}
1059#[doc = "Absolute difference between the arguments"]
1060#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s32)"]
1061#[inline]
1062#[target_feature(enable = "neon")]
1063#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1064#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))]
1065#[cfg_attr(
1066    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1067    assert_instr(sabd)
1068)]
1069#[cfg_attr(
1070    not(target_arch = "arm"),
1071    stable(feature = "neon_intrinsics", since = "1.59.0")
1072)]
1073#[cfg_attr(
1074    target_arch = "arm",
1075    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1076)]
1077pub fn vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
1078    unsafe extern "unadjusted" {
1079        #[cfg_attr(
1080            any(target_arch = "aarch64", target_arch = "arm64ec"),
1081            link_name = "llvm.aarch64.neon.sabd.v4i32"
1082        )]
1083        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4i32")]
1084        fn _vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
1085    }
1086    unsafe { _vabdq_s32(a, b) }
1087}
1088#[doc = "Absolute difference between the arguments"]
1089#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u8)"]
1090#[inline]
1091#[target_feature(enable = "neon")]
1092#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1093#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))]
1094#[cfg_attr(
1095    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1096    assert_instr(uabd)
1097)]
1098#[cfg_attr(
1099    not(target_arch = "arm"),
1100    stable(feature = "neon_intrinsics", since = "1.59.0")
1101)]
1102#[cfg_attr(
1103    target_arch = "arm",
1104    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1105)]
1106pub fn vabd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
1107    unsafe extern "unadjusted" {
1108        #[cfg_attr(
1109            any(target_arch = "aarch64", target_arch = "arm64ec"),
1110            link_name = "llvm.aarch64.neon.uabd.v8i8"
1111        )]
1112        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v8i8")]
1113        fn _vabd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
1114    }
1115    unsafe { _vabd_u8(a, b) }
1116}
1117#[doc = "Absolute difference between the arguments"]
1118#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u8)"]
1119#[inline]
1120#[target_feature(enable = "neon")]
1121#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1122#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))]
1123#[cfg_attr(
1124    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1125    assert_instr(uabd)
1126)]
1127#[cfg_attr(
1128    not(target_arch = "arm"),
1129    stable(feature = "neon_intrinsics", since = "1.59.0")
1130)]
1131#[cfg_attr(
1132    target_arch = "arm",
1133    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1134)]
1135pub fn vabdq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
1136    unsafe extern "unadjusted" {
1137        #[cfg_attr(
1138            any(target_arch = "aarch64", target_arch = "arm64ec"),
1139            link_name = "llvm.aarch64.neon.uabd.v16i8"
1140        )]
1141        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v16i8")]
1142        fn _vabdq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
1143    }
1144    unsafe { _vabdq_u8(a, b) }
1145}
1146#[doc = "Absolute difference between the arguments"]
1147#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u16)"]
1148#[inline]
1149#[target_feature(enable = "neon")]
1150#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1151#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))]
1152#[cfg_attr(
1153    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1154    assert_instr(uabd)
1155)]
1156#[cfg_attr(
1157    not(target_arch = "arm"),
1158    stable(feature = "neon_intrinsics", since = "1.59.0")
1159)]
1160#[cfg_attr(
1161    target_arch = "arm",
1162    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1163)]
1164pub fn vabd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
1165    unsafe extern "unadjusted" {
1166        #[cfg_attr(
1167            any(target_arch = "aarch64", target_arch = "arm64ec"),
1168            link_name = "llvm.aarch64.neon.uabd.v4i16"
1169        )]
1170        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v4i16")]
1171        fn _vabd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
1172    }
1173    unsafe { _vabd_u16(a, b) }
1174}
1175#[doc = "Absolute difference between the arguments"]
1176#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u16)"]
1177#[inline]
1178#[target_feature(enable = "neon")]
1179#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1180#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))]
1181#[cfg_attr(
1182    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1183    assert_instr(uabd)
1184)]
1185#[cfg_attr(
1186    not(target_arch = "arm"),
1187    stable(feature = "neon_intrinsics", since = "1.59.0")
1188)]
1189#[cfg_attr(
1190    target_arch = "arm",
1191    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1192)]
1193pub fn vabdq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
1194    unsafe extern "unadjusted" {
1195        #[cfg_attr(
1196            any(target_arch = "aarch64", target_arch = "arm64ec"),
1197            link_name = "llvm.aarch64.neon.uabd.v8i16"
1198        )]
1199        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v8i16")]
1200        fn _vabdq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
1201    }
1202    unsafe { _vabdq_u16(a, b) }
1203}
1204#[doc = "Absolute difference between the arguments"]
1205#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u32)"]
1206#[inline]
1207#[target_feature(enable = "neon")]
1208#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1209#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))]
1210#[cfg_attr(
1211    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1212    assert_instr(uabd)
1213)]
1214#[cfg_attr(
1215    not(target_arch = "arm"),
1216    stable(feature = "neon_intrinsics", since = "1.59.0")
1217)]
1218#[cfg_attr(
1219    target_arch = "arm",
1220    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1221)]
1222pub fn vabd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
1223    unsafe extern "unadjusted" {
1224        #[cfg_attr(
1225            any(target_arch = "aarch64", target_arch = "arm64ec"),
1226            link_name = "llvm.aarch64.neon.uabd.v2i32"
1227        )]
1228        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v2i32")]
1229        fn _vabd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
1230    }
1231    unsafe { _vabd_u32(a, b) }
1232}
1233#[doc = "Absolute difference between the arguments"]
1234#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u32)"]
1235#[inline]
1236#[target_feature(enable = "neon")]
1237#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1238#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))]
1239#[cfg_attr(
1240    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1241    assert_instr(uabd)
1242)]
1243#[cfg_attr(
1244    not(target_arch = "arm"),
1245    stable(feature = "neon_intrinsics", since = "1.59.0")
1246)]
1247#[cfg_attr(
1248    target_arch = "arm",
1249    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1250)]
1251pub fn vabdq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
1252    unsafe extern "unadjusted" {
1253        #[cfg_attr(
1254            any(target_arch = "aarch64", target_arch = "arm64ec"),
1255            link_name = "llvm.aarch64.neon.uabd.v4i32"
1256        )]
1257        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v4i32")]
1258        fn _vabdq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
1259    }
1260    unsafe { _vabdq_u32(a, b) }
1261}
1262#[doc = "Signed Absolute difference Long"]
1263#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s8)"]
1264#[inline]
1265#[target_feature(enable = "neon")]
1266#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1267#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s8"))]
1268#[cfg_attr(
1269    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1270    assert_instr(sabdl)
1271)]
1272#[cfg_attr(
1273    not(target_arch = "arm"),
1274    stable(feature = "neon_intrinsics", since = "1.59.0")
1275)]
1276#[cfg_attr(
1277    target_arch = "arm",
1278    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1279)]
1280pub fn vabdl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
1281    unsafe {
1282        let c: uint8x8_t = simd_cast(vabd_s8(a, b));
1283        simd_cast(c)
1284    }
1285}
1286#[doc = "Signed Absolute difference Long"]
1287#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s16)"]
1288#[inline]
1289#[target_feature(enable = "neon")]
1290#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1291#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s16"))]
1292#[cfg_attr(
1293    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1294    assert_instr(sabdl)
1295)]
1296#[cfg_attr(
1297    not(target_arch = "arm"),
1298    stable(feature = "neon_intrinsics", since = "1.59.0")
1299)]
1300#[cfg_attr(
1301    target_arch = "arm",
1302    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1303)]
1304pub fn vabdl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
1305    unsafe {
1306        let c: uint16x4_t = simd_cast(vabd_s16(a, b));
1307        simd_cast(c)
1308    }
1309}
1310#[doc = "Signed Absolute difference Long"]
1311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s32)"]
1312#[inline]
1313#[target_feature(enable = "neon")]
1314#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1315#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s32"))]
1316#[cfg_attr(
1317    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1318    assert_instr(sabdl)
1319)]
1320#[cfg_attr(
1321    not(target_arch = "arm"),
1322    stable(feature = "neon_intrinsics", since = "1.59.0")
1323)]
1324#[cfg_attr(
1325    target_arch = "arm",
1326    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1327)]
1328pub fn vabdl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
1329    unsafe {
1330        let c: uint32x2_t = simd_cast(vabd_s32(a, b));
1331        simd_cast(c)
1332    }
1333}
1334#[doc = "Unsigned Absolute difference Long"]
1335#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u8)"]
1336#[inline]
1337#[target_feature(enable = "neon")]
1338#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1339#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u8"))]
1340#[cfg_attr(
1341    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1342    assert_instr(uabdl)
1343)]
1344#[cfg_attr(
1345    not(target_arch = "arm"),
1346    stable(feature = "neon_intrinsics", since = "1.59.0")
1347)]
1348#[cfg_attr(
1349    target_arch = "arm",
1350    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1351)]
1352pub fn vabdl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
1353    unsafe { simd_cast(vabd_u8(a, b)) }
1354}
1355#[doc = "Unsigned Absolute difference Long"]
1356#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u16)"]
1357#[inline]
1358#[target_feature(enable = "neon")]
1359#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1360#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u16"))]
1361#[cfg_attr(
1362    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1363    assert_instr(uabdl)
1364)]
1365#[cfg_attr(
1366    not(target_arch = "arm"),
1367    stable(feature = "neon_intrinsics", since = "1.59.0")
1368)]
1369#[cfg_attr(
1370    target_arch = "arm",
1371    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1372)]
1373pub fn vabdl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
1374    unsafe { simd_cast(vabd_u16(a, b)) }
1375}
1376#[doc = "Unsigned Absolute difference Long"]
1377#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u32)"]
1378#[inline]
1379#[target_feature(enable = "neon")]
1380#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1381#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u32"))]
1382#[cfg_attr(
1383    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1384    assert_instr(uabdl)
1385)]
1386#[cfg_attr(
1387    not(target_arch = "arm"),
1388    stable(feature = "neon_intrinsics", since = "1.59.0")
1389)]
1390#[cfg_attr(
1391    target_arch = "arm",
1392    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1393)]
1394pub fn vabdl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
1395    unsafe { simd_cast(vabd_u32(a, b)) }
1396}
1397#[doc = "Floating-point absolute value"]
1398#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f16)"]
1399#[inline]
1400#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1401#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1402#[cfg_attr(
1403    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1404    assert_instr(fabs)
1405)]
1406#[target_feature(enable = "neon,fp16")]
1407#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1408pub fn vabs_f16(a: float16x4_t) -> float16x4_t {
1409    unsafe { simd_fabs(a) }
1410}
1411#[doc = "Floating-point absolute value"]
1412#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f16)"]
1413#[inline]
1414#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1415#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1416#[cfg_attr(
1417    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1418    assert_instr(fabs)
1419)]
1420#[target_feature(enable = "neon,fp16")]
1421#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1422pub fn vabsq_f16(a: float16x8_t) -> float16x8_t {
1423    unsafe { simd_fabs(a) }
1424}
1425#[doc = "Floating-point absolute value"]
1426#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f32)"]
1427#[inline]
1428#[target_feature(enable = "neon")]
1429#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1430#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1431#[cfg_attr(
1432    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1433    assert_instr(fabs)
1434)]
1435#[cfg_attr(
1436    not(target_arch = "arm"),
1437    stable(feature = "neon_intrinsics", since = "1.59.0")
1438)]
1439#[cfg_attr(
1440    target_arch = "arm",
1441    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1442)]
1443pub fn vabs_f32(a: float32x2_t) -> float32x2_t {
1444    unsafe { simd_fabs(a) }
1445}
1446#[doc = "Floating-point absolute value"]
1447#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f32)"]
1448#[inline]
1449#[target_feature(enable = "neon")]
1450#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1451#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1452#[cfg_attr(
1453    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1454    assert_instr(fabs)
1455)]
1456#[cfg_attr(
1457    not(target_arch = "arm"),
1458    stable(feature = "neon_intrinsics", since = "1.59.0")
1459)]
1460#[cfg_attr(
1461    target_arch = "arm",
1462    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1463)]
1464pub fn vabsq_f32(a: float32x4_t) -> float32x4_t {
1465    unsafe { simd_fabs(a) }
1466}
1467#[doc = "Absolute value (wrapping)."]
1468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s8)"]
1469#[inline]
1470#[target_feature(enable = "neon")]
1471#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1472#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1473#[cfg_attr(
1474    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1475    assert_instr(abs)
1476)]
1477#[cfg_attr(
1478    not(target_arch = "arm"),
1479    stable(feature = "neon_intrinsics", since = "1.59.0")
1480)]
1481#[cfg_attr(
1482    target_arch = "arm",
1483    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1484)]
1485pub fn vabs_s8(a: int8x8_t) -> int8x8_t {
1486    unsafe extern "unadjusted" {
1487        #[cfg_attr(
1488            any(target_arch = "aarch64", target_arch = "arm64ec"),
1489            link_name = "llvm.aarch64.neon.abs.v8i8"
1490        )]
1491        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v8i8")]
1492        fn _vabs_s8(a: int8x8_t) -> int8x8_t;
1493    }
1494    unsafe { _vabs_s8(a) }
1495}
1496#[doc = "Absolute value (wrapping)."]
1497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s8)"]
1498#[inline]
1499#[target_feature(enable = "neon")]
1500#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1501#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1502#[cfg_attr(
1503    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1504    assert_instr(abs)
1505)]
1506#[cfg_attr(
1507    not(target_arch = "arm"),
1508    stable(feature = "neon_intrinsics", since = "1.59.0")
1509)]
1510#[cfg_attr(
1511    target_arch = "arm",
1512    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1513)]
1514pub fn vabsq_s8(a: int8x16_t) -> int8x16_t {
1515    unsafe extern "unadjusted" {
1516        #[cfg_attr(
1517            any(target_arch = "aarch64", target_arch = "arm64ec"),
1518            link_name = "llvm.aarch64.neon.abs.v16i8"
1519        )]
1520        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v16i8")]
1521        fn _vabsq_s8(a: int8x16_t) -> int8x16_t;
1522    }
1523    unsafe { _vabsq_s8(a) }
1524}
1525#[doc = "Absolute value (wrapping)."]
1526#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s16)"]
1527#[inline]
1528#[target_feature(enable = "neon")]
1529#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1530#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1531#[cfg_attr(
1532    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1533    assert_instr(abs)
1534)]
1535#[cfg_attr(
1536    not(target_arch = "arm"),
1537    stable(feature = "neon_intrinsics", since = "1.59.0")
1538)]
1539#[cfg_attr(
1540    target_arch = "arm",
1541    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1542)]
1543pub fn vabs_s16(a: int16x4_t) -> int16x4_t {
1544    unsafe extern "unadjusted" {
1545        #[cfg_attr(
1546            any(target_arch = "aarch64", target_arch = "arm64ec"),
1547            link_name = "llvm.aarch64.neon.abs.v4i16"
1548        )]
1549        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v4i16")]
1550        fn _vabs_s16(a: int16x4_t) -> int16x4_t;
1551    }
1552    unsafe { _vabs_s16(a) }
1553}
1554#[doc = "Absolute value (wrapping)."]
1555#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s16)"]
1556#[inline]
1557#[target_feature(enable = "neon")]
1558#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1559#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1560#[cfg_attr(
1561    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1562    assert_instr(abs)
1563)]
1564#[cfg_attr(
1565    not(target_arch = "arm"),
1566    stable(feature = "neon_intrinsics", since = "1.59.0")
1567)]
1568#[cfg_attr(
1569    target_arch = "arm",
1570    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1571)]
1572pub fn vabsq_s16(a: int16x8_t) -> int16x8_t {
1573    unsafe extern "unadjusted" {
1574        #[cfg_attr(
1575            any(target_arch = "aarch64", target_arch = "arm64ec"),
1576            link_name = "llvm.aarch64.neon.abs.v8i16"
1577        )]
1578        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v8i16")]
1579        fn _vabsq_s16(a: int16x8_t) -> int16x8_t;
1580    }
1581    unsafe { _vabsq_s16(a) }
1582}
1583#[doc = "Absolute value (wrapping)."]
1584#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s32)"]
1585#[inline]
1586#[target_feature(enable = "neon")]
1587#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1588#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1589#[cfg_attr(
1590    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1591    assert_instr(abs)
1592)]
1593#[cfg_attr(
1594    not(target_arch = "arm"),
1595    stable(feature = "neon_intrinsics", since = "1.59.0")
1596)]
1597#[cfg_attr(
1598    target_arch = "arm",
1599    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1600)]
1601pub fn vabs_s32(a: int32x2_t) -> int32x2_t {
1602    unsafe extern "unadjusted" {
1603        #[cfg_attr(
1604            any(target_arch = "aarch64", target_arch = "arm64ec"),
1605            link_name = "llvm.aarch64.neon.abs.v2i32"
1606        )]
1607        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v2i32")]
1608        fn _vabs_s32(a: int32x2_t) -> int32x2_t;
1609    }
1610    unsafe { _vabs_s32(a) }
1611}
1612#[doc = "Absolute value (wrapping)."]
1613#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s32)"]
1614#[inline]
1615#[target_feature(enable = "neon")]
1616#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1617#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1618#[cfg_attr(
1619    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1620    assert_instr(abs)
1621)]
1622#[cfg_attr(
1623    not(target_arch = "arm"),
1624    stable(feature = "neon_intrinsics", since = "1.59.0")
1625)]
1626#[cfg_attr(
1627    target_arch = "arm",
1628    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1629)]
1630pub fn vabsq_s32(a: int32x4_t) -> int32x4_t {
1631    unsafe extern "unadjusted" {
1632        #[cfg_attr(
1633            any(target_arch = "aarch64", target_arch = "arm64ec"),
1634            link_name = "llvm.aarch64.neon.abs.v4i32"
1635        )]
1636        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v4i32")]
1637        fn _vabsq_s32(a: int32x4_t) -> int32x4_t;
1638    }
1639    unsafe { _vabsq_s32(a) }
1640}
1641#[doc = "Floating-point absolute value"]
1642#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsh_f16)"]
1643#[inline]
1644#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1645#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1646#[cfg_attr(
1647    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1648    assert_instr(fabs)
1649)]
1650#[target_feature(enable = "neon,fp16")]
1651#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1652pub fn vabsh_f16(a: f16) -> f16 {
1653    unsafe { simd_extract!(vabs_f16(vdup_n_f16(a)), 0) }
1654}
1655#[doc = "Floating-point Add (vector)."]
1656#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_f16)"]
1657#[inline]
1658#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1659#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
1660#[cfg_attr(
1661    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1662    assert_instr(fadd)
1663)]
1664#[target_feature(enable = "neon,fp16")]
1665#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1666pub fn vadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
1667    unsafe { simd_add(a, b) }
1668}
1669#[doc = "Floating-point Add (vector)."]
1670#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_f16)"]
1671#[inline]
1672#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1673#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
1674#[cfg_attr(
1675    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1676    assert_instr(fadd)
1677)]
1678#[target_feature(enable = "neon,fp16")]
1679#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1680pub fn vaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
1681    unsafe { simd_add(a, b) }
1682}
1683#[doc = "Vector add."]
1684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_f32)"]
1685#[inline]
1686#[target_feature(enable = "neon")]
1687#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1688#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1689#[cfg_attr(
1690    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1691    assert_instr(fadd)
1692)]
1693#[cfg_attr(
1694    not(target_arch = "arm"),
1695    stable(feature = "neon_intrinsics", since = "1.59.0")
1696)]
1697#[cfg_attr(
1698    target_arch = "arm",
1699    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1700)]
1701pub fn vadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
1702    unsafe { simd_add(a, b) }
1703}
1704#[doc = "Vector add."]
1705#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s16)"]
1706#[inline]
1707#[target_feature(enable = "neon")]
1708#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1709#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1710#[cfg_attr(
1711    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1712    assert_instr(add)
1713)]
1714#[cfg_attr(
1715    not(target_arch = "arm"),
1716    stable(feature = "neon_intrinsics", since = "1.59.0")
1717)]
1718#[cfg_attr(
1719    target_arch = "arm",
1720    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1721)]
1722pub fn vadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
1723    unsafe { simd_add(a, b) }
1724}
1725#[doc = "Vector add."]
1726#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s32)"]
1727#[inline]
1728#[target_feature(enable = "neon")]
1729#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1730#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1731#[cfg_attr(
1732    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1733    assert_instr(add)
1734)]
1735#[cfg_attr(
1736    not(target_arch = "arm"),
1737    stable(feature = "neon_intrinsics", since = "1.59.0")
1738)]
1739#[cfg_attr(
1740    target_arch = "arm",
1741    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1742)]
1743pub fn vadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
1744    unsafe { simd_add(a, b) }
1745}
1746#[doc = "Vector add."]
1747#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s8)"]
1748#[inline]
1749#[target_feature(enable = "neon")]
1750#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1751#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1752#[cfg_attr(
1753    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1754    assert_instr(add)
1755)]
1756#[cfg_attr(
1757    not(target_arch = "arm"),
1758    stable(feature = "neon_intrinsics", since = "1.59.0")
1759)]
1760#[cfg_attr(
1761    target_arch = "arm",
1762    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1763)]
1764pub fn vadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
1765    unsafe { simd_add(a, b) }
1766}
1767#[doc = "Vector add."]
1768#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u16)"]
1769#[inline]
1770#[target_feature(enable = "neon")]
1771#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1772#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1773#[cfg_attr(
1774    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1775    assert_instr(add)
1776)]
1777#[cfg_attr(
1778    not(target_arch = "arm"),
1779    stable(feature = "neon_intrinsics", since = "1.59.0")
1780)]
1781#[cfg_attr(
1782    target_arch = "arm",
1783    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1784)]
1785pub fn vadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
1786    unsafe { simd_add(a, b) }
1787}
1788#[doc = "Vector add."]
1789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u32)"]
1790#[inline]
1791#[target_feature(enable = "neon")]
1792#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1793#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1794#[cfg_attr(
1795    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1796    assert_instr(add)
1797)]
1798#[cfg_attr(
1799    not(target_arch = "arm"),
1800    stable(feature = "neon_intrinsics", since = "1.59.0")
1801)]
1802#[cfg_attr(
1803    target_arch = "arm",
1804    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1805)]
1806pub fn vadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
1807    unsafe { simd_add(a, b) }
1808}
1809#[doc = "Vector add."]
1810#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u8)"]
1811#[inline]
1812#[target_feature(enable = "neon")]
1813#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1814#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1815#[cfg_attr(
1816    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1817    assert_instr(add)
1818)]
1819#[cfg_attr(
1820    not(target_arch = "arm"),
1821    stable(feature = "neon_intrinsics", since = "1.59.0")
1822)]
1823#[cfg_attr(
1824    target_arch = "arm",
1825    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1826)]
1827pub fn vadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
1828    unsafe { simd_add(a, b) }
1829}
1830#[doc = "Vector add."]
1831#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_f32)"]
1832#[inline]
1833#[target_feature(enable = "neon")]
1834#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1835#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1836#[cfg_attr(
1837    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1838    assert_instr(fadd)
1839)]
1840#[cfg_attr(
1841    not(target_arch = "arm"),
1842    stable(feature = "neon_intrinsics", since = "1.59.0")
1843)]
1844#[cfg_attr(
1845    target_arch = "arm",
1846    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1847)]
1848pub fn vaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
1849    unsafe { simd_add(a, b) }
1850}
1851#[doc = "Vector add."]
1852#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s16)"]
1853#[inline]
1854#[target_feature(enable = "neon")]
1855#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1856#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1857#[cfg_attr(
1858    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1859    assert_instr(add)
1860)]
1861#[cfg_attr(
1862    not(target_arch = "arm"),
1863    stable(feature = "neon_intrinsics", since = "1.59.0")
1864)]
1865#[cfg_attr(
1866    target_arch = "arm",
1867    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1868)]
1869pub fn vaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
1870    unsafe { simd_add(a, b) }
1871}
1872#[doc = "Vector add."]
1873#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s32)"]
1874#[inline]
1875#[target_feature(enable = "neon")]
1876#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1877#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1878#[cfg_attr(
1879    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1880    assert_instr(add)
1881)]
1882#[cfg_attr(
1883    not(target_arch = "arm"),
1884    stable(feature = "neon_intrinsics", since = "1.59.0")
1885)]
1886#[cfg_attr(
1887    target_arch = "arm",
1888    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1889)]
1890pub fn vaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
1891    unsafe { simd_add(a, b) }
1892}
1893#[doc = "Vector add."]
1894#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s64)"]
1895#[inline]
1896#[target_feature(enable = "neon")]
1897#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1898#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1899#[cfg_attr(
1900    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1901    assert_instr(add)
1902)]
1903#[cfg_attr(
1904    not(target_arch = "arm"),
1905    stable(feature = "neon_intrinsics", since = "1.59.0")
1906)]
1907#[cfg_attr(
1908    target_arch = "arm",
1909    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1910)]
1911pub fn vaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
1912    unsafe { simd_add(a, b) }
1913}
1914#[doc = "Vector add."]
1915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s8)"]
1916#[inline]
1917#[target_feature(enable = "neon")]
1918#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1919#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1920#[cfg_attr(
1921    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1922    assert_instr(add)
1923)]
1924#[cfg_attr(
1925    not(target_arch = "arm"),
1926    stable(feature = "neon_intrinsics", since = "1.59.0")
1927)]
1928#[cfg_attr(
1929    target_arch = "arm",
1930    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1931)]
1932pub fn vaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
1933    unsafe { simd_add(a, b) }
1934}
1935#[doc = "Vector add."]
1936#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u16)"]
1937#[inline]
1938#[target_feature(enable = "neon")]
1939#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1940#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1941#[cfg_attr(
1942    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1943    assert_instr(add)
1944)]
1945#[cfg_attr(
1946    not(target_arch = "arm"),
1947    stable(feature = "neon_intrinsics", since = "1.59.0")
1948)]
1949#[cfg_attr(
1950    target_arch = "arm",
1951    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1952)]
1953pub fn vaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
1954    unsafe { simd_add(a, b) }
1955}
1956#[doc = "Vector add."]
1957#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u32)"]
1958#[inline]
1959#[target_feature(enable = "neon")]
1960#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1961#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1962#[cfg_attr(
1963    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1964    assert_instr(add)
1965)]
1966#[cfg_attr(
1967    not(target_arch = "arm"),
1968    stable(feature = "neon_intrinsics", since = "1.59.0")
1969)]
1970#[cfg_attr(
1971    target_arch = "arm",
1972    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1973)]
1974pub fn vaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
1975    unsafe { simd_add(a, b) }
1976}
1977#[doc = "Vector add."]
1978#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u64)"]
1979#[inline]
1980#[target_feature(enable = "neon")]
1981#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1982#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1983#[cfg_attr(
1984    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1985    assert_instr(add)
1986)]
1987#[cfg_attr(
1988    not(target_arch = "arm"),
1989    stable(feature = "neon_intrinsics", since = "1.59.0")
1990)]
1991#[cfg_attr(
1992    target_arch = "arm",
1993    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1994)]
1995pub fn vaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
1996    unsafe { simd_add(a, b) }
1997}
1998#[doc = "Vector add."]
1999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u8)"]
2000#[inline]
2001#[target_feature(enable = "neon")]
2002#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2003#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
2004#[cfg_attr(
2005    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2006    assert_instr(add)
2007)]
2008#[cfg_attr(
2009    not(target_arch = "arm"),
2010    stable(feature = "neon_intrinsics", since = "1.59.0")
2011)]
2012#[cfg_attr(
2013    target_arch = "arm",
2014    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2015)]
2016pub fn vaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
2017    unsafe { simd_add(a, b) }
2018}
2019#[doc = "Bitwise exclusive OR"]
2020#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p8)"]
2021#[inline]
2022#[target_feature(enable = "neon")]
2023#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2024#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2025#[cfg_attr(
2026    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2027    assert_instr(nop)
2028)]
2029#[cfg_attr(
2030    not(target_arch = "arm"),
2031    stable(feature = "neon_intrinsics", since = "1.59.0")
2032)]
2033#[cfg_attr(
2034    target_arch = "arm",
2035    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2036)]
2037pub fn vadd_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
2038    unsafe { simd_xor(a, b) }
2039}
2040#[doc = "Bitwise exclusive OR"]
2041#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p8)"]
2042#[inline]
2043#[target_feature(enable = "neon")]
2044#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2045#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2046#[cfg_attr(
2047    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2048    assert_instr(nop)
2049)]
2050#[cfg_attr(
2051    not(target_arch = "arm"),
2052    stable(feature = "neon_intrinsics", since = "1.59.0")
2053)]
2054#[cfg_attr(
2055    target_arch = "arm",
2056    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2057)]
2058pub fn vaddq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
2059    unsafe { simd_xor(a, b) }
2060}
2061#[doc = "Bitwise exclusive OR"]
2062#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p16)"]
2063#[inline]
2064#[target_feature(enable = "neon")]
2065#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2066#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2067#[cfg_attr(
2068    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2069    assert_instr(nop)
2070)]
2071#[cfg_attr(
2072    not(target_arch = "arm"),
2073    stable(feature = "neon_intrinsics", since = "1.59.0")
2074)]
2075#[cfg_attr(
2076    target_arch = "arm",
2077    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2078)]
2079pub fn vadd_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
2080    unsafe { simd_xor(a, b) }
2081}
2082#[doc = "Bitwise exclusive OR"]
2083#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p16)"]
2084#[inline]
2085#[target_feature(enable = "neon")]
2086#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2087#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2088#[cfg_attr(
2089    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2090    assert_instr(nop)
2091)]
2092#[cfg_attr(
2093    not(target_arch = "arm"),
2094    stable(feature = "neon_intrinsics", since = "1.59.0")
2095)]
2096#[cfg_attr(
2097    target_arch = "arm",
2098    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2099)]
2100pub fn vaddq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
2101    unsafe { simd_xor(a, b) }
2102}
2103#[doc = "Bitwise exclusive OR"]
2104#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p64)"]
2105#[inline]
2106#[target_feature(enable = "neon")]
2107#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2108#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2109#[cfg_attr(
2110    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2111    assert_instr(nop)
2112)]
2113#[cfg_attr(
2114    not(target_arch = "arm"),
2115    stable(feature = "neon_intrinsics", since = "1.59.0")
2116)]
2117#[cfg_attr(
2118    target_arch = "arm",
2119    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2120)]
2121pub fn vadd_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t {
2122    unsafe { simd_xor(a, b) }
2123}
2124#[doc = "Bitwise exclusive OR"]
2125#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p64)"]
2126#[inline]
2127#[target_feature(enable = "neon")]
2128#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2129#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2130#[cfg_attr(
2131    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2132    assert_instr(nop)
2133)]
2134#[cfg_attr(
2135    not(target_arch = "arm"),
2136    stable(feature = "neon_intrinsics", since = "1.59.0")
2137)]
2138#[cfg_attr(
2139    target_arch = "arm",
2140    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2141)]
2142pub fn vaddq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
2143    unsafe { simd_xor(a, b) }
2144}
2145#[doc = "Add"]
2146#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddh_f16)"]
2147#[inline]
2148#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
2149#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
2150#[cfg_attr(
2151    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2152    assert_instr(fadd)
2153)]
2154#[target_feature(enable = "neon,fp16")]
2155#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2156pub fn vaddh_f16(a: f16, b: f16) -> f16 {
2157    a + b
2158}
2159#[doc = "Add returning High Narrow (high half)."]
2160#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s16)"]
2161#[inline]
2162#[target_feature(enable = "neon")]
2163#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2164#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2165#[cfg_attr(
2166    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2167    assert_instr(addhn2)
2168)]
2169#[cfg_attr(
2170    not(target_arch = "arm"),
2171    stable(feature = "neon_intrinsics", since = "1.59.0")
2172)]
2173#[cfg_attr(
2174    target_arch = "arm",
2175    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2176)]
2177pub fn vaddhn_high_s16(r: int8x8_t, a: int16x8_t, b: int16x8_t) -> int8x16_t {
2178    unsafe {
2179        let x = simd_cast(simd_shr(simd_add(a, b), int16x8_t::splat(8)));
2180        simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15])
2181    }
2182}
2183#[doc = "Add returning High Narrow (high half)."]
2184#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s32)"]
2185#[inline]
2186#[target_feature(enable = "neon")]
2187#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2188#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2189#[cfg_attr(
2190    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2191    assert_instr(addhn2)
2192)]
2193#[cfg_attr(
2194    not(target_arch = "arm"),
2195    stable(feature = "neon_intrinsics", since = "1.59.0")
2196)]
2197#[cfg_attr(
2198    target_arch = "arm",
2199    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2200)]
2201pub fn vaddhn_high_s32(r: int16x4_t, a: int32x4_t, b: int32x4_t) -> int16x8_t {
2202    unsafe {
2203        let x = simd_cast(simd_shr(simd_add(a, b), int32x4_t::splat(16)));
2204        simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7])
2205    }
2206}
2207#[doc = "Add returning High Narrow (high half)."]
2208#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s64)"]
2209#[inline]
2210#[target_feature(enable = "neon")]
2211#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2212#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2213#[cfg_attr(
2214    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2215    assert_instr(addhn2)
2216)]
2217#[cfg_attr(
2218    not(target_arch = "arm"),
2219    stable(feature = "neon_intrinsics", since = "1.59.0")
2220)]
2221#[cfg_attr(
2222    target_arch = "arm",
2223    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2224)]
2225pub fn vaddhn_high_s64(r: int32x2_t, a: int64x2_t, b: int64x2_t) -> int32x4_t {
2226    unsafe {
2227        let x = simd_cast(simd_shr(simd_add(a, b), int64x2_t::splat(32)));
2228        simd_shuffle!(r, x, [0, 1, 2, 3])
2229    }
2230}
2231#[doc = "Add returning High Narrow (high half)."]
2232#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u16)"]
2233#[inline]
2234#[target_feature(enable = "neon")]
2235#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2236#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2237#[cfg_attr(
2238    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2239    assert_instr(addhn2)
2240)]
2241#[cfg_attr(
2242    not(target_arch = "arm"),
2243    stable(feature = "neon_intrinsics", since = "1.59.0")
2244)]
2245#[cfg_attr(
2246    target_arch = "arm",
2247    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2248)]
2249pub fn vaddhn_high_u16(r: uint8x8_t, a: uint16x8_t, b: uint16x8_t) -> uint8x16_t {
2250    unsafe {
2251        let x = simd_cast(simd_shr(simd_add(a, b), uint16x8_t::splat(8)));
2252        simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15])
2253    }
2254}
2255#[doc = "Add returning High Narrow (high half)."]
2256#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u32)"]
2257#[inline]
2258#[target_feature(enable = "neon")]
2259#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2260#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2261#[cfg_attr(
2262    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2263    assert_instr(addhn2)
2264)]
2265#[cfg_attr(
2266    not(target_arch = "arm"),
2267    stable(feature = "neon_intrinsics", since = "1.59.0")
2268)]
2269#[cfg_attr(
2270    target_arch = "arm",
2271    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2272)]
2273pub fn vaddhn_high_u32(r: uint16x4_t, a: uint32x4_t, b: uint32x4_t) -> uint16x8_t {
2274    unsafe {
2275        let x = simd_cast(simd_shr(simd_add(a, b), uint32x4_t::splat(16)));
2276        simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7])
2277    }
2278}
2279#[doc = "Add returning High Narrow (high half)."]
2280#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u64)"]
2281#[inline]
2282#[target_feature(enable = "neon")]
2283#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2284#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2285#[cfg_attr(
2286    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2287    assert_instr(addhn2)
2288)]
2289#[cfg_attr(
2290    not(target_arch = "arm"),
2291    stable(feature = "neon_intrinsics", since = "1.59.0")
2292)]
2293#[cfg_attr(
2294    target_arch = "arm",
2295    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2296)]
2297pub fn vaddhn_high_u64(r: uint32x2_t, a: uint64x2_t, b: uint64x2_t) -> uint32x4_t {
2298    unsafe {
2299        let x = simd_cast(simd_shr(simd_add(a, b), uint64x2_t::splat(32)));
2300        simd_shuffle!(r, x, [0, 1, 2, 3])
2301    }
2302}
2303#[doc = "Add returning High Narrow."]
2304#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s16)"]
2305#[inline]
2306#[target_feature(enable = "neon")]
2307#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2308#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2309#[cfg_attr(
2310    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2311    assert_instr(addhn)
2312)]
2313#[cfg_attr(
2314    not(target_arch = "arm"),
2315    stable(feature = "neon_intrinsics", since = "1.59.0")
2316)]
2317#[cfg_attr(
2318    target_arch = "arm",
2319    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2320)]
2321pub fn vaddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
2322    unsafe { simd_cast(simd_shr(simd_add(a, b), int16x8_t::splat(8))) }
2323}
2324#[doc = "Add returning High Narrow."]
2325#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s32)"]
2326#[inline]
2327#[target_feature(enable = "neon")]
2328#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2329#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2330#[cfg_attr(
2331    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2332    assert_instr(addhn)
2333)]
2334#[cfg_attr(
2335    not(target_arch = "arm"),
2336    stable(feature = "neon_intrinsics", since = "1.59.0")
2337)]
2338#[cfg_attr(
2339    target_arch = "arm",
2340    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2341)]
2342pub fn vaddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
2343    unsafe { simd_cast(simd_shr(simd_add(a, b), int32x4_t::splat(16))) }
2344}
2345#[doc = "Add returning High Narrow."]
2346#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s64)"]
2347#[inline]
2348#[target_feature(enable = "neon")]
2349#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2350#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2351#[cfg_attr(
2352    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2353    assert_instr(addhn)
2354)]
2355#[cfg_attr(
2356    not(target_arch = "arm"),
2357    stable(feature = "neon_intrinsics", since = "1.59.0")
2358)]
2359#[cfg_attr(
2360    target_arch = "arm",
2361    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2362)]
2363pub fn vaddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
2364    unsafe { simd_cast(simd_shr(simd_add(a, b), int64x2_t::splat(32))) }
2365}
2366#[doc = "Add returning High Narrow."]
2367#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u16)"]
2368#[inline]
2369#[target_feature(enable = "neon")]
2370#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2371#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2372#[cfg_attr(
2373    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2374    assert_instr(addhn)
2375)]
2376#[cfg_attr(
2377    not(target_arch = "arm"),
2378    stable(feature = "neon_intrinsics", since = "1.59.0")
2379)]
2380#[cfg_attr(
2381    target_arch = "arm",
2382    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2383)]
2384pub fn vaddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
2385    unsafe { simd_cast(simd_shr(simd_add(a, b), uint16x8_t::splat(8))) }
2386}
2387#[doc = "Add returning High Narrow."]
2388#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u32)"]
2389#[inline]
2390#[target_feature(enable = "neon")]
2391#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2392#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2393#[cfg_attr(
2394    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2395    assert_instr(addhn)
2396)]
2397#[cfg_attr(
2398    not(target_arch = "arm"),
2399    stable(feature = "neon_intrinsics", since = "1.59.0")
2400)]
2401#[cfg_attr(
2402    target_arch = "arm",
2403    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2404)]
2405pub fn vaddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
2406    unsafe { simd_cast(simd_shr(simd_add(a, b), uint32x4_t::splat(16))) }
2407}
2408#[doc = "Add returning High Narrow."]
2409#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u64)"]
2410#[inline]
2411#[target_feature(enable = "neon")]
2412#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2413#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2414#[cfg_attr(
2415    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2416    assert_instr(addhn)
2417)]
2418#[cfg_attr(
2419    not(target_arch = "arm"),
2420    stable(feature = "neon_intrinsics", since = "1.59.0")
2421)]
2422#[cfg_attr(
2423    target_arch = "arm",
2424    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2425)]
2426pub fn vaddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
2427    unsafe { simd_cast(simd_shr(simd_add(a, b), uint64x2_t::splat(32))) }
2428}
2429#[doc = "Signed Add Long (vector, high half)."]
2430#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s16)"]
2431#[inline]
2432#[target_feature(enable = "neon")]
2433#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2434#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2435#[cfg_attr(
2436    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2437    assert_instr(saddl2)
2438)]
2439#[cfg_attr(
2440    not(target_arch = "arm"),
2441    stable(feature = "neon_intrinsics", since = "1.59.0")
2442)]
2443#[cfg_attr(
2444    target_arch = "arm",
2445    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2446)]
2447pub fn vaddl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
2448    unsafe {
2449        let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
2450        let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
2451        let a: int32x4_t = simd_cast(a);
2452        let b: int32x4_t = simd_cast(b);
2453        simd_add(a, b)
2454    }
2455}
2456#[doc = "Signed Add Long (vector, high half)."]
2457#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s32)"]
2458#[inline]
2459#[target_feature(enable = "neon")]
2460#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2461#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2462#[cfg_attr(
2463    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2464    assert_instr(saddl2)
2465)]
2466#[cfg_attr(
2467    not(target_arch = "arm"),
2468    stable(feature = "neon_intrinsics", since = "1.59.0")
2469)]
2470#[cfg_attr(
2471    target_arch = "arm",
2472    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2473)]
2474pub fn vaddl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
2475    unsafe {
2476        let a: int32x2_t = simd_shuffle!(a, a, [2, 3]);
2477        let b: int32x2_t = simd_shuffle!(b, b, [2, 3]);
2478        let a: int64x2_t = simd_cast(a);
2479        let b: int64x2_t = simd_cast(b);
2480        simd_add(a, b)
2481    }
2482}
2483#[doc = "Signed Add Long (vector, high half)."]
2484#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s8)"]
2485#[inline]
2486#[target_feature(enable = "neon")]
2487#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2488#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2489#[cfg_attr(
2490    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2491    assert_instr(saddl2)
2492)]
2493#[cfg_attr(
2494    not(target_arch = "arm"),
2495    stable(feature = "neon_intrinsics", since = "1.59.0")
2496)]
2497#[cfg_attr(
2498    target_arch = "arm",
2499    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2500)]
2501pub fn vaddl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
2502    unsafe {
2503        let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
2504        let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
2505        let a: int16x8_t = simd_cast(a);
2506        let b: int16x8_t = simd_cast(b);
2507        simd_add(a, b)
2508    }
2509}
2510#[doc = "Signed Add Long (vector, high half)."]
2511#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u16)"]
2512#[inline]
2513#[target_feature(enable = "neon")]
2514#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2515#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2516#[cfg_attr(
2517    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2518    assert_instr(uaddl2)
2519)]
2520#[cfg_attr(
2521    not(target_arch = "arm"),
2522    stable(feature = "neon_intrinsics", since = "1.59.0")
2523)]
2524#[cfg_attr(
2525    target_arch = "arm",
2526    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2527)]
2528pub fn vaddl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
2529    unsafe {
2530        let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
2531        let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
2532        let a: uint32x4_t = simd_cast(a);
2533        let b: uint32x4_t = simd_cast(b);
2534        simd_add(a, b)
2535    }
2536}
2537#[doc = "Signed Add Long (vector, high half)."]
2538#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u32)"]
2539#[inline]
2540#[target_feature(enable = "neon")]
2541#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2542#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2543#[cfg_attr(
2544    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2545    assert_instr(uaddl2)
2546)]
2547#[cfg_attr(
2548    not(target_arch = "arm"),
2549    stable(feature = "neon_intrinsics", since = "1.59.0")
2550)]
2551#[cfg_attr(
2552    target_arch = "arm",
2553    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2554)]
2555pub fn vaddl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
2556    unsafe {
2557        let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]);
2558        let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
2559        let a: uint64x2_t = simd_cast(a);
2560        let b: uint64x2_t = simd_cast(b);
2561        simd_add(a, b)
2562    }
2563}
2564#[doc = "Signed Add Long (vector, high half)."]
2565#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u8)"]
2566#[inline]
2567#[target_feature(enable = "neon")]
2568#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2569#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2570#[cfg_attr(
2571    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2572    assert_instr(uaddl2)
2573)]
2574#[cfg_attr(
2575    not(target_arch = "arm"),
2576    stable(feature = "neon_intrinsics", since = "1.59.0")
2577)]
2578#[cfg_attr(
2579    target_arch = "arm",
2580    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2581)]
2582pub fn vaddl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
2583    unsafe {
2584        let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
2585        let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
2586        let a: uint16x8_t = simd_cast(a);
2587        let b: uint16x8_t = simd_cast(b);
2588        simd_add(a, b)
2589    }
2590}
2591#[doc = "Add Long (vector)."]
2592#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s16)"]
2593#[inline]
2594#[target_feature(enable = "neon")]
2595#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2596#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2597#[cfg_attr(
2598    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2599    assert_instr(saddl)
2600)]
2601#[cfg_attr(
2602    not(target_arch = "arm"),
2603    stable(feature = "neon_intrinsics", since = "1.59.0")
2604)]
2605#[cfg_attr(
2606    target_arch = "arm",
2607    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2608)]
2609pub fn vaddl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
2610    unsafe {
2611        let a: int32x4_t = simd_cast(a);
2612        let b: int32x4_t = simd_cast(b);
2613        simd_add(a, b)
2614    }
2615}
2616#[doc = "Add Long (vector)."]
2617#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s32)"]
2618#[inline]
2619#[target_feature(enable = "neon")]
2620#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2621#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2622#[cfg_attr(
2623    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2624    assert_instr(saddl)
2625)]
2626#[cfg_attr(
2627    not(target_arch = "arm"),
2628    stable(feature = "neon_intrinsics", since = "1.59.0")
2629)]
2630#[cfg_attr(
2631    target_arch = "arm",
2632    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2633)]
2634pub fn vaddl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
2635    unsafe {
2636        let a: int64x2_t = simd_cast(a);
2637        let b: int64x2_t = simd_cast(b);
2638        simd_add(a, b)
2639    }
2640}
2641#[doc = "Add Long (vector)."]
2642#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s8)"]
2643#[inline]
2644#[target_feature(enable = "neon")]
2645#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2646#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2647#[cfg_attr(
2648    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2649    assert_instr(saddl)
2650)]
2651#[cfg_attr(
2652    not(target_arch = "arm"),
2653    stable(feature = "neon_intrinsics", since = "1.59.0")
2654)]
2655#[cfg_attr(
2656    target_arch = "arm",
2657    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2658)]
2659pub fn vaddl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
2660    unsafe {
2661        let a: int16x8_t = simd_cast(a);
2662        let b: int16x8_t = simd_cast(b);
2663        simd_add(a, b)
2664    }
2665}
2666#[doc = "Add Long (vector)."]
2667#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u16)"]
2668#[inline]
2669#[target_feature(enable = "neon")]
2670#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2671#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2672#[cfg_attr(
2673    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2674    assert_instr(uaddl)
2675)]
2676#[cfg_attr(
2677    not(target_arch = "arm"),
2678    stable(feature = "neon_intrinsics", since = "1.59.0")
2679)]
2680#[cfg_attr(
2681    target_arch = "arm",
2682    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2683)]
2684pub fn vaddl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
2685    unsafe {
2686        let a: uint32x4_t = simd_cast(a);
2687        let b: uint32x4_t = simd_cast(b);
2688        simd_add(a, b)
2689    }
2690}
2691#[doc = "Add Long (vector)."]
2692#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u32)"]
2693#[inline]
2694#[target_feature(enable = "neon")]
2695#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2696#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2697#[cfg_attr(
2698    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2699    assert_instr(uaddl)
2700)]
2701#[cfg_attr(
2702    not(target_arch = "arm"),
2703    stable(feature = "neon_intrinsics", since = "1.59.0")
2704)]
2705#[cfg_attr(
2706    target_arch = "arm",
2707    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2708)]
2709pub fn vaddl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
2710    unsafe {
2711        let a: uint64x2_t = simd_cast(a);
2712        let b: uint64x2_t = simd_cast(b);
2713        simd_add(a, b)
2714    }
2715}
2716#[doc = "Add Long (vector)."]
2717#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u8)"]
2718#[inline]
2719#[target_feature(enable = "neon")]
2720#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2721#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2722#[cfg_attr(
2723    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2724    assert_instr(uaddl)
2725)]
2726#[cfg_attr(
2727    not(target_arch = "arm"),
2728    stable(feature = "neon_intrinsics", since = "1.59.0")
2729)]
2730#[cfg_attr(
2731    target_arch = "arm",
2732    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2733)]
2734pub fn vaddl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
2735    unsafe {
2736        let a: uint16x8_t = simd_cast(a);
2737        let b: uint16x8_t = simd_cast(b);
2738        simd_add(a, b)
2739    }
2740}
2741#[doc = "Bitwise exclusive OR"]
2742#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p128)"]
2743#[inline]
2744#[target_feature(enable = "neon")]
2745#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2746#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2747#[cfg_attr(
2748    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2749    assert_instr(nop)
2750)]
2751#[cfg_attr(
2752    not(target_arch = "arm"),
2753    stable(feature = "neon_intrinsics", since = "1.59.0")
2754)]
2755#[cfg_attr(
2756    target_arch = "arm",
2757    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2758)]
2759pub fn vaddq_p128(a: p128, b: p128) -> p128 {
2760    a ^ b
2761}
2762#[doc = "Add Wide (high half)."]
2763#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s16)"]
2764#[inline]
2765#[target_feature(enable = "neon")]
2766#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2767#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2768#[cfg_attr(
2769    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2770    assert_instr(saddw2)
2771)]
2772#[cfg_attr(
2773    not(target_arch = "arm"),
2774    stable(feature = "neon_intrinsics", since = "1.59.0")
2775)]
2776#[cfg_attr(
2777    target_arch = "arm",
2778    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2779)]
2780pub fn vaddw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
2781    unsafe {
2782        let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
2783        let b: int32x4_t = simd_cast(b);
2784        simd_add(a, b)
2785    }
2786}
2787#[doc = "Add Wide (high half)."]
2788#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s32)"]
2789#[inline]
2790#[target_feature(enable = "neon")]
2791#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2792#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2793#[cfg_attr(
2794    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2795    assert_instr(saddw2)
2796)]
2797#[cfg_attr(
2798    not(target_arch = "arm"),
2799    stable(feature = "neon_intrinsics", since = "1.59.0")
2800)]
2801#[cfg_attr(
2802    target_arch = "arm",
2803    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2804)]
2805pub fn vaddw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
2806    unsafe {
2807        let b: int32x2_t = simd_shuffle!(b, b, [2, 3]);
2808        let b: int64x2_t = simd_cast(b);
2809        simd_add(a, b)
2810    }
2811}
2812#[doc = "Add Wide (high half)."]
2813#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s8)"]
2814#[inline]
2815#[target_feature(enable = "neon")]
2816#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2817#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2818#[cfg_attr(
2819    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2820    assert_instr(saddw2)
2821)]
2822#[cfg_attr(
2823    not(target_arch = "arm"),
2824    stable(feature = "neon_intrinsics", since = "1.59.0")
2825)]
2826#[cfg_attr(
2827    target_arch = "arm",
2828    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2829)]
2830pub fn vaddw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
2831    unsafe {
2832        let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
2833        let b: int16x8_t = simd_cast(b);
2834        simd_add(a, b)
2835    }
2836}
2837#[doc = "Add Wide (high half)."]
2838#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u16)"]
2839#[inline]
2840#[target_feature(enable = "neon")]
2841#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2842#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2843#[cfg_attr(
2844    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2845    assert_instr(uaddw2)
2846)]
2847#[cfg_attr(
2848    not(target_arch = "arm"),
2849    stable(feature = "neon_intrinsics", since = "1.59.0")
2850)]
2851#[cfg_attr(
2852    target_arch = "arm",
2853    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2854)]
2855pub fn vaddw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
2856    unsafe {
2857        let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
2858        let b: uint32x4_t = simd_cast(b);
2859        simd_add(a, b)
2860    }
2861}
2862#[doc = "Add Wide (high half)."]
2863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u32)"]
2864#[inline]
2865#[target_feature(enable = "neon")]
2866#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2867#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2868#[cfg_attr(
2869    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2870    assert_instr(uaddw2)
2871)]
2872#[cfg_attr(
2873    not(target_arch = "arm"),
2874    stable(feature = "neon_intrinsics", since = "1.59.0")
2875)]
2876#[cfg_attr(
2877    target_arch = "arm",
2878    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2879)]
2880pub fn vaddw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
2881    unsafe {
2882        let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
2883        let b: uint64x2_t = simd_cast(b);
2884        simd_add(a, b)
2885    }
2886}
2887#[doc = "Add Wide (high half)."]
2888#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u8)"]
2889#[inline]
2890#[target_feature(enable = "neon")]
2891#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2892#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2893#[cfg_attr(
2894    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2895    assert_instr(uaddw2)
2896)]
2897#[cfg_attr(
2898    not(target_arch = "arm"),
2899    stable(feature = "neon_intrinsics", since = "1.59.0")
2900)]
2901#[cfg_attr(
2902    target_arch = "arm",
2903    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2904)]
2905pub fn vaddw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
2906    unsafe {
2907        let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
2908        let b: uint16x8_t = simd_cast(b);
2909        simd_add(a, b)
2910    }
2911}
2912#[doc = "Add Wide"]
2913#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s16)"]
2914#[inline]
2915#[target_feature(enable = "neon")]
2916#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2917#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2918#[cfg_attr(
2919    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2920    assert_instr(saddw)
2921)]
2922#[cfg_attr(
2923    not(target_arch = "arm"),
2924    stable(feature = "neon_intrinsics", since = "1.59.0")
2925)]
2926#[cfg_attr(
2927    target_arch = "arm",
2928    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2929)]
2930pub fn vaddw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t {
2931    unsafe {
2932        let b: int32x4_t = simd_cast(b);
2933        simd_add(a, b)
2934    }
2935}
2936#[doc = "Add Wide"]
2937#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s32)"]
2938#[inline]
2939#[target_feature(enable = "neon")]
2940#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2941#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2942#[cfg_attr(
2943    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2944    assert_instr(saddw)
2945)]
2946#[cfg_attr(
2947    not(target_arch = "arm"),
2948    stable(feature = "neon_intrinsics", since = "1.59.0")
2949)]
2950#[cfg_attr(
2951    target_arch = "arm",
2952    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2953)]
2954pub fn vaddw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t {
2955    unsafe {
2956        let b: int64x2_t = simd_cast(b);
2957        simd_add(a, b)
2958    }
2959}
2960#[doc = "Add Wide"]
2961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s8)"]
2962#[inline]
2963#[target_feature(enable = "neon")]
2964#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2965#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2966#[cfg_attr(
2967    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2968    assert_instr(saddw)
2969)]
2970#[cfg_attr(
2971    not(target_arch = "arm"),
2972    stable(feature = "neon_intrinsics", since = "1.59.0")
2973)]
2974#[cfg_attr(
2975    target_arch = "arm",
2976    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2977)]
2978pub fn vaddw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t {
2979    unsafe {
2980        let b: int16x8_t = simd_cast(b);
2981        simd_add(a, b)
2982    }
2983}
2984#[doc = "Add Wide"]
2985#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u16)"]
2986#[inline]
2987#[target_feature(enable = "neon")]
2988#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2989#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2990#[cfg_attr(
2991    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2992    assert_instr(uaddw)
2993)]
2994#[cfg_attr(
2995    not(target_arch = "arm"),
2996    stable(feature = "neon_intrinsics", since = "1.59.0")
2997)]
2998#[cfg_attr(
2999    target_arch = "arm",
3000    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3001)]
3002pub fn vaddw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t {
3003    unsafe {
3004        let b: uint32x4_t = simd_cast(b);
3005        simd_add(a, b)
3006    }
3007}
3008#[doc = "Add Wide"]
3009#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u32)"]
3010#[inline]
3011#[target_feature(enable = "neon")]
3012#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3013#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
3014#[cfg_attr(
3015    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3016    assert_instr(uaddw)
3017)]
3018#[cfg_attr(
3019    not(target_arch = "arm"),
3020    stable(feature = "neon_intrinsics", since = "1.59.0")
3021)]
3022#[cfg_attr(
3023    target_arch = "arm",
3024    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3025)]
3026pub fn vaddw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t {
3027    unsafe {
3028        let b: uint64x2_t = simd_cast(b);
3029        simd_add(a, b)
3030    }
3031}
3032#[doc = "Add Wide"]
3033#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u8)"]
3034#[inline]
3035#[target_feature(enable = "neon")]
3036#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3037#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
3038#[cfg_attr(
3039    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3040    assert_instr(uaddw)
3041)]
3042#[cfg_attr(
3043    not(target_arch = "arm"),
3044    stable(feature = "neon_intrinsics", since = "1.59.0")
3045)]
3046#[cfg_attr(
3047    target_arch = "arm",
3048    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3049)]
3050pub fn vaddw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t {
3051    unsafe {
3052        let b: uint16x8_t = simd_cast(b);
3053        simd_add(a, b)
3054    }
3055}
3056#[doc = "AES single round encryption."]
3057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesdq_u8)"]
3058#[inline]
3059#[target_feature(enable = "aes")]
3060#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3061#[cfg_attr(test, assert_instr(aesd))]
3062#[cfg_attr(
3063    target_arch = "arm",
3064    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3065)]
3066#[cfg_attr(
3067    not(target_arch = "arm"),
3068    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
3069)]
3070pub fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
3071    unsafe extern "unadjusted" {
3072        #[cfg_attr(
3073            any(target_arch = "aarch64", target_arch = "arm64ec"),
3074            link_name = "llvm.aarch64.crypto.aesd"
3075        )]
3076        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesd")]
3077        fn _vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t;
3078    }
3079    unsafe { _vaesdq_u8(data, key) }
3080}
3081#[doc = "AES single round encryption."]
3082#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaeseq_u8)"]
3083#[inline]
3084#[target_feature(enable = "aes")]
3085#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3086#[cfg_attr(test, assert_instr(aese))]
3087#[cfg_attr(
3088    target_arch = "arm",
3089    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3090)]
3091#[cfg_attr(
3092    not(target_arch = "arm"),
3093    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
3094)]
3095pub fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
3096    unsafe extern "unadjusted" {
3097        #[cfg_attr(
3098            any(target_arch = "aarch64", target_arch = "arm64ec"),
3099            link_name = "llvm.aarch64.crypto.aese"
3100        )]
3101        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aese")]
3102        fn _vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t;
3103    }
3104    unsafe { _vaeseq_u8(data, key) }
3105}
3106#[doc = "AES inverse mix columns."]
3107#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesimcq_u8)"]
3108#[inline]
3109#[target_feature(enable = "aes")]
3110#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3111#[cfg_attr(test, assert_instr(aesimc))]
3112#[cfg_attr(
3113    target_arch = "arm",
3114    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3115)]
3116#[cfg_attr(
3117    not(target_arch = "arm"),
3118    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
3119)]
3120pub fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t {
3121    unsafe extern "unadjusted" {
3122        #[cfg_attr(
3123            any(target_arch = "aarch64", target_arch = "arm64ec"),
3124            link_name = "llvm.aarch64.crypto.aesimc"
3125        )]
3126        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesimc")]
3127        fn _vaesimcq_u8(data: uint8x16_t) -> uint8x16_t;
3128    }
3129    unsafe { _vaesimcq_u8(data) }
3130}
3131#[doc = "AES mix columns."]
3132#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesmcq_u8)"]
3133#[inline]
3134#[target_feature(enable = "aes")]
3135#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3136#[cfg_attr(test, assert_instr(aesmc))]
3137#[cfg_attr(
3138    target_arch = "arm",
3139    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3140)]
3141#[cfg_attr(
3142    not(target_arch = "arm"),
3143    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
3144)]
3145pub fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t {
3146    unsafe extern "unadjusted" {
3147        #[cfg_attr(
3148            any(target_arch = "aarch64", target_arch = "arm64ec"),
3149            link_name = "llvm.aarch64.crypto.aesmc"
3150        )]
3151        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesmc")]
3152        fn _vaesmcq_u8(data: uint8x16_t) -> uint8x16_t;
3153    }
3154    unsafe { _vaesmcq_u8(data) }
3155}
3156#[doc = "Vector bitwise and"]
3157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s8)"]
3158#[inline]
3159#[target_feature(enable = "neon")]
3160#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3161#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3162#[cfg_attr(
3163    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3164    assert_instr(and)
3165)]
3166#[cfg_attr(
3167    not(target_arch = "arm"),
3168    stable(feature = "neon_intrinsics", since = "1.59.0")
3169)]
3170#[cfg_attr(
3171    target_arch = "arm",
3172    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3173)]
3174pub fn vand_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
3175    unsafe { simd_and(a, b) }
3176}
3177#[doc = "Vector bitwise and"]
3178#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s8)"]
3179#[inline]
3180#[target_feature(enable = "neon")]
3181#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3182#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3183#[cfg_attr(
3184    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3185    assert_instr(and)
3186)]
3187#[cfg_attr(
3188    not(target_arch = "arm"),
3189    stable(feature = "neon_intrinsics", since = "1.59.0")
3190)]
3191#[cfg_attr(
3192    target_arch = "arm",
3193    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3194)]
3195pub fn vandq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
3196    unsafe { simd_and(a, b) }
3197}
3198#[doc = "Vector bitwise and"]
3199#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s16)"]
3200#[inline]
3201#[target_feature(enable = "neon")]
3202#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3203#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3204#[cfg_attr(
3205    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3206    assert_instr(and)
3207)]
3208#[cfg_attr(
3209    not(target_arch = "arm"),
3210    stable(feature = "neon_intrinsics", since = "1.59.0")
3211)]
3212#[cfg_attr(
3213    target_arch = "arm",
3214    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3215)]
3216pub fn vand_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
3217    unsafe { simd_and(a, b) }
3218}
3219#[doc = "Vector bitwise and"]
3220#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s16)"]
3221#[inline]
3222#[target_feature(enable = "neon")]
3223#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3224#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3225#[cfg_attr(
3226    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3227    assert_instr(and)
3228)]
3229#[cfg_attr(
3230    not(target_arch = "arm"),
3231    stable(feature = "neon_intrinsics", since = "1.59.0")
3232)]
3233#[cfg_attr(
3234    target_arch = "arm",
3235    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3236)]
3237pub fn vandq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
3238    unsafe { simd_and(a, b) }
3239}
3240#[doc = "Vector bitwise and"]
3241#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s32)"]
3242#[inline]
3243#[target_feature(enable = "neon")]
3244#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3245#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3246#[cfg_attr(
3247    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3248    assert_instr(and)
3249)]
3250#[cfg_attr(
3251    not(target_arch = "arm"),
3252    stable(feature = "neon_intrinsics", since = "1.59.0")
3253)]
3254#[cfg_attr(
3255    target_arch = "arm",
3256    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3257)]
3258pub fn vand_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
3259    unsafe { simd_and(a, b) }
3260}
3261#[doc = "Vector bitwise and"]
3262#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s32)"]
3263#[inline]
3264#[target_feature(enable = "neon")]
3265#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3266#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3267#[cfg_attr(
3268    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3269    assert_instr(and)
3270)]
3271#[cfg_attr(
3272    not(target_arch = "arm"),
3273    stable(feature = "neon_intrinsics", since = "1.59.0")
3274)]
3275#[cfg_attr(
3276    target_arch = "arm",
3277    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3278)]
3279pub fn vandq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
3280    unsafe { simd_and(a, b) }
3281}
3282#[doc = "Vector bitwise and"]
3283#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s64)"]
3284#[inline]
3285#[target_feature(enable = "neon")]
3286#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3287#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3288#[cfg_attr(
3289    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3290    assert_instr(and)
3291)]
3292#[cfg_attr(
3293    not(target_arch = "arm"),
3294    stable(feature = "neon_intrinsics", since = "1.59.0")
3295)]
3296#[cfg_attr(
3297    target_arch = "arm",
3298    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3299)]
3300pub fn vand_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
3301    unsafe { simd_and(a, b) }
3302}
3303#[doc = "Vector bitwise and"]
3304#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s64)"]
3305#[inline]
3306#[target_feature(enable = "neon")]
3307#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3308#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3309#[cfg_attr(
3310    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3311    assert_instr(and)
3312)]
3313#[cfg_attr(
3314    not(target_arch = "arm"),
3315    stable(feature = "neon_intrinsics", since = "1.59.0")
3316)]
3317#[cfg_attr(
3318    target_arch = "arm",
3319    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3320)]
3321pub fn vandq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
3322    unsafe { simd_and(a, b) }
3323}
3324#[doc = "Vector bitwise and"]
3325#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u8)"]
3326#[inline]
3327#[target_feature(enable = "neon")]
3328#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3329#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3330#[cfg_attr(
3331    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3332    assert_instr(and)
3333)]
3334#[cfg_attr(
3335    not(target_arch = "arm"),
3336    stable(feature = "neon_intrinsics", since = "1.59.0")
3337)]
3338#[cfg_attr(
3339    target_arch = "arm",
3340    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3341)]
3342pub fn vand_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
3343    unsafe { simd_and(a, b) }
3344}
3345#[doc = "Vector bitwise and"]
3346#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u8)"]
3347#[inline]
3348#[target_feature(enable = "neon")]
3349#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3350#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3351#[cfg_attr(
3352    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3353    assert_instr(and)
3354)]
3355#[cfg_attr(
3356    not(target_arch = "arm"),
3357    stable(feature = "neon_intrinsics", since = "1.59.0")
3358)]
3359#[cfg_attr(
3360    target_arch = "arm",
3361    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3362)]
3363pub fn vandq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
3364    unsafe { simd_and(a, b) }
3365}
3366#[doc = "Vector bitwise and"]
3367#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u16)"]
3368#[inline]
3369#[target_feature(enable = "neon")]
3370#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3371#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3372#[cfg_attr(
3373    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3374    assert_instr(and)
3375)]
3376#[cfg_attr(
3377    not(target_arch = "arm"),
3378    stable(feature = "neon_intrinsics", since = "1.59.0")
3379)]
3380#[cfg_attr(
3381    target_arch = "arm",
3382    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3383)]
3384pub fn vand_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
3385    unsafe { simd_and(a, b) }
3386}
3387#[doc = "Vector bitwise and"]
3388#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u16)"]
3389#[inline]
3390#[target_feature(enable = "neon")]
3391#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3392#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3393#[cfg_attr(
3394    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3395    assert_instr(and)
3396)]
3397#[cfg_attr(
3398    not(target_arch = "arm"),
3399    stable(feature = "neon_intrinsics", since = "1.59.0")
3400)]
3401#[cfg_attr(
3402    target_arch = "arm",
3403    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3404)]
3405pub fn vandq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
3406    unsafe { simd_and(a, b) }
3407}
3408#[doc = "Vector bitwise and"]
3409#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u32)"]
3410#[inline]
3411#[target_feature(enable = "neon")]
3412#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3413#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3414#[cfg_attr(
3415    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3416    assert_instr(and)
3417)]
3418#[cfg_attr(
3419    not(target_arch = "arm"),
3420    stable(feature = "neon_intrinsics", since = "1.59.0")
3421)]
3422#[cfg_attr(
3423    target_arch = "arm",
3424    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3425)]
3426pub fn vand_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
3427    unsafe { simd_and(a, b) }
3428}
3429#[doc = "Vector bitwise and"]
3430#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u32)"]
3431#[inline]
3432#[target_feature(enable = "neon")]
3433#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3434#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3435#[cfg_attr(
3436    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3437    assert_instr(and)
3438)]
3439#[cfg_attr(
3440    not(target_arch = "arm"),
3441    stable(feature = "neon_intrinsics", since = "1.59.0")
3442)]
3443#[cfg_attr(
3444    target_arch = "arm",
3445    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3446)]
3447pub fn vandq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
3448    unsafe { simd_and(a, b) }
3449}
3450#[doc = "Vector bitwise and"]
3451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u64)"]
3452#[inline]
3453#[target_feature(enable = "neon")]
3454#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3455#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3456#[cfg_attr(
3457    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3458    assert_instr(and)
3459)]
3460#[cfg_attr(
3461    not(target_arch = "arm"),
3462    stable(feature = "neon_intrinsics", since = "1.59.0")
3463)]
3464#[cfg_attr(
3465    target_arch = "arm",
3466    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3467)]
3468pub fn vand_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
3469    unsafe { simd_and(a, b) }
3470}
3471#[doc = "Vector bitwise and"]
3472#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u64)"]
3473#[inline]
3474#[target_feature(enable = "neon")]
3475#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3476#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3477#[cfg_attr(
3478    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3479    assert_instr(and)
3480)]
3481#[cfg_attr(
3482    not(target_arch = "arm"),
3483    stable(feature = "neon_intrinsics", since = "1.59.0")
3484)]
3485#[cfg_attr(
3486    target_arch = "arm",
3487    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3488)]
3489pub fn vandq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
3490    unsafe { simd_and(a, b) }
3491}
3492#[doc = "Vector bitwise bit clear."]
3493#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s16)"]
3494#[inline]
3495#[target_feature(enable = "neon")]
3496#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3497#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3498#[cfg_attr(
3499    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3500    assert_instr(bic)
3501)]
3502#[cfg_attr(
3503    not(target_arch = "arm"),
3504    stable(feature = "neon_intrinsics", since = "1.59.0")
3505)]
3506#[cfg_attr(
3507    target_arch = "arm",
3508    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3509)]
3510pub fn vbic_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
3511    let c = int16x4_t::splat(-1);
3512    unsafe { simd_and(simd_xor(b, c), a) }
3513}
3514#[doc = "Vector bitwise bit clear."]
3515#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s32)"]
3516#[inline]
3517#[target_feature(enable = "neon")]
3518#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3519#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3520#[cfg_attr(
3521    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3522    assert_instr(bic)
3523)]
3524#[cfg_attr(
3525    not(target_arch = "arm"),
3526    stable(feature = "neon_intrinsics", since = "1.59.0")
3527)]
3528#[cfg_attr(
3529    target_arch = "arm",
3530    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3531)]
3532pub fn vbic_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
3533    let c = int32x2_t::splat(-1);
3534    unsafe { simd_and(simd_xor(b, c), a) }
3535}
3536#[doc = "Vector bitwise bit clear."]
3537#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s64)"]
3538#[inline]
3539#[target_feature(enable = "neon")]
3540#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3541#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3542#[cfg_attr(
3543    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3544    assert_instr(bic)
3545)]
3546#[cfg_attr(
3547    not(target_arch = "arm"),
3548    stable(feature = "neon_intrinsics", since = "1.59.0")
3549)]
3550#[cfg_attr(
3551    target_arch = "arm",
3552    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3553)]
3554pub fn vbic_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
3555    let c = int64x1_t::splat(-1);
3556    unsafe { simd_and(simd_xor(b, c), a) }
3557}
3558#[doc = "Vector bitwise bit clear."]
3559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s8)"]
3560#[inline]
3561#[target_feature(enable = "neon")]
3562#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3563#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3564#[cfg_attr(
3565    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3566    assert_instr(bic)
3567)]
3568#[cfg_attr(
3569    not(target_arch = "arm"),
3570    stable(feature = "neon_intrinsics", since = "1.59.0")
3571)]
3572#[cfg_attr(
3573    target_arch = "arm",
3574    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3575)]
3576pub fn vbic_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
3577    let c = int8x8_t::splat(-1);
3578    unsafe { simd_and(simd_xor(b, c), a) }
3579}
3580#[doc = "Vector bitwise bit clear."]
3581#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s16)"]
3582#[inline]
3583#[target_feature(enable = "neon")]
3584#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3585#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3586#[cfg_attr(
3587    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3588    assert_instr(bic)
3589)]
3590#[cfg_attr(
3591    not(target_arch = "arm"),
3592    stable(feature = "neon_intrinsics", since = "1.59.0")
3593)]
3594#[cfg_attr(
3595    target_arch = "arm",
3596    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3597)]
3598pub fn vbicq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
3599    let c = int16x8_t::splat(-1);
3600    unsafe { simd_and(simd_xor(b, c), a) }
3601}
3602#[doc = "Vector bitwise bit clear."]
3603#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s32)"]
3604#[inline]
3605#[target_feature(enable = "neon")]
3606#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3607#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3608#[cfg_attr(
3609    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3610    assert_instr(bic)
3611)]
3612#[cfg_attr(
3613    not(target_arch = "arm"),
3614    stable(feature = "neon_intrinsics", since = "1.59.0")
3615)]
3616#[cfg_attr(
3617    target_arch = "arm",
3618    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3619)]
3620pub fn vbicq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
3621    let c = int32x4_t::splat(-1);
3622    unsafe { simd_and(simd_xor(b, c), a) }
3623}
3624#[doc = "Vector bitwise bit clear."]
3625#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s64)"]
3626#[inline]
3627#[target_feature(enable = "neon")]
3628#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3629#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3630#[cfg_attr(
3631    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3632    assert_instr(bic)
3633)]
3634#[cfg_attr(
3635    not(target_arch = "arm"),
3636    stable(feature = "neon_intrinsics", since = "1.59.0")
3637)]
3638#[cfg_attr(
3639    target_arch = "arm",
3640    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3641)]
3642pub fn vbicq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
3643    let c = int64x2_t::splat(-1);
3644    unsafe { simd_and(simd_xor(b, c), a) }
3645}
3646#[doc = "Vector bitwise bit clear."]
3647#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s8)"]
3648#[inline]
3649#[target_feature(enable = "neon")]
3650#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3651#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3652#[cfg_attr(
3653    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3654    assert_instr(bic)
3655)]
3656#[cfg_attr(
3657    not(target_arch = "arm"),
3658    stable(feature = "neon_intrinsics", since = "1.59.0")
3659)]
3660#[cfg_attr(
3661    target_arch = "arm",
3662    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3663)]
3664pub fn vbicq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
3665    let c = int8x16_t::splat(-1);
3666    unsafe { simd_and(simd_xor(b, c), a) }
3667}
3668#[doc = "Vector bitwise bit clear."]
3669#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u16)"]
3670#[inline]
3671#[target_feature(enable = "neon")]
3672#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3673#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3674#[cfg_attr(
3675    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3676    assert_instr(bic)
3677)]
3678#[cfg_attr(
3679    not(target_arch = "arm"),
3680    stable(feature = "neon_intrinsics", since = "1.59.0")
3681)]
3682#[cfg_attr(
3683    target_arch = "arm",
3684    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3685)]
3686pub fn vbic_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
3687    let c = int16x4_t::splat(-1);
3688    unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3689}
3690#[doc = "Vector bitwise bit clear."]
3691#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u32)"]
3692#[inline]
3693#[target_feature(enable = "neon")]
3694#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3695#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3696#[cfg_attr(
3697    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3698    assert_instr(bic)
3699)]
3700#[cfg_attr(
3701    not(target_arch = "arm"),
3702    stable(feature = "neon_intrinsics", since = "1.59.0")
3703)]
3704#[cfg_attr(
3705    target_arch = "arm",
3706    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3707)]
3708pub fn vbic_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
3709    let c = int32x2_t::splat(-1);
3710    unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3711}
3712#[doc = "Vector bitwise bit clear."]
3713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u64)"]
3714#[inline]
3715#[target_feature(enable = "neon")]
3716#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3717#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3718#[cfg_attr(
3719    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3720    assert_instr(bic)
3721)]
3722#[cfg_attr(
3723    not(target_arch = "arm"),
3724    stable(feature = "neon_intrinsics", since = "1.59.0")
3725)]
3726#[cfg_attr(
3727    target_arch = "arm",
3728    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3729)]
3730pub fn vbic_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
3731    let c = int64x1_t::splat(-1);
3732    unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3733}
3734#[doc = "Vector bitwise bit clear."]
3735#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u8)"]
3736#[inline]
3737#[target_feature(enable = "neon")]
3738#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3739#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3740#[cfg_attr(
3741    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3742    assert_instr(bic)
3743)]
3744#[cfg_attr(
3745    not(target_arch = "arm"),
3746    stable(feature = "neon_intrinsics", since = "1.59.0")
3747)]
3748#[cfg_attr(
3749    target_arch = "arm",
3750    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3751)]
3752pub fn vbic_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
3753    let c = int8x8_t::splat(-1);
3754    unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3755}
3756#[doc = "Vector bitwise bit clear."]
3757#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u16)"]
3758#[inline]
3759#[target_feature(enable = "neon")]
3760#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3761#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3762#[cfg_attr(
3763    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3764    assert_instr(bic)
3765)]
3766#[cfg_attr(
3767    not(target_arch = "arm"),
3768    stable(feature = "neon_intrinsics", since = "1.59.0")
3769)]
3770#[cfg_attr(
3771    target_arch = "arm",
3772    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3773)]
3774pub fn vbicq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
3775    let c = int16x8_t::splat(-1);
3776    unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3777}
3778#[doc = "Vector bitwise bit clear."]
3779#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u32)"]
3780#[inline]
3781#[target_feature(enable = "neon")]
3782#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3783#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3784#[cfg_attr(
3785    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3786    assert_instr(bic)
3787)]
3788#[cfg_attr(
3789    not(target_arch = "arm"),
3790    stable(feature = "neon_intrinsics", since = "1.59.0")
3791)]
3792#[cfg_attr(
3793    target_arch = "arm",
3794    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3795)]
3796pub fn vbicq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
3797    let c = int32x4_t::splat(-1);
3798    unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3799}
3800#[doc = "Vector bitwise bit clear."]
3801#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u64)"]
3802#[inline]
3803#[target_feature(enable = "neon")]
3804#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3805#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3806#[cfg_attr(
3807    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3808    assert_instr(bic)
3809)]
3810#[cfg_attr(
3811    not(target_arch = "arm"),
3812    stable(feature = "neon_intrinsics", since = "1.59.0")
3813)]
3814#[cfg_attr(
3815    target_arch = "arm",
3816    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3817)]
3818pub fn vbicq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
3819    let c = int64x2_t::splat(-1);
3820    unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3821}
3822#[doc = "Vector bitwise bit clear."]
3823#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u8)"]
3824#[inline]
3825#[target_feature(enable = "neon")]
3826#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3827#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3828#[cfg_attr(
3829    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3830    assert_instr(bic)
3831)]
3832#[cfg_attr(
3833    not(target_arch = "arm"),
3834    stable(feature = "neon_intrinsics", since = "1.59.0")
3835)]
3836#[cfg_attr(
3837    target_arch = "arm",
3838    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3839)]
3840pub fn vbicq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
3841    let c = int8x16_t::splat(-1);
3842    unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3843}
3844#[doc = "Bitwise Select."]
3845#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_f16)"]
3846#[inline]
3847#[target_feature(enable = "neon,fp16")]
3848#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3849#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3850#[cfg_attr(
3851    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3852    assert_instr(bsl)
3853)]
3854#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
3855pub fn vbsl_f16(a: uint16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
3856    let not = int16x4_t::splat(-1);
3857    unsafe {
3858        transmute(simd_or(
3859            simd_and(a, transmute(b)),
3860            simd_and(simd_xor(a, transmute(not)), transmute(c)),
3861        ))
3862    }
3863}
3864#[doc = "Bitwise Select."]
3865#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_f16)"]
3866#[inline]
3867#[target_feature(enable = "neon,fp16")]
3868#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3869#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3870#[cfg_attr(
3871    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3872    assert_instr(bsl)
3873)]
3874#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
3875pub fn vbslq_f16(a: uint16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
3876    let not = int16x8_t::splat(-1);
3877    unsafe {
3878        transmute(simd_or(
3879            simd_and(a, transmute(b)),
3880            simd_and(simd_xor(a, transmute(not)), transmute(c)),
3881        ))
3882    }
3883}
3884#[doc = "Bitwise Select."]
3885#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_f32)"]
3886#[inline]
3887#[target_feature(enable = "neon")]
3888#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3889#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3890#[cfg_attr(
3891    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3892    assert_instr(bsl)
3893)]
3894#[cfg_attr(
3895    not(target_arch = "arm"),
3896    stable(feature = "neon_intrinsics", since = "1.59.0")
3897)]
3898#[cfg_attr(
3899    target_arch = "arm",
3900    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3901)]
3902pub fn vbsl_f32(a: uint32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
3903    let not = int32x2_t::splat(-1);
3904    unsafe {
3905        transmute(simd_or(
3906            simd_and(a, transmute(b)),
3907            simd_and(simd_xor(a, transmute(not)), transmute(c)),
3908        ))
3909    }
3910}
3911#[doc = "Bitwise Select."]
3912#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_p16)"]
3913#[inline]
3914#[target_feature(enable = "neon")]
3915#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3916#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3917#[cfg_attr(
3918    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3919    assert_instr(bsl)
3920)]
3921#[cfg_attr(
3922    not(target_arch = "arm"),
3923    stable(feature = "neon_intrinsics", since = "1.59.0")
3924)]
3925#[cfg_attr(
3926    target_arch = "arm",
3927    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3928)]
3929pub fn vbsl_p16(a: uint16x4_t, b: poly16x4_t, c: poly16x4_t) -> poly16x4_t {
3930    let not = int16x4_t::splat(-1);
3931    unsafe {
3932        transmute(simd_or(
3933            simd_and(a, transmute(b)),
3934            simd_and(simd_xor(a, transmute(not)), transmute(c)),
3935        ))
3936    }
3937}
3938#[doc = "Bitwise Select."]
3939#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_p8)"]
3940#[inline]
3941#[target_feature(enable = "neon")]
3942#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3943#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3944#[cfg_attr(
3945    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3946    assert_instr(bsl)
3947)]
3948#[cfg_attr(
3949    not(target_arch = "arm"),
3950    stable(feature = "neon_intrinsics", since = "1.59.0")
3951)]
3952#[cfg_attr(
3953    target_arch = "arm",
3954    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3955)]
3956pub fn vbsl_p8(a: uint8x8_t, b: poly8x8_t, c: poly8x8_t) -> poly8x8_t {
3957    let not = int8x8_t::splat(-1);
3958    unsafe {
3959        transmute(simd_or(
3960            simd_and(a, transmute(b)),
3961            simd_and(simd_xor(a, transmute(not)), transmute(c)),
3962        ))
3963    }
3964}
3965#[doc = "Bitwise Select."]
3966#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s16)"]
3967#[inline]
3968#[target_feature(enable = "neon")]
3969#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3970#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3971#[cfg_attr(
3972    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3973    assert_instr(bsl)
3974)]
3975#[cfg_attr(
3976    not(target_arch = "arm"),
3977    stable(feature = "neon_intrinsics", since = "1.59.0")
3978)]
3979#[cfg_attr(
3980    target_arch = "arm",
3981    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3982)]
3983pub fn vbsl_s16(a: uint16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
3984    let not = int16x4_t::splat(-1);
3985    unsafe {
3986        transmute(simd_or(
3987            simd_and(a, transmute(b)),
3988            simd_and(simd_xor(a, transmute(not)), transmute(c)),
3989        ))
3990    }
3991}
3992#[doc = "Bitwise Select."]
3993#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s32)"]
3994#[inline]
3995#[target_feature(enable = "neon")]
3996#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3997#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3998#[cfg_attr(
3999    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4000    assert_instr(bsl)
4001)]
4002#[cfg_attr(
4003    not(target_arch = "arm"),
4004    stable(feature = "neon_intrinsics", since = "1.59.0")
4005)]
4006#[cfg_attr(
4007    target_arch = "arm",
4008    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4009)]
4010pub fn vbsl_s32(a: uint32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
4011    let not = int32x2_t::splat(-1);
4012    unsafe {
4013        transmute(simd_or(
4014            simd_and(a, transmute(b)),
4015            simd_and(simd_xor(a, transmute(not)), transmute(c)),
4016        ))
4017    }
4018}
4019#[doc = "Bitwise Select."]
4020#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s64)"]
4021#[inline]
4022#[target_feature(enable = "neon")]
4023#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4024#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4025#[cfg_attr(
4026    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4027    assert_instr(bsl)
4028)]
4029#[cfg_attr(
4030    not(target_arch = "arm"),
4031    stable(feature = "neon_intrinsics", since = "1.59.0")
4032)]
4033#[cfg_attr(
4034    target_arch = "arm",
4035    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4036)]
4037pub fn vbsl_s64(a: uint64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t {
4038    let not = int64x1_t::splat(-1);
4039    unsafe {
4040        transmute(simd_or(
4041            simd_and(a, transmute(b)),
4042            simd_and(simd_xor(a, transmute(not)), transmute(c)),
4043        ))
4044    }
4045}
4046#[doc = "Bitwise Select."]
4047#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s8)"]
4048#[inline]
4049#[target_feature(enable = "neon")]
4050#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4051#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4052#[cfg_attr(
4053    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4054    assert_instr(bsl)
4055)]
4056#[cfg_attr(
4057    not(target_arch = "arm"),
4058    stable(feature = "neon_intrinsics", since = "1.59.0")
4059)]
4060#[cfg_attr(
4061    target_arch = "arm",
4062    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4063)]
4064pub fn vbsl_s8(a: uint8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
4065    let not = int8x8_t::splat(-1);
4066    unsafe {
4067        transmute(simd_or(
4068            simd_and(a, transmute(b)),
4069            simd_and(simd_xor(a, transmute(not)), transmute(c)),
4070        ))
4071    }
4072}
4073#[doc = "Bitwise Select."]
4074#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_f32)"]
4075#[inline]
4076#[target_feature(enable = "neon")]
4077#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4078#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4079#[cfg_attr(
4080    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4081    assert_instr(bsl)
4082)]
4083#[cfg_attr(
4084    not(target_arch = "arm"),
4085    stable(feature = "neon_intrinsics", since = "1.59.0")
4086)]
4087#[cfg_attr(
4088    target_arch = "arm",
4089    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4090)]
4091pub fn vbslq_f32(a: uint32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
4092    let not = int32x4_t::splat(-1);
4093    unsafe {
4094        transmute(simd_or(
4095            simd_and(a, transmute(b)),
4096            simd_and(simd_xor(a, transmute(not)), transmute(c)),
4097        ))
4098    }
4099}
4100#[doc = "Bitwise Select."]
4101#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_p16)"]
4102#[inline]
4103#[target_feature(enable = "neon")]
4104#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4105#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4106#[cfg_attr(
4107    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4108    assert_instr(bsl)
4109)]
4110#[cfg_attr(
4111    not(target_arch = "arm"),
4112    stable(feature = "neon_intrinsics", since = "1.59.0")
4113)]
4114#[cfg_attr(
4115    target_arch = "arm",
4116    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4117)]
4118pub fn vbslq_p16(a: uint16x8_t, b: poly16x8_t, c: poly16x8_t) -> poly16x8_t {
4119    let not = int16x8_t::splat(-1);
4120    unsafe {
4121        transmute(simd_or(
4122            simd_and(a, transmute(b)),
4123            simd_and(simd_xor(a, transmute(not)), transmute(c)),
4124        ))
4125    }
4126}
4127#[doc = "Bitwise Select."]
4128#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_p8)"]
4129#[inline]
4130#[target_feature(enable = "neon")]
4131#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4132#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4133#[cfg_attr(
4134    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4135    assert_instr(bsl)
4136)]
4137#[cfg_attr(
4138    not(target_arch = "arm"),
4139    stable(feature = "neon_intrinsics", since = "1.59.0")
4140)]
4141#[cfg_attr(
4142    target_arch = "arm",
4143    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4144)]
4145pub fn vbslq_p8(a: uint8x16_t, b: poly8x16_t, c: poly8x16_t) -> poly8x16_t {
4146    let not = int8x16_t::splat(-1);
4147    unsafe {
4148        transmute(simd_or(
4149            simd_and(a, transmute(b)),
4150            simd_and(simd_xor(a, transmute(not)), transmute(c)),
4151        ))
4152    }
4153}
4154#[doc = "Bitwise Select."]
4155#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s16)"]
4156#[inline]
4157#[target_feature(enable = "neon")]
4158#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4159#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4160#[cfg_attr(
4161    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4162    assert_instr(bsl)
4163)]
4164#[cfg_attr(
4165    not(target_arch = "arm"),
4166    stable(feature = "neon_intrinsics", since = "1.59.0")
4167)]
4168#[cfg_attr(
4169    target_arch = "arm",
4170    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4171)]
4172pub fn vbslq_s16(a: uint16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
4173    let not = int16x8_t::splat(-1);
4174    unsafe {
4175        transmute(simd_or(
4176            simd_and(a, transmute(b)),
4177            simd_and(simd_xor(a, transmute(not)), transmute(c)),
4178        ))
4179    }
4180}
4181#[doc = "Bitwise Select."]
4182#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s32)"]
4183#[inline]
4184#[target_feature(enable = "neon")]
4185#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4186#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4187#[cfg_attr(
4188    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4189    assert_instr(bsl)
4190)]
4191#[cfg_attr(
4192    not(target_arch = "arm"),
4193    stable(feature = "neon_intrinsics", since = "1.59.0")
4194)]
4195#[cfg_attr(
4196    target_arch = "arm",
4197    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4198)]
4199pub fn vbslq_s32(a: uint32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
4200    let not = int32x4_t::splat(-1);
4201    unsafe {
4202        transmute(simd_or(
4203            simd_and(a, transmute(b)),
4204            simd_and(simd_xor(a, transmute(not)), transmute(c)),
4205        ))
4206    }
4207}
4208#[doc = "Bitwise Select."]
4209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s64)"]
4210#[inline]
4211#[target_feature(enable = "neon")]
4212#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4213#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4214#[cfg_attr(
4215    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4216    assert_instr(bsl)
4217)]
4218#[cfg_attr(
4219    not(target_arch = "arm"),
4220    stable(feature = "neon_intrinsics", since = "1.59.0")
4221)]
4222#[cfg_attr(
4223    target_arch = "arm",
4224    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4225)]
4226pub fn vbslq_s64(a: uint64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
4227    let not = int64x2_t::splat(-1);
4228    unsafe {
4229        transmute(simd_or(
4230            simd_and(a, transmute(b)),
4231            simd_and(simd_xor(a, transmute(not)), transmute(c)),
4232        ))
4233    }
4234}
4235#[doc = "Bitwise Select."]
4236#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s8)"]
4237#[inline]
4238#[target_feature(enable = "neon")]
4239#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4240#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4241#[cfg_attr(
4242    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4243    assert_instr(bsl)
4244)]
4245#[cfg_attr(
4246    not(target_arch = "arm"),
4247    stable(feature = "neon_intrinsics", since = "1.59.0")
4248)]
4249#[cfg_attr(
4250    target_arch = "arm",
4251    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4252)]
4253pub fn vbslq_s8(a: uint8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
4254    let not = int8x16_t::splat(-1);
4255    unsafe {
4256        transmute(simd_or(
4257            simd_and(a, transmute(b)),
4258            simd_and(simd_xor(a, transmute(not)), transmute(c)),
4259        ))
4260    }
4261}
4262#[doc = "Bitwise Select."]
4263#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u16)"]
4264#[inline]
4265#[target_feature(enable = "neon")]
4266#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4267#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4268#[cfg_attr(
4269    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4270    assert_instr(bsl)
4271)]
4272#[cfg_attr(
4273    not(target_arch = "arm"),
4274    stable(feature = "neon_intrinsics", since = "1.59.0")
4275)]
4276#[cfg_attr(
4277    target_arch = "arm",
4278    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4279)]
4280pub fn vbsl_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
4281    let not = int16x4_t::splat(-1);
4282    unsafe {
4283        transmute(simd_or(
4284            simd_and(a, b),
4285            simd_and(simd_xor(a, transmute(not)), c),
4286        ))
4287    }
4288}
4289#[doc = "Bitwise Select."]
4290#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u32)"]
4291#[inline]
4292#[target_feature(enable = "neon")]
4293#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4294#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4295#[cfg_attr(
4296    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4297    assert_instr(bsl)
4298)]
4299#[cfg_attr(
4300    not(target_arch = "arm"),
4301    stable(feature = "neon_intrinsics", since = "1.59.0")
4302)]
4303#[cfg_attr(
4304    target_arch = "arm",
4305    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4306)]
4307pub fn vbsl_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
4308    let not = int32x2_t::splat(-1);
4309    unsafe {
4310        transmute(simd_or(
4311            simd_and(a, b),
4312            simd_and(simd_xor(a, transmute(not)), c),
4313        ))
4314    }
4315}
4316#[doc = "Bitwise Select."]
4317#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u64)"]
4318#[inline]
4319#[target_feature(enable = "neon")]
4320#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4321#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4322#[cfg_attr(
4323    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4324    assert_instr(bsl)
4325)]
4326#[cfg_attr(
4327    not(target_arch = "arm"),
4328    stable(feature = "neon_intrinsics", since = "1.59.0")
4329)]
4330#[cfg_attr(
4331    target_arch = "arm",
4332    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4333)]
4334pub fn vbsl_u64(a: uint64x1_t, b: uint64x1_t, c: uint64x1_t) -> uint64x1_t {
4335    let not = int64x1_t::splat(-1);
4336    unsafe {
4337        transmute(simd_or(
4338            simd_and(a, b),
4339            simd_and(simd_xor(a, transmute(not)), c),
4340        ))
4341    }
4342}
4343#[doc = "Bitwise Select."]
4344#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u8)"]
4345#[inline]
4346#[target_feature(enable = "neon")]
4347#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4348#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4349#[cfg_attr(
4350    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4351    assert_instr(bsl)
4352)]
4353#[cfg_attr(
4354    not(target_arch = "arm"),
4355    stable(feature = "neon_intrinsics", since = "1.59.0")
4356)]
4357#[cfg_attr(
4358    target_arch = "arm",
4359    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4360)]
4361pub fn vbsl_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
4362    let not = int8x8_t::splat(-1);
4363    unsafe {
4364        transmute(simd_or(
4365            simd_and(a, b),
4366            simd_and(simd_xor(a, transmute(not)), c),
4367        ))
4368    }
4369}
4370#[doc = "Bitwise Select."]
4371#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u16)"]
4372#[inline]
4373#[target_feature(enable = "neon")]
4374#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4375#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4376#[cfg_attr(
4377    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4378    assert_instr(bsl)
4379)]
4380#[cfg_attr(
4381    not(target_arch = "arm"),
4382    stable(feature = "neon_intrinsics", since = "1.59.0")
4383)]
4384#[cfg_attr(
4385    target_arch = "arm",
4386    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4387)]
4388pub fn vbslq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
4389    let not = int16x8_t::splat(-1);
4390    unsafe {
4391        transmute(simd_or(
4392            simd_and(a, b),
4393            simd_and(simd_xor(a, transmute(not)), c),
4394        ))
4395    }
4396}
4397#[doc = "Bitwise Select."]
4398#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u32)"]
4399#[inline]
4400#[target_feature(enable = "neon")]
4401#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4402#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4403#[cfg_attr(
4404    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4405    assert_instr(bsl)
4406)]
4407#[cfg_attr(
4408    not(target_arch = "arm"),
4409    stable(feature = "neon_intrinsics", since = "1.59.0")
4410)]
4411#[cfg_attr(
4412    target_arch = "arm",
4413    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4414)]
4415pub fn vbslq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
4416    let not = int32x4_t::splat(-1);
4417    unsafe {
4418        transmute(simd_or(
4419            simd_and(a, b),
4420            simd_and(simd_xor(a, transmute(not)), c),
4421        ))
4422    }
4423}
4424#[doc = "Bitwise Select."]
4425#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u64)"]
4426#[inline]
4427#[target_feature(enable = "neon")]
4428#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4429#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4430#[cfg_attr(
4431    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4432    assert_instr(bsl)
4433)]
4434#[cfg_attr(
4435    not(target_arch = "arm"),
4436    stable(feature = "neon_intrinsics", since = "1.59.0")
4437)]
4438#[cfg_attr(
4439    target_arch = "arm",
4440    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4441)]
4442pub fn vbslq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
4443    let not = int64x2_t::splat(-1);
4444    unsafe {
4445        transmute(simd_or(
4446            simd_and(a, b),
4447            simd_and(simd_xor(a, transmute(not)), c),
4448        ))
4449    }
4450}
4451#[doc = "Bitwise Select."]
4452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u8)"]
4453#[inline]
4454#[target_feature(enable = "neon")]
4455#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4456#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4457#[cfg_attr(
4458    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4459    assert_instr(bsl)
4460)]
4461#[cfg_attr(
4462    not(target_arch = "arm"),
4463    stable(feature = "neon_intrinsics", since = "1.59.0")
4464)]
4465#[cfg_attr(
4466    target_arch = "arm",
4467    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4468)]
4469pub fn vbslq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
4470    let not = int8x16_t::splat(-1);
4471    unsafe {
4472        transmute(simd_or(
4473            simd_and(a, b),
4474            simd_and(simd_xor(a, transmute(not)), c),
4475        ))
4476    }
4477}
4478#[doc = "Floating-point absolute compare greater than or equal"]
4479#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f16)"]
4480#[inline]
4481#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4482#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
4483#[cfg_attr(
4484    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4485    assert_instr(facge)
4486)]
4487#[target_feature(enable = "neon,fp16")]
4488#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4489pub fn vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
4490    unsafe extern "unadjusted" {
4491        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v4i16.v4f16")]
4492        #[cfg_attr(
4493            any(target_arch = "aarch64", target_arch = "arm64ec"),
4494            link_name = "llvm.aarch64.neon.facge.v4i16.v4f16"
4495        )]
4496        fn _vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t;
4497    }
4498    unsafe { _vcage_f16(a, b) }
4499}
4500#[doc = "Floating-point absolute compare greater than or equal"]
4501#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f16)"]
4502#[inline]
4503#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4504#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
4505#[cfg_attr(
4506    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4507    assert_instr(facge)
4508)]
4509#[target_feature(enable = "neon,fp16")]
4510#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4511pub fn vcageq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
4512    unsafe extern "unadjusted" {
4513        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v8i16.v8f16")]
4514        #[cfg_attr(
4515            any(target_arch = "aarch64", target_arch = "arm64ec"),
4516            link_name = "llvm.aarch64.neon.facge.v8i16.v8f16"
4517        )]
4518        fn _vcageq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t;
4519    }
4520    unsafe { _vcageq_f16(a, b) }
4521}
4522#[doc = "Floating-point absolute compare greater than or equal"]
4523#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f32)"]
4524#[inline]
4525#[target_feature(enable = "neon")]
4526#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4527#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
4528#[cfg_attr(
4529    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4530    assert_instr(facge)
4531)]
4532#[cfg_attr(
4533    not(target_arch = "arm"),
4534    stable(feature = "neon_intrinsics", since = "1.59.0")
4535)]
4536#[cfg_attr(
4537    target_arch = "arm",
4538    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4539)]
4540pub fn vcage_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
4541    unsafe extern "unadjusted" {
4542        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v2i32.v2f32")]
4543        #[cfg_attr(
4544            any(target_arch = "aarch64", target_arch = "arm64ec"),
4545            link_name = "llvm.aarch64.neon.facge.v2i32.v2f32"
4546        )]
4547        fn _vcage_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t;
4548    }
4549    unsafe { _vcage_f32(a, b) }
4550}
4551#[doc = "Floating-point absolute compare greater than or equal"]
4552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f32)"]
4553#[inline]
4554#[target_feature(enable = "neon")]
4555#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4556#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
4557#[cfg_attr(
4558    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4559    assert_instr(facge)
4560)]
4561#[cfg_attr(
4562    not(target_arch = "arm"),
4563    stable(feature = "neon_intrinsics", since = "1.59.0")
4564)]
4565#[cfg_attr(
4566    target_arch = "arm",
4567    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4568)]
4569pub fn vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
4570    unsafe extern "unadjusted" {
4571        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v4i32.v4f32")]
4572        #[cfg_attr(
4573            any(target_arch = "aarch64", target_arch = "arm64ec"),
4574            link_name = "llvm.aarch64.neon.facge.v4i32.v4f32"
4575        )]
4576        fn _vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t;
4577    }
4578    unsafe { _vcageq_f32(a, b) }
4579}
4580#[doc = "Floating-point absolute compare greater than"]
4581#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f16)"]
4582#[inline]
4583#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4584#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
4585#[cfg_attr(
4586    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4587    assert_instr(facgt)
4588)]
4589#[target_feature(enable = "neon,fp16")]
4590#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4591pub fn vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
4592    unsafe extern "unadjusted" {
4593        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v4i16.v4f16")]
4594        #[cfg_attr(
4595            any(target_arch = "aarch64", target_arch = "arm64ec"),
4596            link_name = "llvm.aarch64.neon.facgt.v4i16.v4f16"
4597        )]
4598        fn _vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t;
4599    }
4600    unsafe { _vcagt_f16(a, b) }
4601}
4602#[doc = "Floating-point absolute compare greater than"]
4603#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f16)"]
4604#[inline]
4605#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4606#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
4607#[cfg_attr(
4608    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4609    assert_instr(facgt)
4610)]
4611#[target_feature(enable = "neon,fp16")]
4612#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4613pub fn vcagtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
4614    unsafe extern "unadjusted" {
4615        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v8i16.v8f16")]
4616        #[cfg_attr(
4617            any(target_arch = "aarch64", target_arch = "arm64ec"),
4618            link_name = "llvm.aarch64.neon.facgt.v8i16.v8f16"
4619        )]
4620        fn _vcagtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t;
4621    }
4622    unsafe { _vcagtq_f16(a, b) }
4623}
4624#[doc = "Floating-point absolute compare greater than"]
4625#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f32)"]
4626#[inline]
4627#[target_feature(enable = "neon")]
4628#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4629#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
4630#[cfg_attr(
4631    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4632    assert_instr(facgt)
4633)]
4634#[cfg_attr(
4635    not(target_arch = "arm"),
4636    stable(feature = "neon_intrinsics", since = "1.59.0")
4637)]
4638#[cfg_attr(
4639    target_arch = "arm",
4640    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4641)]
4642pub fn vcagt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
4643    unsafe extern "unadjusted" {
4644        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v2i32.v2f32")]
4645        #[cfg_attr(
4646            any(target_arch = "aarch64", target_arch = "arm64ec"),
4647            link_name = "llvm.aarch64.neon.facgt.v2i32.v2f32"
4648        )]
4649        fn _vcagt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t;
4650    }
4651    unsafe { _vcagt_f32(a, b) }
4652}
4653#[doc = "Floating-point absolute compare greater than"]
4654#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f32)"]
4655#[inline]
4656#[target_feature(enable = "neon")]
4657#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4658#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
4659#[cfg_attr(
4660    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4661    assert_instr(facgt)
4662)]
4663#[cfg_attr(
4664    not(target_arch = "arm"),
4665    stable(feature = "neon_intrinsics", since = "1.59.0")
4666)]
4667#[cfg_attr(
4668    target_arch = "arm",
4669    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4670)]
4671pub fn vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
4672    unsafe extern "unadjusted" {
4673        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v4i32.v4f32")]
4674        #[cfg_attr(
4675            any(target_arch = "aarch64", target_arch = "arm64ec"),
4676            link_name = "llvm.aarch64.neon.facgt.v4i32.v4f32"
4677        )]
4678        fn _vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t;
4679    }
4680    unsafe { _vcagtq_f32(a, b) }
4681}
4682#[doc = "Floating-point absolute compare less than or equal"]
4683#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f16)"]
4684#[inline]
4685#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4686#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
4687#[cfg_attr(
4688    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4689    assert_instr(facge)
4690)]
4691#[target_feature(enable = "neon,fp16")]
4692#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4693pub fn vcale_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
4694    vcage_f16(b, a)
4695}
4696#[doc = "Floating-point absolute compare less than or equal"]
4697#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f16)"]
4698#[inline]
4699#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4700#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
4701#[cfg_attr(
4702    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4703    assert_instr(facge)
4704)]
4705#[target_feature(enable = "neon,fp16")]
4706#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4707pub fn vcaleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
4708    vcageq_f16(b, a)
4709}
4710#[doc = "Floating-point absolute compare less than or equal"]
4711#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f32)"]
4712#[inline]
4713#[target_feature(enable = "neon")]
4714#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4715#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
4716#[cfg_attr(
4717    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4718    assert_instr(facge)
4719)]
4720#[cfg_attr(
4721    not(target_arch = "arm"),
4722    stable(feature = "neon_intrinsics", since = "1.59.0")
4723)]
4724#[cfg_attr(
4725    target_arch = "arm",
4726    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4727)]
4728pub fn vcale_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
4729    vcage_f32(b, a)
4730}
4731#[doc = "Floating-point absolute compare less than or equal"]
4732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f32)"]
4733#[inline]
4734#[target_feature(enable = "neon")]
4735#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4736#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
4737#[cfg_attr(
4738    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4739    assert_instr(facge)
4740)]
4741#[cfg_attr(
4742    not(target_arch = "arm"),
4743    stable(feature = "neon_intrinsics", since = "1.59.0")
4744)]
4745#[cfg_attr(
4746    target_arch = "arm",
4747    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4748)]
4749pub fn vcaleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
4750    vcageq_f32(b, a)
4751}
4752#[doc = "Floating-point absolute compare less than"]
4753#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f16)"]
4754#[inline]
4755#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4756#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
4757#[cfg_attr(
4758    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4759    assert_instr(facgt)
4760)]
4761#[target_feature(enable = "neon,fp16")]
4762#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4763pub fn vcalt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
4764    vcagt_f16(b, a)
4765}
4766#[doc = "Floating-point absolute compare less than"]
4767#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f16)"]
4768#[inline]
4769#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4770#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
4771#[cfg_attr(
4772    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4773    assert_instr(facgt)
4774)]
4775#[target_feature(enable = "neon,fp16")]
4776#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4777pub fn vcaltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
4778    vcagtq_f16(b, a)
4779}
4780#[doc = "Floating-point absolute compare less than"]
4781#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f32)"]
4782#[inline]
4783#[target_feature(enable = "neon")]
4784#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4785#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
4786#[cfg_attr(
4787    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4788    assert_instr(facgt)
4789)]
4790#[cfg_attr(
4791    not(target_arch = "arm"),
4792    stable(feature = "neon_intrinsics", since = "1.59.0")
4793)]
4794#[cfg_attr(
4795    target_arch = "arm",
4796    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4797)]
4798pub fn vcalt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
4799    vcagt_f32(b, a)
4800}
4801#[doc = "Floating-point absolute compare less than"]
4802#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f32)"]
4803#[inline]
4804#[target_feature(enable = "neon")]
4805#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4806#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
4807#[cfg_attr(
4808    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4809    assert_instr(facgt)
4810)]
4811#[cfg_attr(
4812    not(target_arch = "arm"),
4813    stable(feature = "neon_intrinsics", since = "1.59.0")
4814)]
4815#[cfg_attr(
4816    target_arch = "arm",
4817    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4818)]
4819pub fn vcaltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
4820    vcagtq_f32(b, a)
4821}
4822#[doc = "Floating-point compare equal"]
4823#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f16)"]
4824#[inline]
4825#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4826#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f16"))]
4827#[cfg_attr(
4828    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4829    assert_instr(fcmeq)
4830)]
4831#[target_feature(enable = "neon,fp16")]
4832#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4833pub fn vceq_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
4834    unsafe { simd_eq(a, b) }
4835}
4836#[doc = "Floating-point compare equal"]
4837#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f16)"]
4838#[inline]
4839#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4840#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f16"))]
4841#[cfg_attr(
4842    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4843    assert_instr(fcmeq)
4844)]
4845#[target_feature(enable = "neon,fp16")]
4846#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4847pub fn vceqq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
4848    unsafe { simd_eq(a, b) }
4849}
4850#[doc = "Floating-point compare equal"]
4851#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f32)"]
4852#[inline]
4853#[target_feature(enable = "neon")]
4854#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4855#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))]
4856#[cfg_attr(
4857    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4858    assert_instr(fcmeq)
4859)]
4860#[cfg_attr(
4861    not(target_arch = "arm"),
4862    stable(feature = "neon_intrinsics", since = "1.59.0")
4863)]
4864#[cfg_attr(
4865    target_arch = "arm",
4866    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4867)]
4868pub fn vceq_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
4869    unsafe { simd_eq(a, b) }
4870}
4871#[doc = "Floating-point compare equal"]
4872#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f32)"]
4873#[inline]
4874#[target_feature(enable = "neon")]
4875#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4876#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))]
4877#[cfg_attr(
4878    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4879    assert_instr(fcmeq)
4880)]
4881#[cfg_attr(
4882    not(target_arch = "arm"),
4883    stable(feature = "neon_intrinsics", since = "1.59.0")
4884)]
4885#[cfg_attr(
4886    target_arch = "arm",
4887    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4888)]
4889pub fn vceqq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
4890    unsafe { simd_eq(a, b) }
4891}
4892#[doc = "Compare bitwise Equal (vector)"]
4893#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s8)"]
4894#[inline]
4895#[target_feature(enable = "neon")]
4896#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4897#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
4898#[cfg_attr(
4899    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4900    assert_instr(cmeq)
4901)]
4902#[cfg_attr(
4903    not(target_arch = "arm"),
4904    stable(feature = "neon_intrinsics", since = "1.59.0")
4905)]
4906#[cfg_attr(
4907    target_arch = "arm",
4908    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4909)]
4910pub fn vceq_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
4911    unsafe { simd_eq(a, b) }
4912}
4913#[doc = "Compare bitwise Equal (vector)"]
4914#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s8)"]
4915#[inline]
4916#[target_feature(enable = "neon")]
4917#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4918#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
4919#[cfg_attr(
4920    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4921    assert_instr(cmeq)
4922)]
4923#[cfg_attr(
4924    not(target_arch = "arm"),
4925    stable(feature = "neon_intrinsics", since = "1.59.0")
4926)]
4927#[cfg_attr(
4928    target_arch = "arm",
4929    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4930)]
4931pub fn vceqq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
4932    unsafe { simd_eq(a, b) }
4933}
4934#[doc = "Compare bitwise Equal (vector)"]
4935#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s16)"]
4936#[inline]
4937#[target_feature(enable = "neon")]
4938#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4939#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
4940#[cfg_attr(
4941    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4942    assert_instr(cmeq)
4943)]
4944#[cfg_attr(
4945    not(target_arch = "arm"),
4946    stable(feature = "neon_intrinsics", since = "1.59.0")
4947)]
4948#[cfg_attr(
4949    target_arch = "arm",
4950    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4951)]
4952pub fn vceq_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
4953    unsafe { simd_eq(a, b) }
4954}
4955#[doc = "Compare bitwise Equal (vector)"]
4956#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s16)"]
4957#[inline]
4958#[target_feature(enable = "neon")]
4959#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4960#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
4961#[cfg_attr(
4962    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4963    assert_instr(cmeq)
4964)]
4965#[cfg_attr(
4966    not(target_arch = "arm"),
4967    stable(feature = "neon_intrinsics", since = "1.59.0")
4968)]
4969#[cfg_attr(
4970    target_arch = "arm",
4971    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4972)]
4973pub fn vceqq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
4974    unsafe { simd_eq(a, b) }
4975}
4976#[doc = "Compare bitwise Equal (vector)"]
4977#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s32)"]
4978#[inline]
4979#[target_feature(enable = "neon")]
4980#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4981#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
4982#[cfg_attr(
4983    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4984    assert_instr(cmeq)
4985)]
4986#[cfg_attr(
4987    not(target_arch = "arm"),
4988    stable(feature = "neon_intrinsics", since = "1.59.0")
4989)]
4990#[cfg_attr(
4991    target_arch = "arm",
4992    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4993)]
4994pub fn vceq_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
4995    unsafe { simd_eq(a, b) }
4996}
4997#[doc = "Compare bitwise Equal (vector)"]
4998#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s32)"]
4999#[inline]
5000#[target_feature(enable = "neon")]
5001#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5002#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
5003#[cfg_attr(
5004    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5005    assert_instr(cmeq)
5006)]
5007#[cfg_attr(
5008    not(target_arch = "arm"),
5009    stable(feature = "neon_intrinsics", since = "1.59.0")
5010)]
5011#[cfg_attr(
5012    target_arch = "arm",
5013    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5014)]
5015pub fn vceqq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
5016    unsafe { simd_eq(a, b) }
5017}
5018#[doc = "Compare bitwise Equal (vector)"]
5019#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u8)"]
5020#[inline]
5021#[target_feature(enable = "neon")]
5022#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5023#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
5024#[cfg_attr(
5025    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5026    assert_instr(cmeq)
5027)]
5028#[cfg_attr(
5029    not(target_arch = "arm"),
5030    stable(feature = "neon_intrinsics", since = "1.59.0")
5031)]
5032#[cfg_attr(
5033    target_arch = "arm",
5034    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5035)]
5036pub fn vceq_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
5037    unsafe { simd_eq(a, b) }
5038}
5039#[doc = "Compare bitwise Equal (vector)"]
5040#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u8)"]
5041#[inline]
5042#[target_feature(enable = "neon")]
5043#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5044#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
5045#[cfg_attr(
5046    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5047    assert_instr(cmeq)
5048)]
5049#[cfg_attr(
5050    not(target_arch = "arm"),
5051    stable(feature = "neon_intrinsics", since = "1.59.0")
5052)]
5053#[cfg_attr(
5054    target_arch = "arm",
5055    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5056)]
5057pub fn vceqq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
5058    unsafe { simd_eq(a, b) }
5059}
5060#[doc = "Compare bitwise Equal (vector)"]
5061#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u16)"]
5062#[inline]
5063#[target_feature(enable = "neon")]
5064#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5065#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
5066#[cfg_attr(
5067    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5068    assert_instr(cmeq)
5069)]
5070#[cfg_attr(
5071    not(target_arch = "arm"),
5072    stable(feature = "neon_intrinsics", since = "1.59.0")
5073)]
5074#[cfg_attr(
5075    target_arch = "arm",
5076    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5077)]
5078pub fn vceq_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
5079    unsafe { simd_eq(a, b) }
5080}
5081#[doc = "Compare bitwise Equal (vector)"]
5082#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u16)"]
5083#[inline]
5084#[target_feature(enable = "neon")]
5085#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5086#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
5087#[cfg_attr(
5088    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5089    assert_instr(cmeq)
5090)]
5091#[cfg_attr(
5092    not(target_arch = "arm"),
5093    stable(feature = "neon_intrinsics", since = "1.59.0")
5094)]
5095#[cfg_attr(
5096    target_arch = "arm",
5097    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5098)]
5099pub fn vceqq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
5100    unsafe { simd_eq(a, b) }
5101}
5102#[doc = "Compare bitwise Equal (vector)"]
5103#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u32)"]
5104#[inline]
5105#[target_feature(enable = "neon")]
5106#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5107#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
5108#[cfg_attr(
5109    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5110    assert_instr(cmeq)
5111)]
5112#[cfg_attr(
5113    not(target_arch = "arm"),
5114    stable(feature = "neon_intrinsics", since = "1.59.0")
5115)]
5116#[cfg_attr(
5117    target_arch = "arm",
5118    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5119)]
5120pub fn vceq_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
5121    unsafe { simd_eq(a, b) }
5122}
5123#[doc = "Compare bitwise Equal (vector)"]
5124#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u32)"]
5125#[inline]
5126#[target_feature(enable = "neon")]
5127#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5128#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
5129#[cfg_attr(
5130    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5131    assert_instr(cmeq)
5132)]
5133#[cfg_attr(
5134    not(target_arch = "arm"),
5135    stable(feature = "neon_intrinsics", since = "1.59.0")
5136)]
5137#[cfg_attr(
5138    target_arch = "arm",
5139    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5140)]
5141pub fn vceqq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
5142    unsafe { simd_eq(a, b) }
5143}
5144#[doc = "Compare bitwise Equal (vector)"]
5145#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p8)"]
5146#[inline]
5147#[target_feature(enable = "neon")]
5148#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5149#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
5150#[cfg_attr(
5151    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5152    assert_instr(cmeq)
5153)]
5154#[cfg_attr(
5155    not(target_arch = "arm"),
5156    stable(feature = "neon_intrinsics", since = "1.59.0")
5157)]
5158#[cfg_attr(
5159    target_arch = "arm",
5160    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5161)]
5162pub fn vceq_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t {
5163    unsafe { simd_eq(a, b) }
5164}
5165#[doc = "Compare bitwise Equal (vector)"]
5166#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p8)"]
5167#[inline]
5168#[target_feature(enable = "neon")]
5169#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5170#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
5171#[cfg_attr(
5172    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5173    assert_instr(cmeq)
5174)]
5175#[cfg_attr(
5176    not(target_arch = "arm"),
5177    stable(feature = "neon_intrinsics", since = "1.59.0")
5178)]
5179#[cfg_attr(
5180    target_arch = "arm",
5181    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5182)]
5183pub fn vceqq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t {
5184    unsafe { simd_eq(a, b) }
5185}
5186#[doc = "Floating-point compare greater than or equal"]
5187#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f16)"]
5188#[inline]
5189#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5190#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5191#[cfg_attr(
5192    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5193    assert_instr(fcmge)
5194)]
5195#[target_feature(enable = "neon,fp16")]
5196#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5197pub fn vcge_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
5198    unsafe { simd_ge(a, b) }
5199}
5200#[doc = "Floating-point compare greater than or equal"]
5201#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f16)"]
5202#[inline]
5203#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5204#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5205#[cfg_attr(
5206    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5207    assert_instr(fcmge)
5208)]
5209#[target_feature(enable = "neon,fp16")]
5210#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5211pub fn vcgeq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
5212    unsafe { simd_ge(a, b) }
5213}
5214#[doc = "Floating-point compare greater than or equal"]
5215#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f32)"]
5216#[inline]
5217#[target_feature(enable = "neon")]
5218#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5219#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
5220#[cfg_attr(
5221    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5222    assert_instr(fcmge)
5223)]
5224#[cfg_attr(
5225    not(target_arch = "arm"),
5226    stable(feature = "neon_intrinsics", since = "1.59.0")
5227)]
5228#[cfg_attr(
5229    target_arch = "arm",
5230    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5231)]
5232pub fn vcge_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
5233    unsafe { simd_ge(a, b) }
5234}
5235#[doc = "Floating-point compare greater than or equal"]
5236#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f32)"]
5237#[inline]
5238#[target_feature(enable = "neon")]
5239#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5240#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
5241#[cfg_attr(
5242    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5243    assert_instr(fcmge)
5244)]
5245#[cfg_attr(
5246    not(target_arch = "arm"),
5247    stable(feature = "neon_intrinsics", since = "1.59.0")
5248)]
5249#[cfg_attr(
5250    target_arch = "arm",
5251    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5252)]
5253pub fn vcgeq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
5254    unsafe { simd_ge(a, b) }
5255}
5256#[doc = "Compare signed greater than or equal"]
5257#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s8)"]
5258#[inline]
5259#[target_feature(enable = "neon")]
5260#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5261#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
5262#[cfg_attr(
5263    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5264    assert_instr(cmge)
5265)]
5266#[cfg_attr(
5267    not(target_arch = "arm"),
5268    stable(feature = "neon_intrinsics", since = "1.59.0")
5269)]
5270#[cfg_attr(
5271    target_arch = "arm",
5272    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5273)]
5274pub fn vcge_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
5275    unsafe { simd_ge(a, b) }
5276}
5277#[doc = "Compare signed greater than or equal"]
5278#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s8)"]
5279#[inline]
5280#[target_feature(enable = "neon")]
5281#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5282#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
5283#[cfg_attr(
5284    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5285    assert_instr(cmge)
5286)]
5287#[cfg_attr(
5288    not(target_arch = "arm"),
5289    stable(feature = "neon_intrinsics", since = "1.59.0")
5290)]
5291#[cfg_attr(
5292    target_arch = "arm",
5293    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5294)]
5295pub fn vcgeq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
5296    unsafe { simd_ge(a, b) }
5297}
5298#[doc = "Compare signed greater than or equal"]
5299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s16)"]
5300#[inline]
5301#[target_feature(enable = "neon")]
5302#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5303#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
5304#[cfg_attr(
5305    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5306    assert_instr(cmge)
5307)]
5308#[cfg_attr(
5309    not(target_arch = "arm"),
5310    stable(feature = "neon_intrinsics", since = "1.59.0")
5311)]
5312#[cfg_attr(
5313    target_arch = "arm",
5314    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5315)]
5316pub fn vcge_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
5317    unsafe { simd_ge(a, b) }
5318}
5319#[doc = "Compare signed greater than or equal"]
5320#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s16)"]
5321#[inline]
5322#[target_feature(enable = "neon")]
5323#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5324#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
5325#[cfg_attr(
5326    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5327    assert_instr(cmge)
5328)]
5329#[cfg_attr(
5330    not(target_arch = "arm"),
5331    stable(feature = "neon_intrinsics", since = "1.59.0")
5332)]
5333#[cfg_attr(
5334    target_arch = "arm",
5335    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5336)]
5337pub fn vcgeq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
5338    unsafe { simd_ge(a, b) }
5339}
5340#[doc = "Compare signed greater than or equal"]
5341#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s32)"]
5342#[inline]
5343#[target_feature(enable = "neon")]
5344#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5345#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
5346#[cfg_attr(
5347    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5348    assert_instr(cmge)
5349)]
5350#[cfg_attr(
5351    not(target_arch = "arm"),
5352    stable(feature = "neon_intrinsics", since = "1.59.0")
5353)]
5354#[cfg_attr(
5355    target_arch = "arm",
5356    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5357)]
5358pub fn vcge_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
5359    unsafe { simd_ge(a, b) }
5360}
5361#[doc = "Compare signed greater than or equal"]
5362#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s32)"]
5363#[inline]
5364#[target_feature(enable = "neon")]
5365#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5366#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
5367#[cfg_attr(
5368    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5369    assert_instr(cmge)
5370)]
5371#[cfg_attr(
5372    not(target_arch = "arm"),
5373    stable(feature = "neon_intrinsics", since = "1.59.0")
5374)]
5375#[cfg_attr(
5376    target_arch = "arm",
5377    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5378)]
5379pub fn vcgeq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
5380    unsafe { simd_ge(a, b) }
5381}
5382#[doc = "Compare unsigned greater than or equal"]
5383#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u8)"]
5384#[inline]
5385#[target_feature(enable = "neon")]
5386#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5387#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
5388#[cfg_attr(
5389    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5390    assert_instr(cmhs)
5391)]
5392#[cfg_attr(
5393    not(target_arch = "arm"),
5394    stable(feature = "neon_intrinsics", since = "1.59.0")
5395)]
5396#[cfg_attr(
5397    target_arch = "arm",
5398    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5399)]
5400pub fn vcge_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
5401    unsafe { simd_ge(a, b) }
5402}
5403#[doc = "Compare unsigned greater than or equal"]
5404#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u8)"]
5405#[inline]
5406#[target_feature(enable = "neon")]
5407#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5408#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
5409#[cfg_attr(
5410    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5411    assert_instr(cmhs)
5412)]
5413#[cfg_attr(
5414    not(target_arch = "arm"),
5415    stable(feature = "neon_intrinsics", since = "1.59.0")
5416)]
5417#[cfg_attr(
5418    target_arch = "arm",
5419    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5420)]
5421pub fn vcgeq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
5422    unsafe { simd_ge(a, b) }
5423}
5424#[doc = "Compare unsigned greater than or equal"]
5425#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u16)"]
5426#[inline]
5427#[target_feature(enable = "neon")]
5428#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5429#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
5430#[cfg_attr(
5431    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5432    assert_instr(cmhs)
5433)]
5434#[cfg_attr(
5435    not(target_arch = "arm"),
5436    stable(feature = "neon_intrinsics", since = "1.59.0")
5437)]
5438#[cfg_attr(
5439    target_arch = "arm",
5440    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5441)]
5442pub fn vcge_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
5443    unsafe { simd_ge(a, b) }
5444}
5445#[doc = "Compare unsigned greater than or equal"]
5446#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u16)"]
5447#[inline]
5448#[target_feature(enable = "neon")]
5449#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5450#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
5451#[cfg_attr(
5452    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5453    assert_instr(cmhs)
5454)]
5455#[cfg_attr(
5456    not(target_arch = "arm"),
5457    stable(feature = "neon_intrinsics", since = "1.59.0")
5458)]
5459#[cfg_attr(
5460    target_arch = "arm",
5461    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5462)]
5463pub fn vcgeq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
5464    unsafe { simd_ge(a, b) }
5465}
5466#[doc = "Compare unsigned greater than or equal"]
5467#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u32)"]
5468#[inline]
5469#[target_feature(enable = "neon")]
5470#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5471#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
5472#[cfg_attr(
5473    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5474    assert_instr(cmhs)
5475)]
5476#[cfg_attr(
5477    not(target_arch = "arm"),
5478    stable(feature = "neon_intrinsics", since = "1.59.0")
5479)]
5480#[cfg_attr(
5481    target_arch = "arm",
5482    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5483)]
5484pub fn vcge_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
5485    unsafe { simd_ge(a, b) }
5486}
5487#[doc = "Compare unsigned greater than or equal"]
5488#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u32)"]
5489#[inline]
5490#[target_feature(enable = "neon")]
5491#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5492#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
5493#[cfg_attr(
5494    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5495    assert_instr(cmhs)
5496)]
5497#[cfg_attr(
5498    not(target_arch = "arm"),
5499    stable(feature = "neon_intrinsics", since = "1.59.0")
5500)]
5501#[cfg_attr(
5502    target_arch = "arm",
5503    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5504)]
5505pub fn vcgeq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
5506    unsafe { simd_ge(a, b) }
5507}
5508#[doc = "Floating-point compare greater than or equal to zero"]
5509#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f16)"]
5510#[inline]
5511#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5512#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5513#[cfg_attr(
5514    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5515    assert_instr(fcmge)
5516)]
5517#[target_feature(enable = "neon,fp16")]
5518#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5519pub fn vcgez_f16(a: float16x4_t) -> uint16x4_t {
5520    let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
5521    unsafe { simd_ge(a, transmute(b)) }
5522}
5523#[doc = "Floating-point compare greater than or equal to zero"]
5524#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f16)"]
5525#[inline]
5526#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5527#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5528#[cfg_attr(
5529    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5530    assert_instr(fcmge)
5531)]
5532#[target_feature(enable = "neon,fp16")]
5533#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5534pub fn vcgezq_f16(a: float16x8_t) -> uint16x8_t {
5535    let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
5536    unsafe { simd_ge(a, transmute(b)) }
5537}
5538#[doc = "Floating-point compare greater than"]
5539#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f16)"]
5540#[inline]
5541#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5542#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
5543#[cfg_attr(
5544    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5545    assert_instr(fcmgt)
5546)]
5547#[target_feature(enable = "neon,fp16")]
5548#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5549pub fn vcgt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
5550    unsafe { simd_gt(a, b) }
5551}
5552#[doc = "Floating-point compare greater than"]
5553#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f16)"]
5554#[inline]
5555#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5556#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
5557#[cfg_attr(
5558    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5559    assert_instr(fcmgt)
5560)]
5561#[target_feature(enable = "neon,fp16")]
5562#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5563pub fn vcgtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
5564    unsafe { simd_gt(a, b) }
5565}
5566#[doc = "Floating-point compare greater than"]
5567#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f32)"]
5568#[inline]
5569#[target_feature(enable = "neon")]
5570#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5571#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
5572#[cfg_attr(
5573    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5574    assert_instr(fcmgt)
5575)]
5576#[cfg_attr(
5577    not(target_arch = "arm"),
5578    stable(feature = "neon_intrinsics", since = "1.59.0")
5579)]
5580#[cfg_attr(
5581    target_arch = "arm",
5582    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5583)]
5584pub fn vcgt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
5585    unsafe { simd_gt(a, b) }
5586}
5587#[doc = "Floating-point compare greater than"]
5588#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f32)"]
5589#[inline]
5590#[target_feature(enable = "neon")]
5591#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5592#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
5593#[cfg_attr(
5594    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5595    assert_instr(fcmgt)
5596)]
5597#[cfg_attr(
5598    not(target_arch = "arm"),
5599    stable(feature = "neon_intrinsics", since = "1.59.0")
5600)]
5601#[cfg_attr(
5602    target_arch = "arm",
5603    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5604)]
5605pub fn vcgtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
5606    unsafe { simd_gt(a, b) }
5607}
5608#[doc = "Compare signed greater than"]
5609#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s8)"]
5610#[inline]
5611#[target_feature(enable = "neon")]
5612#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5613#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
5614#[cfg_attr(
5615    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5616    assert_instr(cmgt)
5617)]
5618#[cfg_attr(
5619    not(target_arch = "arm"),
5620    stable(feature = "neon_intrinsics", since = "1.59.0")
5621)]
5622#[cfg_attr(
5623    target_arch = "arm",
5624    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5625)]
5626pub fn vcgt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
5627    unsafe { simd_gt(a, b) }
5628}
5629#[doc = "Compare signed greater than"]
5630#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s8)"]
5631#[inline]
5632#[target_feature(enable = "neon")]
5633#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5634#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
5635#[cfg_attr(
5636    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5637    assert_instr(cmgt)
5638)]
5639#[cfg_attr(
5640    not(target_arch = "arm"),
5641    stable(feature = "neon_intrinsics", since = "1.59.0")
5642)]
5643#[cfg_attr(
5644    target_arch = "arm",
5645    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5646)]
5647pub fn vcgtq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
5648    unsafe { simd_gt(a, b) }
5649}
5650#[doc = "Compare signed greater than"]
5651#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s16)"]
5652#[inline]
5653#[target_feature(enable = "neon")]
5654#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5655#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
5656#[cfg_attr(
5657    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5658    assert_instr(cmgt)
5659)]
5660#[cfg_attr(
5661    not(target_arch = "arm"),
5662    stable(feature = "neon_intrinsics", since = "1.59.0")
5663)]
5664#[cfg_attr(
5665    target_arch = "arm",
5666    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5667)]
5668pub fn vcgt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
5669    unsafe { simd_gt(a, b) }
5670}
5671#[doc = "Compare signed greater than"]
5672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s16)"]
5673#[inline]
5674#[target_feature(enable = "neon")]
5675#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5676#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
5677#[cfg_attr(
5678    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5679    assert_instr(cmgt)
5680)]
5681#[cfg_attr(
5682    not(target_arch = "arm"),
5683    stable(feature = "neon_intrinsics", since = "1.59.0")
5684)]
5685#[cfg_attr(
5686    target_arch = "arm",
5687    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5688)]
5689pub fn vcgtq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
5690    unsafe { simd_gt(a, b) }
5691}
5692#[doc = "Compare signed greater than"]
5693#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s32)"]
5694#[inline]
5695#[target_feature(enable = "neon")]
5696#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5697#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
5698#[cfg_attr(
5699    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5700    assert_instr(cmgt)
5701)]
5702#[cfg_attr(
5703    not(target_arch = "arm"),
5704    stable(feature = "neon_intrinsics", since = "1.59.0")
5705)]
5706#[cfg_attr(
5707    target_arch = "arm",
5708    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5709)]
5710pub fn vcgt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
5711    unsafe { simd_gt(a, b) }
5712}
5713#[doc = "Compare signed greater than"]
5714#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s32)"]
5715#[inline]
5716#[target_feature(enable = "neon")]
5717#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5718#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
5719#[cfg_attr(
5720    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5721    assert_instr(cmgt)
5722)]
5723#[cfg_attr(
5724    not(target_arch = "arm"),
5725    stable(feature = "neon_intrinsics", since = "1.59.0")
5726)]
5727#[cfg_attr(
5728    target_arch = "arm",
5729    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5730)]
5731pub fn vcgtq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
5732    unsafe { simd_gt(a, b) }
5733}
5734#[doc = "Compare unsigned greater than"]
5735#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u8)"]
5736#[inline]
5737#[target_feature(enable = "neon")]
5738#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5739#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
5740#[cfg_attr(
5741    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5742    assert_instr(cmhi)
5743)]
5744#[cfg_attr(
5745    not(target_arch = "arm"),
5746    stable(feature = "neon_intrinsics", since = "1.59.0")
5747)]
5748#[cfg_attr(
5749    target_arch = "arm",
5750    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5751)]
5752pub fn vcgt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
5753    unsafe { simd_gt(a, b) }
5754}
5755#[doc = "Compare unsigned greater than"]
5756#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u8)"]
5757#[inline]
5758#[target_feature(enable = "neon")]
5759#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5760#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
5761#[cfg_attr(
5762    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5763    assert_instr(cmhi)
5764)]
5765#[cfg_attr(
5766    not(target_arch = "arm"),
5767    stable(feature = "neon_intrinsics", since = "1.59.0")
5768)]
5769#[cfg_attr(
5770    target_arch = "arm",
5771    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5772)]
5773pub fn vcgtq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
5774    unsafe { simd_gt(a, b) }
5775}
5776#[doc = "Compare unsigned greater than"]
5777#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u16)"]
5778#[inline]
5779#[target_feature(enable = "neon")]
5780#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5781#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
5782#[cfg_attr(
5783    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5784    assert_instr(cmhi)
5785)]
5786#[cfg_attr(
5787    not(target_arch = "arm"),
5788    stable(feature = "neon_intrinsics", since = "1.59.0")
5789)]
5790#[cfg_attr(
5791    target_arch = "arm",
5792    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5793)]
5794pub fn vcgt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
5795    unsafe { simd_gt(a, b) }
5796}
5797#[doc = "Compare unsigned greater than"]
5798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u16)"]
5799#[inline]
5800#[target_feature(enable = "neon")]
5801#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5802#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
5803#[cfg_attr(
5804    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5805    assert_instr(cmhi)
5806)]
5807#[cfg_attr(
5808    not(target_arch = "arm"),
5809    stable(feature = "neon_intrinsics", since = "1.59.0")
5810)]
5811#[cfg_attr(
5812    target_arch = "arm",
5813    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5814)]
5815pub fn vcgtq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
5816    unsafe { simd_gt(a, b) }
5817}
5818#[doc = "Compare unsigned greater than"]
5819#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u32)"]
5820#[inline]
5821#[target_feature(enable = "neon")]
5822#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5823#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
5824#[cfg_attr(
5825    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5826    assert_instr(cmhi)
5827)]
5828#[cfg_attr(
5829    not(target_arch = "arm"),
5830    stable(feature = "neon_intrinsics", since = "1.59.0")
5831)]
5832#[cfg_attr(
5833    target_arch = "arm",
5834    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5835)]
5836pub fn vcgt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
5837    unsafe { simd_gt(a, b) }
5838}
5839#[doc = "Compare unsigned greater than"]
5840#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u32)"]
5841#[inline]
5842#[target_feature(enable = "neon")]
5843#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5844#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
5845#[cfg_attr(
5846    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5847    assert_instr(cmhi)
5848)]
5849#[cfg_attr(
5850    not(target_arch = "arm"),
5851    stable(feature = "neon_intrinsics", since = "1.59.0")
5852)]
5853#[cfg_attr(
5854    target_arch = "arm",
5855    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5856)]
5857pub fn vcgtq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
5858    unsafe { simd_gt(a, b) }
5859}
5860#[doc = "Floating-point compare greater than zero"]
5861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f16)"]
5862#[inline]
5863#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5864#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
5865#[cfg_attr(
5866    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5867    assert_instr(fcmgt)
5868)]
5869#[target_feature(enable = "neon,fp16")]
5870#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5871pub fn vcgtz_f16(a: float16x4_t) -> uint16x4_t {
5872    let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
5873    unsafe { simd_gt(a, transmute(b)) }
5874}
5875#[doc = "Floating-point compare greater than zero"]
5876#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f16)"]
5877#[inline]
5878#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5879#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
5880#[cfg_attr(
5881    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5882    assert_instr(fcmgt)
5883)]
5884#[target_feature(enable = "neon,fp16")]
5885#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5886pub fn vcgtzq_f16(a: float16x8_t) -> uint16x8_t {
5887    let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
5888    unsafe { simd_gt(a, transmute(b)) }
5889}
5890#[doc = "Floating-point compare less than or equal"]
5891#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f16)"]
5892#[inline]
5893#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5894#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5895#[cfg_attr(
5896    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5897    assert_instr(fcmge)
5898)]
5899#[target_feature(enable = "neon,fp16")]
5900#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5901pub fn vcle_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
5902    unsafe { simd_le(a, b) }
5903}
5904#[doc = "Floating-point compare less than or equal"]
5905#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f16)"]
5906#[inline]
5907#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5908#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5909#[cfg_attr(
5910    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5911    assert_instr(fcmge)
5912)]
5913#[target_feature(enable = "neon,fp16")]
5914#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5915pub fn vcleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
5916    unsafe { simd_le(a, b) }
5917}
5918#[doc = "Floating-point compare less than or equal"]
5919#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f32)"]
5920#[inline]
5921#[target_feature(enable = "neon")]
5922#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5923#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
5924#[cfg_attr(
5925    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5926    assert_instr(fcmge)
5927)]
5928#[cfg_attr(
5929    not(target_arch = "arm"),
5930    stable(feature = "neon_intrinsics", since = "1.59.0")
5931)]
5932#[cfg_attr(
5933    target_arch = "arm",
5934    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5935)]
5936pub fn vcle_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
5937    unsafe { simd_le(a, b) }
5938}
5939#[doc = "Floating-point compare less than or equal"]
5940#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f32)"]
5941#[inline]
5942#[target_feature(enable = "neon")]
5943#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5944#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
5945#[cfg_attr(
5946    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5947    assert_instr(fcmge)
5948)]
5949#[cfg_attr(
5950    not(target_arch = "arm"),
5951    stable(feature = "neon_intrinsics", since = "1.59.0")
5952)]
5953#[cfg_attr(
5954    target_arch = "arm",
5955    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5956)]
5957pub fn vcleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
5958    unsafe { simd_le(a, b) }
5959}
5960#[doc = "Compare signed less than or equal"]
5961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s8)"]
5962#[inline]
5963#[target_feature(enable = "neon")]
5964#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5965#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
5966#[cfg_attr(
5967    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5968    assert_instr(cmge)
5969)]
5970#[cfg_attr(
5971    not(target_arch = "arm"),
5972    stable(feature = "neon_intrinsics", since = "1.59.0")
5973)]
5974#[cfg_attr(
5975    target_arch = "arm",
5976    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5977)]
5978pub fn vcle_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
5979    unsafe { simd_le(a, b) }
5980}
5981#[doc = "Compare signed less than or equal"]
5982#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s8)"]
5983#[inline]
5984#[target_feature(enable = "neon")]
5985#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5986#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
5987#[cfg_attr(
5988    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5989    assert_instr(cmge)
5990)]
5991#[cfg_attr(
5992    not(target_arch = "arm"),
5993    stable(feature = "neon_intrinsics", since = "1.59.0")
5994)]
5995#[cfg_attr(
5996    target_arch = "arm",
5997    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5998)]
5999pub fn vcleq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
6000    unsafe { simd_le(a, b) }
6001}
6002#[doc = "Compare signed less than or equal"]
6003#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s16)"]
6004#[inline]
6005#[target_feature(enable = "neon")]
6006#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6007#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
6008#[cfg_attr(
6009    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6010    assert_instr(cmge)
6011)]
6012#[cfg_attr(
6013    not(target_arch = "arm"),
6014    stable(feature = "neon_intrinsics", since = "1.59.0")
6015)]
6016#[cfg_attr(
6017    target_arch = "arm",
6018    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6019)]
6020pub fn vcle_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
6021    unsafe { simd_le(a, b) }
6022}
6023#[doc = "Compare signed less than or equal"]
6024#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s16)"]
6025#[inline]
6026#[target_feature(enable = "neon")]
6027#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6028#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
6029#[cfg_attr(
6030    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6031    assert_instr(cmge)
6032)]
6033#[cfg_attr(
6034    not(target_arch = "arm"),
6035    stable(feature = "neon_intrinsics", since = "1.59.0")
6036)]
6037#[cfg_attr(
6038    target_arch = "arm",
6039    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6040)]
6041pub fn vcleq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
6042    unsafe { simd_le(a, b) }
6043}
6044#[doc = "Compare signed less than or equal"]
6045#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s32)"]
6046#[inline]
6047#[target_feature(enable = "neon")]
6048#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6049#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
6050#[cfg_attr(
6051    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6052    assert_instr(cmge)
6053)]
6054#[cfg_attr(
6055    not(target_arch = "arm"),
6056    stable(feature = "neon_intrinsics", since = "1.59.0")
6057)]
6058#[cfg_attr(
6059    target_arch = "arm",
6060    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6061)]
6062pub fn vcle_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
6063    unsafe { simd_le(a, b) }
6064}
6065#[doc = "Compare signed less than or equal"]
6066#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s32)"]
6067#[inline]
6068#[target_feature(enable = "neon")]
6069#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6070#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
6071#[cfg_attr(
6072    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6073    assert_instr(cmge)
6074)]
6075#[cfg_attr(
6076    not(target_arch = "arm"),
6077    stable(feature = "neon_intrinsics", since = "1.59.0")
6078)]
6079#[cfg_attr(
6080    target_arch = "arm",
6081    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6082)]
6083pub fn vcleq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
6084    unsafe { simd_le(a, b) }
6085}
6086#[doc = "Compare unsigned less than or equal"]
6087#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u8)"]
6088#[inline]
6089#[target_feature(enable = "neon")]
6090#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6091#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
6092#[cfg_attr(
6093    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6094    assert_instr(cmhs)
6095)]
6096#[cfg_attr(
6097    not(target_arch = "arm"),
6098    stable(feature = "neon_intrinsics", since = "1.59.0")
6099)]
6100#[cfg_attr(
6101    target_arch = "arm",
6102    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6103)]
6104pub fn vcle_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
6105    unsafe { simd_le(a, b) }
6106}
6107#[doc = "Compare unsigned less than or equal"]
6108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u8)"]
6109#[inline]
6110#[target_feature(enable = "neon")]
6111#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6112#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
6113#[cfg_attr(
6114    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6115    assert_instr(cmhs)
6116)]
6117#[cfg_attr(
6118    not(target_arch = "arm"),
6119    stable(feature = "neon_intrinsics", since = "1.59.0")
6120)]
6121#[cfg_attr(
6122    target_arch = "arm",
6123    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6124)]
6125pub fn vcleq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
6126    unsafe { simd_le(a, b) }
6127}
6128#[doc = "Compare unsigned less than or equal"]
6129#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u16)"]
6130#[inline]
6131#[target_feature(enable = "neon")]
6132#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6133#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
6134#[cfg_attr(
6135    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6136    assert_instr(cmhs)
6137)]
6138#[cfg_attr(
6139    not(target_arch = "arm"),
6140    stable(feature = "neon_intrinsics", since = "1.59.0")
6141)]
6142#[cfg_attr(
6143    target_arch = "arm",
6144    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6145)]
6146pub fn vcle_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
6147    unsafe { simd_le(a, b) }
6148}
6149#[doc = "Compare unsigned less than or equal"]
6150#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u16)"]
6151#[inline]
6152#[target_feature(enable = "neon")]
6153#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6154#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
6155#[cfg_attr(
6156    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6157    assert_instr(cmhs)
6158)]
6159#[cfg_attr(
6160    not(target_arch = "arm"),
6161    stable(feature = "neon_intrinsics", since = "1.59.0")
6162)]
6163#[cfg_attr(
6164    target_arch = "arm",
6165    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6166)]
6167pub fn vcleq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
6168    unsafe { simd_le(a, b) }
6169}
6170#[doc = "Compare unsigned less than or equal"]
6171#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u32)"]
6172#[inline]
6173#[target_feature(enable = "neon")]
6174#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6175#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
6176#[cfg_attr(
6177    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6178    assert_instr(cmhs)
6179)]
6180#[cfg_attr(
6181    not(target_arch = "arm"),
6182    stable(feature = "neon_intrinsics", since = "1.59.0")
6183)]
6184#[cfg_attr(
6185    target_arch = "arm",
6186    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6187)]
6188pub fn vcle_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
6189    unsafe { simd_le(a, b) }
6190}
6191#[doc = "Compare unsigned less than or equal"]
6192#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u32)"]
6193#[inline]
6194#[target_feature(enable = "neon")]
6195#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6196#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
6197#[cfg_attr(
6198    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6199    assert_instr(cmhs)
6200)]
6201#[cfg_attr(
6202    not(target_arch = "arm"),
6203    stable(feature = "neon_intrinsics", since = "1.59.0")
6204)]
6205#[cfg_attr(
6206    target_arch = "arm",
6207    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6208)]
6209pub fn vcleq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
6210    unsafe { simd_le(a, b) }
6211}
6212#[doc = "Floating-point compare less than or equal to zero"]
6213#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f16)"]
6214#[inline]
6215#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6216#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcle.f16"))]
6217#[cfg_attr(
6218    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6219    assert_instr(fcmle)
6220)]
6221#[target_feature(enable = "neon,fp16")]
6222#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6223pub fn vclez_f16(a: float16x4_t) -> uint16x4_t {
6224    let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
6225    unsafe { simd_le(a, transmute(b)) }
6226}
6227#[doc = "Floating-point compare less than or equal to zero"]
6228#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f16)"]
6229#[inline]
6230#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6231#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcle.f16"))]
6232#[cfg_attr(
6233    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6234    assert_instr(fcmle)
6235)]
6236#[target_feature(enable = "neon,fp16")]
6237#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6238pub fn vclezq_f16(a: float16x8_t) -> uint16x8_t {
6239    let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
6240    unsafe { simd_le(a, transmute(b)) }
6241}
6242#[doc = "Count leading sign bits"]
6243#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s8)"]
6244#[inline]
6245#[target_feature(enable = "neon")]
6246#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6247#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))]
6248#[cfg_attr(
6249    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6250    assert_instr(cls)
6251)]
6252#[cfg_attr(
6253    not(target_arch = "arm"),
6254    stable(feature = "neon_intrinsics", since = "1.59.0")
6255)]
6256#[cfg_attr(
6257    target_arch = "arm",
6258    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6259)]
6260pub fn vcls_s8(a: int8x8_t) -> int8x8_t {
6261    unsafe extern "unadjusted" {
6262        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v8i8")]
6263        #[cfg_attr(
6264            any(target_arch = "aarch64", target_arch = "arm64ec"),
6265            link_name = "llvm.aarch64.neon.cls.v8i8"
6266        )]
6267        fn _vcls_s8(a: int8x8_t) -> int8x8_t;
6268    }
6269    unsafe { _vcls_s8(a) }
6270}
6271#[doc = "Count leading sign bits"]
6272#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s8)"]
6273#[inline]
6274#[target_feature(enable = "neon")]
6275#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6276#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))]
6277#[cfg_attr(
6278    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6279    assert_instr(cls)
6280)]
6281#[cfg_attr(
6282    not(target_arch = "arm"),
6283    stable(feature = "neon_intrinsics", since = "1.59.0")
6284)]
6285#[cfg_attr(
6286    target_arch = "arm",
6287    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6288)]
6289pub fn vclsq_s8(a: int8x16_t) -> int8x16_t {
6290    unsafe extern "unadjusted" {
6291        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v16i8")]
6292        #[cfg_attr(
6293            any(target_arch = "aarch64", target_arch = "arm64ec"),
6294            link_name = "llvm.aarch64.neon.cls.v16i8"
6295        )]
6296        fn _vclsq_s8(a: int8x16_t) -> int8x16_t;
6297    }
6298    unsafe { _vclsq_s8(a) }
6299}
6300#[doc = "Count leading sign bits"]
6301#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s16)"]
6302#[inline]
6303#[target_feature(enable = "neon")]
6304#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6305#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))]
6306#[cfg_attr(
6307    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6308    assert_instr(cls)
6309)]
6310#[cfg_attr(
6311    not(target_arch = "arm"),
6312    stable(feature = "neon_intrinsics", since = "1.59.0")
6313)]
6314#[cfg_attr(
6315    target_arch = "arm",
6316    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6317)]
6318pub fn vcls_s16(a: int16x4_t) -> int16x4_t {
6319    unsafe extern "unadjusted" {
6320        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v4i16")]
6321        #[cfg_attr(
6322            any(target_arch = "aarch64", target_arch = "arm64ec"),
6323            link_name = "llvm.aarch64.neon.cls.v4i16"
6324        )]
6325        fn _vcls_s16(a: int16x4_t) -> int16x4_t;
6326    }
6327    unsafe { _vcls_s16(a) }
6328}
6329#[doc = "Count leading sign bits"]
6330#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s16)"]
6331#[inline]
6332#[target_feature(enable = "neon")]
6333#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6334#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))]
6335#[cfg_attr(
6336    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6337    assert_instr(cls)
6338)]
6339#[cfg_attr(
6340    not(target_arch = "arm"),
6341    stable(feature = "neon_intrinsics", since = "1.59.0")
6342)]
6343#[cfg_attr(
6344    target_arch = "arm",
6345    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6346)]
6347pub fn vclsq_s16(a: int16x8_t) -> int16x8_t {
6348    unsafe extern "unadjusted" {
6349        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v8i16")]
6350        #[cfg_attr(
6351            any(target_arch = "aarch64", target_arch = "arm64ec"),
6352            link_name = "llvm.aarch64.neon.cls.v8i16"
6353        )]
6354        fn _vclsq_s16(a: int16x8_t) -> int16x8_t;
6355    }
6356    unsafe { _vclsq_s16(a) }
6357}
6358#[doc = "Count leading sign bits"]
6359#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s32)"]
6360#[inline]
6361#[target_feature(enable = "neon")]
6362#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6363#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))]
6364#[cfg_attr(
6365    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6366    assert_instr(cls)
6367)]
6368#[cfg_attr(
6369    not(target_arch = "arm"),
6370    stable(feature = "neon_intrinsics", since = "1.59.0")
6371)]
6372#[cfg_attr(
6373    target_arch = "arm",
6374    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6375)]
6376pub fn vcls_s32(a: int32x2_t) -> int32x2_t {
6377    unsafe extern "unadjusted" {
6378        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v2i32")]
6379        #[cfg_attr(
6380            any(target_arch = "aarch64", target_arch = "arm64ec"),
6381            link_name = "llvm.aarch64.neon.cls.v2i32"
6382        )]
6383        fn _vcls_s32(a: int32x2_t) -> int32x2_t;
6384    }
6385    unsafe { _vcls_s32(a) }
6386}
6387#[doc = "Count leading sign bits"]
6388#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s32)"]
6389#[inline]
6390#[target_feature(enable = "neon")]
6391#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6392#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))]
6393#[cfg_attr(
6394    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6395    assert_instr(cls)
6396)]
6397#[cfg_attr(
6398    not(target_arch = "arm"),
6399    stable(feature = "neon_intrinsics", since = "1.59.0")
6400)]
6401#[cfg_attr(
6402    target_arch = "arm",
6403    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6404)]
6405pub fn vclsq_s32(a: int32x4_t) -> int32x4_t {
6406    unsafe extern "unadjusted" {
6407        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v4i32")]
6408        #[cfg_attr(
6409            any(target_arch = "aarch64", target_arch = "arm64ec"),
6410            link_name = "llvm.aarch64.neon.cls.v4i32"
6411        )]
6412        fn _vclsq_s32(a: int32x4_t) -> int32x4_t;
6413    }
6414    unsafe { _vclsq_s32(a) }
6415}
6416#[doc = "Count leading sign bits"]
6417#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u8)"]
6418#[inline]
6419#[target_feature(enable = "neon")]
6420#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6421#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6422#[cfg_attr(
6423    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6424    assert_instr(cls)
6425)]
6426#[cfg_attr(
6427    not(target_arch = "arm"),
6428    stable(feature = "neon_intrinsics", since = "1.59.0")
6429)]
6430#[cfg_attr(
6431    target_arch = "arm",
6432    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6433)]
6434pub fn vcls_u8(a: uint8x8_t) -> int8x8_t {
6435    unsafe { vcls_s8(transmute(a)) }
6436}
6437#[doc = "Count leading sign bits"]
6438#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u8)"]
6439#[inline]
6440#[target_feature(enable = "neon")]
6441#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6442#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6443#[cfg_attr(
6444    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6445    assert_instr(cls)
6446)]
6447#[cfg_attr(
6448    not(target_arch = "arm"),
6449    stable(feature = "neon_intrinsics", since = "1.59.0")
6450)]
6451#[cfg_attr(
6452    target_arch = "arm",
6453    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6454)]
6455pub fn vclsq_u8(a: uint8x16_t) -> int8x16_t {
6456    unsafe { vclsq_s8(transmute(a)) }
6457}
6458#[doc = "Count leading sign bits"]
6459#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u16)"]
6460#[inline]
6461#[target_feature(enable = "neon")]
6462#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6463#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6464#[cfg_attr(
6465    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6466    assert_instr(cls)
6467)]
6468#[cfg_attr(
6469    not(target_arch = "arm"),
6470    stable(feature = "neon_intrinsics", since = "1.59.0")
6471)]
6472#[cfg_attr(
6473    target_arch = "arm",
6474    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6475)]
6476pub fn vcls_u16(a: uint16x4_t) -> int16x4_t {
6477    unsafe { vcls_s16(transmute(a)) }
6478}
6479#[doc = "Count leading sign bits"]
6480#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u16)"]
6481#[inline]
6482#[target_feature(enable = "neon")]
6483#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6484#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6485#[cfg_attr(
6486    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6487    assert_instr(cls)
6488)]
6489#[cfg_attr(
6490    not(target_arch = "arm"),
6491    stable(feature = "neon_intrinsics", since = "1.59.0")
6492)]
6493#[cfg_attr(
6494    target_arch = "arm",
6495    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6496)]
6497pub fn vclsq_u16(a: uint16x8_t) -> int16x8_t {
6498    unsafe { vclsq_s16(transmute(a)) }
6499}
6500#[doc = "Count leading sign bits"]
6501#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u32)"]
6502#[inline]
6503#[target_feature(enable = "neon")]
6504#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6505#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6506#[cfg_attr(
6507    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6508    assert_instr(cls)
6509)]
6510#[cfg_attr(
6511    not(target_arch = "arm"),
6512    stable(feature = "neon_intrinsics", since = "1.59.0")
6513)]
6514#[cfg_attr(
6515    target_arch = "arm",
6516    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6517)]
6518pub fn vcls_u32(a: uint32x2_t) -> int32x2_t {
6519    unsafe { vcls_s32(transmute(a)) }
6520}
6521#[doc = "Count leading sign bits"]
6522#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u32)"]
6523#[inline]
6524#[target_feature(enable = "neon")]
6525#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6526#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6527#[cfg_attr(
6528    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6529    assert_instr(cls)
6530)]
6531#[cfg_attr(
6532    not(target_arch = "arm"),
6533    stable(feature = "neon_intrinsics", since = "1.59.0")
6534)]
6535#[cfg_attr(
6536    target_arch = "arm",
6537    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6538)]
6539pub fn vclsq_u32(a: uint32x4_t) -> int32x4_t {
6540    unsafe { vclsq_s32(transmute(a)) }
6541}
6542#[doc = "Floating-point compare less than"]
6543#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f16)"]
6544#[inline]
6545#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6546#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
6547#[cfg_attr(
6548    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6549    assert_instr(fcmgt)
6550)]
6551#[target_feature(enable = "neon,fp16")]
6552#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6553pub fn vclt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
6554    unsafe { simd_lt(a, b) }
6555}
6556#[doc = "Floating-point compare less than"]
6557#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f16)"]
6558#[inline]
6559#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6560#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
6561#[cfg_attr(
6562    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6563    assert_instr(fcmgt)
6564)]
6565#[target_feature(enable = "neon,fp16")]
6566#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6567pub fn vcltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
6568    unsafe { simd_lt(a, b) }
6569}
6570#[doc = "Floating-point compare less than"]
6571#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f32)"]
6572#[inline]
6573#[target_feature(enable = "neon")]
6574#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6575#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
6576#[cfg_attr(
6577    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6578    assert_instr(fcmgt)
6579)]
6580#[cfg_attr(
6581    not(target_arch = "arm"),
6582    stable(feature = "neon_intrinsics", since = "1.59.0")
6583)]
6584#[cfg_attr(
6585    target_arch = "arm",
6586    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6587)]
6588pub fn vclt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
6589    unsafe { simd_lt(a, b) }
6590}
6591#[doc = "Floating-point compare less than"]
6592#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f32)"]
6593#[inline]
6594#[target_feature(enable = "neon")]
6595#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6596#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
6597#[cfg_attr(
6598    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6599    assert_instr(fcmgt)
6600)]
6601#[cfg_attr(
6602    not(target_arch = "arm"),
6603    stable(feature = "neon_intrinsics", since = "1.59.0")
6604)]
6605#[cfg_attr(
6606    target_arch = "arm",
6607    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6608)]
6609pub fn vcltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
6610    unsafe { simd_lt(a, b) }
6611}
6612#[doc = "Compare signed less than"]
6613#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s8)"]
6614#[inline]
6615#[target_feature(enable = "neon")]
6616#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6617#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
6618#[cfg_attr(
6619    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6620    assert_instr(cmgt)
6621)]
6622#[cfg_attr(
6623    not(target_arch = "arm"),
6624    stable(feature = "neon_intrinsics", since = "1.59.0")
6625)]
6626#[cfg_attr(
6627    target_arch = "arm",
6628    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6629)]
6630pub fn vclt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
6631    unsafe { simd_lt(a, b) }
6632}
6633#[doc = "Compare signed less than"]
6634#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s8)"]
6635#[inline]
6636#[target_feature(enable = "neon")]
6637#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6638#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
6639#[cfg_attr(
6640    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6641    assert_instr(cmgt)
6642)]
6643#[cfg_attr(
6644    not(target_arch = "arm"),
6645    stable(feature = "neon_intrinsics", since = "1.59.0")
6646)]
6647#[cfg_attr(
6648    target_arch = "arm",
6649    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6650)]
6651pub fn vcltq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
6652    unsafe { simd_lt(a, b) }
6653}
6654#[doc = "Compare signed less than"]
6655#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s16)"]
6656#[inline]
6657#[target_feature(enable = "neon")]
6658#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6659#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
6660#[cfg_attr(
6661    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6662    assert_instr(cmgt)
6663)]
6664#[cfg_attr(
6665    not(target_arch = "arm"),
6666    stable(feature = "neon_intrinsics", since = "1.59.0")
6667)]
6668#[cfg_attr(
6669    target_arch = "arm",
6670    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6671)]
6672pub fn vclt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
6673    unsafe { simd_lt(a, b) }
6674}
6675#[doc = "Compare signed less than"]
6676#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s16)"]
6677#[inline]
6678#[target_feature(enable = "neon")]
6679#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6680#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
6681#[cfg_attr(
6682    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6683    assert_instr(cmgt)
6684)]
6685#[cfg_attr(
6686    not(target_arch = "arm"),
6687    stable(feature = "neon_intrinsics", since = "1.59.0")
6688)]
6689#[cfg_attr(
6690    target_arch = "arm",
6691    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6692)]
6693pub fn vcltq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
6694    unsafe { simd_lt(a, b) }
6695}
6696#[doc = "Compare signed less than"]
6697#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s32)"]
6698#[inline]
6699#[target_feature(enable = "neon")]
6700#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6701#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
6702#[cfg_attr(
6703    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6704    assert_instr(cmgt)
6705)]
6706#[cfg_attr(
6707    not(target_arch = "arm"),
6708    stable(feature = "neon_intrinsics", since = "1.59.0")
6709)]
6710#[cfg_attr(
6711    target_arch = "arm",
6712    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6713)]
6714pub fn vclt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
6715    unsafe { simd_lt(a, b) }
6716}
6717#[doc = "Compare signed less than"]
6718#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s32)"]
6719#[inline]
6720#[target_feature(enable = "neon")]
6721#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6722#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
6723#[cfg_attr(
6724    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6725    assert_instr(cmgt)
6726)]
6727#[cfg_attr(
6728    not(target_arch = "arm"),
6729    stable(feature = "neon_intrinsics", since = "1.59.0")
6730)]
6731#[cfg_attr(
6732    target_arch = "arm",
6733    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6734)]
6735pub fn vcltq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
6736    unsafe { simd_lt(a, b) }
6737}
6738#[doc = "Compare unsigned less than"]
6739#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u8)"]
6740#[inline]
6741#[target_feature(enable = "neon")]
6742#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6743#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
6744#[cfg_attr(
6745    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6746    assert_instr(cmhi)
6747)]
6748#[cfg_attr(
6749    not(target_arch = "arm"),
6750    stable(feature = "neon_intrinsics", since = "1.59.0")
6751)]
6752#[cfg_attr(
6753    target_arch = "arm",
6754    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6755)]
6756pub fn vclt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
6757    unsafe { simd_lt(a, b) }
6758}
6759#[doc = "Compare unsigned less than"]
6760#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u8)"]
6761#[inline]
6762#[target_feature(enable = "neon")]
6763#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6764#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
6765#[cfg_attr(
6766    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6767    assert_instr(cmhi)
6768)]
6769#[cfg_attr(
6770    not(target_arch = "arm"),
6771    stable(feature = "neon_intrinsics", since = "1.59.0")
6772)]
6773#[cfg_attr(
6774    target_arch = "arm",
6775    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6776)]
6777pub fn vcltq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
6778    unsafe { simd_lt(a, b) }
6779}
6780#[doc = "Compare unsigned less than"]
6781#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u16)"]
6782#[inline]
6783#[target_feature(enable = "neon")]
6784#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6785#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
6786#[cfg_attr(
6787    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6788    assert_instr(cmhi)
6789)]
6790#[cfg_attr(
6791    not(target_arch = "arm"),
6792    stable(feature = "neon_intrinsics", since = "1.59.0")
6793)]
6794#[cfg_attr(
6795    target_arch = "arm",
6796    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6797)]
6798pub fn vclt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
6799    unsafe { simd_lt(a, b) }
6800}
6801#[doc = "Compare unsigned less than"]
6802#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u16)"]
6803#[inline]
6804#[target_feature(enable = "neon")]
6805#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6806#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
6807#[cfg_attr(
6808    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6809    assert_instr(cmhi)
6810)]
6811#[cfg_attr(
6812    not(target_arch = "arm"),
6813    stable(feature = "neon_intrinsics", since = "1.59.0")
6814)]
6815#[cfg_attr(
6816    target_arch = "arm",
6817    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6818)]
6819pub fn vcltq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
6820    unsafe { simd_lt(a, b) }
6821}
6822#[doc = "Compare unsigned less than"]
6823#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u32)"]
6824#[inline]
6825#[target_feature(enable = "neon")]
6826#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6827#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
6828#[cfg_attr(
6829    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6830    assert_instr(cmhi)
6831)]
6832#[cfg_attr(
6833    not(target_arch = "arm"),
6834    stable(feature = "neon_intrinsics", since = "1.59.0")
6835)]
6836#[cfg_attr(
6837    target_arch = "arm",
6838    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6839)]
6840pub fn vclt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
6841    unsafe { simd_lt(a, b) }
6842}
6843#[doc = "Compare unsigned less than"]
6844#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u32)"]
6845#[inline]
6846#[target_feature(enable = "neon")]
6847#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6848#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
6849#[cfg_attr(
6850    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6851    assert_instr(cmhi)
6852)]
6853#[cfg_attr(
6854    not(target_arch = "arm"),
6855    stable(feature = "neon_intrinsics", since = "1.59.0")
6856)]
6857#[cfg_attr(
6858    target_arch = "arm",
6859    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6860)]
6861pub fn vcltq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
6862    unsafe { simd_lt(a, b) }
6863}
6864#[doc = "Floating-point compare less than"]
6865#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f16)"]
6866#[inline]
6867#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6868#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclt.f16"))]
6869#[cfg_attr(
6870    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6871    assert_instr(fcmlt)
6872)]
6873#[target_feature(enable = "neon,fp16")]
6874#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6875pub fn vcltz_f16(a: float16x4_t) -> uint16x4_t {
6876    let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
6877    unsafe { simd_lt(a, transmute(b)) }
6878}
6879#[doc = "Floating-point compare less than"]
6880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f16)"]
6881#[inline]
6882#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6883#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclt.f16"))]
6884#[cfg_attr(
6885    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6886    assert_instr(fcmlt)
6887)]
6888#[target_feature(enable = "neon,fp16")]
6889#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6890pub fn vcltzq_f16(a: float16x8_t) -> uint16x8_t {
6891    let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
6892    unsafe { simd_lt(a, transmute(b)) }
6893}
6894#[doc = "Count leading zero bits"]
6895#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s8)"]
6896#[inline]
6897#[target_feature(enable = "neon")]
6898#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6899#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
6900#[cfg_attr(
6901    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6902    assert_instr(clz)
6903)]
6904#[cfg_attr(
6905    not(target_arch = "arm"),
6906    stable(feature = "neon_intrinsics", since = "1.59.0")
6907)]
6908#[cfg_attr(
6909    target_arch = "arm",
6910    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6911)]
6912pub fn vclz_s8(a: int8x8_t) -> int8x8_t {
6913    unsafe { simd_ctlz(a) }
6914}
6915#[doc = "Count leading zero bits"]
6916#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s8)"]
6917#[inline]
6918#[target_feature(enable = "neon")]
6919#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6920#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
6921#[cfg_attr(
6922    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6923    assert_instr(clz)
6924)]
6925#[cfg_attr(
6926    not(target_arch = "arm"),
6927    stable(feature = "neon_intrinsics", since = "1.59.0")
6928)]
6929#[cfg_attr(
6930    target_arch = "arm",
6931    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6932)]
6933pub fn vclzq_s8(a: int8x16_t) -> int8x16_t {
6934    unsafe { simd_ctlz(a) }
6935}
6936#[doc = "Count leading zero bits"]
6937#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s16)"]
6938#[inline]
6939#[target_feature(enable = "neon")]
6940#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6941#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
6942#[cfg_attr(
6943    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6944    assert_instr(clz)
6945)]
6946#[cfg_attr(
6947    not(target_arch = "arm"),
6948    stable(feature = "neon_intrinsics", since = "1.59.0")
6949)]
6950#[cfg_attr(
6951    target_arch = "arm",
6952    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6953)]
6954pub fn vclz_s16(a: int16x4_t) -> int16x4_t {
6955    unsafe { simd_ctlz(a) }
6956}
6957#[doc = "Count leading zero bits"]
6958#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s16)"]
6959#[inline]
6960#[target_feature(enable = "neon")]
6961#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6962#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
6963#[cfg_attr(
6964    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6965    assert_instr(clz)
6966)]
6967#[cfg_attr(
6968    not(target_arch = "arm"),
6969    stable(feature = "neon_intrinsics", since = "1.59.0")
6970)]
6971#[cfg_attr(
6972    target_arch = "arm",
6973    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6974)]
6975pub fn vclzq_s16(a: int16x8_t) -> int16x8_t {
6976    unsafe { simd_ctlz(a) }
6977}
6978#[doc = "Count leading zero bits"]
6979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s32)"]
6980#[inline]
6981#[target_feature(enable = "neon")]
6982#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6983#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
6984#[cfg_attr(
6985    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6986    assert_instr(clz)
6987)]
6988#[cfg_attr(
6989    not(target_arch = "arm"),
6990    stable(feature = "neon_intrinsics", since = "1.59.0")
6991)]
6992#[cfg_attr(
6993    target_arch = "arm",
6994    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6995)]
6996pub fn vclz_s32(a: int32x2_t) -> int32x2_t {
6997    unsafe { simd_ctlz(a) }
6998}
6999#[doc = "Count leading zero bits"]
7000#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s32)"]
7001#[inline]
7002#[target_feature(enable = "neon")]
7003#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7004#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
7005#[cfg_attr(
7006    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7007    assert_instr(clz)
7008)]
7009#[cfg_attr(
7010    not(target_arch = "arm"),
7011    stable(feature = "neon_intrinsics", since = "1.59.0")
7012)]
7013#[cfg_attr(
7014    target_arch = "arm",
7015    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7016)]
7017pub fn vclzq_s32(a: int32x4_t) -> int32x4_t {
7018    unsafe { simd_ctlz(a) }
7019}
7020#[doc = "Count leading zero bits"]
7021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"]
7022#[inline]
7023#[cfg(target_endian = "little")]
7024#[target_feature(enable = "neon")]
7025#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7026#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
7027#[cfg_attr(
7028    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7029    assert_instr(clz)
7030)]
7031#[cfg_attr(
7032    not(target_arch = "arm"),
7033    stable(feature = "neon_intrinsics", since = "1.59.0")
7034)]
7035#[cfg_attr(
7036    target_arch = "arm",
7037    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7038)]
7039pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t {
7040    unsafe { transmute(vclz_s16(transmute(a))) }
7041}
7042#[doc = "Count leading zero bits"]
7043#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"]
7044#[inline]
7045#[cfg(target_endian = "big")]
7046#[target_feature(enable = "neon")]
7047#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7048#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
7049#[cfg_attr(
7050    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7051    assert_instr(clz)
7052)]
7053#[cfg_attr(
7054    not(target_arch = "arm"),
7055    stable(feature = "neon_intrinsics", since = "1.59.0")
7056)]
7057#[cfg_attr(
7058    target_arch = "arm",
7059    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7060)]
7061pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t {
7062    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
7063    unsafe {
7064        let ret_val: uint16x4_t = transmute(vclz_s16(transmute(a)));
7065        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
7066    }
7067}
7068#[doc = "Count leading zero bits"]
7069#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"]
7070#[inline]
7071#[cfg(target_endian = "little")]
7072#[target_feature(enable = "neon")]
7073#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7074#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
7075#[cfg_attr(
7076    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7077    assert_instr(clz)
7078)]
7079#[cfg_attr(
7080    not(target_arch = "arm"),
7081    stable(feature = "neon_intrinsics", since = "1.59.0")
7082)]
7083#[cfg_attr(
7084    target_arch = "arm",
7085    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7086)]
7087pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t {
7088    unsafe { transmute(vclzq_s16(transmute(a))) }
7089}
7090#[doc = "Count leading zero bits"]
7091#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"]
7092#[inline]
7093#[cfg(target_endian = "big")]
7094#[target_feature(enable = "neon")]
7095#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7096#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
7097#[cfg_attr(
7098    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7099    assert_instr(clz)
7100)]
7101#[cfg_attr(
7102    not(target_arch = "arm"),
7103    stable(feature = "neon_intrinsics", since = "1.59.0")
7104)]
7105#[cfg_attr(
7106    target_arch = "arm",
7107    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7108)]
7109pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t {
7110    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
7111    unsafe {
7112        let ret_val: uint16x8_t = transmute(vclzq_s16(transmute(a)));
7113        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
7114    }
7115}
7116#[doc = "Count leading zero bits"]
7117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"]
7118#[inline]
7119#[cfg(target_endian = "little")]
7120#[target_feature(enable = "neon")]
7121#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7122#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
7123#[cfg_attr(
7124    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7125    assert_instr(clz)
7126)]
7127#[cfg_attr(
7128    not(target_arch = "arm"),
7129    stable(feature = "neon_intrinsics", since = "1.59.0")
7130)]
7131#[cfg_attr(
7132    target_arch = "arm",
7133    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7134)]
7135pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t {
7136    unsafe { transmute(vclz_s32(transmute(a))) }
7137}
7138#[doc = "Count leading zero bits"]
7139#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"]
7140#[inline]
7141#[cfg(target_endian = "big")]
7142#[target_feature(enable = "neon")]
7143#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7144#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
7145#[cfg_attr(
7146    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7147    assert_instr(clz)
7148)]
7149#[cfg_attr(
7150    not(target_arch = "arm"),
7151    stable(feature = "neon_intrinsics", since = "1.59.0")
7152)]
7153#[cfg_attr(
7154    target_arch = "arm",
7155    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7156)]
7157pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t {
7158    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
7159    unsafe {
7160        let ret_val: uint32x2_t = transmute(vclz_s32(transmute(a)));
7161        simd_shuffle!(ret_val, ret_val, [1, 0])
7162    }
7163}
7164#[doc = "Count leading zero bits"]
7165#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"]
7166#[inline]
7167#[cfg(target_endian = "little")]
7168#[target_feature(enable = "neon")]
7169#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7170#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
7171#[cfg_attr(
7172    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7173    assert_instr(clz)
7174)]
7175#[cfg_attr(
7176    not(target_arch = "arm"),
7177    stable(feature = "neon_intrinsics", since = "1.59.0")
7178)]
7179#[cfg_attr(
7180    target_arch = "arm",
7181    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7182)]
7183pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t {
7184    unsafe { transmute(vclzq_s32(transmute(a))) }
7185}
7186#[doc = "Count leading zero bits"]
7187#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"]
7188#[inline]
7189#[cfg(target_endian = "big")]
7190#[target_feature(enable = "neon")]
7191#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7192#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
7193#[cfg_attr(
7194    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7195    assert_instr(clz)
7196)]
7197#[cfg_attr(
7198    not(target_arch = "arm"),
7199    stable(feature = "neon_intrinsics", since = "1.59.0")
7200)]
7201#[cfg_attr(
7202    target_arch = "arm",
7203    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7204)]
7205pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t {
7206    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
7207    unsafe {
7208        let ret_val: uint32x4_t = transmute(vclzq_s32(transmute(a)));
7209        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
7210    }
7211}
7212#[doc = "Count leading zero bits"]
7213#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"]
7214#[inline]
7215#[cfg(target_endian = "little")]
7216#[target_feature(enable = "neon")]
7217#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7218#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
7219#[cfg_attr(
7220    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7221    assert_instr(clz)
7222)]
7223#[cfg_attr(
7224    not(target_arch = "arm"),
7225    stable(feature = "neon_intrinsics", since = "1.59.0")
7226)]
7227#[cfg_attr(
7228    target_arch = "arm",
7229    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7230)]
7231pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t {
7232    unsafe { transmute(vclz_s8(transmute(a))) }
7233}
7234#[doc = "Count leading zero bits"]
7235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"]
7236#[inline]
7237#[cfg(target_endian = "big")]
7238#[target_feature(enable = "neon")]
7239#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7240#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
7241#[cfg_attr(
7242    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7243    assert_instr(clz)
7244)]
7245#[cfg_attr(
7246    not(target_arch = "arm"),
7247    stable(feature = "neon_intrinsics", since = "1.59.0")
7248)]
7249#[cfg_attr(
7250    target_arch = "arm",
7251    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7252)]
7253pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t {
7254    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
7255    unsafe {
7256        let ret_val: uint8x8_t = transmute(vclz_s8(transmute(a)));
7257        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
7258    }
7259}
7260#[doc = "Count leading zero bits"]
7261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"]
7262#[inline]
7263#[cfg(target_endian = "little")]
7264#[target_feature(enable = "neon")]
7265#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7266#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
7267#[cfg_attr(
7268    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7269    assert_instr(clz)
7270)]
7271#[cfg_attr(
7272    not(target_arch = "arm"),
7273    stable(feature = "neon_intrinsics", since = "1.59.0")
7274)]
7275#[cfg_attr(
7276    target_arch = "arm",
7277    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7278)]
7279pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t {
7280    unsafe { transmute(vclzq_s8(transmute(a))) }
7281}
7282#[doc = "Count leading zero bits"]
7283#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"]
7284#[inline]
7285#[cfg(target_endian = "big")]
7286#[target_feature(enable = "neon")]
7287#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7288#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
7289#[cfg_attr(
7290    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7291    assert_instr(clz)
7292)]
7293#[cfg_attr(
7294    not(target_arch = "arm"),
7295    stable(feature = "neon_intrinsics", since = "1.59.0")
7296)]
7297#[cfg_attr(
7298    target_arch = "arm",
7299    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7300)]
7301pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t {
7302    let a: uint8x16_t =
7303        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
7304    unsafe {
7305        let ret_val: uint8x16_t = transmute(vclzq_s8(transmute(a)));
7306        simd_shuffle!(
7307            ret_val,
7308            ret_val,
7309            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
7310        )
7311    }
7312}
7313#[doc = "Population count per byte."]
7314#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_s8)"]
7315#[inline]
7316#[target_feature(enable = "neon")]
7317#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7318#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7319#[cfg_attr(
7320    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7321    assert_instr(cnt)
7322)]
7323#[cfg_attr(
7324    not(target_arch = "arm"),
7325    stable(feature = "neon_intrinsics", since = "1.59.0")
7326)]
7327#[cfg_attr(
7328    target_arch = "arm",
7329    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7330)]
7331pub fn vcnt_s8(a: int8x8_t) -> int8x8_t {
7332    unsafe { simd_ctpop(a) }
7333}
7334#[doc = "Population count per byte."]
7335#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_s8)"]
7336#[inline]
7337#[target_feature(enable = "neon")]
7338#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7339#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7340#[cfg_attr(
7341    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7342    assert_instr(cnt)
7343)]
7344#[cfg_attr(
7345    not(target_arch = "arm"),
7346    stable(feature = "neon_intrinsics", since = "1.59.0")
7347)]
7348#[cfg_attr(
7349    target_arch = "arm",
7350    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7351)]
7352pub fn vcntq_s8(a: int8x16_t) -> int8x16_t {
7353    unsafe { simd_ctpop(a) }
7354}
7355#[doc = "Population count per byte."]
7356#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"]
7357#[inline]
7358#[cfg(target_endian = "little")]
7359#[target_feature(enable = "neon")]
7360#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7361#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7362#[cfg_attr(
7363    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7364    assert_instr(cnt)
7365)]
7366#[cfg_attr(
7367    not(target_arch = "arm"),
7368    stable(feature = "neon_intrinsics", since = "1.59.0")
7369)]
7370#[cfg_attr(
7371    target_arch = "arm",
7372    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7373)]
7374pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t {
7375    unsafe { transmute(vcnt_s8(transmute(a))) }
7376}
7377#[doc = "Population count per byte."]
7378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"]
7379#[inline]
7380#[cfg(target_endian = "big")]
7381#[target_feature(enable = "neon")]
7382#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7383#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7384#[cfg_attr(
7385    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7386    assert_instr(cnt)
7387)]
7388#[cfg_attr(
7389    not(target_arch = "arm"),
7390    stable(feature = "neon_intrinsics", since = "1.59.0")
7391)]
7392#[cfg_attr(
7393    target_arch = "arm",
7394    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7395)]
7396pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t {
7397    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
7398    unsafe {
7399        let ret_val: uint8x8_t = transmute(vcnt_s8(transmute(a)));
7400        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
7401    }
7402}
7403#[doc = "Population count per byte."]
7404#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"]
7405#[inline]
7406#[cfg(target_endian = "little")]
7407#[target_feature(enable = "neon")]
7408#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7409#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7410#[cfg_attr(
7411    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7412    assert_instr(cnt)
7413)]
7414#[cfg_attr(
7415    not(target_arch = "arm"),
7416    stable(feature = "neon_intrinsics", since = "1.59.0")
7417)]
7418#[cfg_attr(
7419    target_arch = "arm",
7420    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7421)]
7422pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t {
7423    unsafe { transmute(vcntq_s8(transmute(a))) }
7424}
7425#[doc = "Population count per byte."]
7426#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"]
7427#[inline]
7428#[cfg(target_endian = "big")]
7429#[target_feature(enable = "neon")]
7430#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7431#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7432#[cfg_attr(
7433    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7434    assert_instr(cnt)
7435)]
7436#[cfg_attr(
7437    not(target_arch = "arm"),
7438    stable(feature = "neon_intrinsics", since = "1.59.0")
7439)]
7440#[cfg_attr(
7441    target_arch = "arm",
7442    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7443)]
7444pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t {
7445    let a: uint8x16_t =
7446        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
7447    unsafe {
7448        let ret_val: uint8x16_t = transmute(vcntq_s8(transmute(a)));
7449        simd_shuffle!(
7450            ret_val,
7451            ret_val,
7452            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
7453        )
7454    }
7455}
7456#[doc = "Population count per byte."]
7457#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"]
7458#[inline]
7459#[cfg(target_endian = "little")]
7460#[target_feature(enable = "neon")]
7461#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7462#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7463#[cfg_attr(
7464    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7465    assert_instr(cnt)
7466)]
7467#[cfg_attr(
7468    not(target_arch = "arm"),
7469    stable(feature = "neon_intrinsics", since = "1.59.0")
7470)]
7471#[cfg_attr(
7472    target_arch = "arm",
7473    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7474)]
7475pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t {
7476    unsafe { transmute(vcnt_s8(transmute(a))) }
7477}
7478#[doc = "Population count per byte."]
7479#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"]
7480#[inline]
7481#[cfg(target_endian = "big")]
7482#[target_feature(enable = "neon")]
7483#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7484#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7485#[cfg_attr(
7486    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7487    assert_instr(cnt)
7488)]
7489#[cfg_attr(
7490    not(target_arch = "arm"),
7491    stable(feature = "neon_intrinsics", since = "1.59.0")
7492)]
7493#[cfg_attr(
7494    target_arch = "arm",
7495    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7496)]
7497pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t {
7498    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
7499    unsafe {
7500        let ret_val: poly8x8_t = transmute(vcnt_s8(transmute(a)));
7501        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
7502    }
7503}
7504#[doc = "Population count per byte."]
7505#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"]
7506#[inline]
7507#[cfg(target_endian = "little")]
7508#[target_feature(enable = "neon")]
7509#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7510#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7511#[cfg_attr(
7512    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7513    assert_instr(cnt)
7514)]
7515#[cfg_attr(
7516    not(target_arch = "arm"),
7517    stable(feature = "neon_intrinsics", since = "1.59.0")
7518)]
7519#[cfg_attr(
7520    target_arch = "arm",
7521    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7522)]
7523pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t {
7524    unsafe { transmute(vcntq_s8(transmute(a))) }
7525}
7526#[doc = "Population count per byte."]
7527#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"]
7528#[inline]
7529#[cfg(target_endian = "big")]
7530#[target_feature(enable = "neon")]
7531#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7532#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7533#[cfg_attr(
7534    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7535    assert_instr(cnt)
7536)]
7537#[cfg_attr(
7538    not(target_arch = "arm"),
7539    stable(feature = "neon_intrinsics", since = "1.59.0")
7540)]
7541#[cfg_attr(
7542    target_arch = "arm",
7543    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7544)]
7545pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t {
7546    let a: poly8x16_t =
7547        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
7548    unsafe {
7549        let ret_val: poly8x16_t = transmute(vcntq_s8(transmute(a)));
7550        simd_shuffle!(
7551            ret_val,
7552            ret_val,
7553            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
7554        )
7555    }
7556}
7557#[doc = "Join two smaller vectors into a single larger vector"]
7558#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f16)"]
7559#[inline]
7560#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7561#[target_feature(enable = "neon,fp16")]
7562#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7563#[cfg_attr(test, assert_instr(nop))]
7564pub fn vcombine_f16(a: float16x4_t, b: float16x4_t) -> float16x8_t {
7565    unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) }
7566}
7567#[doc = "Join two smaller vectors into a single larger vector"]
7568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f32)"]
7569#[inline]
7570#[target_feature(enable = "neon")]
7571#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7572#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7573#[cfg_attr(
7574    not(target_arch = "arm"),
7575    stable(feature = "neon_intrinsics", since = "1.59.0")
7576)]
7577#[cfg_attr(
7578    target_arch = "arm",
7579    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7580)]
7581pub fn vcombine_f32(a: float32x2_t, b: float32x2_t) -> float32x4_t {
7582    unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) }
7583}
7584#[doc = "Join two smaller vectors into a single larger vector"]
7585#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s8)"]
7586#[inline]
7587#[target_feature(enable = "neon")]
7588#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7589#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7590#[cfg_attr(
7591    not(target_arch = "arm"),
7592    stable(feature = "neon_intrinsics", since = "1.59.0")
7593)]
7594#[cfg_attr(
7595    target_arch = "arm",
7596    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7597)]
7598pub fn vcombine_s8(a: int8x8_t, b: int8x8_t) -> int8x16_t {
7599    unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
7600}
7601#[doc = "Join two smaller vectors into a single larger vector"]
7602#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s16)"]
7603#[inline]
7604#[target_feature(enable = "neon")]
7605#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7606#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7607#[cfg_attr(
7608    not(target_arch = "arm"),
7609    stable(feature = "neon_intrinsics", since = "1.59.0")
7610)]
7611#[cfg_attr(
7612    target_arch = "arm",
7613    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7614)]
7615pub fn vcombine_s16(a: int16x4_t, b: int16x4_t) -> int16x8_t {
7616    unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) }
7617}
7618#[doc = "Join two smaller vectors into a single larger vector"]
7619#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s32)"]
7620#[inline]
7621#[target_feature(enable = "neon")]
7622#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7623#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7624#[cfg_attr(
7625    not(target_arch = "arm"),
7626    stable(feature = "neon_intrinsics", since = "1.59.0")
7627)]
7628#[cfg_attr(
7629    target_arch = "arm",
7630    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7631)]
7632pub fn vcombine_s32(a: int32x2_t, b: int32x2_t) -> int32x4_t {
7633    unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) }
7634}
7635#[doc = "Join two smaller vectors into a single larger vector"]
7636#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s64)"]
7637#[inline]
7638#[target_feature(enable = "neon")]
7639#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7640#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7641#[cfg_attr(
7642    not(target_arch = "arm"),
7643    stable(feature = "neon_intrinsics", since = "1.59.0")
7644)]
7645#[cfg_attr(
7646    target_arch = "arm",
7647    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7648)]
7649pub fn vcombine_s64(a: int64x1_t, b: int64x1_t) -> int64x2_t {
7650    unsafe { simd_shuffle!(a, b, [0, 1]) }
7651}
7652#[doc = "Join two smaller vectors into a single larger vector"]
7653#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u8)"]
7654#[inline]
7655#[target_feature(enable = "neon")]
7656#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7657#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7658#[cfg_attr(
7659    not(target_arch = "arm"),
7660    stable(feature = "neon_intrinsics", since = "1.59.0")
7661)]
7662#[cfg_attr(
7663    target_arch = "arm",
7664    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7665)]
7666pub fn vcombine_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t {
7667    unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
7668}
7669#[doc = "Join two smaller vectors into a single larger vector"]
7670#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u16)"]
7671#[inline]
7672#[target_feature(enable = "neon")]
7673#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7674#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7675#[cfg_attr(
7676    not(target_arch = "arm"),
7677    stable(feature = "neon_intrinsics", since = "1.59.0")
7678)]
7679#[cfg_attr(
7680    target_arch = "arm",
7681    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7682)]
7683pub fn vcombine_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x8_t {
7684    unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) }
7685}
7686#[doc = "Join two smaller vectors into a single larger vector"]
7687#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u32)"]
7688#[inline]
7689#[target_feature(enable = "neon")]
7690#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7691#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7692#[cfg_attr(
7693    not(target_arch = "arm"),
7694    stable(feature = "neon_intrinsics", since = "1.59.0")
7695)]
7696#[cfg_attr(
7697    target_arch = "arm",
7698    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7699)]
7700pub fn vcombine_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x4_t {
7701    unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) }
7702}
7703#[doc = "Join two smaller vectors into a single larger vector"]
7704#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u64)"]
7705#[inline]
7706#[target_feature(enable = "neon")]
7707#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7708#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7709#[cfg_attr(
7710    not(target_arch = "arm"),
7711    stable(feature = "neon_intrinsics", since = "1.59.0")
7712)]
7713#[cfg_attr(
7714    target_arch = "arm",
7715    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7716)]
7717pub fn vcombine_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x2_t {
7718    unsafe { simd_shuffle!(a, b, [0, 1]) }
7719}
7720#[doc = "Join two smaller vectors into a single larger vector"]
7721#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p8)"]
7722#[inline]
7723#[target_feature(enable = "neon")]
7724#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7725#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7726#[cfg_attr(
7727    not(target_arch = "arm"),
7728    stable(feature = "neon_intrinsics", since = "1.59.0")
7729)]
7730#[cfg_attr(
7731    target_arch = "arm",
7732    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7733)]
7734pub fn vcombine_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x16_t {
7735    unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
7736}
7737#[doc = "Join two smaller vectors into a single larger vector"]
7738#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p16)"]
7739#[inline]
7740#[target_feature(enable = "neon")]
7741#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7742#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7743#[cfg_attr(
7744    not(target_arch = "arm"),
7745    stable(feature = "neon_intrinsics", since = "1.59.0")
7746)]
7747#[cfg_attr(
7748    target_arch = "arm",
7749    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7750)]
7751pub fn vcombine_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x8_t {
7752    unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) }
7753}
7754#[doc = "Join two smaller vectors into a single larger vector"]
7755#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p64)"]
7756#[inline]
7757#[target_feature(enable = "neon")]
7758#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7759#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7760#[cfg_attr(
7761    not(target_arch = "arm"),
7762    stable(feature = "neon_intrinsics", since = "1.59.0")
7763)]
7764#[cfg_attr(
7765    target_arch = "arm",
7766    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7767)]
7768pub fn vcombine_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x2_t {
7769    unsafe { simd_shuffle!(a, b, [0, 1]) }
7770}
7771#[doc = "Insert vector element from another vector element"]
7772#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"]
7773#[inline]
7774#[cfg(target_endian = "little")]
7775#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7776#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7777#[cfg_attr(
7778    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7779    assert_instr(nop)
7780)]
7781#[target_feature(enable = "neon,fp16")]
7782#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7783pub fn vcreate_f16(a: u64) -> float16x4_t {
7784    unsafe { transmute(a) }
7785}
7786#[doc = "Insert vector element from another vector element"]
7787#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"]
7788#[inline]
7789#[cfg(target_endian = "big")]
7790#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7791#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7792#[cfg_attr(
7793    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7794    assert_instr(nop)
7795)]
7796#[target_feature(enable = "neon,fp16")]
7797#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7798pub fn vcreate_f16(a: u64) -> float16x4_t {
7799    unsafe {
7800        let ret_val: float16x4_t = transmute(a);
7801        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
7802    }
7803}
7804#[doc = "Insert vector element from another vector element"]
7805#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"]
7806#[inline]
7807#[cfg(target_endian = "little")]
7808#[target_feature(enable = "neon")]
7809#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7810#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7811#[cfg_attr(
7812    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7813    assert_instr(nop)
7814)]
7815#[cfg_attr(
7816    not(target_arch = "arm"),
7817    stable(feature = "neon_intrinsics", since = "1.59.0")
7818)]
7819#[cfg_attr(
7820    target_arch = "arm",
7821    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7822)]
7823pub fn vcreate_f32(a: u64) -> float32x2_t {
7824    unsafe { transmute(a) }
7825}
7826#[doc = "Insert vector element from another vector element"]
7827#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"]
7828#[inline]
7829#[cfg(target_endian = "big")]
7830#[target_feature(enable = "neon")]
7831#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7832#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7833#[cfg_attr(
7834    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7835    assert_instr(nop)
7836)]
7837#[cfg_attr(
7838    not(target_arch = "arm"),
7839    stable(feature = "neon_intrinsics", since = "1.59.0")
7840)]
7841#[cfg_attr(
7842    target_arch = "arm",
7843    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7844)]
7845pub fn vcreate_f32(a: u64) -> float32x2_t {
7846    unsafe {
7847        let ret_val: float32x2_t = transmute(a);
7848        simd_shuffle!(ret_val, ret_val, [1, 0])
7849    }
7850}
7851#[doc = "Insert vector element from another vector element"]
7852#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"]
7853#[inline]
7854#[cfg(target_endian = "little")]
7855#[target_feature(enable = "neon")]
7856#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7857#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7858#[cfg_attr(
7859    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7860    assert_instr(nop)
7861)]
7862#[cfg_attr(
7863    not(target_arch = "arm"),
7864    stable(feature = "neon_intrinsics", since = "1.59.0")
7865)]
7866#[cfg_attr(
7867    target_arch = "arm",
7868    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7869)]
7870pub fn vcreate_s8(a: u64) -> int8x8_t {
7871    unsafe { transmute(a) }
7872}
7873#[doc = "Insert vector element from another vector element"]
7874#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"]
7875#[inline]
7876#[cfg(target_endian = "big")]
7877#[target_feature(enable = "neon")]
7878#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7879#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7880#[cfg_attr(
7881    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7882    assert_instr(nop)
7883)]
7884#[cfg_attr(
7885    not(target_arch = "arm"),
7886    stable(feature = "neon_intrinsics", since = "1.59.0")
7887)]
7888#[cfg_attr(
7889    target_arch = "arm",
7890    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7891)]
7892pub fn vcreate_s8(a: u64) -> int8x8_t {
7893    unsafe {
7894        let ret_val: int8x8_t = transmute(a);
7895        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
7896    }
7897}
7898#[doc = "Insert vector element from another vector element"]
7899#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"]
7900#[inline]
7901#[cfg(target_endian = "little")]
7902#[target_feature(enable = "neon")]
7903#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7904#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7905#[cfg_attr(
7906    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7907    assert_instr(nop)
7908)]
7909#[cfg_attr(
7910    not(target_arch = "arm"),
7911    stable(feature = "neon_intrinsics", since = "1.59.0")
7912)]
7913#[cfg_attr(
7914    target_arch = "arm",
7915    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7916)]
7917pub fn vcreate_s16(a: u64) -> int16x4_t {
7918    unsafe { transmute(a) }
7919}
7920#[doc = "Insert vector element from another vector element"]
7921#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"]
7922#[inline]
7923#[cfg(target_endian = "big")]
7924#[target_feature(enable = "neon")]
7925#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7926#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7927#[cfg_attr(
7928    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7929    assert_instr(nop)
7930)]
7931#[cfg_attr(
7932    not(target_arch = "arm"),
7933    stable(feature = "neon_intrinsics", since = "1.59.0")
7934)]
7935#[cfg_attr(
7936    target_arch = "arm",
7937    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7938)]
7939pub fn vcreate_s16(a: u64) -> int16x4_t {
7940    unsafe {
7941        let ret_val: int16x4_t = transmute(a);
7942        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
7943    }
7944}
7945#[doc = "Insert vector element from another vector element"]
7946#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"]
7947#[inline]
7948#[cfg(target_endian = "little")]
7949#[target_feature(enable = "neon")]
7950#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7951#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7952#[cfg_attr(
7953    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7954    assert_instr(nop)
7955)]
7956#[cfg_attr(
7957    not(target_arch = "arm"),
7958    stable(feature = "neon_intrinsics", since = "1.59.0")
7959)]
7960#[cfg_attr(
7961    target_arch = "arm",
7962    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7963)]
7964pub fn vcreate_s32(a: u64) -> int32x2_t {
7965    unsafe { transmute(a) }
7966}
7967#[doc = "Insert vector element from another vector element"]
7968#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"]
7969#[inline]
7970#[cfg(target_endian = "big")]
7971#[target_feature(enable = "neon")]
7972#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7973#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7974#[cfg_attr(
7975    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7976    assert_instr(nop)
7977)]
7978#[cfg_attr(
7979    not(target_arch = "arm"),
7980    stable(feature = "neon_intrinsics", since = "1.59.0")
7981)]
7982#[cfg_attr(
7983    target_arch = "arm",
7984    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7985)]
7986pub fn vcreate_s32(a: u64) -> int32x2_t {
7987    unsafe {
7988        let ret_val: int32x2_t = transmute(a);
7989        simd_shuffle!(ret_val, ret_val, [1, 0])
7990    }
7991}
7992#[doc = "Insert vector element from another vector element"]
7993#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s64)"]
7994#[inline]
7995#[target_feature(enable = "neon")]
7996#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7997#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7998#[cfg_attr(
7999    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8000    assert_instr(nop)
8001)]
8002#[cfg_attr(
8003    not(target_arch = "arm"),
8004    stable(feature = "neon_intrinsics", since = "1.59.0")
8005)]
8006#[cfg_attr(
8007    target_arch = "arm",
8008    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8009)]
8010pub fn vcreate_s64(a: u64) -> int64x1_t {
8011    unsafe { transmute(a) }
8012}
8013#[doc = "Insert vector element from another vector element"]
8014#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"]
8015#[inline]
8016#[cfg(target_endian = "little")]
8017#[target_feature(enable = "neon")]
8018#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8019#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8020#[cfg_attr(
8021    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8022    assert_instr(nop)
8023)]
8024#[cfg_attr(
8025    not(target_arch = "arm"),
8026    stable(feature = "neon_intrinsics", since = "1.59.0")
8027)]
8028#[cfg_attr(
8029    target_arch = "arm",
8030    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8031)]
8032pub fn vcreate_u8(a: u64) -> uint8x8_t {
8033    unsafe { transmute(a) }
8034}
8035#[doc = "Insert vector element from another vector element"]
8036#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"]
8037#[inline]
8038#[cfg(target_endian = "big")]
8039#[target_feature(enable = "neon")]
8040#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8041#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8042#[cfg_attr(
8043    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8044    assert_instr(nop)
8045)]
8046#[cfg_attr(
8047    not(target_arch = "arm"),
8048    stable(feature = "neon_intrinsics", since = "1.59.0")
8049)]
8050#[cfg_attr(
8051    target_arch = "arm",
8052    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8053)]
8054pub fn vcreate_u8(a: u64) -> uint8x8_t {
8055    unsafe {
8056        let ret_val: uint8x8_t = transmute(a);
8057        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
8058    }
8059}
8060#[doc = "Insert vector element from another vector element"]
8061#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"]
8062#[inline]
8063#[cfg(target_endian = "little")]
8064#[target_feature(enable = "neon")]
8065#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8066#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8067#[cfg_attr(
8068    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8069    assert_instr(nop)
8070)]
8071#[cfg_attr(
8072    not(target_arch = "arm"),
8073    stable(feature = "neon_intrinsics", since = "1.59.0")
8074)]
8075#[cfg_attr(
8076    target_arch = "arm",
8077    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8078)]
8079pub fn vcreate_u16(a: u64) -> uint16x4_t {
8080    unsafe { transmute(a) }
8081}
8082#[doc = "Insert vector element from another vector element"]
8083#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"]
8084#[inline]
8085#[cfg(target_endian = "big")]
8086#[target_feature(enable = "neon")]
8087#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8088#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8089#[cfg_attr(
8090    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8091    assert_instr(nop)
8092)]
8093#[cfg_attr(
8094    not(target_arch = "arm"),
8095    stable(feature = "neon_intrinsics", since = "1.59.0")
8096)]
8097#[cfg_attr(
8098    target_arch = "arm",
8099    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8100)]
8101pub fn vcreate_u16(a: u64) -> uint16x4_t {
8102    unsafe {
8103        let ret_val: uint16x4_t = transmute(a);
8104        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
8105    }
8106}
8107#[doc = "Insert vector element from another vector element"]
8108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"]
8109#[inline]
8110#[cfg(target_endian = "little")]
8111#[target_feature(enable = "neon")]
8112#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8113#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8114#[cfg_attr(
8115    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8116    assert_instr(nop)
8117)]
8118#[cfg_attr(
8119    not(target_arch = "arm"),
8120    stable(feature = "neon_intrinsics", since = "1.59.0")
8121)]
8122#[cfg_attr(
8123    target_arch = "arm",
8124    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8125)]
8126pub fn vcreate_u32(a: u64) -> uint32x2_t {
8127    unsafe { transmute(a) }
8128}
8129#[doc = "Insert vector element from another vector element"]
8130#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"]
8131#[inline]
8132#[cfg(target_endian = "big")]
8133#[target_feature(enable = "neon")]
8134#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8135#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8136#[cfg_attr(
8137    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8138    assert_instr(nop)
8139)]
8140#[cfg_attr(
8141    not(target_arch = "arm"),
8142    stable(feature = "neon_intrinsics", since = "1.59.0")
8143)]
8144#[cfg_attr(
8145    target_arch = "arm",
8146    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8147)]
8148pub fn vcreate_u32(a: u64) -> uint32x2_t {
8149    unsafe {
8150        let ret_val: uint32x2_t = transmute(a);
8151        simd_shuffle!(ret_val, ret_val, [1, 0])
8152    }
8153}
8154#[doc = "Insert vector element from another vector element"]
8155#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u64)"]
8156#[inline]
8157#[target_feature(enable = "neon")]
8158#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8159#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8160#[cfg_attr(
8161    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8162    assert_instr(nop)
8163)]
8164#[cfg_attr(
8165    not(target_arch = "arm"),
8166    stable(feature = "neon_intrinsics", since = "1.59.0")
8167)]
8168#[cfg_attr(
8169    target_arch = "arm",
8170    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8171)]
8172pub fn vcreate_u64(a: u64) -> uint64x1_t {
8173    unsafe { transmute(a) }
8174}
8175#[doc = "Insert vector element from another vector element"]
8176#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"]
8177#[inline]
8178#[cfg(target_endian = "little")]
8179#[target_feature(enable = "neon")]
8180#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8181#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8182#[cfg_attr(
8183    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8184    assert_instr(nop)
8185)]
8186#[cfg_attr(
8187    not(target_arch = "arm"),
8188    stable(feature = "neon_intrinsics", since = "1.59.0")
8189)]
8190#[cfg_attr(
8191    target_arch = "arm",
8192    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8193)]
8194pub fn vcreate_p8(a: u64) -> poly8x8_t {
8195    unsafe { transmute(a) }
8196}
8197#[doc = "Insert vector element from another vector element"]
8198#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"]
8199#[inline]
8200#[cfg(target_endian = "big")]
8201#[target_feature(enable = "neon")]
8202#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8203#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8204#[cfg_attr(
8205    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8206    assert_instr(nop)
8207)]
8208#[cfg_attr(
8209    not(target_arch = "arm"),
8210    stable(feature = "neon_intrinsics", since = "1.59.0")
8211)]
8212#[cfg_attr(
8213    target_arch = "arm",
8214    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8215)]
8216pub fn vcreate_p8(a: u64) -> poly8x8_t {
8217    unsafe {
8218        let ret_val: poly8x8_t = transmute(a);
8219        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
8220    }
8221}
8222#[doc = "Insert vector element from another vector element"]
8223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"]
8224#[inline]
8225#[cfg(target_endian = "little")]
8226#[target_feature(enable = "neon")]
8227#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8228#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8229#[cfg_attr(
8230    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8231    assert_instr(nop)
8232)]
8233#[cfg_attr(
8234    not(target_arch = "arm"),
8235    stable(feature = "neon_intrinsics", since = "1.59.0")
8236)]
8237#[cfg_attr(
8238    target_arch = "arm",
8239    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8240)]
8241pub fn vcreate_p16(a: u64) -> poly16x4_t {
8242    unsafe { transmute(a) }
8243}
8244#[doc = "Insert vector element from another vector element"]
8245#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"]
8246#[inline]
8247#[cfg(target_endian = "big")]
8248#[target_feature(enable = "neon")]
8249#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8250#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8251#[cfg_attr(
8252    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8253    assert_instr(nop)
8254)]
8255#[cfg_attr(
8256    not(target_arch = "arm"),
8257    stable(feature = "neon_intrinsics", since = "1.59.0")
8258)]
8259#[cfg_attr(
8260    target_arch = "arm",
8261    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8262)]
8263pub fn vcreate_p16(a: u64) -> poly16x4_t {
8264    unsafe {
8265        let ret_val: poly16x4_t = transmute(a);
8266        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
8267    }
8268}
8269#[doc = "Insert vector element from another vector element"]
8270#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p64)"]
8271#[inline]
8272#[target_feature(enable = "neon,aes")]
8273#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8274#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8275#[cfg_attr(
8276    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8277    assert_instr(nop)
8278)]
8279#[cfg_attr(
8280    not(target_arch = "arm"),
8281    stable(feature = "neon_intrinsics", since = "1.59.0")
8282)]
8283#[cfg_attr(
8284    target_arch = "arm",
8285    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8286)]
8287pub fn vcreate_p64(a: u64) -> poly64x1_t {
8288    unsafe { transmute(a) }
8289}
8290#[doc = "Floating-point convert to lower precision narrow"]
8291#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_f32)"]
8292#[inline]
8293#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8294# [cfg_attr (all (test , target_arch = "arm") , assert_instr (vcvt . f16 . f32))]
8295#[cfg_attr(
8296    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8297    assert_instr(fcvtn)
8298)]
8299#[target_feature(enable = "neon,fp16")]
8300#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8301pub fn vcvt_f16_f32(a: float32x4_t) -> float16x4_t {
8302    unsafe { simd_cast(a) }
8303}
8304#[doc = "Fixed-point convert to floating-point"]
8305#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_s16)"]
8306#[inline]
8307#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8308#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8309#[cfg_attr(
8310    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8311    assert_instr(scvtf)
8312)]
8313#[target_feature(enable = "neon,fp16")]
8314#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8315pub fn vcvt_f16_s16(a: int16x4_t) -> float16x4_t {
8316    unsafe { simd_cast(a) }
8317}
8318#[doc = "Fixed-point convert to floating-point"]
8319#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f16_s16)"]
8320#[inline]
8321#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8322#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8323#[cfg_attr(
8324    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8325    assert_instr(scvtf)
8326)]
8327#[target_feature(enable = "neon,fp16")]
8328#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8329pub fn vcvtq_f16_s16(a: int16x8_t) -> float16x8_t {
8330    unsafe { simd_cast(a) }
8331}
8332#[doc = "Fixed-point convert to floating-point"]
8333#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_u16)"]
8334#[inline]
8335#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8336#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8337#[cfg_attr(
8338    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8339    assert_instr(ucvtf)
8340)]
8341#[target_feature(enable = "neon,fp16")]
8342#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8343pub fn vcvt_f16_u16(a: uint16x4_t) -> float16x4_t {
8344    unsafe { simd_cast(a) }
8345}
8346#[doc = "Fixed-point convert to floating-point"]
8347#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f16_u16)"]
8348#[inline]
8349#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8350#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8351#[cfg_attr(
8352    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8353    assert_instr(ucvtf)
8354)]
8355#[target_feature(enable = "neon,fp16")]
8356#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8357pub fn vcvtq_f16_u16(a: uint16x8_t) -> float16x8_t {
8358    unsafe { simd_cast(a) }
8359}
8360#[doc = "Floating-point convert to higher precision long"]
8361#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f16)"]
8362#[inline]
8363#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8364#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8365#[cfg_attr(
8366    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8367    assert_instr(fcvtl)
8368)]
8369#[target_feature(enable = "neon,fp16")]
8370#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8371pub fn vcvt_f32_f16(a: float16x4_t) -> float32x4_t {
8372    unsafe { simd_cast(a) }
8373}
8374#[doc = "Fixed-point convert to floating-point"]
8375#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_s32)"]
8376#[inline]
8377#[target_feature(enable = "neon")]
8378#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8379#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8380#[cfg_attr(
8381    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8382    assert_instr(scvtf)
8383)]
8384#[cfg_attr(
8385    not(target_arch = "arm"),
8386    stable(feature = "neon_intrinsics", since = "1.59.0")
8387)]
8388#[cfg_attr(
8389    target_arch = "arm",
8390    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8391)]
8392pub fn vcvt_f32_s32(a: int32x2_t) -> float32x2_t {
8393    unsafe { simd_cast(a) }
8394}
8395#[doc = "Fixed-point convert to floating-point"]
8396#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_s32)"]
8397#[inline]
8398#[target_feature(enable = "neon")]
8399#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8400#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8401#[cfg_attr(
8402    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8403    assert_instr(scvtf)
8404)]
8405#[cfg_attr(
8406    not(target_arch = "arm"),
8407    stable(feature = "neon_intrinsics", since = "1.59.0")
8408)]
8409#[cfg_attr(
8410    target_arch = "arm",
8411    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8412)]
8413pub fn vcvtq_f32_s32(a: int32x4_t) -> float32x4_t {
8414    unsafe { simd_cast(a) }
8415}
8416#[doc = "Fixed-point convert to floating-point"]
8417#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_u32)"]
8418#[inline]
8419#[target_feature(enable = "neon")]
8420#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8421#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8422#[cfg_attr(
8423    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8424    assert_instr(ucvtf)
8425)]
8426#[cfg_attr(
8427    not(target_arch = "arm"),
8428    stable(feature = "neon_intrinsics", since = "1.59.0")
8429)]
8430#[cfg_attr(
8431    target_arch = "arm",
8432    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8433)]
8434pub fn vcvt_f32_u32(a: uint32x2_t) -> float32x2_t {
8435    unsafe { simd_cast(a) }
8436}
8437#[doc = "Fixed-point convert to floating-point"]
8438#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_u32)"]
8439#[inline]
8440#[target_feature(enable = "neon")]
8441#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8442#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8443#[cfg_attr(
8444    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8445    assert_instr(ucvtf)
8446)]
8447#[cfg_attr(
8448    not(target_arch = "arm"),
8449    stable(feature = "neon_intrinsics", since = "1.59.0")
8450)]
8451#[cfg_attr(
8452    target_arch = "arm",
8453    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8454)]
8455pub fn vcvtq_f32_u32(a: uint32x4_t) -> float32x4_t {
8456    unsafe { simd_cast(a) }
8457}
8458#[doc = "Fixed-point convert to floating-point"]
8459#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f16_s16)"]
8460#[inline]
8461#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8462#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8463#[cfg_attr(
8464    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8465    assert_instr(scvtf, N = 1)
8466)]
8467#[rustc_legacy_const_generics(1)]
8468#[target_feature(enable = "neon,fp16")]
8469#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8470pub fn vcvt_n_f16_s16<const N: i32>(a: int16x4_t) -> float16x4_t {
8471    static_assert!(N >= 1 && N <= 16);
8472    unsafe extern "unadjusted" {
8473        #[cfg_attr(
8474            target_arch = "arm",
8475            link_name = "llvm.arm.neon.vcvtfxs2fp.v4f16.v4i16"
8476        )]
8477        #[cfg_attr(
8478            any(target_arch = "aarch64", target_arch = "arm64ec"),
8479            link_name = "llvm.aarch64.neon.vcvtfxs2fp.v4f16.v4i16"
8480        )]
8481        fn _vcvt_n_f16_s16(a: int16x4_t, n: i32) -> float16x4_t;
8482    }
8483    unsafe { _vcvt_n_f16_s16(a, N) }
8484}
8485#[doc = "Fixed-point convert to floating-point"]
8486#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f16_s16)"]
8487#[inline]
8488#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8489#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8490#[cfg_attr(
8491    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8492    assert_instr(scvtf, N = 1)
8493)]
8494#[rustc_legacy_const_generics(1)]
8495#[target_feature(enable = "neon,fp16")]
8496#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8497pub fn vcvtq_n_f16_s16<const N: i32>(a: int16x8_t) -> float16x8_t {
8498    static_assert!(N >= 1 && N <= 16);
8499    unsafe extern "unadjusted" {
8500        #[cfg_attr(
8501            target_arch = "arm",
8502            link_name = "llvm.arm.neon.vcvtfxs2fp.v8f16.v8i16"
8503        )]
8504        #[cfg_attr(
8505            any(target_arch = "aarch64", target_arch = "arm64ec"),
8506            link_name = "llvm.aarch64.neon.vcvtfxs2fp.v8f16.v8i16"
8507        )]
8508        fn _vcvtq_n_f16_s16(a: int16x8_t, n: i32) -> float16x8_t;
8509    }
8510    unsafe { _vcvtq_n_f16_s16(a, N) }
8511}
8512#[doc = "Fixed-point convert to floating-point"]
8513#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f16_u16)"]
8514#[inline]
8515#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8516#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8517#[cfg_attr(
8518    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8519    assert_instr(ucvtf, N = 1)
8520)]
8521#[rustc_legacy_const_generics(1)]
8522#[target_feature(enable = "neon,fp16")]
8523#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8524pub fn vcvt_n_f16_u16<const N: i32>(a: uint16x4_t) -> float16x4_t {
8525    static_assert!(N >= 1 && N <= 16);
8526    unsafe extern "unadjusted" {
8527        #[cfg_attr(
8528            target_arch = "arm",
8529            link_name = "llvm.arm.neon.vcvtfxu2fp.v4f16.v4i16"
8530        )]
8531        #[cfg_attr(
8532            any(target_arch = "aarch64", target_arch = "arm64ec"),
8533            link_name = "llvm.aarch64.neon.vcvtfxu2fp.v4f16.v4i16"
8534        )]
8535        fn _vcvt_n_f16_u16(a: uint16x4_t, n: i32) -> float16x4_t;
8536    }
8537    unsafe { _vcvt_n_f16_u16(a, N) }
8538}
8539#[doc = "Fixed-point convert to floating-point"]
8540#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f16_u16)"]
8541#[inline]
8542#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8543#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8544#[cfg_attr(
8545    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8546    assert_instr(ucvtf, N = 1)
8547)]
8548#[rustc_legacy_const_generics(1)]
8549#[target_feature(enable = "neon,fp16")]
8550#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8551pub fn vcvtq_n_f16_u16<const N: i32>(a: uint16x8_t) -> float16x8_t {
8552    static_assert!(N >= 1 && N <= 16);
8553    unsafe extern "unadjusted" {
8554        #[cfg_attr(
8555            target_arch = "arm",
8556            link_name = "llvm.arm.neon.vcvtfxu2fp.v8f16.v8i16"
8557        )]
8558        #[cfg_attr(
8559            any(target_arch = "aarch64", target_arch = "arm64ec"),
8560            link_name = "llvm.aarch64.neon.vcvtfxu2fp.v8f16.v8i16"
8561        )]
8562        fn _vcvtq_n_f16_u16(a: uint16x8_t, n: i32) -> float16x8_t;
8563    }
8564    unsafe { _vcvtq_n_f16_u16(a, N) }
8565}
8566#[doc = "Fixed-point convert to floating-point"]
8567#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"]
8568#[inline]
8569#[cfg(target_arch = "arm")]
8570#[target_feature(enable = "neon,v7")]
8571#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8572#[rustc_legacy_const_generics(1)]
8573#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8574pub fn vcvt_n_f32_s32<const N: i32>(a: int32x2_t) -> float32x2_t {
8575    static_assert!(N >= 1 && N <= 32);
8576    unsafe extern "unadjusted" {
8577        #[cfg_attr(
8578            target_arch = "arm",
8579            link_name = "llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32"
8580        )]
8581        fn _vcvt_n_f32_s32(a: int32x2_t, n: i32) -> float32x2_t;
8582    }
8583    unsafe { _vcvt_n_f32_s32(a, N) }
8584}
8585#[doc = "Fixed-point convert to floating-point"]
8586#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"]
8587#[inline]
8588#[cfg(target_arch = "arm")]
8589#[target_feature(enable = "neon,v7")]
8590#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8591#[rustc_legacy_const_generics(1)]
8592#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8593pub fn vcvtq_n_f32_s32<const N: i32>(a: int32x4_t) -> float32x4_t {
8594    static_assert!(N >= 1 && N <= 32);
8595    unsafe extern "unadjusted" {
8596        #[cfg_attr(
8597            target_arch = "arm",
8598            link_name = "llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32"
8599        )]
8600        fn _vcvtq_n_f32_s32(a: int32x4_t, n: i32) -> float32x4_t;
8601    }
8602    unsafe { _vcvtq_n_f32_s32(a, N) }
8603}
8604#[doc = "Fixed-point convert to floating-point"]
8605#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"]
8606#[inline]
8607#[target_feature(enable = "neon")]
8608#[cfg(not(target_arch = "arm"))]
8609#[cfg_attr(test, assert_instr(scvtf, N = 2))]
8610#[rustc_legacy_const_generics(1)]
8611#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8612pub fn vcvt_n_f32_s32<const N: i32>(a: int32x2_t) -> float32x2_t {
8613    static_assert!(N >= 1 && N <= 32);
8614    unsafe extern "unadjusted" {
8615        #[cfg_attr(
8616            any(target_arch = "aarch64", target_arch = "arm64ec"),
8617            link_name = "llvm.aarch64.neon.vcvtfxs2fp.v2f32.v2i32"
8618        )]
8619        fn _vcvt_n_f32_s32(a: int32x2_t, n: i32) -> float32x2_t;
8620    }
8621    unsafe { _vcvt_n_f32_s32(a, N) }
8622}
8623#[doc = "Fixed-point convert to floating-point"]
8624#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"]
8625#[inline]
8626#[target_feature(enable = "neon")]
8627#[cfg(not(target_arch = "arm"))]
8628#[cfg_attr(test, assert_instr(scvtf, N = 2))]
8629#[rustc_legacy_const_generics(1)]
8630#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8631pub fn vcvtq_n_f32_s32<const N: i32>(a: int32x4_t) -> float32x4_t {
8632    static_assert!(N >= 1 && N <= 32);
8633    unsafe extern "unadjusted" {
8634        #[cfg_attr(
8635            any(target_arch = "aarch64", target_arch = "arm64ec"),
8636            link_name = "llvm.aarch64.neon.vcvtfxs2fp.v4f32.v4i32"
8637        )]
8638        fn _vcvtq_n_f32_s32(a: int32x4_t, n: i32) -> float32x4_t;
8639    }
8640    unsafe { _vcvtq_n_f32_s32(a, N) }
8641}
8642#[doc = "Fixed-point convert to floating-point"]
8643#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"]
8644#[inline]
8645#[cfg(target_arch = "arm")]
8646#[target_feature(enable = "neon,v7")]
8647#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8648#[rustc_legacy_const_generics(1)]
8649#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8650pub fn vcvt_n_f32_u32<const N: i32>(a: uint32x2_t) -> float32x2_t {
8651    static_assert!(N >= 1 && N <= 32);
8652    unsafe extern "unadjusted" {
8653        #[cfg_attr(
8654            target_arch = "arm",
8655            link_name = "llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32"
8656        )]
8657        fn _vcvt_n_f32_u32(a: uint32x2_t, n: i32) -> float32x2_t;
8658    }
8659    unsafe { _vcvt_n_f32_u32(a, N) }
8660}
8661#[doc = "Fixed-point convert to floating-point"]
8662#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"]
8663#[inline]
8664#[cfg(target_arch = "arm")]
8665#[target_feature(enable = "neon,v7")]
8666#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8667#[rustc_legacy_const_generics(1)]
8668#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8669pub fn vcvtq_n_f32_u32<const N: i32>(a: uint32x4_t) -> float32x4_t {
8670    static_assert!(N >= 1 && N <= 32);
8671    unsafe extern "unadjusted" {
8672        #[cfg_attr(
8673            target_arch = "arm",
8674            link_name = "llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32"
8675        )]
8676        fn _vcvtq_n_f32_u32(a: uint32x4_t, n: i32) -> float32x4_t;
8677    }
8678    unsafe { _vcvtq_n_f32_u32(a, N) }
8679}
8680#[doc = "Fixed-point convert to floating-point"]
8681#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"]
8682#[inline]
8683#[target_feature(enable = "neon")]
8684#[cfg(not(target_arch = "arm"))]
8685#[cfg_attr(test, assert_instr(ucvtf, N = 2))]
8686#[rustc_legacy_const_generics(1)]
8687#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8688pub fn vcvt_n_f32_u32<const N: i32>(a: uint32x2_t) -> float32x2_t {
8689    static_assert!(N >= 1 && N <= 32);
8690    unsafe extern "unadjusted" {
8691        #[cfg_attr(
8692            any(target_arch = "aarch64", target_arch = "arm64ec"),
8693            link_name = "llvm.aarch64.neon.vcvtfxu2fp.v2f32.v2i32"
8694        )]
8695        fn _vcvt_n_f32_u32(a: uint32x2_t, n: i32) -> float32x2_t;
8696    }
8697    unsafe { _vcvt_n_f32_u32(a, N) }
8698}
8699#[doc = "Fixed-point convert to floating-point"]
8700#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"]
8701#[inline]
8702#[target_feature(enable = "neon")]
8703#[cfg(not(target_arch = "arm"))]
8704#[cfg_attr(test, assert_instr(ucvtf, N = 2))]
8705#[rustc_legacy_const_generics(1)]
8706#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8707pub fn vcvtq_n_f32_u32<const N: i32>(a: uint32x4_t) -> float32x4_t {
8708    static_assert!(N >= 1 && N <= 32);
8709    unsafe extern "unadjusted" {
8710        #[cfg_attr(
8711            any(target_arch = "aarch64", target_arch = "arm64ec"),
8712            link_name = "llvm.aarch64.neon.vcvtfxu2fp.v4f32.v4i32"
8713        )]
8714        fn _vcvtq_n_f32_u32(a: uint32x4_t, n: i32) -> float32x4_t;
8715    }
8716    unsafe { _vcvtq_n_f32_u32(a, N) }
8717}
8718#[doc = "Floating-point convert to signed fixed-point"]
8719#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s16_f16)"]
8720#[inline]
8721#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8722#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8723#[cfg_attr(
8724    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8725    assert_instr(fcvtzs, N = 1)
8726)]
8727#[rustc_legacy_const_generics(1)]
8728#[target_feature(enable = "neon,fp16")]
8729#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8730pub fn vcvt_n_s16_f16<const N: i32>(a: float16x4_t) -> int16x4_t {
8731    static_assert!(N >= 1 && N <= 16);
8732    unsafe extern "unadjusted" {
8733        #[cfg_attr(
8734            target_arch = "arm",
8735            link_name = "llvm.arm.neon.vcvtfp2fxs.v4i16.v4f16"
8736        )]
8737        #[cfg_attr(
8738            any(target_arch = "aarch64", target_arch = "arm64ec"),
8739            link_name = "llvm.aarch64.neon.vcvtfp2fxs.v4i16.v4f16"
8740        )]
8741        fn _vcvt_n_s16_f16(a: float16x4_t, n: i32) -> int16x4_t;
8742    }
8743    unsafe { _vcvt_n_s16_f16(a, N) }
8744}
8745#[doc = "Floating-point convert to signed fixed-point"]
8746#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s16_f16)"]
8747#[inline]
8748#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8749#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8750#[cfg_attr(
8751    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8752    assert_instr(fcvtzs, N = 1)
8753)]
8754#[rustc_legacy_const_generics(1)]
8755#[target_feature(enable = "neon,fp16")]
8756#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8757pub fn vcvtq_n_s16_f16<const N: i32>(a: float16x8_t) -> int16x8_t {
8758    static_assert!(N >= 1 && N <= 16);
8759    unsafe extern "unadjusted" {
8760        #[cfg_attr(
8761            target_arch = "arm",
8762            link_name = "llvm.arm.neon.vcvtfp2fxs.v8i16.v8f16"
8763        )]
8764        #[cfg_attr(
8765            any(target_arch = "aarch64", target_arch = "arm64ec"),
8766            link_name = "llvm.aarch64.neon.vcvtfp2fxs.v8i16.v8f16"
8767        )]
8768        fn _vcvtq_n_s16_f16(a: float16x8_t, n: i32) -> int16x8_t;
8769    }
8770    unsafe { _vcvtq_n_s16_f16(a, N) }
8771}
8772#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8773#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"]
8774#[inline]
8775#[cfg(target_arch = "arm")]
8776#[target_feature(enable = "neon,v7")]
8777#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8778#[rustc_legacy_const_generics(1)]
8779#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8780pub fn vcvt_n_s32_f32<const N: i32>(a: float32x2_t) -> int32x2_t {
8781    static_assert!(N >= 1 && N <= 32);
8782    unsafe extern "unadjusted" {
8783        #[cfg_attr(
8784            target_arch = "arm",
8785            link_name = "llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32"
8786        )]
8787        fn _vcvt_n_s32_f32(a: float32x2_t, n: i32) -> int32x2_t;
8788    }
8789    unsafe { _vcvt_n_s32_f32(a, N) }
8790}
8791#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8792#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"]
8793#[inline]
8794#[cfg(target_arch = "arm")]
8795#[target_feature(enable = "neon,v7")]
8796#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8797#[rustc_legacy_const_generics(1)]
8798#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8799pub fn vcvtq_n_s32_f32<const N: i32>(a: float32x4_t) -> int32x4_t {
8800    static_assert!(N >= 1 && N <= 32);
8801    unsafe extern "unadjusted" {
8802        #[cfg_attr(
8803            target_arch = "arm",
8804            link_name = "llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32"
8805        )]
8806        fn _vcvtq_n_s32_f32(a: float32x4_t, n: i32) -> int32x4_t;
8807    }
8808    unsafe { _vcvtq_n_s32_f32(a, N) }
8809}
8810#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"]
8812#[inline]
8813#[target_feature(enable = "neon")]
8814#[cfg(not(target_arch = "arm"))]
8815#[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
8816#[rustc_legacy_const_generics(1)]
8817#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8818pub fn vcvt_n_s32_f32<const N: i32>(a: float32x2_t) -> int32x2_t {
8819    static_assert!(N >= 1 && N <= 32);
8820    unsafe extern "unadjusted" {
8821        #[cfg_attr(
8822            any(target_arch = "aarch64", target_arch = "arm64ec"),
8823            link_name = "llvm.aarch64.neon.vcvtfp2fxs.v2i32.v2f32"
8824        )]
8825        fn _vcvt_n_s32_f32(a: float32x2_t, n: i32) -> int32x2_t;
8826    }
8827    unsafe { _vcvt_n_s32_f32(a, N) }
8828}
8829#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"]
8831#[inline]
8832#[target_feature(enable = "neon")]
8833#[cfg(not(target_arch = "arm"))]
8834#[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
8835#[rustc_legacy_const_generics(1)]
8836#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8837pub fn vcvtq_n_s32_f32<const N: i32>(a: float32x4_t) -> int32x4_t {
8838    static_assert!(N >= 1 && N <= 32);
8839    unsafe extern "unadjusted" {
8840        #[cfg_attr(
8841            any(target_arch = "aarch64", target_arch = "arm64ec"),
8842            link_name = "llvm.aarch64.neon.vcvtfp2fxs.v4i32.v4f32"
8843        )]
8844        fn _vcvtq_n_s32_f32(a: float32x4_t, n: i32) -> int32x4_t;
8845    }
8846    unsafe { _vcvtq_n_s32_f32(a, N) }
8847}
8848#[doc = "Fixed-point convert to unsigned fixed-point, rounding toward zero"]
8849#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u16_f16)"]
8850#[inline]
8851#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8852#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8853#[cfg_attr(
8854    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8855    assert_instr(fcvtzu, N = 1)
8856)]
8857#[rustc_legacy_const_generics(1)]
8858#[target_feature(enable = "neon,fp16")]
8859#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8860pub fn vcvt_n_u16_f16<const N: i32>(a: float16x4_t) -> uint16x4_t {
8861    static_assert!(N >= 1 && N <= 16);
8862    unsafe extern "unadjusted" {
8863        #[cfg_attr(
8864            target_arch = "arm",
8865            link_name = "llvm.arm.neon.vcvtfp2fxu.v4i16.v4f16"
8866        )]
8867        #[cfg_attr(
8868            any(target_arch = "aarch64", target_arch = "arm64ec"),
8869            link_name = "llvm.aarch64.neon.vcvtfp2fxu.v4i16.v4f16"
8870        )]
8871        fn _vcvt_n_u16_f16(a: float16x4_t, n: i32) -> uint16x4_t;
8872    }
8873    unsafe { _vcvt_n_u16_f16(a, N) }
8874}
8875#[doc = "Fixed-point convert to unsigned fixed-point, rounding toward zero"]
8876#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u16_f16)"]
8877#[inline]
8878#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8879#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8880#[cfg_attr(
8881    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8882    assert_instr(fcvtzu, N = 1)
8883)]
8884#[rustc_legacy_const_generics(1)]
8885#[target_feature(enable = "neon,fp16")]
8886#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8887pub fn vcvtq_n_u16_f16<const N: i32>(a: float16x8_t) -> uint16x8_t {
8888    static_assert!(N >= 1 && N <= 16);
8889    unsafe extern "unadjusted" {
8890        #[cfg_attr(
8891            target_arch = "arm",
8892            link_name = "llvm.arm.neon.vcvtfp2fxu.v8i16.v8f16"
8893        )]
8894        #[cfg_attr(
8895            any(target_arch = "aarch64", target_arch = "arm64ec"),
8896            link_name = "llvm.aarch64.neon.vcvtfp2fxu.v8i16.v8f16"
8897        )]
8898        fn _vcvtq_n_u16_f16(a: float16x8_t, n: i32) -> uint16x8_t;
8899    }
8900    unsafe { _vcvtq_n_u16_f16(a, N) }
8901}
8902#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8903#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"]
8904#[inline]
8905#[cfg(target_arch = "arm")]
8906#[target_feature(enable = "neon,v7")]
8907#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8908#[rustc_legacy_const_generics(1)]
8909#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8910pub fn vcvt_n_u32_f32<const N: i32>(a: float32x2_t) -> uint32x2_t {
8911    static_assert!(N >= 1 && N <= 32);
8912    unsafe extern "unadjusted" {
8913        #[cfg_attr(
8914            target_arch = "arm",
8915            link_name = "llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32"
8916        )]
8917        fn _vcvt_n_u32_f32(a: float32x2_t, n: i32) -> uint32x2_t;
8918    }
8919    unsafe { _vcvt_n_u32_f32(a, N) }
8920}
8921#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8922#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"]
8923#[inline]
8924#[cfg(target_arch = "arm")]
8925#[target_feature(enable = "neon,v7")]
8926#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8927#[rustc_legacy_const_generics(1)]
8928#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8929pub fn vcvtq_n_u32_f32<const N: i32>(a: float32x4_t) -> uint32x4_t {
8930    static_assert!(N >= 1 && N <= 32);
8931    unsafe extern "unadjusted" {
8932        #[cfg_attr(
8933            target_arch = "arm",
8934            link_name = "llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32"
8935        )]
8936        fn _vcvtq_n_u32_f32(a: float32x4_t, n: i32) -> uint32x4_t;
8937    }
8938    unsafe { _vcvtq_n_u32_f32(a, N) }
8939}
8940#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8941#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"]
8942#[inline]
8943#[target_feature(enable = "neon")]
8944#[cfg(not(target_arch = "arm"))]
8945#[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
8946#[rustc_legacy_const_generics(1)]
8947#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8948pub fn vcvt_n_u32_f32<const N: i32>(a: float32x2_t) -> uint32x2_t {
8949    static_assert!(N >= 1 && N <= 32);
8950    unsafe extern "unadjusted" {
8951        #[cfg_attr(
8952            any(target_arch = "aarch64", target_arch = "arm64ec"),
8953            link_name = "llvm.aarch64.neon.vcvtfp2fxu.v2i32.v2f32"
8954        )]
8955        fn _vcvt_n_u32_f32(a: float32x2_t, n: i32) -> uint32x2_t;
8956    }
8957    unsafe { _vcvt_n_u32_f32(a, N) }
8958}
8959#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8960#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"]
8961#[inline]
8962#[target_feature(enable = "neon")]
8963#[cfg(not(target_arch = "arm"))]
8964#[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
8965#[rustc_legacy_const_generics(1)]
8966#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8967pub fn vcvtq_n_u32_f32<const N: i32>(a: float32x4_t) -> uint32x4_t {
8968    static_assert!(N >= 1 && N <= 32);
8969    unsafe extern "unadjusted" {
8970        #[cfg_attr(
8971            any(target_arch = "aarch64", target_arch = "arm64ec"),
8972            link_name = "llvm.aarch64.neon.vcvtfp2fxu.v4i32.v4f32"
8973        )]
8974        fn _vcvtq_n_u32_f32(a: float32x4_t, n: i32) -> uint32x4_t;
8975    }
8976    unsafe { _vcvtq_n_u32_f32(a, N) }
8977}
8978#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
8979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s16_f16)"]
8980#[inline]
8981#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8982#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8983#[cfg_attr(
8984    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8985    assert_instr(fcvtzs)
8986)]
8987#[target_feature(enable = "neon,fp16")]
8988#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8989pub fn vcvt_s16_f16(a: float16x4_t) -> int16x4_t {
8990    unsafe { simd_cast(a) }
8991}
8992#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
8993#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s16_f16)"]
8994#[inline]
8995#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8996#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8997#[cfg_attr(
8998    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8999    assert_instr(fcvtzs)
9000)]
9001#[target_feature(enable = "neon,fp16")]
9002#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9003pub fn vcvtq_s16_f16(a: float16x8_t) -> int16x8_t {
9004    unsafe { simd_cast(a) }
9005}
9006#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
9007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s32_f32)"]
9008#[inline]
9009#[target_feature(enable = "neon")]
9010#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9011#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9012#[cfg_attr(
9013    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9014    assert_instr(fcvtzs)
9015)]
9016#[cfg_attr(
9017    not(target_arch = "arm"),
9018    stable(feature = "neon_intrinsics", since = "1.59.0")
9019)]
9020#[cfg_attr(
9021    target_arch = "arm",
9022    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9023)]
9024pub fn vcvt_s32_f32(a: float32x2_t) -> int32x2_t {
9025    unsafe extern "unadjusted" {
9026        #[cfg_attr(target_arch = "arm", link_name = "llvm.fptosi.sat.v2i32.v2f32")]
9027        #[cfg_attr(
9028            any(target_arch = "aarch64", target_arch = "arm64ec"),
9029            link_name = "llvm.fptosi.sat.v2i32.v2f32"
9030        )]
9031        fn _vcvt_s32_f32(a: float32x2_t) -> int32x2_t;
9032    }
9033    unsafe { _vcvt_s32_f32(a) }
9034}
9035#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
9036#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s32_f32)"]
9037#[inline]
9038#[target_feature(enable = "neon")]
9039#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9040#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9041#[cfg_attr(
9042    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9043    assert_instr(fcvtzs)
9044)]
9045#[cfg_attr(
9046    not(target_arch = "arm"),
9047    stable(feature = "neon_intrinsics", since = "1.59.0")
9048)]
9049#[cfg_attr(
9050    target_arch = "arm",
9051    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9052)]
9053pub fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t {
9054    unsafe extern "unadjusted" {
9055        #[cfg_attr(target_arch = "arm", link_name = "llvm.fptosi.sat.v4i32.v4f32")]
9056        #[cfg_attr(
9057            any(target_arch = "aarch64", target_arch = "arm64ec"),
9058            link_name = "llvm.fptosi.sat.v4i32.v4f32"
9059        )]
9060        fn _vcvtq_s32_f32(a: float32x4_t) -> int32x4_t;
9061    }
9062    unsafe { _vcvtq_s32_f32(a) }
9063}
9064#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
9065#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u16_f16)"]
9066#[inline]
9067#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9068#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9069#[cfg_attr(
9070    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9071    assert_instr(fcvtzu)
9072)]
9073#[target_feature(enable = "neon,fp16")]
9074#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9075pub fn vcvt_u16_f16(a: float16x4_t) -> uint16x4_t {
9076    unsafe { simd_cast(a) }
9077}
9078#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
9079#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u16_f16)"]
9080#[inline]
9081#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9082#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9083#[cfg_attr(
9084    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9085    assert_instr(fcvtzu)
9086)]
9087#[target_feature(enable = "neon,fp16")]
9088#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9089pub fn vcvtq_u16_f16(a: float16x8_t) -> uint16x8_t {
9090    unsafe { simd_cast(a) }
9091}
9092#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
9093#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u32_f32)"]
9094#[inline]
9095#[target_feature(enable = "neon")]
9096#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9097#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9098#[cfg_attr(
9099    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9100    assert_instr(fcvtzu)
9101)]
9102#[cfg_attr(
9103    not(target_arch = "arm"),
9104    stable(feature = "neon_intrinsics", since = "1.59.0")
9105)]
9106#[cfg_attr(
9107    target_arch = "arm",
9108    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9109)]
9110pub fn vcvt_u32_f32(a: float32x2_t) -> uint32x2_t {
9111    unsafe extern "unadjusted" {
9112        #[cfg_attr(target_arch = "arm", link_name = "llvm.fptoui.sat.v2i32.v2f32")]
9113        #[cfg_attr(
9114            any(target_arch = "aarch64", target_arch = "arm64ec"),
9115            link_name = "llvm.fptoui.sat.v2i32.v2f32"
9116        )]
9117        fn _vcvt_u32_f32(a: float32x2_t) -> uint32x2_t;
9118    }
9119    unsafe { _vcvt_u32_f32(a) }
9120}
9121#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
9122#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u32_f32)"]
9123#[inline]
9124#[target_feature(enable = "neon")]
9125#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9126#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9127#[cfg_attr(
9128    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9129    assert_instr(fcvtzu)
9130)]
9131#[cfg_attr(
9132    not(target_arch = "arm"),
9133    stable(feature = "neon_intrinsics", since = "1.59.0")
9134)]
9135#[cfg_attr(
9136    target_arch = "arm",
9137    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9138)]
9139pub fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t {
9140    unsafe extern "unadjusted" {
9141        #[cfg_attr(target_arch = "arm", link_name = "llvm.fptoui.sat.v4i32.v4f32")]
9142        #[cfg_attr(
9143            any(target_arch = "aarch64", target_arch = "arm64ec"),
9144            link_name = "llvm.fptoui.sat.v4i32.v4f32"
9145        )]
9146        fn _vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t;
9147    }
9148    unsafe { _vcvtq_u32_f32(a) }
9149}
9150#[doc = "Dot product arithmetic (indexed)"]
9151#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_s32)"]
9152#[inline]
9153#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9154#[target_feature(enable = "neon,dotprod")]
9155#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
9156#[cfg_attr(
9157    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9158    assert_instr(sdot, LANE = 0)
9159)]
9160#[rustc_legacy_const_generics(3)]
9161#[cfg_attr(
9162    not(target_arch = "arm"),
9163    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9164)]
9165#[cfg_attr(
9166    target_arch = "arm",
9167    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9168)]
9169pub fn vdot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t {
9170    static_assert_uimm_bits!(LANE, 1);
9171    unsafe {
9172        let c: int32x2_t = transmute(c);
9173        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
9174        vdot_s32(a, b, transmute(c))
9175    }
9176}
9177#[doc = "Dot product arithmetic (indexed)"]
9178#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32)"]
9179#[inline]
9180#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9181#[target_feature(enable = "neon,dotprod")]
9182#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
9183#[cfg_attr(
9184    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9185    assert_instr(sdot, LANE = 0)
9186)]
9187#[rustc_legacy_const_generics(3)]
9188#[cfg_attr(
9189    not(target_arch = "arm"),
9190    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9191)]
9192#[cfg_attr(
9193    target_arch = "arm",
9194    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9195)]
9196pub fn vdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x8_t) -> int32x4_t {
9197    static_assert_uimm_bits!(LANE, 1);
9198    unsafe {
9199        let c: int32x2_t = transmute(c);
9200        let c: int32x4_t =
9201            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
9202        vdotq_s32(a, b, transmute(c))
9203    }
9204}
9205#[doc = "Dot product arithmetic (indexed)"]
9206#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32)"]
9207#[inline]
9208#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9209#[target_feature(enable = "neon,dotprod")]
9210#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
9211#[cfg_attr(
9212    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9213    assert_instr(udot, LANE = 0)
9214)]
9215#[rustc_legacy_const_generics(3)]
9216#[cfg_attr(
9217    not(target_arch = "arm"),
9218    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9219)]
9220#[cfg_attr(
9221    target_arch = "arm",
9222    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9223)]
9224pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t {
9225    static_assert_uimm_bits!(LANE, 1);
9226    unsafe {
9227        let c: uint32x2_t = transmute(c);
9228        let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
9229        vdot_u32(a, b, transmute(c))
9230    }
9231}
9232#[doc = "Dot product arithmetic (indexed)"]
9233#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32)"]
9234#[inline]
9235#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9236#[target_feature(enable = "neon,dotprod")]
9237#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
9238#[cfg_attr(
9239    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9240    assert_instr(udot, LANE = 0)
9241)]
9242#[rustc_legacy_const_generics(3)]
9243#[cfg_attr(
9244    not(target_arch = "arm"),
9245    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9246)]
9247#[cfg_attr(
9248    target_arch = "arm",
9249    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9250)]
9251pub fn vdotq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x8_t) -> uint32x4_t {
9252    static_assert_uimm_bits!(LANE, 1);
9253    unsafe {
9254        let c: uint32x2_t = transmute(c);
9255        let c: uint32x4_t =
9256            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
9257        vdotq_u32(a, b, transmute(c))
9258    }
9259}
9260#[doc = "Dot product arithmetic (vector)"]
9261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_s32)"]
9262#[inline]
9263#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9264#[target_feature(enable = "neon,dotprod")]
9265#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))]
9266#[cfg_attr(
9267    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9268    assert_instr(sdot)
9269)]
9270#[cfg_attr(
9271    not(target_arch = "arm"),
9272    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9273)]
9274#[cfg_attr(
9275    target_arch = "arm",
9276    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9277)]
9278pub fn vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t {
9279    unsafe extern "unadjusted" {
9280        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sdot.v2i32.v8i8")]
9281        #[cfg_attr(
9282            any(target_arch = "aarch64", target_arch = "arm64ec"),
9283            link_name = "llvm.aarch64.neon.sdot.v2i32.v8i8"
9284        )]
9285        fn _vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t;
9286    }
9287    unsafe { _vdot_s32(a, b, c) }
9288}
9289#[doc = "Dot product arithmetic (vector)"]
9290#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_s32)"]
9291#[inline]
9292#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9293#[target_feature(enable = "neon,dotprod")]
9294#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))]
9295#[cfg_attr(
9296    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9297    assert_instr(sdot)
9298)]
9299#[cfg_attr(
9300    not(target_arch = "arm"),
9301    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9302)]
9303#[cfg_attr(
9304    target_arch = "arm",
9305    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9306)]
9307pub fn vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
9308    unsafe extern "unadjusted" {
9309        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sdot.v4i32.v16i8")]
9310        #[cfg_attr(
9311            any(target_arch = "aarch64", target_arch = "arm64ec"),
9312            link_name = "llvm.aarch64.neon.sdot.v4i32.v16i8"
9313        )]
9314        fn _vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t;
9315    }
9316    unsafe { _vdotq_s32(a, b, c) }
9317}
9318#[doc = "Dot product arithmetic (vector)"]
9319#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_u32)"]
9320#[inline]
9321#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9322#[target_feature(enable = "neon,dotprod")]
9323#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))]
9324#[cfg_attr(
9325    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9326    assert_instr(udot)
9327)]
9328#[cfg_attr(
9329    not(target_arch = "arm"),
9330    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9331)]
9332#[cfg_attr(
9333    target_arch = "arm",
9334    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9335)]
9336pub fn vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t {
9337    unsafe extern "unadjusted" {
9338        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.udot.v2i32.v8i8")]
9339        #[cfg_attr(
9340            any(target_arch = "aarch64", target_arch = "arm64ec"),
9341            link_name = "llvm.aarch64.neon.udot.v2i32.v8i8"
9342        )]
9343        fn _vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t;
9344    }
9345    unsafe { _vdot_u32(a, b, c) }
9346}
9347#[doc = "Dot product arithmetic (vector)"]
9348#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_u32)"]
9349#[inline]
9350#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9351#[target_feature(enable = "neon,dotprod")]
9352#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))]
9353#[cfg_attr(
9354    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9355    assert_instr(udot)
9356)]
9357#[cfg_attr(
9358    not(target_arch = "arm"),
9359    unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9360)]
9361#[cfg_attr(
9362    target_arch = "arm",
9363    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9364)]
9365pub fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
9366    unsafe extern "unadjusted" {
9367        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.udot.v4i32.v16i8")]
9368        #[cfg_attr(
9369            any(target_arch = "aarch64", target_arch = "arm64ec"),
9370            link_name = "llvm.aarch64.neon.udot.v4i32.v16i8"
9371        )]
9372        fn _vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t;
9373    }
9374    unsafe { _vdotq_u32(a, b, c) }
9375}
9376#[doc = "Set all vector lanes to the same value"]
9377#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f16)"]
9378#[inline]
9379#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9380#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9381#[cfg_attr(
9382    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9383    assert_instr(dup, N = 2)
9384)]
9385#[rustc_legacy_const_generics(1)]
9386#[target_feature(enable = "neon,fp16")]
9387#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9388pub fn vdup_lane_f16<const N: i32>(a: float16x4_t) -> float16x4_t {
9389    static_assert_uimm_bits!(N, 2);
9390    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9391}
9392#[doc = "Set all vector lanes to the same value"]
9393#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f16)"]
9394#[inline]
9395#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9396#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9397#[cfg_attr(
9398    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9399    assert_instr(dup, N = 2)
9400)]
9401#[rustc_legacy_const_generics(1)]
9402#[target_feature(enable = "neon,fp16")]
9403#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9404pub fn vdupq_lane_f16<const N: i32>(a: float16x4_t) -> float16x8_t {
9405    static_assert_uimm_bits!(N, 2);
9406    unsafe {
9407        simd_shuffle!(
9408            a,
9409            a,
9410            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9411        )
9412    }
9413}
9414#[doc = "Set all vector lanes to the same value"]
9415#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f32)"]
9416#[inline]
9417#[target_feature(enable = "neon")]
9418#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9419#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9420#[cfg_attr(
9421    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9422    assert_instr(dup, N = 1)
9423)]
9424#[rustc_legacy_const_generics(1)]
9425#[cfg_attr(
9426    not(target_arch = "arm"),
9427    stable(feature = "neon_intrinsics", since = "1.59.0")
9428)]
9429#[cfg_attr(
9430    target_arch = "arm",
9431    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9432)]
9433pub fn vdup_lane_f32<const N: i32>(a: float32x2_t) -> float32x2_t {
9434    static_assert_uimm_bits!(N, 1);
9435    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
9436}
9437#[doc = "Set all vector lanes to the same value"]
9438#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s32)"]
9439#[inline]
9440#[target_feature(enable = "neon")]
9441#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9442#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9443#[cfg_attr(
9444    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9445    assert_instr(dup, N = 1)
9446)]
9447#[rustc_legacy_const_generics(1)]
9448#[cfg_attr(
9449    not(target_arch = "arm"),
9450    stable(feature = "neon_intrinsics", since = "1.59.0")
9451)]
9452#[cfg_attr(
9453    target_arch = "arm",
9454    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9455)]
9456pub fn vdup_lane_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
9457    static_assert_uimm_bits!(N, 1);
9458    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
9459}
9460#[doc = "Set all vector lanes to the same value"]
9461#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u32)"]
9462#[inline]
9463#[target_feature(enable = "neon")]
9464#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9465#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9466#[cfg_attr(
9467    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9468    assert_instr(dup, N = 1)
9469)]
9470#[rustc_legacy_const_generics(1)]
9471#[cfg_attr(
9472    not(target_arch = "arm"),
9473    stable(feature = "neon_intrinsics", since = "1.59.0")
9474)]
9475#[cfg_attr(
9476    target_arch = "arm",
9477    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9478)]
9479pub fn vdup_lane_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
9480    static_assert_uimm_bits!(N, 1);
9481    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
9482}
9483#[doc = "Set all vector lanes to the same value"]
9484#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f32)"]
9485#[inline]
9486#[target_feature(enable = "neon")]
9487#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9488#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9489#[cfg_attr(
9490    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9491    assert_instr(dup, N = 1)
9492)]
9493#[rustc_legacy_const_generics(1)]
9494#[cfg_attr(
9495    not(target_arch = "arm"),
9496    stable(feature = "neon_intrinsics", since = "1.59.0")
9497)]
9498#[cfg_attr(
9499    target_arch = "arm",
9500    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9501)]
9502pub fn vdupq_lane_f32<const N: i32>(a: float32x2_t) -> float32x4_t {
9503    static_assert_uimm_bits!(N, 1);
9504    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9505}
9506#[doc = "Set all vector lanes to the same value"]
9507#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s32)"]
9508#[inline]
9509#[target_feature(enable = "neon")]
9510#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9511#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9512#[cfg_attr(
9513    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9514    assert_instr(dup, N = 1)
9515)]
9516#[rustc_legacy_const_generics(1)]
9517#[cfg_attr(
9518    not(target_arch = "arm"),
9519    stable(feature = "neon_intrinsics", since = "1.59.0")
9520)]
9521#[cfg_attr(
9522    target_arch = "arm",
9523    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9524)]
9525pub fn vdupq_lane_s32<const N: i32>(a: int32x2_t) -> int32x4_t {
9526    static_assert_uimm_bits!(N, 1);
9527    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9528}
9529#[doc = "Set all vector lanes to the same value"]
9530#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u32)"]
9531#[inline]
9532#[target_feature(enable = "neon")]
9533#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9534#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9535#[cfg_attr(
9536    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9537    assert_instr(dup, N = 1)
9538)]
9539#[rustc_legacy_const_generics(1)]
9540#[cfg_attr(
9541    not(target_arch = "arm"),
9542    stable(feature = "neon_intrinsics", since = "1.59.0")
9543)]
9544#[cfg_attr(
9545    target_arch = "arm",
9546    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9547)]
9548pub fn vdupq_lane_u32<const N: i32>(a: uint32x2_t) -> uint32x4_t {
9549    static_assert_uimm_bits!(N, 1);
9550    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9551}
9552#[doc = "Set all vector lanes to the same value"]
9553#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p16)"]
9554#[inline]
9555#[target_feature(enable = "neon")]
9556#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9557#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9558#[cfg_attr(
9559    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9560    assert_instr(dup, N = 2)
9561)]
9562#[rustc_legacy_const_generics(1)]
9563#[cfg_attr(
9564    not(target_arch = "arm"),
9565    stable(feature = "neon_intrinsics", since = "1.59.0")
9566)]
9567#[cfg_attr(
9568    target_arch = "arm",
9569    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9570)]
9571pub fn vdup_lane_p16<const N: i32>(a: poly16x4_t) -> poly16x4_t {
9572    static_assert_uimm_bits!(N, 2);
9573    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9574}
9575#[doc = "Set all vector lanes to the same value"]
9576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s16)"]
9577#[inline]
9578#[target_feature(enable = "neon")]
9579#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9580#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9581#[cfg_attr(
9582    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9583    assert_instr(dup, N = 2)
9584)]
9585#[rustc_legacy_const_generics(1)]
9586#[cfg_attr(
9587    not(target_arch = "arm"),
9588    stable(feature = "neon_intrinsics", since = "1.59.0")
9589)]
9590#[cfg_attr(
9591    target_arch = "arm",
9592    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9593)]
9594pub fn vdup_lane_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
9595    static_assert_uimm_bits!(N, 2);
9596    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9597}
9598#[doc = "Set all vector lanes to the same value"]
9599#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u16)"]
9600#[inline]
9601#[target_feature(enable = "neon")]
9602#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9603#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9604#[cfg_attr(
9605    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9606    assert_instr(dup, N = 2)
9607)]
9608#[rustc_legacy_const_generics(1)]
9609#[cfg_attr(
9610    not(target_arch = "arm"),
9611    stable(feature = "neon_intrinsics", since = "1.59.0")
9612)]
9613#[cfg_attr(
9614    target_arch = "arm",
9615    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9616)]
9617pub fn vdup_lane_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
9618    static_assert_uimm_bits!(N, 2);
9619    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9620}
9621#[doc = "Set all vector lanes to the same value"]
9622#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p16)"]
9623#[inline]
9624#[target_feature(enable = "neon")]
9625#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9626#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9627#[cfg_attr(
9628    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9629    assert_instr(dup, N = 2)
9630)]
9631#[rustc_legacy_const_generics(1)]
9632#[cfg_attr(
9633    not(target_arch = "arm"),
9634    stable(feature = "neon_intrinsics", since = "1.59.0")
9635)]
9636#[cfg_attr(
9637    target_arch = "arm",
9638    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9639)]
9640pub fn vdupq_lane_p16<const N: i32>(a: poly16x4_t) -> poly16x8_t {
9641    static_assert_uimm_bits!(N, 2);
9642    unsafe {
9643        simd_shuffle!(
9644            a,
9645            a,
9646            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9647        )
9648    }
9649}
9650#[doc = "Set all vector lanes to the same value"]
9651#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s16)"]
9652#[inline]
9653#[target_feature(enable = "neon")]
9654#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9655#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9656#[cfg_attr(
9657    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9658    assert_instr(dup, N = 2)
9659)]
9660#[rustc_legacy_const_generics(1)]
9661#[cfg_attr(
9662    not(target_arch = "arm"),
9663    stable(feature = "neon_intrinsics", since = "1.59.0")
9664)]
9665#[cfg_attr(
9666    target_arch = "arm",
9667    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9668)]
9669pub fn vdupq_lane_s16<const N: i32>(a: int16x4_t) -> int16x8_t {
9670    static_assert_uimm_bits!(N, 2);
9671    unsafe {
9672        simd_shuffle!(
9673            a,
9674            a,
9675            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9676        )
9677    }
9678}
9679#[doc = "Set all vector lanes to the same value"]
9680#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u16)"]
9681#[inline]
9682#[target_feature(enable = "neon")]
9683#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9684#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9685#[cfg_attr(
9686    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9687    assert_instr(dup, N = 2)
9688)]
9689#[rustc_legacy_const_generics(1)]
9690#[cfg_attr(
9691    not(target_arch = "arm"),
9692    stable(feature = "neon_intrinsics", since = "1.59.0")
9693)]
9694#[cfg_attr(
9695    target_arch = "arm",
9696    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9697)]
9698pub fn vdupq_lane_u16<const N: i32>(a: uint16x4_t) -> uint16x8_t {
9699    static_assert_uimm_bits!(N, 2);
9700    unsafe {
9701        simd_shuffle!(
9702            a,
9703            a,
9704            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9705        )
9706    }
9707}
9708#[doc = "Set all vector lanes to the same value"]
9709#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p8)"]
9710#[inline]
9711#[target_feature(enable = "neon")]
9712#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9713#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9714#[cfg_attr(
9715    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9716    assert_instr(dup, N = 4)
9717)]
9718#[rustc_legacy_const_generics(1)]
9719#[cfg_attr(
9720    not(target_arch = "arm"),
9721    stable(feature = "neon_intrinsics", since = "1.59.0")
9722)]
9723#[cfg_attr(
9724    target_arch = "arm",
9725    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9726)]
9727pub fn vdup_lane_p8<const N: i32>(a: poly8x8_t) -> poly8x8_t {
9728    static_assert_uimm_bits!(N, 3);
9729    unsafe {
9730        simd_shuffle!(
9731            a,
9732            a,
9733            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9734        )
9735    }
9736}
9737#[doc = "Set all vector lanes to the same value"]
9738#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s8)"]
9739#[inline]
9740#[target_feature(enable = "neon")]
9741#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9742#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9743#[cfg_attr(
9744    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9745    assert_instr(dup, N = 4)
9746)]
9747#[rustc_legacy_const_generics(1)]
9748#[cfg_attr(
9749    not(target_arch = "arm"),
9750    stable(feature = "neon_intrinsics", since = "1.59.0")
9751)]
9752#[cfg_attr(
9753    target_arch = "arm",
9754    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9755)]
9756pub fn vdup_lane_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
9757    static_assert_uimm_bits!(N, 3);
9758    unsafe {
9759        simd_shuffle!(
9760            a,
9761            a,
9762            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9763        )
9764    }
9765}
9766#[doc = "Set all vector lanes to the same value"]
9767#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u8)"]
9768#[inline]
9769#[target_feature(enable = "neon")]
9770#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9771#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9772#[cfg_attr(
9773    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9774    assert_instr(dup, N = 4)
9775)]
9776#[rustc_legacy_const_generics(1)]
9777#[cfg_attr(
9778    not(target_arch = "arm"),
9779    stable(feature = "neon_intrinsics", since = "1.59.0")
9780)]
9781#[cfg_attr(
9782    target_arch = "arm",
9783    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9784)]
9785pub fn vdup_lane_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
9786    static_assert_uimm_bits!(N, 3);
9787    unsafe {
9788        simd_shuffle!(
9789            a,
9790            a,
9791            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9792        )
9793    }
9794}
9795#[doc = "Set all vector lanes to the same value"]
9796#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p8)"]
9797#[inline]
9798#[target_feature(enable = "neon")]
9799#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9800#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9801#[cfg_attr(
9802    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9803    assert_instr(dup, N = 4)
9804)]
9805#[rustc_legacy_const_generics(1)]
9806#[cfg_attr(
9807    not(target_arch = "arm"),
9808    stable(feature = "neon_intrinsics", since = "1.59.0")
9809)]
9810#[cfg_attr(
9811    target_arch = "arm",
9812    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9813)]
9814pub fn vdupq_lane_p8<const N: i32>(a: poly8x8_t) -> poly8x16_t {
9815    static_assert_uimm_bits!(N, 3);
9816    unsafe {
9817        simd_shuffle!(
9818            a,
9819            a,
9820            [
9821                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
9822                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
9823            ]
9824        )
9825    }
9826}
9827#[doc = "Set all vector lanes to the same value"]
9828#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s8)"]
9829#[inline]
9830#[target_feature(enable = "neon")]
9831#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9832#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9833#[cfg_attr(
9834    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9835    assert_instr(dup, N = 4)
9836)]
9837#[rustc_legacy_const_generics(1)]
9838#[cfg_attr(
9839    not(target_arch = "arm"),
9840    stable(feature = "neon_intrinsics", since = "1.59.0")
9841)]
9842#[cfg_attr(
9843    target_arch = "arm",
9844    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9845)]
9846pub fn vdupq_lane_s8<const N: i32>(a: int8x8_t) -> int8x16_t {
9847    static_assert_uimm_bits!(N, 3);
9848    unsafe {
9849        simd_shuffle!(
9850            a,
9851            a,
9852            [
9853                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
9854                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
9855            ]
9856        )
9857    }
9858}
9859#[doc = "Set all vector lanes to the same value"]
9860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u8)"]
9861#[inline]
9862#[target_feature(enable = "neon")]
9863#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9864#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9865#[cfg_attr(
9866    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9867    assert_instr(dup, N = 4)
9868)]
9869#[rustc_legacy_const_generics(1)]
9870#[cfg_attr(
9871    not(target_arch = "arm"),
9872    stable(feature = "neon_intrinsics", since = "1.59.0")
9873)]
9874#[cfg_attr(
9875    target_arch = "arm",
9876    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9877)]
9878pub fn vdupq_lane_u8<const N: i32>(a: uint8x8_t) -> uint8x16_t {
9879    static_assert_uimm_bits!(N, 3);
9880    unsafe {
9881        simd_shuffle!(
9882            a,
9883            a,
9884            [
9885                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
9886                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
9887            ]
9888        )
9889    }
9890}
9891#[doc = "Set all vector lanes to the same value"]
9892#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s64)"]
9893#[inline]
9894#[target_feature(enable = "neon")]
9895#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9896#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
9897#[cfg_attr(
9898    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9899    assert_instr(nop, N = 0)
9900)]
9901#[rustc_legacy_const_generics(1)]
9902#[cfg_attr(
9903    not(target_arch = "arm"),
9904    stable(feature = "neon_intrinsics", since = "1.59.0")
9905)]
9906#[cfg_attr(
9907    target_arch = "arm",
9908    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9909)]
9910pub fn vdup_lane_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
9911    static_assert!(N == 0);
9912    a
9913}
9914#[doc = "Set all vector lanes to the same value"]
9915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u64)"]
9916#[inline]
9917#[target_feature(enable = "neon")]
9918#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9919#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
9920#[cfg_attr(
9921    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9922    assert_instr(nop, N = 0)
9923)]
9924#[rustc_legacy_const_generics(1)]
9925#[cfg_attr(
9926    not(target_arch = "arm"),
9927    stable(feature = "neon_intrinsics", since = "1.59.0")
9928)]
9929#[cfg_attr(
9930    target_arch = "arm",
9931    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9932)]
9933pub fn vdup_lane_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
9934    static_assert!(N == 0);
9935    a
9936}
9937#[doc = "Set all vector lanes to the same value"]
9938#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f16)"]
9939#[inline]
9940#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9941#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
9942#[cfg_attr(
9943    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9944    assert_instr(dup, N = 4)
9945)]
9946#[rustc_legacy_const_generics(1)]
9947#[target_feature(enable = "neon,fp16")]
9948#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9949pub fn vdup_laneq_f16<const N: i32>(a: float16x8_t) -> float16x4_t {
9950    static_assert_uimm_bits!(N, 3);
9951    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9952}
9953#[doc = "Set all vector lanes to the same value"]
9954#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f16)"]
9955#[inline]
9956#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9957#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
9958#[cfg_attr(
9959    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9960    assert_instr(dup, N = 4)
9961)]
9962#[rustc_legacy_const_generics(1)]
9963#[target_feature(enable = "neon,fp16")]
9964#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9965pub fn vdupq_laneq_f16<const N: i32>(a: float16x8_t) -> float16x8_t {
9966    static_assert_uimm_bits!(N, 3);
9967    unsafe {
9968        simd_shuffle!(
9969            a,
9970            a,
9971            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9972        )
9973    }
9974}
9975#[doc = "Set all vector lanes to the same value"]
9976#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f32)"]
9977#[inline]
9978#[target_feature(enable = "neon")]
9979#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9980#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
9981#[cfg_attr(
9982    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9983    assert_instr(dup, N = 2)
9984)]
9985#[rustc_legacy_const_generics(1)]
9986#[cfg_attr(
9987    not(target_arch = "arm"),
9988    stable(feature = "neon_intrinsics", since = "1.59.0")
9989)]
9990#[cfg_attr(
9991    target_arch = "arm",
9992    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9993)]
9994pub fn vdup_laneq_f32<const N: i32>(a: float32x4_t) -> float32x2_t {
9995    static_assert_uimm_bits!(N, 2);
9996    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
9997}
9998#[doc = "Set all vector lanes to the same value"]
9999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s32)"]
10000#[inline]
10001#[target_feature(enable = "neon")]
10002#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10003#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
10004#[cfg_attr(
10005    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10006    assert_instr(dup, N = 2)
10007)]
10008#[rustc_legacy_const_generics(1)]
10009#[cfg_attr(
10010    not(target_arch = "arm"),
10011    stable(feature = "neon_intrinsics", since = "1.59.0")
10012)]
10013#[cfg_attr(
10014    target_arch = "arm",
10015    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10016)]
10017pub fn vdup_laneq_s32<const N: i32>(a: int32x4_t) -> int32x2_t {
10018    static_assert_uimm_bits!(N, 2);
10019    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
10020}
10021#[doc = "Set all vector lanes to the same value"]
10022#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u32)"]
10023#[inline]
10024#[target_feature(enable = "neon")]
10025#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10026#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
10027#[cfg_attr(
10028    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10029    assert_instr(dup, N = 2)
10030)]
10031#[rustc_legacy_const_generics(1)]
10032#[cfg_attr(
10033    not(target_arch = "arm"),
10034    stable(feature = "neon_intrinsics", since = "1.59.0")
10035)]
10036#[cfg_attr(
10037    target_arch = "arm",
10038    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10039)]
10040pub fn vdup_laneq_u32<const N: i32>(a: uint32x4_t) -> uint32x2_t {
10041    static_assert_uimm_bits!(N, 2);
10042    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
10043}
10044#[doc = "Set all vector lanes to the same value"]
10045#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f32)"]
10046#[inline]
10047#[target_feature(enable = "neon")]
10048#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10049#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
10050#[cfg_attr(
10051    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10052    assert_instr(dup, N = 2)
10053)]
10054#[rustc_legacy_const_generics(1)]
10055#[cfg_attr(
10056    not(target_arch = "arm"),
10057    stable(feature = "neon_intrinsics", since = "1.59.0")
10058)]
10059#[cfg_attr(
10060    target_arch = "arm",
10061    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10062)]
10063pub fn vdupq_laneq_f32<const N: i32>(a: float32x4_t) -> float32x4_t {
10064    static_assert_uimm_bits!(N, 2);
10065    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10066}
10067#[doc = "Set all vector lanes to the same value"]
10068#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s32)"]
10069#[inline]
10070#[target_feature(enable = "neon")]
10071#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10072#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
10073#[cfg_attr(
10074    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10075    assert_instr(dup, N = 2)
10076)]
10077#[rustc_legacy_const_generics(1)]
10078#[cfg_attr(
10079    not(target_arch = "arm"),
10080    stable(feature = "neon_intrinsics", since = "1.59.0")
10081)]
10082#[cfg_attr(
10083    target_arch = "arm",
10084    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10085)]
10086pub fn vdupq_laneq_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
10087    static_assert_uimm_bits!(N, 2);
10088    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10089}
10090#[doc = "Set all vector lanes to the same value"]
10091#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u32)"]
10092#[inline]
10093#[target_feature(enable = "neon")]
10094#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10095#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
10096#[cfg_attr(
10097    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10098    assert_instr(dup, N = 2)
10099)]
10100#[rustc_legacy_const_generics(1)]
10101#[cfg_attr(
10102    not(target_arch = "arm"),
10103    stable(feature = "neon_intrinsics", since = "1.59.0")
10104)]
10105#[cfg_attr(
10106    target_arch = "arm",
10107    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10108)]
10109pub fn vdupq_laneq_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
10110    static_assert_uimm_bits!(N, 2);
10111    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10112}
10113#[doc = "Set all vector lanes to the same value"]
10114#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p16)"]
10115#[inline]
10116#[target_feature(enable = "neon")]
10117#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10118#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10119#[cfg_attr(
10120    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10121    assert_instr(dup, N = 4)
10122)]
10123#[rustc_legacy_const_generics(1)]
10124#[cfg_attr(
10125    not(target_arch = "arm"),
10126    stable(feature = "neon_intrinsics", since = "1.59.0")
10127)]
10128#[cfg_attr(
10129    target_arch = "arm",
10130    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10131)]
10132pub fn vdup_laneq_p16<const N: i32>(a: poly16x8_t) -> poly16x4_t {
10133    static_assert_uimm_bits!(N, 3);
10134    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10135}
10136#[doc = "Set all vector lanes to the same value"]
10137#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s16)"]
10138#[inline]
10139#[target_feature(enable = "neon")]
10140#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10141#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10142#[cfg_attr(
10143    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10144    assert_instr(dup, N = 4)
10145)]
10146#[rustc_legacy_const_generics(1)]
10147#[cfg_attr(
10148    not(target_arch = "arm"),
10149    stable(feature = "neon_intrinsics", since = "1.59.0")
10150)]
10151#[cfg_attr(
10152    target_arch = "arm",
10153    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10154)]
10155pub fn vdup_laneq_s16<const N: i32>(a: int16x8_t) -> int16x4_t {
10156    static_assert_uimm_bits!(N, 3);
10157    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10158}
10159#[doc = "Set all vector lanes to the same value"]
10160#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u16)"]
10161#[inline]
10162#[target_feature(enable = "neon")]
10163#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10164#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10165#[cfg_attr(
10166    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10167    assert_instr(dup, N = 4)
10168)]
10169#[rustc_legacy_const_generics(1)]
10170#[cfg_attr(
10171    not(target_arch = "arm"),
10172    stable(feature = "neon_intrinsics", since = "1.59.0")
10173)]
10174#[cfg_attr(
10175    target_arch = "arm",
10176    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10177)]
10178pub fn vdup_laneq_u16<const N: i32>(a: uint16x8_t) -> uint16x4_t {
10179    static_assert_uimm_bits!(N, 3);
10180    unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10181}
10182#[doc = "Set all vector lanes to the same value"]
10183#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p16)"]
10184#[inline]
10185#[target_feature(enable = "neon")]
10186#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10187#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10188#[cfg_attr(
10189    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10190    assert_instr(dup, N = 4)
10191)]
10192#[rustc_legacy_const_generics(1)]
10193#[cfg_attr(
10194    not(target_arch = "arm"),
10195    stable(feature = "neon_intrinsics", since = "1.59.0")
10196)]
10197#[cfg_attr(
10198    target_arch = "arm",
10199    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10200)]
10201pub fn vdupq_laneq_p16<const N: i32>(a: poly16x8_t) -> poly16x8_t {
10202    static_assert_uimm_bits!(N, 3);
10203    unsafe {
10204        simd_shuffle!(
10205            a,
10206            a,
10207            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10208        )
10209    }
10210}
10211#[doc = "Set all vector lanes to the same value"]
10212#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s16)"]
10213#[inline]
10214#[target_feature(enable = "neon")]
10215#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10216#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10217#[cfg_attr(
10218    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10219    assert_instr(dup, N = 4)
10220)]
10221#[rustc_legacy_const_generics(1)]
10222#[cfg_attr(
10223    not(target_arch = "arm"),
10224    stable(feature = "neon_intrinsics", since = "1.59.0")
10225)]
10226#[cfg_attr(
10227    target_arch = "arm",
10228    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10229)]
10230pub fn vdupq_laneq_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
10231    static_assert_uimm_bits!(N, 3);
10232    unsafe {
10233        simd_shuffle!(
10234            a,
10235            a,
10236            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10237        )
10238    }
10239}
10240#[doc = "Set all vector lanes to the same value"]
10241#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u16)"]
10242#[inline]
10243#[target_feature(enable = "neon")]
10244#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10245#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10246#[cfg_attr(
10247    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10248    assert_instr(dup, N = 4)
10249)]
10250#[rustc_legacy_const_generics(1)]
10251#[cfg_attr(
10252    not(target_arch = "arm"),
10253    stable(feature = "neon_intrinsics", since = "1.59.0")
10254)]
10255#[cfg_attr(
10256    target_arch = "arm",
10257    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10258)]
10259pub fn vdupq_laneq_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
10260    static_assert_uimm_bits!(N, 3);
10261    unsafe {
10262        simd_shuffle!(
10263            a,
10264            a,
10265            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10266        )
10267    }
10268}
10269#[doc = "Set all vector lanes to the same value"]
10270#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p8)"]
10271#[inline]
10272#[target_feature(enable = "neon")]
10273#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10274#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10275#[cfg_attr(
10276    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10277    assert_instr(dup, N = 8)
10278)]
10279#[rustc_legacy_const_generics(1)]
10280#[cfg_attr(
10281    not(target_arch = "arm"),
10282    stable(feature = "neon_intrinsics", since = "1.59.0")
10283)]
10284#[cfg_attr(
10285    target_arch = "arm",
10286    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10287)]
10288pub fn vdup_laneq_p8<const N: i32>(a: poly8x16_t) -> poly8x8_t {
10289    static_assert_uimm_bits!(N, 4);
10290    unsafe {
10291        simd_shuffle!(
10292            a,
10293            a,
10294            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10295        )
10296    }
10297}
10298#[doc = "Set all vector lanes to the same value"]
10299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s8)"]
10300#[inline]
10301#[target_feature(enable = "neon")]
10302#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10303#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10304#[cfg_attr(
10305    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10306    assert_instr(dup, N = 8)
10307)]
10308#[rustc_legacy_const_generics(1)]
10309#[cfg_attr(
10310    not(target_arch = "arm"),
10311    stable(feature = "neon_intrinsics", since = "1.59.0")
10312)]
10313#[cfg_attr(
10314    target_arch = "arm",
10315    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10316)]
10317pub fn vdup_laneq_s8<const N: i32>(a: int8x16_t) -> int8x8_t {
10318    static_assert_uimm_bits!(N, 4);
10319    unsafe {
10320        simd_shuffle!(
10321            a,
10322            a,
10323            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10324        )
10325    }
10326}
10327#[doc = "Set all vector lanes to the same value"]
10328#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u8)"]
10329#[inline]
10330#[target_feature(enable = "neon")]
10331#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10332#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10333#[cfg_attr(
10334    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10335    assert_instr(dup, N = 8)
10336)]
10337#[rustc_legacy_const_generics(1)]
10338#[cfg_attr(
10339    not(target_arch = "arm"),
10340    stable(feature = "neon_intrinsics", since = "1.59.0")
10341)]
10342#[cfg_attr(
10343    target_arch = "arm",
10344    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10345)]
10346pub fn vdup_laneq_u8<const N: i32>(a: uint8x16_t) -> uint8x8_t {
10347    static_assert_uimm_bits!(N, 4);
10348    unsafe {
10349        simd_shuffle!(
10350            a,
10351            a,
10352            [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10353        )
10354    }
10355}
10356#[doc = "Set all vector lanes to the same value"]
10357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p8)"]
10358#[inline]
10359#[target_feature(enable = "neon")]
10360#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10361#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10362#[cfg_attr(
10363    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10364    assert_instr(dup, N = 8)
10365)]
10366#[rustc_legacy_const_generics(1)]
10367#[cfg_attr(
10368    not(target_arch = "arm"),
10369    stable(feature = "neon_intrinsics", since = "1.59.0")
10370)]
10371#[cfg_attr(
10372    target_arch = "arm",
10373    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10374)]
10375pub fn vdupq_laneq_p8<const N: i32>(a: poly8x16_t) -> poly8x16_t {
10376    static_assert_uimm_bits!(N, 4);
10377    unsafe {
10378        simd_shuffle!(
10379            a,
10380            a,
10381            [
10382                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
10383                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
10384            ]
10385        )
10386    }
10387}
10388#[doc = "Set all vector lanes to the same value"]
10389#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s8)"]
10390#[inline]
10391#[target_feature(enable = "neon")]
10392#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10393#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10394#[cfg_attr(
10395    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10396    assert_instr(dup, N = 8)
10397)]
10398#[rustc_legacy_const_generics(1)]
10399#[cfg_attr(
10400    not(target_arch = "arm"),
10401    stable(feature = "neon_intrinsics", since = "1.59.0")
10402)]
10403#[cfg_attr(
10404    target_arch = "arm",
10405    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10406)]
10407pub fn vdupq_laneq_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
10408    static_assert_uimm_bits!(N, 4);
10409    unsafe {
10410        simd_shuffle!(
10411            a,
10412            a,
10413            [
10414                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
10415                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
10416            ]
10417        )
10418    }
10419}
10420#[doc = "Set all vector lanes to the same value"]
10421#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u8)"]
10422#[inline]
10423#[target_feature(enable = "neon")]
10424#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10425#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10426#[cfg_attr(
10427    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10428    assert_instr(dup, N = 8)
10429)]
10430#[rustc_legacy_const_generics(1)]
10431#[cfg_attr(
10432    not(target_arch = "arm"),
10433    stable(feature = "neon_intrinsics", since = "1.59.0")
10434)]
10435#[cfg_attr(
10436    target_arch = "arm",
10437    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10438)]
10439pub fn vdupq_laneq_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
10440    static_assert_uimm_bits!(N, 4);
10441    unsafe {
10442        simd_shuffle!(
10443            a,
10444            a,
10445            [
10446                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
10447                N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
10448            ]
10449        )
10450    }
10451}
10452#[doc = "Set all vector lanes to the same value"]
10453#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s64)"]
10454#[inline]
10455#[target_feature(enable = "neon")]
10456#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10457#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
10458#[cfg_attr(
10459    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10460    assert_instr(nop, N = 1)
10461)]
10462#[rustc_legacy_const_generics(1)]
10463#[cfg_attr(
10464    not(target_arch = "arm"),
10465    stable(feature = "neon_intrinsics", since = "1.59.0")
10466)]
10467#[cfg_attr(
10468    target_arch = "arm",
10469    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10470)]
10471pub fn vdup_laneq_s64<const N: i32>(a: int64x2_t) -> int64x1_t {
10472    static_assert_uimm_bits!(N, 1);
10473    unsafe { transmute::<i64, _>(simd_extract!(a, N as u32)) }
10474}
10475#[doc = "Set all vector lanes to the same value"]
10476#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u64)"]
10477#[inline]
10478#[target_feature(enable = "neon")]
10479#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10480#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
10481#[cfg_attr(
10482    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10483    assert_instr(nop, N = 1)
10484)]
10485#[rustc_legacy_const_generics(1)]
10486#[cfg_attr(
10487    not(target_arch = "arm"),
10488    stable(feature = "neon_intrinsics", since = "1.59.0")
10489)]
10490#[cfg_attr(
10491    target_arch = "arm",
10492    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10493)]
10494pub fn vdup_laneq_u64<const N: i32>(a: uint64x2_t) -> uint64x1_t {
10495    static_assert_uimm_bits!(N, 1);
10496    unsafe { transmute::<u64, _>(simd_extract!(a, N as u32)) }
10497}
10498#[doc = "Create a new vector with all lanes set to a value"]
10499#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f16)"]
10500#[inline]
10501#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10502#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10503#[cfg_attr(
10504    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10505    assert_instr(dup)
10506)]
10507#[target_feature(enable = "neon,fp16")]
10508#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10509pub fn vdup_n_f16(a: f16) -> float16x4_t {
10510    float16x4_t::splat(a)
10511}
10512#[doc = "Create a new vector with all lanes set to a value"]
10513#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f16)"]
10514#[inline]
10515#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10516#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10517#[cfg_attr(
10518    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10519    assert_instr(dup)
10520)]
10521#[target_feature(enable = "neon,fp16")]
10522#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10523pub fn vdupq_n_f16(a: f16) -> float16x8_t {
10524    float16x8_t::splat(a)
10525}
10526#[doc = "Duplicate vector element to vector or scalar"]
10527#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32)"]
10528#[inline]
10529#[target_feature(enable = "neon")]
10530#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10531#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10532#[cfg_attr(
10533    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10534    assert_instr(dup)
10535)]
10536#[cfg_attr(
10537    not(target_arch = "arm"),
10538    stable(feature = "neon_intrinsics", since = "1.59.0")
10539)]
10540#[cfg_attr(
10541    target_arch = "arm",
10542    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10543)]
10544pub fn vdup_n_f32(value: f32) -> float32x2_t {
10545    float32x2_t::splat(value)
10546}
10547#[doc = "Duplicate vector element to vector or scalar"]
10548#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p16)"]
10549#[inline]
10550#[target_feature(enable = "neon")]
10551#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10552#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10553#[cfg_attr(
10554    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10555    assert_instr(dup)
10556)]
10557#[cfg_attr(
10558    not(target_arch = "arm"),
10559    stable(feature = "neon_intrinsics", since = "1.59.0")
10560)]
10561#[cfg_attr(
10562    target_arch = "arm",
10563    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10564)]
10565pub fn vdup_n_p16(value: p16) -> poly16x4_t {
10566    poly16x4_t::splat(value)
10567}
10568#[doc = "Duplicate vector element to vector or scalar"]
10569#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p8)"]
10570#[inline]
10571#[target_feature(enable = "neon")]
10572#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10573#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10574#[cfg_attr(
10575    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10576    assert_instr(dup)
10577)]
10578#[cfg_attr(
10579    not(target_arch = "arm"),
10580    stable(feature = "neon_intrinsics", since = "1.59.0")
10581)]
10582#[cfg_attr(
10583    target_arch = "arm",
10584    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10585)]
10586pub fn vdup_n_p8(value: p8) -> poly8x8_t {
10587    poly8x8_t::splat(value)
10588}
10589#[doc = "Duplicate vector element to vector or scalar"]
10590#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s16)"]
10591#[inline]
10592#[target_feature(enable = "neon")]
10593#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10594#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10595#[cfg_attr(
10596    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10597    assert_instr(dup)
10598)]
10599#[cfg_attr(
10600    not(target_arch = "arm"),
10601    stable(feature = "neon_intrinsics", since = "1.59.0")
10602)]
10603#[cfg_attr(
10604    target_arch = "arm",
10605    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10606)]
10607pub fn vdup_n_s16(value: i16) -> int16x4_t {
10608    int16x4_t::splat(value)
10609}
10610#[doc = "Duplicate vector element to vector or scalar"]
10611#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s32)"]
10612#[inline]
10613#[target_feature(enable = "neon")]
10614#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10615#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10616#[cfg_attr(
10617    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10618    assert_instr(dup)
10619)]
10620#[cfg_attr(
10621    not(target_arch = "arm"),
10622    stable(feature = "neon_intrinsics", since = "1.59.0")
10623)]
10624#[cfg_attr(
10625    target_arch = "arm",
10626    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10627)]
10628pub fn vdup_n_s32(value: i32) -> int32x2_t {
10629    int32x2_t::splat(value)
10630}
10631#[doc = "Duplicate vector element to vector or scalar"]
10632#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s64)"]
10633#[inline]
10634#[target_feature(enable = "neon")]
10635#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10636#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
10637#[cfg_attr(
10638    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10639    assert_instr(fmov)
10640)]
10641#[cfg_attr(
10642    not(target_arch = "arm"),
10643    stable(feature = "neon_intrinsics", since = "1.59.0")
10644)]
10645#[cfg_attr(
10646    target_arch = "arm",
10647    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10648)]
10649pub fn vdup_n_s64(value: i64) -> int64x1_t {
10650    int64x1_t::splat(value)
10651}
10652#[doc = "Duplicate vector element to vector or scalar"]
10653#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s8)"]
10654#[inline]
10655#[target_feature(enable = "neon")]
10656#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10657#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10658#[cfg_attr(
10659    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10660    assert_instr(dup)
10661)]
10662#[cfg_attr(
10663    not(target_arch = "arm"),
10664    stable(feature = "neon_intrinsics", since = "1.59.0")
10665)]
10666#[cfg_attr(
10667    target_arch = "arm",
10668    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10669)]
10670pub fn vdup_n_s8(value: i8) -> int8x8_t {
10671    int8x8_t::splat(value)
10672}
10673#[doc = "Duplicate vector element to vector or scalar"]
10674#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u16)"]
10675#[inline]
10676#[target_feature(enable = "neon")]
10677#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10678#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10679#[cfg_attr(
10680    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10681    assert_instr(dup)
10682)]
10683#[cfg_attr(
10684    not(target_arch = "arm"),
10685    stable(feature = "neon_intrinsics", since = "1.59.0")
10686)]
10687#[cfg_attr(
10688    target_arch = "arm",
10689    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10690)]
10691pub fn vdup_n_u16(value: u16) -> uint16x4_t {
10692    uint16x4_t::splat(value)
10693}
10694#[doc = "Duplicate vector element to vector or scalar"]
10695#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u32)"]
10696#[inline]
10697#[target_feature(enable = "neon")]
10698#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10699#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10700#[cfg_attr(
10701    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10702    assert_instr(dup)
10703)]
10704#[cfg_attr(
10705    not(target_arch = "arm"),
10706    stable(feature = "neon_intrinsics", since = "1.59.0")
10707)]
10708#[cfg_attr(
10709    target_arch = "arm",
10710    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10711)]
10712pub fn vdup_n_u32(value: u32) -> uint32x2_t {
10713    uint32x2_t::splat(value)
10714}
10715#[doc = "Duplicate vector element to vector or scalar"]
10716#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u64)"]
10717#[inline]
10718#[target_feature(enable = "neon")]
10719#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10720#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
10721#[cfg_attr(
10722    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10723    assert_instr(fmov)
10724)]
10725#[cfg_attr(
10726    not(target_arch = "arm"),
10727    stable(feature = "neon_intrinsics", since = "1.59.0")
10728)]
10729#[cfg_attr(
10730    target_arch = "arm",
10731    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10732)]
10733pub fn vdup_n_u64(value: u64) -> uint64x1_t {
10734    uint64x1_t::splat(value)
10735}
10736#[doc = "Duplicate vector element to vector or scalar"]
10737#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u8)"]
10738#[inline]
10739#[target_feature(enable = "neon")]
10740#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10741#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10742#[cfg_attr(
10743    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10744    assert_instr(dup)
10745)]
10746#[cfg_attr(
10747    not(target_arch = "arm"),
10748    stable(feature = "neon_intrinsics", since = "1.59.0")
10749)]
10750#[cfg_attr(
10751    target_arch = "arm",
10752    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10753)]
10754pub fn vdup_n_u8(value: u8) -> uint8x8_t {
10755    uint8x8_t::splat(value)
10756}
10757#[doc = "Duplicate vector element to vector or scalar"]
10758#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32)"]
10759#[inline]
10760#[target_feature(enable = "neon")]
10761#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10762#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10763#[cfg_attr(
10764    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10765    assert_instr(dup)
10766)]
10767#[cfg_attr(
10768    not(target_arch = "arm"),
10769    stable(feature = "neon_intrinsics", since = "1.59.0")
10770)]
10771#[cfg_attr(
10772    target_arch = "arm",
10773    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10774)]
10775pub fn vdupq_n_f32(value: f32) -> float32x4_t {
10776    float32x4_t::splat(value)
10777}
10778#[doc = "Duplicate vector element to vector or scalar"]
10779#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p16)"]
10780#[inline]
10781#[target_feature(enable = "neon")]
10782#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10783#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10784#[cfg_attr(
10785    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10786    assert_instr(dup)
10787)]
10788#[cfg_attr(
10789    not(target_arch = "arm"),
10790    stable(feature = "neon_intrinsics", since = "1.59.0")
10791)]
10792#[cfg_attr(
10793    target_arch = "arm",
10794    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10795)]
10796pub fn vdupq_n_p16(value: p16) -> poly16x8_t {
10797    poly16x8_t::splat(value)
10798}
10799#[doc = "Duplicate vector element to vector or scalar"]
10800#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p8)"]
10801#[inline]
10802#[target_feature(enable = "neon")]
10803#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10804#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10805#[cfg_attr(
10806    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10807    assert_instr(dup)
10808)]
10809#[cfg_attr(
10810    not(target_arch = "arm"),
10811    stable(feature = "neon_intrinsics", since = "1.59.0")
10812)]
10813#[cfg_attr(
10814    target_arch = "arm",
10815    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10816)]
10817pub fn vdupq_n_p8(value: p8) -> poly8x16_t {
10818    poly8x16_t::splat(value)
10819}
10820#[doc = "Duplicate vector element to vector or scalar"]
10821#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s16)"]
10822#[inline]
10823#[target_feature(enable = "neon")]
10824#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10825#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10826#[cfg_attr(
10827    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10828    assert_instr(dup)
10829)]
10830#[cfg_attr(
10831    not(target_arch = "arm"),
10832    stable(feature = "neon_intrinsics", since = "1.59.0")
10833)]
10834#[cfg_attr(
10835    target_arch = "arm",
10836    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10837)]
10838pub fn vdupq_n_s16(value: i16) -> int16x8_t {
10839    int16x8_t::splat(value)
10840}
10841#[doc = "Duplicate vector element to vector or scalar"]
10842#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s32)"]
10843#[inline]
10844#[target_feature(enable = "neon")]
10845#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10846#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10847#[cfg_attr(
10848    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10849    assert_instr(dup)
10850)]
10851#[cfg_attr(
10852    not(target_arch = "arm"),
10853    stable(feature = "neon_intrinsics", since = "1.59.0")
10854)]
10855#[cfg_attr(
10856    target_arch = "arm",
10857    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10858)]
10859pub fn vdupq_n_s32(value: i32) -> int32x4_t {
10860    int32x4_t::splat(value)
10861}
10862#[doc = "Duplicate vector element to vector or scalar"]
10863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s64)"]
10864#[inline]
10865#[target_feature(enable = "neon")]
10866#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10867#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
10868#[cfg_attr(
10869    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10870    assert_instr(dup)
10871)]
10872#[cfg_attr(
10873    not(target_arch = "arm"),
10874    stable(feature = "neon_intrinsics", since = "1.59.0")
10875)]
10876#[cfg_attr(
10877    target_arch = "arm",
10878    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10879)]
10880pub fn vdupq_n_s64(value: i64) -> int64x2_t {
10881    int64x2_t::splat(value)
10882}
10883#[doc = "Duplicate vector element to vector or scalar"]
10884#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s8)"]
10885#[inline]
10886#[target_feature(enable = "neon")]
10887#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10888#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10889#[cfg_attr(
10890    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10891    assert_instr(dup)
10892)]
10893#[cfg_attr(
10894    not(target_arch = "arm"),
10895    stable(feature = "neon_intrinsics", since = "1.59.0")
10896)]
10897#[cfg_attr(
10898    target_arch = "arm",
10899    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10900)]
10901pub fn vdupq_n_s8(value: i8) -> int8x16_t {
10902    int8x16_t::splat(value)
10903}
10904#[doc = "Duplicate vector element to vector or scalar"]
10905#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u16)"]
10906#[inline]
10907#[target_feature(enable = "neon")]
10908#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10909#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10910#[cfg_attr(
10911    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10912    assert_instr(dup)
10913)]
10914#[cfg_attr(
10915    not(target_arch = "arm"),
10916    stable(feature = "neon_intrinsics", since = "1.59.0")
10917)]
10918#[cfg_attr(
10919    target_arch = "arm",
10920    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10921)]
10922pub fn vdupq_n_u16(value: u16) -> uint16x8_t {
10923    uint16x8_t::splat(value)
10924}
10925#[doc = "Duplicate vector element to vector or scalar"]
10926#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u32)"]
10927#[inline]
10928#[target_feature(enable = "neon")]
10929#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10930#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10931#[cfg_attr(
10932    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10933    assert_instr(dup)
10934)]
10935#[cfg_attr(
10936    not(target_arch = "arm"),
10937    stable(feature = "neon_intrinsics", since = "1.59.0")
10938)]
10939#[cfg_attr(
10940    target_arch = "arm",
10941    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10942)]
10943pub fn vdupq_n_u32(value: u32) -> uint32x4_t {
10944    uint32x4_t::splat(value)
10945}
10946#[doc = "Duplicate vector element to vector or scalar"]
10947#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u64)"]
10948#[inline]
10949#[target_feature(enable = "neon")]
10950#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10951#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
10952#[cfg_attr(
10953    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10954    assert_instr(dup)
10955)]
10956#[cfg_attr(
10957    not(target_arch = "arm"),
10958    stable(feature = "neon_intrinsics", since = "1.59.0")
10959)]
10960#[cfg_attr(
10961    target_arch = "arm",
10962    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10963)]
10964pub fn vdupq_n_u64(value: u64) -> uint64x2_t {
10965    uint64x2_t::splat(value)
10966}
10967#[doc = "Duplicate vector element to vector or scalar"]
10968#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u8)"]
10969#[inline]
10970#[target_feature(enable = "neon")]
10971#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10972#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10973#[cfg_attr(
10974    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10975    assert_instr(dup)
10976)]
10977#[cfg_attr(
10978    not(target_arch = "arm"),
10979    stable(feature = "neon_intrinsics", since = "1.59.0")
10980)]
10981#[cfg_attr(
10982    target_arch = "arm",
10983    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10984)]
10985pub fn vdupq_n_u8(value: u8) -> uint8x16_t {
10986    uint8x16_t::splat(value)
10987}
10988#[doc = "Duplicate vector element to vector or scalar"]
10989#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32_vfp4)"]
10990#[inline]
10991#[target_feature(enable = "neon")]
10992#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
10993#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10994#[cfg_attr(
10995    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10996    assert_instr(dup)
10997)]
10998#[cfg_attr(
10999    not(target_arch = "arm"),
11000    stable(feature = "neon_intrinsics", since = "1.59.0")
11001)]
11002#[cfg_attr(
11003    target_arch = "arm",
11004    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11005)]
11006fn vdup_n_f32_vfp4(value: f32) -> float32x2_t {
11007    float32x2_t::splat(value)
11008}
11009#[doc = "Duplicate vector element to vector or scalar"]
11010#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32_vfp4)"]
11011#[inline]
11012#[target_feature(enable = "neon")]
11013#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
11014#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
11015#[cfg_attr(
11016    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11017    assert_instr(dup)
11018)]
11019#[cfg_attr(
11020    not(target_arch = "arm"),
11021    stable(feature = "neon_intrinsics", since = "1.59.0")
11022)]
11023#[cfg_attr(
11024    target_arch = "arm",
11025    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11026)]
11027fn vdupq_n_f32_vfp4(value: f32) -> float32x4_t {
11028    float32x4_t::splat(value)
11029}
11030#[doc = "Set all vector lanes to the same value"]
11031#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s64)"]
11032#[inline]
11033#[target_feature(enable = "neon")]
11034#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11035#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))]
11036#[cfg_attr(
11037    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11038    assert_instr(dup, N = 0)
11039)]
11040#[rustc_legacy_const_generics(1)]
11041#[cfg_attr(
11042    not(target_arch = "arm"),
11043    stable(feature = "neon_intrinsics", since = "1.59.0")
11044)]
11045#[cfg_attr(
11046    target_arch = "arm",
11047    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11048)]
11049pub fn vdupq_lane_s64<const N: i32>(a: int64x1_t) -> int64x2_t {
11050    static_assert!(N == 0);
11051    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
11052}
11053#[doc = "Set all vector lanes to the same value"]
11054#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u64)"]
11055#[inline]
11056#[target_feature(enable = "neon")]
11057#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11058#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))]
11059#[cfg_attr(
11060    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11061    assert_instr(dup, N = 0)
11062)]
11063#[rustc_legacy_const_generics(1)]
11064#[cfg_attr(
11065    not(target_arch = "arm"),
11066    stable(feature = "neon_intrinsics", since = "1.59.0")
11067)]
11068#[cfg_attr(
11069    target_arch = "arm",
11070    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11071)]
11072pub fn vdupq_lane_u64<const N: i32>(a: uint64x1_t) -> uint64x2_t {
11073    static_assert!(N == 0);
11074    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
11075}
11076#[doc = "Set all vector lanes to the same value"]
11077#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s64)"]
11078#[inline]
11079#[target_feature(enable = "neon")]
11080#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11081#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
11082#[cfg_attr(
11083    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11084    assert_instr(dup, N = 1)
11085)]
11086#[rustc_legacy_const_generics(1)]
11087#[cfg_attr(
11088    not(target_arch = "arm"),
11089    stable(feature = "neon_intrinsics", since = "1.59.0")
11090)]
11091#[cfg_attr(
11092    target_arch = "arm",
11093    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11094)]
11095pub fn vdupq_laneq_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
11096    static_assert_uimm_bits!(N, 1);
11097    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
11098}
11099#[doc = "Set all vector lanes to the same value"]
11100#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u64)"]
11101#[inline]
11102#[target_feature(enable = "neon")]
11103#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11104#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
11105#[cfg_attr(
11106    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11107    assert_instr(dup, N = 1)
11108)]
11109#[rustc_legacy_const_generics(1)]
11110#[cfg_attr(
11111    not(target_arch = "arm"),
11112    stable(feature = "neon_intrinsics", since = "1.59.0")
11113)]
11114#[cfg_attr(
11115    target_arch = "arm",
11116    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11117)]
11118pub fn vdupq_laneq_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
11119    static_assert_uimm_bits!(N, 1);
11120    unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
11121}
11122#[doc = "Vector bitwise exclusive or (vector)"]
11123#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s8)"]
11124#[inline]
11125#[target_feature(enable = "neon")]
11126#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11127#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11128#[cfg_attr(
11129    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11130    assert_instr(eor)
11131)]
11132#[cfg_attr(
11133    not(target_arch = "arm"),
11134    stable(feature = "neon_intrinsics", since = "1.59.0")
11135)]
11136#[cfg_attr(
11137    target_arch = "arm",
11138    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11139)]
11140pub fn veor_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
11141    unsafe { simd_xor(a, b) }
11142}
11143#[doc = "Vector bitwise exclusive or (vector)"]
11144#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s8)"]
11145#[inline]
11146#[target_feature(enable = "neon")]
11147#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11148#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11149#[cfg_attr(
11150    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11151    assert_instr(eor)
11152)]
11153#[cfg_attr(
11154    not(target_arch = "arm"),
11155    stable(feature = "neon_intrinsics", since = "1.59.0")
11156)]
11157#[cfg_attr(
11158    target_arch = "arm",
11159    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11160)]
11161pub fn veorq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
11162    unsafe { simd_xor(a, b) }
11163}
11164#[doc = "Vector bitwise exclusive or (vector)"]
11165#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s16)"]
11166#[inline]
11167#[target_feature(enable = "neon")]
11168#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11169#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11170#[cfg_attr(
11171    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11172    assert_instr(eor)
11173)]
11174#[cfg_attr(
11175    not(target_arch = "arm"),
11176    stable(feature = "neon_intrinsics", since = "1.59.0")
11177)]
11178#[cfg_attr(
11179    target_arch = "arm",
11180    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11181)]
11182pub fn veor_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
11183    unsafe { simd_xor(a, b) }
11184}
11185#[doc = "Vector bitwise exclusive or (vector)"]
11186#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s16)"]
11187#[inline]
11188#[target_feature(enable = "neon")]
11189#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11190#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11191#[cfg_attr(
11192    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11193    assert_instr(eor)
11194)]
11195#[cfg_attr(
11196    not(target_arch = "arm"),
11197    stable(feature = "neon_intrinsics", since = "1.59.0")
11198)]
11199#[cfg_attr(
11200    target_arch = "arm",
11201    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11202)]
11203pub fn veorq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
11204    unsafe { simd_xor(a, b) }
11205}
11206#[doc = "Vector bitwise exclusive or (vector)"]
11207#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s32)"]
11208#[inline]
11209#[target_feature(enable = "neon")]
11210#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11211#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11212#[cfg_attr(
11213    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11214    assert_instr(eor)
11215)]
11216#[cfg_attr(
11217    not(target_arch = "arm"),
11218    stable(feature = "neon_intrinsics", since = "1.59.0")
11219)]
11220#[cfg_attr(
11221    target_arch = "arm",
11222    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11223)]
11224pub fn veor_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
11225    unsafe { simd_xor(a, b) }
11226}
11227#[doc = "Vector bitwise exclusive or (vector)"]
11228#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s32)"]
11229#[inline]
11230#[target_feature(enable = "neon")]
11231#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11232#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11233#[cfg_attr(
11234    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11235    assert_instr(eor)
11236)]
11237#[cfg_attr(
11238    not(target_arch = "arm"),
11239    stable(feature = "neon_intrinsics", since = "1.59.0")
11240)]
11241#[cfg_attr(
11242    target_arch = "arm",
11243    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11244)]
11245pub fn veorq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
11246    unsafe { simd_xor(a, b) }
11247}
11248#[doc = "Vector bitwise exclusive or (vector)"]
11249#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s64)"]
11250#[inline]
11251#[target_feature(enable = "neon")]
11252#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11253#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11254#[cfg_attr(
11255    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11256    assert_instr(eor)
11257)]
11258#[cfg_attr(
11259    not(target_arch = "arm"),
11260    stable(feature = "neon_intrinsics", since = "1.59.0")
11261)]
11262#[cfg_attr(
11263    target_arch = "arm",
11264    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11265)]
11266pub fn veor_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
11267    unsafe { simd_xor(a, b) }
11268}
11269#[doc = "Vector bitwise exclusive or (vector)"]
11270#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s64)"]
11271#[inline]
11272#[target_feature(enable = "neon")]
11273#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11274#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11275#[cfg_attr(
11276    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11277    assert_instr(eor)
11278)]
11279#[cfg_attr(
11280    not(target_arch = "arm"),
11281    stable(feature = "neon_intrinsics", since = "1.59.0")
11282)]
11283#[cfg_attr(
11284    target_arch = "arm",
11285    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11286)]
11287pub fn veorq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
11288    unsafe { simd_xor(a, b) }
11289}
11290#[doc = "Vector bitwise exclusive or (vector)"]
11291#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u8)"]
11292#[inline]
11293#[target_feature(enable = "neon")]
11294#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11295#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11296#[cfg_attr(
11297    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11298    assert_instr(eor)
11299)]
11300#[cfg_attr(
11301    not(target_arch = "arm"),
11302    stable(feature = "neon_intrinsics", since = "1.59.0")
11303)]
11304#[cfg_attr(
11305    target_arch = "arm",
11306    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11307)]
11308pub fn veor_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
11309    unsafe { simd_xor(a, b) }
11310}
11311#[doc = "Vector bitwise exclusive or (vector)"]
11312#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u8)"]
11313#[inline]
11314#[target_feature(enable = "neon")]
11315#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11316#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11317#[cfg_attr(
11318    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11319    assert_instr(eor)
11320)]
11321#[cfg_attr(
11322    not(target_arch = "arm"),
11323    stable(feature = "neon_intrinsics", since = "1.59.0")
11324)]
11325#[cfg_attr(
11326    target_arch = "arm",
11327    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11328)]
11329pub fn veorq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
11330    unsafe { simd_xor(a, b) }
11331}
11332#[doc = "Vector bitwise exclusive or (vector)"]
11333#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u16)"]
11334#[inline]
11335#[target_feature(enable = "neon")]
11336#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11337#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11338#[cfg_attr(
11339    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11340    assert_instr(eor)
11341)]
11342#[cfg_attr(
11343    not(target_arch = "arm"),
11344    stable(feature = "neon_intrinsics", since = "1.59.0")
11345)]
11346#[cfg_attr(
11347    target_arch = "arm",
11348    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11349)]
11350pub fn veor_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
11351    unsafe { simd_xor(a, b) }
11352}
11353#[doc = "Vector bitwise exclusive or (vector)"]
11354#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u16)"]
11355#[inline]
11356#[target_feature(enable = "neon")]
11357#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11358#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11359#[cfg_attr(
11360    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11361    assert_instr(eor)
11362)]
11363#[cfg_attr(
11364    not(target_arch = "arm"),
11365    stable(feature = "neon_intrinsics", since = "1.59.0")
11366)]
11367#[cfg_attr(
11368    target_arch = "arm",
11369    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11370)]
11371pub fn veorq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
11372    unsafe { simd_xor(a, b) }
11373}
11374#[doc = "Vector bitwise exclusive or (vector)"]
11375#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u32)"]
11376#[inline]
11377#[target_feature(enable = "neon")]
11378#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11379#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11380#[cfg_attr(
11381    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11382    assert_instr(eor)
11383)]
11384#[cfg_attr(
11385    not(target_arch = "arm"),
11386    stable(feature = "neon_intrinsics", since = "1.59.0")
11387)]
11388#[cfg_attr(
11389    target_arch = "arm",
11390    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11391)]
11392pub fn veor_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
11393    unsafe { simd_xor(a, b) }
11394}
11395#[doc = "Vector bitwise exclusive or (vector)"]
11396#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u32)"]
11397#[inline]
11398#[target_feature(enable = "neon")]
11399#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11400#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11401#[cfg_attr(
11402    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11403    assert_instr(eor)
11404)]
11405#[cfg_attr(
11406    not(target_arch = "arm"),
11407    stable(feature = "neon_intrinsics", since = "1.59.0")
11408)]
11409#[cfg_attr(
11410    target_arch = "arm",
11411    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11412)]
11413pub fn veorq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
11414    unsafe { simd_xor(a, b) }
11415}
11416#[doc = "Vector bitwise exclusive or (vector)"]
11417#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u64)"]
11418#[inline]
11419#[target_feature(enable = "neon")]
11420#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11421#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11422#[cfg_attr(
11423    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11424    assert_instr(eor)
11425)]
11426#[cfg_attr(
11427    not(target_arch = "arm"),
11428    stable(feature = "neon_intrinsics", since = "1.59.0")
11429)]
11430#[cfg_attr(
11431    target_arch = "arm",
11432    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11433)]
11434pub fn veor_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
11435    unsafe { simd_xor(a, b) }
11436}
11437#[doc = "Vector bitwise exclusive or (vector)"]
11438#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u64)"]
11439#[inline]
11440#[target_feature(enable = "neon")]
11441#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11442#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11443#[cfg_attr(
11444    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11445    assert_instr(eor)
11446)]
11447#[cfg_attr(
11448    not(target_arch = "arm"),
11449    stable(feature = "neon_intrinsics", since = "1.59.0")
11450)]
11451#[cfg_attr(
11452    target_arch = "arm",
11453    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11454)]
11455pub fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
11456    unsafe { simd_xor(a, b) }
11457}
11458#[doc = "Extract vector from pair of vectors"]
11459#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f16)"]
11460#[inline]
11461#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11462#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
11463#[cfg_attr(
11464    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11465    assert_instr(ext, N = 3)
11466)]
11467#[rustc_legacy_const_generics(2)]
11468#[target_feature(enable = "neon,fp16")]
11469#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
11470pub fn vext_f16<const N: i32>(a: float16x4_t, b: float16x4_t) -> float16x4_t {
11471    static_assert_uimm_bits!(N, 2);
11472    unsafe {
11473        match N & 0b11 {
11474            0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
11475            1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
11476            2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
11477            3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
11478            _ => unreachable_unchecked(),
11479        }
11480    }
11481}
11482#[doc = "Extract vector from pair of vectors"]
11483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f32)"]
11484#[inline]
11485#[target_feature(enable = "neon")]
11486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11487#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
11488#[cfg_attr(
11489    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11490    assert_instr(ext, N = 1)
11491)]
11492#[rustc_legacy_const_generics(2)]
11493#[cfg_attr(
11494    not(target_arch = "arm"),
11495    stable(feature = "neon_intrinsics", since = "1.59.0")
11496)]
11497#[cfg_attr(
11498    target_arch = "arm",
11499    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11500)]
11501pub fn vext_f32<const N: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t {
11502    static_assert_uimm_bits!(N, 1);
11503    unsafe {
11504        match N & 0b1 {
11505            0 => simd_shuffle!(a, b, [0, 1]),
11506            1 => simd_shuffle!(a, b, [1, 2]),
11507            _ => unreachable_unchecked(),
11508        }
11509    }
11510}
11511#[doc = "Extract vector from pair of vectors"]
11512#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s32)"]
11513#[inline]
11514#[target_feature(enable = "neon")]
11515#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11516#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
11517#[cfg_attr(
11518    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11519    assert_instr(ext, N = 1)
11520)]
11521#[rustc_legacy_const_generics(2)]
11522#[cfg_attr(
11523    not(target_arch = "arm"),
11524    stable(feature = "neon_intrinsics", since = "1.59.0")
11525)]
11526#[cfg_attr(
11527    target_arch = "arm",
11528    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11529)]
11530pub fn vext_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
11531    static_assert_uimm_bits!(N, 1);
11532    unsafe {
11533        match N & 0b1 {
11534            0 => simd_shuffle!(a, b, [0, 1]),
11535            1 => simd_shuffle!(a, b, [1, 2]),
11536            _ => unreachable_unchecked(),
11537        }
11538    }
11539}
11540#[doc = "Extract vector from pair of vectors"]
11541#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u32)"]
11542#[inline]
11543#[target_feature(enable = "neon")]
11544#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11545#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
11546#[cfg_attr(
11547    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11548    assert_instr(ext, N = 1)
11549)]
11550#[rustc_legacy_const_generics(2)]
11551#[cfg_attr(
11552    not(target_arch = "arm"),
11553    stable(feature = "neon_intrinsics", since = "1.59.0")
11554)]
11555#[cfg_attr(
11556    target_arch = "arm",
11557    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11558)]
11559pub fn vext_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
11560    static_assert_uimm_bits!(N, 1);
11561    unsafe {
11562        match N & 0b1 {
11563            0 => simd_shuffle!(a, b, [0, 1]),
11564            1 => simd_shuffle!(a, b, [1, 2]),
11565            _ => unreachable_unchecked(),
11566        }
11567    }
11568}
11569#[doc = "Extract vector from pair of vectors"]
11570#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s64)"]
11571#[doc = "## Safety"]
11572#[doc = "  * Neon instrinsic unsafe"]
11573#[inline]
11574#[target_feature(enable = "neon")]
11575#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11576#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
11577#[cfg_attr(
11578    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11579    assert_instr(nop, N = 0)
11580)]
11581#[rustc_legacy_const_generics(2)]
11582#[cfg_attr(
11583    not(target_arch = "arm"),
11584    stable(feature = "neon_intrinsics", since = "1.59.0")
11585)]
11586#[cfg_attr(
11587    target_arch = "arm",
11588    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11589)]
11590pub unsafe fn vext_s64<const N: i32>(a: int64x1_t, _b: int64x1_t) -> int64x1_t {
11591    static_assert!(N == 0);
11592    a
11593}
11594#[doc = "Extract vector from pair of vectors"]
11595#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u64)"]
11596#[doc = "## Safety"]
11597#[doc = "  * Neon instrinsic unsafe"]
11598#[inline]
11599#[target_feature(enable = "neon")]
11600#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11601#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
11602#[cfg_attr(
11603    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11604    assert_instr(nop, N = 0)
11605)]
11606#[rustc_legacy_const_generics(2)]
11607#[cfg_attr(
11608    not(target_arch = "arm"),
11609    stable(feature = "neon_intrinsics", since = "1.59.0")
11610)]
11611#[cfg_attr(
11612    target_arch = "arm",
11613    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11614)]
11615pub unsafe fn vext_u64<const N: i32>(a: uint64x1_t, _b: uint64x1_t) -> uint64x1_t {
11616    static_assert!(N == 0);
11617    a
11618}
11619#[doc = "Extract vector from pair of vectors"]
11620#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s8)"]
11621#[inline]
11622#[target_feature(enable = "neon")]
11623#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11624#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11625#[cfg_attr(
11626    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11627    assert_instr(ext, N = 7)
11628)]
11629#[rustc_legacy_const_generics(2)]
11630#[cfg_attr(
11631    not(target_arch = "arm"),
11632    stable(feature = "neon_intrinsics", since = "1.59.0")
11633)]
11634#[cfg_attr(
11635    target_arch = "arm",
11636    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11637)]
11638pub fn vext_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
11639    static_assert_uimm_bits!(N, 3);
11640    unsafe {
11641        match N & 0b111 {
11642            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11643            1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11644            2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11645            3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11646            4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11647            5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11648            6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11649            7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11650            _ => unreachable_unchecked(),
11651        }
11652    }
11653}
11654#[doc = "Extract vector from pair of vectors"]
11655#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s16)"]
11656#[inline]
11657#[target_feature(enable = "neon")]
11658#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11659#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11660#[cfg_attr(
11661    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11662    assert_instr(ext, N = 7)
11663)]
11664#[rustc_legacy_const_generics(2)]
11665#[cfg_attr(
11666    not(target_arch = "arm"),
11667    stable(feature = "neon_intrinsics", since = "1.59.0")
11668)]
11669#[cfg_attr(
11670    target_arch = "arm",
11671    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11672)]
11673pub fn vextq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
11674    static_assert_uimm_bits!(N, 3);
11675    unsafe {
11676        match N & 0b111 {
11677            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11678            1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11679            2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11680            3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11681            4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11682            5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11683            6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11684            7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11685            _ => unreachable_unchecked(),
11686        }
11687    }
11688}
11689#[doc = "Extract vector from pair of vectors"]
11690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u8)"]
11691#[inline]
11692#[target_feature(enable = "neon")]
11693#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11694#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11695#[cfg_attr(
11696    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11697    assert_instr(ext, N = 7)
11698)]
11699#[rustc_legacy_const_generics(2)]
11700#[cfg_attr(
11701    not(target_arch = "arm"),
11702    stable(feature = "neon_intrinsics", since = "1.59.0")
11703)]
11704#[cfg_attr(
11705    target_arch = "arm",
11706    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11707)]
11708pub fn vext_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
11709    static_assert_uimm_bits!(N, 3);
11710    unsafe {
11711        match N & 0b111 {
11712            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11713            1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11714            2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11715            3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11716            4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11717            5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11718            6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11719            7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11720            _ => unreachable_unchecked(),
11721        }
11722    }
11723}
11724#[doc = "Extract vector from pair of vectors"]
11725#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u16)"]
11726#[inline]
11727#[target_feature(enable = "neon")]
11728#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11729#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11730#[cfg_attr(
11731    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11732    assert_instr(ext, N = 7)
11733)]
11734#[rustc_legacy_const_generics(2)]
11735#[cfg_attr(
11736    not(target_arch = "arm"),
11737    stable(feature = "neon_intrinsics", since = "1.59.0")
11738)]
11739#[cfg_attr(
11740    target_arch = "arm",
11741    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11742)]
11743pub fn vextq_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
11744    static_assert_uimm_bits!(N, 3);
11745    unsafe {
11746        match N & 0b111 {
11747            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11748            1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11749            2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11750            3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11751            4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11752            5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11753            6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11754            7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11755            _ => unreachable_unchecked(),
11756        }
11757    }
11758}
11759#[doc = "Extract vector from pair of vectors"]
11760#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p8)"]
11761#[inline]
11762#[target_feature(enable = "neon")]
11763#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11764#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11765#[cfg_attr(
11766    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11767    assert_instr(ext, N = 7)
11768)]
11769#[rustc_legacy_const_generics(2)]
11770#[cfg_attr(
11771    not(target_arch = "arm"),
11772    stable(feature = "neon_intrinsics", since = "1.59.0")
11773)]
11774#[cfg_attr(
11775    target_arch = "arm",
11776    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11777)]
11778pub fn vext_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
11779    static_assert_uimm_bits!(N, 3);
11780    unsafe {
11781        match N & 0b111 {
11782            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11783            1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11784            2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11785            3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11786            4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11787            5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11788            6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11789            7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11790            _ => unreachable_unchecked(),
11791        }
11792    }
11793}
11794#[doc = "Extract vector from pair of vectors"]
11795#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p16)"]
11796#[inline]
11797#[target_feature(enable = "neon")]
11798#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11799#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11800#[cfg_attr(
11801    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11802    assert_instr(ext, N = 7)
11803)]
11804#[rustc_legacy_const_generics(2)]
11805#[cfg_attr(
11806    not(target_arch = "arm"),
11807    stable(feature = "neon_intrinsics", since = "1.59.0")
11808)]
11809#[cfg_attr(
11810    target_arch = "arm",
11811    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11812)]
11813pub fn vextq_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
11814    static_assert_uimm_bits!(N, 3);
11815    unsafe {
11816        match N & 0b111 {
11817            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11818            1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11819            2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11820            3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11821            4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11822            5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11823            6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11824            7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11825            _ => unreachable_unchecked(),
11826        }
11827    }
11828}
11829#[doc = "Extract vector from pair of vectors"]
11830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f16)"]
11831#[inline]
11832#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11833#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11834#[cfg_attr(
11835    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11836    assert_instr(ext, N = 7)
11837)]
11838#[rustc_legacy_const_generics(2)]
11839#[target_feature(enable = "neon,fp16")]
11840#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
11841pub fn vextq_f16<const N: i32>(a: float16x8_t, b: float16x8_t) -> float16x8_t {
11842    static_assert_uimm_bits!(N, 3);
11843    unsafe {
11844        match N & 0b111 {
11845            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11846            1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11847            2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11848            3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11849            4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11850            5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11851            6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11852            7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11853            _ => unreachable_unchecked(),
11854        }
11855    }
11856}
11857#[doc = "Extract vector from pair of vectors"]
11858#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f32)"]
11859#[inline]
11860#[target_feature(enable = "neon")]
11861#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11862#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
11863#[cfg_attr(
11864    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11865    assert_instr(ext, N = 3)
11866)]
11867#[rustc_legacy_const_generics(2)]
11868#[cfg_attr(
11869    not(target_arch = "arm"),
11870    stable(feature = "neon_intrinsics", since = "1.59.0")
11871)]
11872#[cfg_attr(
11873    target_arch = "arm",
11874    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11875)]
11876pub fn vextq_f32<const N: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t {
11877    static_assert_uimm_bits!(N, 2);
11878    unsafe {
11879        match N & 0b11 {
11880            0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
11881            1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
11882            2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
11883            3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
11884            _ => unreachable_unchecked(),
11885        }
11886    }
11887}
11888#[doc = "Extract vector from pair of vectors"]
11889#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s16)"]
11890#[inline]
11891#[target_feature(enable = "neon")]
11892#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11893#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
11894#[cfg_attr(
11895    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11896    assert_instr(ext, N = 3)
11897)]
11898#[rustc_legacy_const_generics(2)]
11899#[cfg_attr(
11900    not(target_arch = "arm"),
11901    stable(feature = "neon_intrinsics", since = "1.59.0")
11902)]
11903#[cfg_attr(
11904    target_arch = "arm",
11905    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11906)]
11907pub fn vext_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
11908    static_assert_uimm_bits!(N, 2);
11909    unsafe {
11910        match N & 0b11 {
11911            0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
11912            1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
11913            2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
11914            3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
11915            _ => unreachable_unchecked(),
11916        }
11917    }
11918}
11919#[doc = "Extract vector from pair of vectors"]
11920#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s32)"]
11921#[inline]
11922#[target_feature(enable = "neon")]
11923#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11924#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
11925#[cfg_attr(
11926    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11927    assert_instr(ext, N = 3)
11928)]
11929#[rustc_legacy_const_generics(2)]
11930#[cfg_attr(
11931    not(target_arch = "arm"),
11932    stable(feature = "neon_intrinsics", since = "1.59.0")
11933)]
11934#[cfg_attr(
11935    target_arch = "arm",
11936    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11937)]
11938pub fn vextq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
11939    static_assert_uimm_bits!(N, 2);
11940    unsafe {
11941        match N & 0b11 {
11942            0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
11943            1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
11944            2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
11945            3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
11946            _ => unreachable_unchecked(),
11947        }
11948    }
11949}
11950#[doc = "Extract vector from pair of vectors"]
11951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u16)"]
11952#[inline]
11953#[target_feature(enable = "neon")]
11954#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11955#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
11956#[cfg_attr(
11957    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11958    assert_instr(ext, N = 3)
11959)]
11960#[rustc_legacy_const_generics(2)]
11961#[cfg_attr(
11962    not(target_arch = "arm"),
11963    stable(feature = "neon_intrinsics", since = "1.59.0")
11964)]
11965#[cfg_attr(
11966    target_arch = "arm",
11967    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11968)]
11969pub fn vext_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
11970    static_assert_uimm_bits!(N, 2);
11971    unsafe {
11972        match N & 0b11 {
11973            0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
11974            1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
11975            2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
11976            3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
11977            _ => unreachable_unchecked(),
11978        }
11979    }
11980}
11981#[doc = "Extract vector from pair of vectors"]
11982#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u32)"]
11983#[inline]
11984#[target_feature(enable = "neon")]
11985#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11986#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
11987#[cfg_attr(
11988    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11989    assert_instr(ext, N = 3)
11990)]
11991#[rustc_legacy_const_generics(2)]
11992#[cfg_attr(
11993    not(target_arch = "arm"),
11994    stable(feature = "neon_intrinsics", since = "1.59.0")
11995)]
11996#[cfg_attr(
11997    target_arch = "arm",
11998    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11999)]
12000pub fn vextq_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
12001    static_assert_uimm_bits!(N, 2);
12002    unsafe {
12003        match N & 0b11 {
12004            0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
12005            1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
12006            2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
12007            3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
12008            _ => unreachable_unchecked(),
12009        }
12010    }
12011}
12012#[doc = "Extract vector from pair of vectors"]
12013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p16)"]
12014#[inline]
12015#[target_feature(enable = "neon")]
12016#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12017#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
12018#[cfg_attr(
12019    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12020    assert_instr(ext, N = 3)
12021)]
12022#[rustc_legacy_const_generics(2)]
12023#[cfg_attr(
12024    not(target_arch = "arm"),
12025    stable(feature = "neon_intrinsics", since = "1.59.0")
12026)]
12027#[cfg_attr(
12028    target_arch = "arm",
12029    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12030)]
12031pub fn vext_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
12032    static_assert_uimm_bits!(N, 2);
12033    unsafe {
12034        match N & 0b11 {
12035            0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
12036            1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
12037            2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
12038            3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
12039            _ => unreachable_unchecked(),
12040        }
12041    }
12042}
12043#[doc = "Extract vector from pair of vectors"]
12044#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s64)"]
12045#[inline]
12046#[target_feature(enable = "neon")]
12047#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12048#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
12049#[cfg_attr(
12050    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12051    assert_instr(ext, N = 1)
12052)]
12053#[rustc_legacy_const_generics(2)]
12054#[cfg_attr(
12055    not(target_arch = "arm"),
12056    stable(feature = "neon_intrinsics", since = "1.59.0")
12057)]
12058#[cfg_attr(
12059    target_arch = "arm",
12060    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12061)]
12062pub fn vextq_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
12063    static_assert_uimm_bits!(N, 1);
12064    unsafe {
12065        match N & 0b1 {
12066            0 => simd_shuffle!(a, b, [0, 1]),
12067            1 => simd_shuffle!(a, b, [1, 2]),
12068            _ => unreachable_unchecked(),
12069        }
12070    }
12071}
12072#[doc = "Extract vector from pair of vectors"]
12073#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u64)"]
12074#[inline]
12075#[target_feature(enable = "neon")]
12076#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12077#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
12078#[cfg_attr(
12079    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12080    assert_instr(ext, N = 1)
12081)]
12082#[rustc_legacy_const_generics(2)]
12083#[cfg_attr(
12084    not(target_arch = "arm"),
12085    stable(feature = "neon_intrinsics", since = "1.59.0")
12086)]
12087#[cfg_attr(
12088    target_arch = "arm",
12089    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12090)]
12091pub fn vextq_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
12092    static_assert_uimm_bits!(N, 1);
12093    unsafe {
12094        match N & 0b1 {
12095            0 => simd_shuffle!(a, b, [0, 1]),
12096            1 => simd_shuffle!(a, b, [1, 2]),
12097            _ => unreachable_unchecked(),
12098        }
12099    }
12100}
12101#[doc = "Extract vector from pair of vectors"]
12102#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s8)"]
12103#[inline]
12104#[target_feature(enable = "neon")]
12105#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12106#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
12107#[cfg_attr(
12108    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12109    assert_instr(ext, N = 15)
12110)]
12111#[rustc_legacy_const_generics(2)]
12112#[cfg_attr(
12113    not(target_arch = "arm"),
12114    stable(feature = "neon_intrinsics", since = "1.59.0")
12115)]
12116#[cfg_attr(
12117    target_arch = "arm",
12118    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12119)]
12120pub fn vextq_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
12121    static_assert_uimm_bits!(N, 4);
12122    unsafe {
12123        match N & 0b1111 {
12124            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]),
12125            1 => simd_shuffle!(
12126                a,
12127                b,
12128                [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
12129            ),
12130            2 => simd_shuffle!(
12131                a,
12132                b,
12133                [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]
12134            ),
12135            3 => simd_shuffle!(
12136                a,
12137                b,
12138                [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]
12139            ),
12140            4 => simd_shuffle!(
12141                a,
12142                b,
12143                [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]
12144            ),
12145            5 => simd_shuffle!(
12146                a,
12147                b,
12148                [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]
12149            ),
12150            6 => simd_shuffle!(
12151                a,
12152                b,
12153                [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]
12154            ),
12155            7 => simd_shuffle!(
12156                a,
12157                b,
12158                [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]
12159            ),
12160            8 => simd_shuffle!(
12161                a,
12162                b,
12163                [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]
12164            ),
12165            9 => simd_shuffle!(
12166                a,
12167                b,
12168                [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]
12169            ),
12170            10 => simd_shuffle!(
12171                a,
12172                b,
12173                [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]
12174            ),
12175            11 => simd_shuffle!(
12176                a,
12177                b,
12178                [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]
12179            ),
12180            12 => simd_shuffle!(
12181                a,
12182                b,
12183                [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]
12184            ),
12185            13 => simd_shuffle!(
12186                a,
12187                b,
12188                [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]
12189            ),
12190            14 => simd_shuffle!(
12191                a,
12192                b,
12193                [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]
12194            ),
12195            15 => simd_shuffle!(
12196                a,
12197                b,
12198                [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]
12199            ),
12200            _ => unreachable_unchecked(),
12201        }
12202    }
12203}
12204#[doc = "Extract vector from pair of vectors"]
12205#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u8)"]
12206#[inline]
12207#[target_feature(enable = "neon")]
12208#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12209#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
12210#[cfg_attr(
12211    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12212    assert_instr(ext, N = 15)
12213)]
12214#[rustc_legacy_const_generics(2)]
12215#[cfg_attr(
12216    not(target_arch = "arm"),
12217    stable(feature = "neon_intrinsics", since = "1.59.0")
12218)]
12219#[cfg_attr(
12220    target_arch = "arm",
12221    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12222)]
12223pub fn vextq_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
12224    static_assert_uimm_bits!(N, 4);
12225    unsafe {
12226        match N & 0b1111 {
12227            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]),
12228            1 => simd_shuffle!(
12229                a,
12230                b,
12231                [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
12232            ),
12233            2 => simd_shuffle!(
12234                a,
12235                b,
12236                [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]
12237            ),
12238            3 => simd_shuffle!(
12239                a,
12240                b,
12241                [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]
12242            ),
12243            4 => simd_shuffle!(
12244                a,
12245                b,
12246                [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]
12247            ),
12248            5 => simd_shuffle!(
12249                a,
12250                b,
12251                [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]
12252            ),
12253            6 => simd_shuffle!(
12254                a,
12255                b,
12256                [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]
12257            ),
12258            7 => simd_shuffle!(
12259                a,
12260                b,
12261                [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]
12262            ),
12263            8 => simd_shuffle!(
12264                a,
12265                b,
12266                [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]
12267            ),
12268            9 => simd_shuffle!(
12269                a,
12270                b,
12271                [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]
12272            ),
12273            10 => simd_shuffle!(
12274                a,
12275                b,
12276                [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]
12277            ),
12278            11 => simd_shuffle!(
12279                a,
12280                b,
12281                [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]
12282            ),
12283            12 => simd_shuffle!(
12284                a,
12285                b,
12286                [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]
12287            ),
12288            13 => simd_shuffle!(
12289                a,
12290                b,
12291                [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]
12292            ),
12293            14 => simd_shuffle!(
12294                a,
12295                b,
12296                [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]
12297            ),
12298            15 => simd_shuffle!(
12299                a,
12300                b,
12301                [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]
12302            ),
12303            _ => unreachable_unchecked(),
12304        }
12305    }
12306}
12307#[doc = "Extract vector from pair of vectors"]
12308#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p8)"]
12309#[inline]
12310#[target_feature(enable = "neon")]
12311#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12312#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
12313#[cfg_attr(
12314    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12315    assert_instr(ext, N = 15)
12316)]
12317#[rustc_legacy_const_generics(2)]
12318#[cfg_attr(
12319    not(target_arch = "arm"),
12320    stable(feature = "neon_intrinsics", since = "1.59.0")
12321)]
12322#[cfg_attr(
12323    target_arch = "arm",
12324    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12325)]
12326pub fn vextq_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
12327    static_assert_uimm_bits!(N, 4);
12328    unsafe {
12329        match N & 0b1111 {
12330            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]),
12331            1 => simd_shuffle!(
12332                a,
12333                b,
12334                [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
12335            ),
12336            2 => simd_shuffle!(
12337                a,
12338                b,
12339                [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]
12340            ),
12341            3 => simd_shuffle!(
12342                a,
12343                b,
12344                [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]
12345            ),
12346            4 => simd_shuffle!(
12347                a,
12348                b,
12349                [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]
12350            ),
12351            5 => simd_shuffle!(
12352                a,
12353                b,
12354                [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]
12355            ),
12356            6 => simd_shuffle!(
12357                a,
12358                b,
12359                [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]
12360            ),
12361            7 => simd_shuffle!(
12362                a,
12363                b,
12364                [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]
12365            ),
12366            8 => simd_shuffle!(
12367                a,
12368                b,
12369                [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]
12370            ),
12371            9 => simd_shuffle!(
12372                a,
12373                b,
12374                [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]
12375            ),
12376            10 => simd_shuffle!(
12377                a,
12378                b,
12379                [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]
12380            ),
12381            11 => simd_shuffle!(
12382                a,
12383                b,
12384                [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]
12385            ),
12386            12 => simd_shuffle!(
12387                a,
12388                b,
12389                [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]
12390            ),
12391            13 => simd_shuffle!(
12392                a,
12393                b,
12394                [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]
12395            ),
12396            14 => simd_shuffle!(
12397                a,
12398                b,
12399                [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]
12400            ),
12401            15 => simd_shuffle!(
12402                a,
12403                b,
12404                [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]
12405            ),
12406            _ => unreachable_unchecked(),
12407        }
12408    }
12409}
12410#[doc = "Floating-point fused Multiply-Add to accumulator (vector)"]
12411#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f16)"]
12412#[inline]
12413#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12414#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12415#[cfg_attr(
12416    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12417    assert_instr(fmla)
12418)]
12419#[target_feature(enable = "neon,fp16")]
12420#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12421pub fn vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
12422    unsafe { simd_fma(b, c, a) }
12423}
12424#[doc = "Floating-point fused Multiply-Add to accumulator (vector)"]
12425#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f16)"]
12426#[inline]
12427#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12428#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12429#[cfg_attr(
12430    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12431    assert_instr(fmla)
12432)]
12433#[target_feature(enable = "neon,fp16")]
12434#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12435pub fn vfmaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
12436    unsafe { simd_fma(b, c, a) }
12437}
12438#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
12439#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f32)"]
12440#[inline]
12441#[target_feature(enable = "neon")]
12442#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12443#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12444#[cfg_attr(
12445    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12446    assert_instr(fmla)
12447)]
12448#[cfg_attr(
12449    not(target_arch = "arm"),
12450    stable(feature = "neon_intrinsics", since = "1.59.0")
12451)]
12452#[cfg_attr(
12453    target_arch = "arm",
12454    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12455)]
12456pub fn vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
12457    unsafe { simd_fma(b, c, a) }
12458}
12459#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
12460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f32)"]
12461#[inline]
12462#[target_feature(enable = "neon")]
12463#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12464#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12465#[cfg_attr(
12466    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12467    assert_instr(fmla)
12468)]
12469#[cfg_attr(
12470    not(target_arch = "arm"),
12471    stable(feature = "neon_intrinsics", since = "1.59.0")
12472)]
12473#[cfg_attr(
12474    target_arch = "arm",
12475    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12476)]
12477pub fn vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
12478    unsafe { simd_fma(b, c, a) }
12479}
12480#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
12481#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f32)"]
12482#[inline]
12483#[target_feature(enable = "neon")]
12484#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12485#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12486#[cfg_attr(
12487    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12488    assert_instr(fmla)
12489)]
12490#[cfg_attr(
12491    not(target_arch = "arm"),
12492    stable(feature = "neon_intrinsics", since = "1.59.0")
12493)]
12494#[cfg_attr(
12495    target_arch = "arm",
12496    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12497)]
12498pub fn vfma_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
12499    vfma_f32(a, b, vdup_n_f32_vfp4(c))
12500}
12501#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
12502#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f32)"]
12503#[inline]
12504#[target_feature(enable = "neon")]
12505#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12506#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12507#[cfg_attr(
12508    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12509    assert_instr(fmla)
12510)]
12511#[cfg_attr(
12512    not(target_arch = "arm"),
12513    stable(feature = "neon_intrinsics", since = "1.59.0")
12514)]
12515#[cfg_attr(
12516    target_arch = "arm",
12517    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12518)]
12519pub fn vfmaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
12520    vfmaq_f32(a, b, vdupq_n_f32_vfp4(c))
12521}
12522#[doc = "Floating-point fused multiply-subtract from accumulator"]
12523#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f16)"]
12524#[inline]
12525#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
12526#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12527#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
12528#[cfg_attr(
12529    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12530    assert_instr(fmls)
12531)]
12532#[target_feature(enable = "neon,fp16")]
12533#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12534pub fn vfms_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
12535    unsafe {
12536        let b: float16x4_t = simd_neg(b);
12537        vfma_f16(a, b, c)
12538    }
12539}
12540#[doc = "Floating-point fused multiply-subtract from accumulator"]
12541#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f16)"]
12542#[inline]
12543#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
12544#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12545#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
12546#[cfg_attr(
12547    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12548    assert_instr(fmls)
12549)]
12550#[target_feature(enable = "neon,fp16")]
12551#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12552pub fn vfmsq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
12553    unsafe {
12554        let b: float16x8_t = simd_neg(b);
12555        vfmaq_f16(a, b, c)
12556    }
12557}
12558#[doc = "Floating-point fused multiply-subtract from accumulator"]
12559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f32)"]
12560#[inline]
12561#[target_feature(enable = "neon")]
12562#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12563#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
12564#[cfg_attr(
12565    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12566    assert_instr(fmls)
12567)]
12568#[cfg_attr(
12569    not(target_arch = "arm"),
12570    stable(feature = "neon_intrinsics", since = "1.59.0")
12571)]
12572#[cfg_attr(
12573    target_arch = "arm",
12574    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12575)]
12576pub fn vfms_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
12577    unsafe {
12578        let b: float32x2_t = simd_neg(b);
12579        vfma_f32(a, b, c)
12580    }
12581}
12582#[doc = "Floating-point fused multiply-subtract from accumulator"]
12583#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f32)"]
12584#[inline]
12585#[target_feature(enable = "neon")]
12586#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12587#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
12588#[cfg_attr(
12589    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12590    assert_instr(fmls)
12591)]
12592#[cfg_attr(
12593    not(target_arch = "arm"),
12594    stable(feature = "neon_intrinsics", since = "1.59.0")
12595)]
12596#[cfg_attr(
12597    target_arch = "arm",
12598    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12599)]
12600pub fn vfmsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
12601    unsafe {
12602        let b: float32x4_t = simd_neg(b);
12603        vfmaq_f32(a, b, c)
12604    }
12605}
12606#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
12607#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f32)"]
12608#[inline]
12609#[target_feature(enable = "neon")]
12610#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12611#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
12612#[cfg_attr(
12613    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12614    assert_instr(fmls)
12615)]
12616#[cfg_attr(
12617    not(target_arch = "arm"),
12618    stable(feature = "neon_intrinsics", since = "1.59.0")
12619)]
12620#[cfg_attr(
12621    target_arch = "arm",
12622    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12623)]
12624pub fn vfms_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
12625    vfms_f32(a, b, vdup_n_f32_vfp4(c))
12626}
12627#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
12628#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f32)"]
12629#[inline]
12630#[target_feature(enable = "neon")]
12631#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12632#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
12633#[cfg_attr(
12634    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12635    assert_instr(fmls)
12636)]
12637#[cfg_attr(
12638    not(target_arch = "arm"),
12639    stable(feature = "neon_intrinsics", since = "1.59.0")
12640)]
12641#[cfg_attr(
12642    target_arch = "arm",
12643    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12644)]
12645pub fn vfmsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
12646    vfmsq_f32(a, b, vdupq_n_f32_vfp4(c))
12647}
12648#[doc = "Duplicate vector element to vector"]
12649#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f16)"]
12650#[inline]
12651#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12652#[target_feature(enable = "neon,fp16")]
12653#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12654#[cfg_attr(test, assert_instr(nop))]
12655pub fn vget_high_f16(a: float16x8_t) -> float16x4_t {
12656    unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) }
12657}
12658#[doc = "Duplicate vector element to vector"]
12659#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f16)"]
12660#[inline]
12661#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12662#[target_feature(enable = "neon,fp16")]
12663#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12664#[cfg_attr(test, assert_instr(nop))]
12665pub fn vget_low_f16(a: float16x8_t) -> float16x4_t {
12666    unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }
12667}
12668#[doc = "Duplicate vector element to vector or scalar"]
12669#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f32)"]
12670#[inline]
12671#[target_feature(enable = "neon")]
12672#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12673#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12674#[cfg_attr(
12675    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12676    assert_instr(ext)
12677)]
12678#[cfg_attr(
12679    not(target_arch = "arm"),
12680    stable(feature = "neon_intrinsics", since = "1.59.0")
12681)]
12682#[cfg_attr(
12683    target_arch = "arm",
12684    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12685)]
12686pub fn vget_high_f32(a: float32x4_t) -> float32x2_t {
12687    unsafe { simd_shuffle!(a, a, [2, 3]) }
12688}
12689#[doc = "Duplicate vector element to vector or scalar"]
12690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p16)"]
12691#[inline]
12692#[target_feature(enable = "neon")]
12693#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12694#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12695#[cfg_attr(
12696    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12697    assert_instr(ext)
12698)]
12699#[cfg_attr(
12700    not(target_arch = "arm"),
12701    stable(feature = "neon_intrinsics", since = "1.59.0")
12702)]
12703#[cfg_attr(
12704    target_arch = "arm",
12705    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12706)]
12707pub fn vget_high_p16(a: poly16x8_t) -> poly16x4_t {
12708    unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) }
12709}
12710#[doc = "Duplicate vector element to vector or scalar"]
12711#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p8)"]
12712#[inline]
12713#[target_feature(enable = "neon")]
12714#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12715#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12716#[cfg_attr(
12717    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12718    assert_instr(ext)
12719)]
12720#[cfg_attr(
12721    not(target_arch = "arm"),
12722    stable(feature = "neon_intrinsics", since = "1.59.0")
12723)]
12724#[cfg_attr(
12725    target_arch = "arm",
12726    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12727)]
12728pub fn vget_high_p8(a: poly8x16_t) -> poly8x8_t {
12729    unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) }
12730}
12731#[doc = "Duplicate vector element to vector or scalar"]
12732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s16)"]
12733#[inline]
12734#[target_feature(enable = "neon")]
12735#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12736#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12737#[cfg_attr(
12738    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12739    assert_instr(ext)
12740)]
12741#[cfg_attr(
12742    not(target_arch = "arm"),
12743    stable(feature = "neon_intrinsics", since = "1.59.0")
12744)]
12745#[cfg_attr(
12746    target_arch = "arm",
12747    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12748)]
12749pub fn vget_high_s16(a: int16x8_t) -> int16x4_t {
12750    unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) }
12751}
12752#[doc = "Duplicate vector element to vector or scalar"]
12753#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s32)"]
12754#[inline]
12755#[target_feature(enable = "neon")]
12756#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12757#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12758#[cfg_attr(
12759    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12760    assert_instr(ext)
12761)]
12762#[cfg_attr(
12763    not(target_arch = "arm"),
12764    stable(feature = "neon_intrinsics", since = "1.59.0")
12765)]
12766#[cfg_attr(
12767    target_arch = "arm",
12768    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12769)]
12770pub fn vget_high_s32(a: int32x4_t) -> int32x2_t {
12771    unsafe { simd_shuffle!(a, a, [2, 3]) }
12772}
12773#[doc = "Duplicate vector element to vector or scalar"]
12774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s8)"]
12775#[inline]
12776#[target_feature(enable = "neon")]
12777#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12778#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12779#[cfg_attr(
12780    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12781    assert_instr(ext)
12782)]
12783#[cfg_attr(
12784    not(target_arch = "arm"),
12785    stable(feature = "neon_intrinsics", since = "1.59.0")
12786)]
12787#[cfg_attr(
12788    target_arch = "arm",
12789    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12790)]
12791pub fn vget_high_s8(a: int8x16_t) -> int8x8_t {
12792    unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) }
12793}
12794#[doc = "Duplicate vector element to vector or scalar"]
12795#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u16)"]
12796#[inline]
12797#[target_feature(enable = "neon")]
12798#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12799#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12800#[cfg_attr(
12801    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12802    assert_instr(ext)
12803)]
12804#[cfg_attr(
12805    not(target_arch = "arm"),
12806    stable(feature = "neon_intrinsics", since = "1.59.0")
12807)]
12808#[cfg_attr(
12809    target_arch = "arm",
12810    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12811)]
12812pub fn vget_high_u16(a: uint16x8_t) -> uint16x4_t {
12813    unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) }
12814}
12815#[doc = "Duplicate vector element to vector or scalar"]
12816#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u32)"]
12817#[inline]
12818#[target_feature(enable = "neon")]
12819#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12820#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12821#[cfg_attr(
12822    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12823    assert_instr(ext)
12824)]
12825#[cfg_attr(
12826    not(target_arch = "arm"),
12827    stable(feature = "neon_intrinsics", since = "1.59.0")
12828)]
12829#[cfg_attr(
12830    target_arch = "arm",
12831    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12832)]
12833pub fn vget_high_u32(a: uint32x4_t) -> uint32x2_t {
12834    unsafe { simd_shuffle!(a, a, [2, 3]) }
12835}
12836#[doc = "Duplicate vector element to vector or scalar"]
12837#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u8)"]
12838#[inline]
12839#[target_feature(enable = "neon")]
12840#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12841#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12842#[cfg_attr(
12843    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12844    assert_instr(ext)
12845)]
12846#[cfg_attr(
12847    not(target_arch = "arm"),
12848    stable(feature = "neon_intrinsics", since = "1.59.0")
12849)]
12850#[cfg_attr(
12851    target_arch = "arm",
12852    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12853)]
12854pub fn vget_high_u8(a: uint8x16_t) -> uint8x8_t {
12855    unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) }
12856}
12857#[doc = "Duplicate vector element to vector or scalar"]
12858#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s64)"]
12859#[inline]
12860#[target_feature(enable = "neon")]
12861#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12862#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12863#[cfg_attr(
12864    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12865    assert_instr(ext)
12866)]
12867#[cfg_attr(
12868    not(target_arch = "arm"),
12869    stable(feature = "neon_intrinsics", since = "1.59.0")
12870)]
12871#[cfg_attr(
12872    target_arch = "arm",
12873    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12874)]
12875pub fn vget_high_s64(a: int64x2_t) -> int64x1_t {
12876    unsafe { int64x1_t([simd_extract!(a, 1)]) }
12877}
12878#[doc = "Duplicate vector element to vector or scalar"]
12879#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u64)"]
12880#[inline]
12881#[target_feature(enable = "neon")]
12882#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12883#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12884#[cfg_attr(
12885    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12886    assert_instr(ext)
12887)]
12888#[cfg_attr(
12889    not(target_arch = "arm"),
12890    stable(feature = "neon_intrinsics", since = "1.59.0")
12891)]
12892#[cfg_attr(
12893    target_arch = "arm",
12894    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12895)]
12896pub fn vget_high_u64(a: uint64x2_t) -> uint64x1_t {
12897    unsafe { uint64x1_t([simd_extract!(a, 1)]) }
12898}
12899#[doc = "Duplicate vector element to scalar"]
12900#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f16)"]
12901#[inline]
12902#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12903#[target_feature(enable = "neon,fp16")]
12904#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
12905#[cfg_attr(
12906    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12907    assert_instr(nop, LANE = 0)
12908)]
12909#[rustc_legacy_const_generics(1)]
12910#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12911pub fn vget_lane_f16<const LANE: i32>(a: float16x4_t) -> f16 {
12912    static_assert_uimm_bits!(LANE, 2);
12913    unsafe { simd_extract!(a, LANE as u32) }
12914}
12915#[doc = "Duplicate vector element to scalar"]
12916#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f16)"]
12917#[inline]
12918#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12919#[target_feature(enable = "neon,fp16")]
12920#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
12921#[cfg_attr(
12922    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12923    assert_instr(nop, LANE = 0)
12924)]
12925#[rustc_legacy_const_generics(1)]
12926#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12927pub fn vgetq_lane_f16<const LANE: i32>(a: float16x8_t) -> f16 {
12928    static_assert_uimm_bits!(LANE, 3);
12929    unsafe { simd_extract!(a, LANE as u32) }
12930}
12931#[doc = "Move vector element to general-purpose register"]
12932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f32)"]
12933#[inline]
12934#[target_feature(enable = "neon")]
12935#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12936#[rustc_legacy_const_generics(1)]
12937#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
12938#[cfg_attr(
12939    not(target_arch = "arm"),
12940    stable(feature = "neon_intrinsics", since = "1.59.0")
12941)]
12942#[cfg_attr(
12943    target_arch = "arm",
12944    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12945)]
12946pub fn vget_lane_f32<const IMM5: i32>(v: float32x2_t) -> f32 {
12947    static_assert_uimm_bits!(IMM5, 1);
12948    unsafe { simd_extract!(v, IMM5 as u32) }
12949}
12950#[doc = "Move vector element to general-purpose register"]
12951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p16)"]
12952#[inline]
12953#[target_feature(enable = "neon")]
12954#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12955#[rustc_legacy_const_generics(1)]
12956#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
12957#[cfg_attr(
12958    not(target_arch = "arm"),
12959    stable(feature = "neon_intrinsics", since = "1.59.0")
12960)]
12961#[cfg_attr(
12962    target_arch = "arm",
12963    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12964)]
12965pub fn vget_lane_p16<const IMM5: i32>(v: poly16x4_t) -> p16 {
12966    static_assert_uimm_bits!(IMM5, 2);
12967    unsafe { simd_extract!(v, IMM5 as u32) }
12968}
12969#[doc = "Move vector element to general-purpose register"]
12970#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p8)"]
12971#[inline]
12972#[target_feature(enable = "neon")]
12973#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12974#[rustc_legacy_const_generics(1)]
12975#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
12976#[cfg_attr(
12977    not(target_arch = "arm"),
12978    stable(feature = "neon_intrinsics", since = "1.59.0")
12979)]
12980#[cfg_attr(
12981    target_arch = "arm",
12982    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12983)]
12984pub fn vget_lane_p8<const IMM5: i32>(v: poly8x8_t) -> p8 {
12985    static_assert_uimm_bits!(IMM5, 3);
12986    unsafe { simd_extract!(v, IMM5 as u32) }
12987}
12988#[doc = "Move vector element to general-purpose register"]
12989#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s16)"]
12990#[inline]
12991#[target_feature(enable = "neon")]
12992#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12993#[rustc_legacy_const_generics(1)]
12994#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
12995#[cfg_attr(
12996    not(target_arch = "arm"),
12997    stable(feature = "neon_intrinsics", since = "1.59.0")
12998)]
12999#[cfg_attr(
13000    target_arch = "arm",
13001    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13002)]
13003pub fn vget_lane_s16<const IMM5: i32>(v: int16x4_t) -> i16 {
13004    static_assert_uimm_bits!(IMM5, 2);
13005    unsafe { simd_extract!(v, IMM5 as u32) }
13006}
13007#[doc = "Move vector element to general-purpose register"]
13008#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s32)"]
13009#[inline]
13010#[target_feature(enable = "neon")]
13011#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13012#[rustc_legacy_const_generics(1)]
13013#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13014#[cfg_attr(
13015    not(target_arch = "arm"),
13016    stable(feature = "neon_intrinsics", since = "1.59.0")
13017)]
13018#[cfg_attr(
13019    target_arch = "arm",
13020    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13021)]
13022pub fn vget_lane_s32<const IMM5: i32>(v: int32x2_t) -> i32 {
13023    static_assert_uimm_bits!(IMM5, 1);
13024    unsafe { simd_extract!(v, IMM5 as u32) }
13025}
13026#[doc = "Move vector element to general-purpose register"]
13027#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s8)"]
13028#[inline]
13029#[target_feature(enable = "neon")]
13030#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13031#[rustc_legacy_const_generics(1)]
13032#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13033#[cfg_attr(
13034    not(target_arch = "arm"),
13035    stable(feature = "neon_intrinsics", since = "1.59.0")
13036)]
13037#[cfg_attr(
13038    target_arch = "arm",
13039    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13040)]
13041pub fn vget_lane_s8<const IMM5: i32>(v: int8x8_t) -> i8 {
13042    static_assert_uimm_bits!(IMM5, 3);
13043    unsafe { simd_extract!(v, IMM5 as u32) }
13044}
13045#[doc = "Move vector element to general-purpose register"]
13046#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u16)"]
13047#[inline]
13048#[target_feature(enable = "neon")]
13049#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13050#[rustc_legacy_const_generics(1)]
13051#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13052#[cfg_attr(
13053    not(target_arch = "arm"),
13054    stable(feature = "neon_intrinsics", since = "1.59.0")
13055)]
13056#[cfg_attr(
13057    target_arch = "arm",
13058    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13059)]
13060pub fn vget_lane_u16<const IMM5: i32>(v: uint16x4_t) -> u16 {
13061    static_assert_uimm_bits!(IMM5, 2);
13062    unsafe { simd_extract!(v, IMM5 as u32) }
13063}
13064#[doc = "Move vector element to general-purpose register"]
13065#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u32)"]
13066#[inline]
13067#[target_feature(enable = "neon")]
13068#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13069#[rustc_legacy_const_generics(1)]
13070#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13071#[cfg_attr(
13072    not(target_arch = "arm"),
13073    stable(feature = "neon_intrinsics", since = "1.59.0")
13074)]
13075#[cfg_attr(
13076    target_arch = "arm",
13077    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13078)]
13079pub fn vget_lane_u32<const IMM5: i32>(v: uint32x2_t) -> u32 {
13080    static_assert_uimm_bits!(IMM5, 1);
13081    unsafe { simd_extract!(v, IMM5 as u32) }
13082}
13083#[doc = "Move vector element to general-purpose register"]
13084#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u8)"]
13085#[inline]
13086#[target_feature(enable = "neon")]
13087#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13088#[rustc_legacy_const_generics(1)]
13089#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13090#[cfg_attr(
13091    not(target_arch = "arm"),
13092    stable(feature = "neon_intrinsics", since = "1.59.0")
13093)]
13094#[cfg_attr(
13095    target_arch = "arm",
13096    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13097)]
13098pub fn vget_lane_u8<const IMM5: i32>(v: uint8x8_t) -> u8 {
13099    static_assert_uimm_bits!(IMM5, 3);
13100    unsafe { simd_extract!(v, IMM5 as u32) }
13101}
13102#[doc = "Move vector element to general-purpose register"]
13103#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f32)"]
13104#[inline]
13105#[target_feature(enable = "neon")]
13106#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13107#[rustc_legacy_const_generics(1)]
13108#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13109#[cfg_attr(
13110    not(target_arch = "arm"),
13111    stable(feature = "neon_intrinsics", since = "1.59.0")
13112)]
13113#[cfg_attr(
13114    target_arch = "arm",
13115    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13116)]
13117pub fn vgetq_lane_f32<const IMM5: i32>(v: float32x4_t) -> f32 {
13118    static_assert_uimm_bits!(IMM5, 2);
13119    unsafe { simd_extract!(v, IMM5 as u32) }
13120}
13121#[doc = "Move vector element to general-purpose register"]
13122#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p16)"]
13123#[inline]
13124#[target_feature(enable = "neon")]
13125#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13126#[rustc_legacy_const_generics(1)]
13127#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13128#[cfg_attr(
13129    not(target_arch = "arm"),
13130    stable(feature = "neon_intrinsics", since = "1.59.0")
13131)]
13132#[cfg_attr(
13133    target_arch = "arm",
13134    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13135)]
13136pub fn vgetq_lane_p16<const IMM5: i32>(v: poly16x8_t) -> p16 {
13137    static_assert_uimm_bits!(IMM5, 3);
13138    unsafe { simd_extract!(v, IMM5 as u32) }
13139}
13140#[doc = "Move vector element to general-purpose register"]
13141#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p64)"]
13142#[inline]
13143#[target_feature(enable = "neon")]
13144#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13145#[rustc_legacy_const_generics(1)]
13146#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13147#[cfg_attr(
13148    not(target_arch = "arm"),
13149    stable(feature = "neon_intrinsics", since = "1.59.0")
13150)]
13151#[cfg_attr(
13152    target_arch = "arm",
13153    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13154)]
13155pub fn vgetq_lane_p64<const IMM5: i32>(v: poly64x2_t) -> p64 {
13156    static_assert_uimm_bits!(IMM5, 1);
13157    unsafe { simd_extract!(v, IMM5 as u32) }
13158}
13159#[doc = "Move vector element to general-purpose register"]
13160#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p8)"]
13161#[inline]
13162#[target_feature(enable = "neon")]
13163#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13164#[rustc_legacy_const_generics(1)]
13165#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13166#[cfg_attr(
13167    not(target_arch = "arm"),
13168    stable(feature = "neon_intrinsics", since = "1.59.0")
13169)]
13170#[cfg_attr(
13171    target_arch = "arm",
13172    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13173)]
13174pub fn vgetq_lane_p8<const IMM5: i32>(v: poly8x16_t) -> p8 {
13175    static_assert_uimm_bits!(IMM5, 4);
13176    unsafe { simd_extract!(v, IMM5 as u32) }
13177}
13178#[doc = "Move vector element to general-purpose register"]
13179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s16)"]
13180#[inline]
13181#[target_feature(enable = "neon")]
13182#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13183#[rustc_legacy_const_generics(1)]
13184#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13185#[cfg_attr(
13186    not(target_arch = "arm"),
13187    stable(feature = "neon_intrinsics", since = "1.59.0")
13188)]
13189#[cfg_attr(
13190    target_arch = "arm",
13191    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13192)]
13193pub fn vgetq_lane_s16<const IMM5: i32>(v: int16x8_t) -> i16 {
13194    static_assert_uimm_bits!(IMM5, 3);
13195    unsafe { simd_extract!(v, IMM5 as u32) }
13196}
13197#[doc = "Move vector element to general-purpose register"]
13198#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s32)"]
13199#[inline]
13200#[target_feature(enable = "neon")]
13201#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13202#[rustc_legacy_const_generics(1)]
13203#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13204#[cfg_attr(
13205    not(target_arch = "arm"),
13206    stable(feature = "neon_intrinsics", since = "1.59.0")
13207)]
13208#[cfg_attr(
13209    target_arch = "arm",
13210    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13211)]
13212pub fn vgetq_lane_s32<const IMM5: i32>(v: int32x4_t) -> i32 {
13213    static_assert_uimm_bits!(IMM5, 2);
13214    unsafe { simd_extract!(v, IMM5 as u32) }
13215}
13216#[doc = "Move vector element to general-purpose register"]
13217#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s64)"]
13218#[inline]
13219#[target_feature(enable = "neon")]
13220#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13221#[rustc_legacy_const_generics(1)]
13222#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13223#[cfg_attr(
13224    not(target_arch = "arm"),
13225    stable(feature = "neon_intrinsics", since = "1.59.0")
13226)]
13227#[cfg_attr(
13228    target_arch = "arm",
13229    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13230)]
13231pub fn vgetq_lane_s64<const IMM5: i32>(v: int64x2_t) -> i64 {
13232    static_assert_uimm_bits!(IMM5, 1);
13233    unsafe { simd_extract!(v, IMM5 as u32) }
13234}
13235#[doc = "Move vector element to general-purpose register"]
13236#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s8)"]
13237#[inline]
13238#[target_feature(enable = "neon")]
13239#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13240#[rustc_legacy_const_generics(1)]
13241#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13242#[cfg_attr(
13243    not(target_arch = "arm"),
13244    stable(feature = "neon_intrinsics", since = "1.59.0")
13245)]
13246#[cfg_attr(
13247    target_arch = "arm",
13248    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13249)]
13250pub fn vgetq_lane_s8<const IMM5: i32>(v: int8x16_t) -> i8 {
13251    static_assert_uimm_bits!(IMM5, 4);
13252    unsafe { simd_extract!(v, IMM5 as u32) }
13253}
13254#[doc = "Move vector element to general-purpose register"]
13255#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u16)"]
13256#[inline]
13257#[target_feature(enable = "neon")]
13258#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13259#[rustc_legacy_const_generics(1)]
13260#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13261#[cfg_attr(
13262    not(target_arch = "arm"),
13263    stable(feature = "neon_intrinsics", since = "1.59.0")
13264)]
13265#[cfg_attr(
13266    target_arch = "arm",
13267    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13268)]
13269pub fn vgetq_lane_u16<const IMM5: i32>(v: uint16x8_t) -> u16 {
13270    static_assert_uimm_bits!(IMM5, 3);
13271    unsafe { simd_extract!(v, IMM5 as u32) }
13272}
13273#[doc = "Move vector element to general-purpose register"]
13274#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u32)"]
13275#[inline]
13276#[target_feature(enable = "neon")]
13277#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13278#[rustc_legacy_const_generics(1)]
13279#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13280#[cfg_attr(
13281    not(target_arch = "arm"),
13282    stable(feature = "neon_intrinsics", since = "1.59.0")
13283)]
13284#[cfg_attr(
13285    target_arch = "arm",
13286    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13287)]
13288pub fn vgetq_lane_u32<const IMM5: i32>(v: uint32x4_t) -> u32 {
13289    static_assert_uimm_bits!(IMM5, 2);
13290    unsafe { simd_extract!(v, IMM5 as u32) }
13291}
13292#[doc = "Move vector element to general-purpose register"]
13293#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u64)"]
13294#[inline]
13295#[target_feature(enable = "neon")]
13296#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13297#[rustc_legacy_const_generics(1)]
13298#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13299#[cfg_attr(
13300    not(target_arch = "arm"),
13301    stable(feature = "neon_intrinsics", since = "1.59.0")
13302)]
13303#[cfg_attr(
13304    target_arch = "arm",
13305    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13306)]
13307pub fn vgetq_lane_u64<const IMM5: i32>(v: uint64x2_t) -> u64 {
13308    static_assert_uimm_bits!(IMM5, 2);
13309    unsafe { simd_extract!(v, IMM5 as u32) }
13310}
13311#[doc = "Move vector element to general-purpose register"]
13312#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u8)"]
13313#[inline]
13314#[target_feature(enable = "neon")]
13315#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13316#[rustc_legacy_const_generics(1)]
13317#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13318#[cfg_attr(
13319    not(target_arch = "arm"),
13320    stable(feature = "neon_intrinsics", since = "1.59.0")
13321)]
13322#[cfg_attr(
13323    target_arch = "arm",
13324    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13325)]
13326pub fn vgetq_lane_u8<const IMM5: i32>(v: uint8x16_t) -> u8 {
13327    static_assert_uimm_bits!(IMM5, 4);
13328    unsafe { simd_extract!(v, IMM5 as u32) }
13329}
13330#[doc = "Move vector element to general-purpose register"]
13331#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p64)"]
13332#[inline]
13333#[target_feature(enable = "neon")]
13334#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13335#[rustc_legacy_const_generics(1)]
13336#[cfg_attr(test, assert_instr(nop, IMM5 = 0))]
13337#[cfg_attr(
13338    not(target_arch = "arm"),
13339    stable(feature = "neon_intrinsics", since = "1.59.0")
13340)]
13341#[cfg_attr(
13342    target_arch = "arm",
13343    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13344)]
13345pub fn vget_lane_p64<const IMM5: i32>(v: poly64x1_t) -> p64 {
13346    static_assert!(IMM5 == 0);
13347    unsafe { simd_extract!(v, IMM5 as u32) }
13348}
13349#[doc = "Move vector element to general-purpose register"]
13350#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s64)"]
13351#[inline]
13352#[target_feature(enable = "neon")]
13353#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13354#[rustc_legacy_const_generics(1)]
13355#[cfg_attr(test, assert_instr(nop, IMM5 = 0))]
13356#[cfg_attr(
13357    not(target_arch = "arm"),
13358    stable(feature = "neon_intrinsics", since = "1.59.0")
13359)]
13360#[cfg_attr(
13361    target_arch = "arm",
13362    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13363)]
13364pub fn vget_lane_s64<const IMM5: i32>(v: int64x1_t) -> i64 {
13365    static_assert!(IMM5 == 0);
13366    unsafe { simd_extract!(v, IMM5 as u32) }
13367}
13368#[doc = "Move vector element to general-purpose register"]
13369#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u64)"]
13370#[inline]
13371#[target_feature(enable = "neon")]
13372#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13373#[rustc_legacy_const_generics(1)]
13374#[cfg_attr(test, assert_instr(nop, IMM5 = 0))]
13375#[cfg_attr(
13376    not(target_arch = "arm"),
13377    stable(feature = "neon_intrinsics", since = "1.59.0")
13378)]
13379#[cfg_attr(
13380    target_arch = "arm",
13381    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13382)]
13383pub fn vget_lane_u64<const IMM5: i32>(v: uint64x1_t) -> u64 {
13384    static_assert!(IMM5 == 0);
13385    unsafe { simd_extract!(v, 0) }
13386}
13387#[doc = "Duplicate vector element to vector or scalar"]
13388#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f32)"]
13389#[inline]
13390#[target_feature(enable = "neon")]
13391#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13392#[cfg_attr(test, assert_instr(nop))]
13393#[cfg_attr(
13394    not(target_arch = "arm"),
13395    stable(feature = "neon_intrinsics", since = "1.59.0")
13396)]
13397#[cfg_attr(
13398    target_arch = "arm",
13399    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13400)]
13401pub fn vget_low_f32(a: float32x4_t) -> float32x2_t {
13402    unsafe { simd_shuffle!(a, a, [0, 1]) }
13403}
13404#[doc = "Duplicate vector element to vector or scalar"]
13405#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p16)"]
13406#[inline]
13407#[target_feature(enable = "neon")]
13408#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13409#[cfg_attr(test, assert_instr(nop))]
13410#[cfg_attr(
13411    not(target_arch = "arm"),
13412    stable(feature = "neon_intrinsics", since = "1.59.0")
13413)]
13414#[cfg_attr(
13415    target_arch = "arm",
13416    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13417)]
13418pub fn vget_low_p16(a: poly16x8_t) -> poly16x4_t {
13419    unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }
13420}
13421#[doc = "Duplicate vector element to vector or scalar"]
13422#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p8)"]
13423#[inline]
13424#[target_feature(enable = "neon")]
13425#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13426#[cfg_attr(test, assert_instr(nop))]
13427#[cfg_attr(
13428    not(target_arch = "arm"),
13429    stable(feature = "neon_intrinsics", since = "1.59.0")
13430)]
13431#[cfg_attr(
13432    target_arch = "arm",
13433    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13434)]
13435pub fn vget_low_p8(a: poly8x16_t) -> poly8x8_t {
13436    unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }
13437}
13438#[doc = "Duplicate vector element to vector or scalar"]
13439#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s16)"]
13440#[inline]
13441#[target_feature(enable = "neon")]
13442#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13443#[cfg_attr(test, assert_instr(nop))]
13444#[cfg_attr(
13445    not(target_arch = "arm"),
13446    stable(feature = "neon_intrinsics", since = "1.59.0")
13447)]
13448#[cfg_attr(
13449    target_arch = "arm",
13450    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13451)]
13452pub fn vget_low_s16(a: int16x8_t) -> int16x4_t {
13453    unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }
13454}
13455#[doc = "Duplicate vector element to vector or scalar"]
13456#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s32)"]
13457#[inline]
13458#[target_feature(enable = "neon")]
13459#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13460#[cfg_attr(test, assert_instr(nop))]
13461#[cfg_attr(
13462    not(target_arch = "arm"),
13463    stable(feature = "neon_intrinsics", since = "1.59.0")
13464)]
13465#[cfg_attr(
13466    target_arch = "arm",
13467    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13468)]
13469pub fn vget_low_s32(a: int32x4_t) -> int32x2_t {
13470    unsafe { simd_shuffle!(a, a, [0, 1]) }
13471}
13472#[doc = "Duplicate vector element to vector or scalar"]
13473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s8)"]
13474#[inline]
13475#[target_feature(enable = "neon")]
13476#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13477#[cfg_attr(test, assert_instr(nop))]
13478#[cfg_attr(
13479    not(target_arch = "arm"),
13480    stable(feature = "neon_intrinsics", since = "1.59.0")
13481)]
13482#[cfg_attr(
13483    target_arch = "arm",
13484    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13485)]
13486pub fn vget_low_s8(a: int8x16_t) -> int8x8_t {
13487    unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }
13488}
13489#[doc = "Duplicate vector element to vector or scalar"]
13490#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u16)"]
13491#[inline]
13492#[target_feature(enable = "neon")]
13493#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13494#[cfg_attr(test, assert_instr(nop))]
13495#[cfg_attr(
13496    not(target_arch = "arm"),
13497    stable(feature = "neon_intrinsics", since = "1.59.0")
13498)]
13499#[cfg_attr(
13500    target_arch = "arm",
13501    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13502)]
13503pub fn vget_low_u16(a: uint16x8_t) -> uint16x4_t {
13504    unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }
13505}
13506#[doc = "Duplicate vector element to vector or scalar"]
13507#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u32)"]
13508#[inline]
13509#[target_feature(enable = "neon")]
13510#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13511#[cfg_attr(test, assert_instr(nop))]
13512#[cfg_attr(
13513    not(target_arch = "arm"),
13514    stable(feature = "neon_intrinsics", since = "1.59.0")
13515)]
13516#[cfg_attr(
13517    target_arch = "arm",
13518    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13519)]
13520pub fn vget_low_u32(a: uint32x4_t) -> uint32x2_t {
13521    unsafe { simd_shuffle!(a, a, [0, 1]) }
13522}
13523#[doc = "Duplicate vector element to vector or scalar"]
13524#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u8)"]
13525#[inline]
13526#[target_feature(enable = "neon")]
13527#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13528#[cfg_attr(test, assert_instr(nop))]
13529#[cfg_attr(
13530    not(target_arch = "arm"),
13531    stable(feature = "neon_intrinsics", since = "1.59.0")
13532)]
13533#[cfg_attr(
13534    target_arch = "arm",
13535    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13536)]
13537pub fn vget_low_u8(a: uint8x16_t) -> uint8x8_t {
13538    unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }
13539}
13540#[doc = "Duplicate vector element to vector or scalar"]
13541#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s64)"]
13542#[inline]
13543#[target_feature(enable = "neon")]
13544#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13545#[cfg_attr(test, assert_instr(nop))]
13546#[cfg_attr(
13547    not(target_arch = "arm"),
13548    stable(feature = "neon_intrinsics", since = "1.59.0")
13549)]
13550#[cfg_attr(
13551    target_arch = "arm",
13552    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13553)]
13554pub fn vget_low_s64(a: int64x2_t) -> int64x1_t {
13555    unsafe { int64x1_t([simd_extract!(a, 0)]) }
13556}
13557#[doc = "Duplicate vector element to vector or scalar"]
13558#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u64)"]
13559#[inline]
13560#[target_feature(enable = "neon")]
13561#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13562#[cfg_attr(test, assert_instr(nop))]
13563#[cfg_attr(
13564    not(target_arch = "arm"),
13565    stable(feature = "neon_intrinsics", since = "1.59.0")
13566)]
13567#[cfg_attr(
13568    target_arch = "arm",
13569    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13570)]
13571pub fn vget_low_u64(a: uint64x2_t) -> uint64x1_t {
13572    unsafe { uint64x1_t([simd_extract!(a, 0)]) }
13573}
13574#[doc = "Halving add"]
13575#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s8)"]
13576#[inline]
13577#[target_feature(enable = "neon")]
13578#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13579#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))]
13580#[cfg_attr(
13581    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13582    assert_instr(shadd)
13583)]
13584#[cfg_attr(
13585    not(target_arch = "arm"),
13586    stable(feature = "neon_intrinsics", since = "1.59.0")
13587)]
13588#[cfg_attr(
13589    target_arch = "arm",
13590    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13591)]
13592pub fn vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
13593    unsafe extern "unadjusted" {
13594        #[cfg_attr(
13595            any(target_arch = "aarch64", target_arch = "arm64ec"),
13596            link_name = "llvm.aarch64.neon.shadd.v8i8"
13597        )]
13598        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i8")]
13599        fn _vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
13600    }
13601    unsafe { _vhadd_s8(a, b) }
13602}
13603#[doc = "Halving add"]
13604#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s8)"]
13605#[inline]
13606#[target_feature(enable = "neon")]
13607#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13608#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))]
13609#[cfg_attr(
13610    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13611    assert_instr(shadd)
13612)]
13613#[cfg_attr(
13614    not(target_arch = "arm"),
13615    stable(feature = "neon_intrinsics", since = "1.59.0")
13616)]
13617#[cfg_attr(
13618    target_arch = "arm",
13619    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13620)]
13621pub fn vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
13622    unsafe extern "unadjusted" {
13623        #[cfg_attr(
13624            any(target_arch = "aarch64", target_arch = "arm64ec"),
13625            link_name = "llvm.aarch64.neon.shadd.v16i8"
13626        )]
13627        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v16i8")]
13628        fn _vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
13629    }
13630    unsafe { _vhaddq_s8(a, b) }
13631}
13632#[doc = "Halving add"]
13633#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s16)"]
13634#[inline]
13635#[target_feature(enable = "neon")]
13636#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13637#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))]
13638#[cfg_attr(
13639    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13640    assert_instr(shadd)
13641)]
13642#[cfg_attr(
13643    not(target_arch = "arm"),
13644    stable(feature = "neon_intrinsics", since = "1.59.0")
13645)]
13646#[cfg_attr(
13647    target_arch = "arm",
13648    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13649)]
13650pub fn vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
13651    unsafe extern "unadjusted" {
13652        #[cfg_attr(
13653            any(target_arch = "aarch64", target_arch = "arm64ec"),
13654            link_name = "llvm.aarch64.neon.shadd.v4i16"
13655        )]
13656        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i16")]
13657        fn _vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
13658    }
13659    unsafe { _vhadd_s16(a, b) }
13660}
13661#[doc = "Halving add"]
13662#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s16)"]
13663#[inline]
13664#[target_feature(enable = "neon")]
13665#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13666#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))]
13667#[cfg_attr(
13668    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13669    assert_instr(shadd)
13670)]
13671#[cfg_attr(
13672    not(target_arch = "arm"),
13673    stable(feature = "neon_intrinsics", since = "1.59.0")
13674)]
13675#[cfg_attr(
13676    target_arch = "arm",
13677    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13678)]
13679pub fn vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
13680    unsafe extern "unadjusted" {
13681        #[cfg_attr(
13682            any(target_arch = "aarch64", target_arch = "arm64ec"),
13683            link_name = "llvm.aarch64.neon.shadd.v8i16"
13684        )]
13685        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i16")]
13686        fn _vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
13687    }
13688    unsafe { _vhaddq_s16(a, b) }
13689}
13690#[doc = "Halving add"]
13691#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s32)"]
13692#[inline]
13693#[target_feature(enable = "neon")]
13694#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13695#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))]
13696#[cfg_attr(
13697    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13698    assert_instr(shadd)
13699)]
13700#[cfg_attr(
13701    not(target_arch = "arm"),
13702    stable(feature = "neon_intrinsics", since = "1.59.0")
13703)]
13704#[cfg_attr(
13705    target_arch = "arm",
13706    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13707)]
13708pub fn vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
13709    unsafe extern "unadjusted" {
13710        #[cfg_attr(
13711            any(target_arch = "aarch64", target_arch = "arm64ec"),
13712            link_name = "llvm.aarch64.neon.shadd.v2i32"
13713        )]
13714        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v2i32")]
13715        fn _vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
13716    }
13717    unsafe { _vhadd_s32(a, b) }
13718}
13719#[doc = "Halving add"]
13720#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s32)"]
13721#[inline]
13722#[target_feature(enable = "neon")]
13723#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13724#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))]
13725#[cfg_attr(
13726    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13727    assert_instr(shadd)
13728)]
13729#[cfg_attr(
13730    not(target_arch = "arm"),
13731    stable(feature = "neon_intrinsics", since = "1.59.0")
13732)]
13733#[cfg_attr(
13734    target_arch = "arm",
13735    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13736)]
13737pub fn vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
13738    unsafe extern "unadjusted" {
13739        #[cfg_attr(
13740            any(target_arch = "aarch64", target_arch = "arm64ec"),
13741            link_name = "llvm.aarch64.neon.shadd.v4i32"
13742        )]
13743        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i32")]
13744        fn _vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
13745    }
13746    unsafe { _vhaddq_s32(a, b) }
13747}
13748#[doc = "Halving add"]
13749#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u8)"]
13750#[inline]
13751#[target_feature(enable = "neon")]
13752#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13753#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))]
13754#[cfg_attr(
13755    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13756    assert_instr(uhadd)
13757)]
13758#[cfg_attr(
13759    not(target_arch = "arm"),
13760    stable(feature = "neon_intrinsics", since = "1.59.0")
13761)]
13762#[cfg_attr(
13763    target_arch = "arm",
13764    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13765)]
13766pub fn vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
13767    unsafe extern "unadjusted" {
13768        #[cfg_attr(
13769            any(target_arch = "aarch64", target_arch = "arm64ec"),
13770            link_name = "llvm.aarch64.neon.uhadd.v8i8"
13771        )]
13772        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i8")]
13773        fn _vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
13774    }
13775    unsafe { _vhadd_u8(a, b) }
13776}
13777#[doc = "Halving add"]
13778#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u8)"]
13779#[inline]
13780#[target_feature(enable = "neon")]
13781#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13782#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))]
13783#[cfg_attr(
13784    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13785    assert_instr(uhadd)
13786)]
13787#[cfg_attr(
13788    not(target_arch = "arm"),
13789    stable(feature = "neon_intrinsics", since = "1.59.0")
13790)]
13791#[cfg_attr(
13792    target_arch = "arm",
13793    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13794)]
13795pub fn vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
13796    unsafe extern "unadjusted" {
13797        #[cfg_attr(
13798            any(target_arch = "aarch64", target_arch = "arm64ec"),
13799            link_name = "llvm.aarch64.neon.uhadd.v16i8"
13800        )]
13801        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v16i8")]
13802        fn _vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
13803    }
13804    unsafe { _vhaddq_u8(a, b) }
13805}
13806#[doc = "Halving add"]
13807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u16)"]
13808#[inline]
13809#[target_feature(enable = "neon")]
13810#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13811#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))]
13812#[cfg_attr(
13813    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13814    assert_instr(uhadd)
13815)]
13816#[cfg_attr(
13817    not(target_arch = "arm"),
13818    stable(feature = "neon_intrinsics", since = "1.59.0")
13819)]
13820#[cfg_attr(
13821    target_arch = "arm",
13822    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13823)]
13824pub fn vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
13825    unsafe extern "unadjusted" {
13826        #[cfg_attr(
13827            any(target_arch = "aarch64", target_arch = "arm64ec"),
13828            link_name = "llvm.aarch64.neon.uhadd.v4i16"
13829        )]
13830        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i16")]
13831        fn _vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
13832    }
13833    unsafe { _vhadd_u16(a, b) }
13834}
13835#[doc = "Halving add"]
13836#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u16)"]
13837#[inline]
13838#[target_feature(enable = "neon")]
13839#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13840#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))]
13841#[cfg_attr(
13842    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13843    assert_instr(uhadd)
13844)]
13845#[cfg_attr(
13846    not(target_arch = "arm"),
13847    stable(feature = "neon_intrinsics", since = "1.59.0")
13848)]
13849#[cfg_attr(
13850    target_arch = "arm",
13851    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13852)]
13853pub fn vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
13854    unsafe extern "unadjusted" {
13855        #[cfg_attr(
13856            any(target_arch = "aarch64", target_arch = "arm64ec"),
13857            link_name = "llvm.aarch64.neon.uhadd.v8i16"
13858        )]
13859        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i16")]
13860        fn _vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
13861    }
13862    unsafe { _vhaddq_u16(a, b) }
13863}
13864#[doc = "Halving add"]
13865#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u32)"]
13866#[inline]
13867#[target_feature(enable = "neon")]
13868#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13869#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))]
13870#[cfg_attr(
13871    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13872    assert_instr(uhadd)
13873)]
13874#[cfg_attr(
13875    not(target_arch = "arm"),
13876    stable(feature = "neon_intrinsics", since = "1.59.0")
13877)]
13878#[cfg_attr(
13879    target_arch = "arm",
13880    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13881)]
13882pub fn vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
13883    unsafe extern "unadjusted" {
13884        #[cfg_attr(
13885            any(target_arch = "aarch64", target_arch = "arm64ec"),
13886            link_name = "llvm.aarch64.neon.uhadd.v2i32"
13887        )]
13888        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v2i32")]
13889        fn _vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
13890    }
13891    unsafe { _vhadd_u32(a, b) }
13892}
13893#[doc = "Halving add"]
13894#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u32)"]
13895#[inline]
13896#[target_feature(enable = "neon")]
13897#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13898#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))]
13899#[cfg_attr(
13900    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13901    assert_instr(uhadd)
13902)]
13903#[cfg_attr(
13904    not(target_arch = "arm"),
13905    stable(feature = "neon_intrinsics", since = "1.59.0")
13906)]
13907#[cfg_attr(
13908    target_arch = "arm",
13909    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13910)]
13911pub fn vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
13912    unsafe extern "unadjusted" {
13913        #[cfg_attr(
13914            any(target_arch = "aarch64", target_arch = "arm64ec"),
13915            link_name = "llvm.aarch64.neon.uhadd.v4i32"
13916        )]
13917        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i32")]
13918        fn _vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
13919    }
13920    unsafe { _vhaddq_u32(a, b) }
13921}
13922#[doc = "Signed halving subtract"]
13923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s16)"]
13924#[inline]
13925#[target_feature(enable = "neon")]
13926#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13927#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))]
13928#[cfg_attr(
13929    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13930    assert_instr(shsub)
13931)]
13932#[cfg_attr(
13933    not(target_arch = "arm"),
13934    stable(feature = "neon_intrinsics", since = "1.59.0")
13935)]
13936#[cfg_attr(
13937    target_arch = "arm",
13938    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13939)]
13940pub fn vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
13941    unsafe extern "unadjusted" {
13942        #[cfg_attr(
13943            any(target_arch = "aarch64", target_arch = "arm64ec"),
13944            link_name = "llvm.aarch64.neon.shsub.v4i16"
13945        )]
13946        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i16")]
13947        fn _vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
13948    }
13949    unsafe { _vhsub_s16(a, b) }
13950}
13951#[doc = "Signed halving subtract"]
13952#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s16)"]
13953#[inline]
13954#[target_feature(enable = "neon")]
13955#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13956#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))]
13957#[cfg_attr(
13958    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13959    assert_instr(shsub)
13960)]
13961#[cfg_attr(
13962    not(target_arch = "arm"),
13963    stable(feature = "neon_intrinsics", since = "1.59.0")
13964)]
13965#[cfg_attr(
13966    target_arch = "arm",
13967    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13968)]
13969pub fn vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
13970    unsafe extern "unadjusted" {
13971        #[cfg_attr(
13972            any(target_arch = "aarch64", target_arch = "arm64ec"),
13973            link_name = "llvm.aarch64.neon.shsub.v8i16"
13974        )]
13975        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i16")]
13976        fn _vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
13977    }
13978    unsafe { _vhsubq_s16(a, b) }
13979}
13980#[doc = "Signed halving subtract"]
13981#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s32)"]
13982#[inline]
13983#[target_feature(enable = "neon")]
13984#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13985#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))]
13986#[cfg_attr(
13987    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13988    assert_instr(shsub)
13989)]
13990#[cfg_attr(
13991    not(target_arch = "arm"),
13992    stable(feature = "neon_intrinsics", since = "1.59.0")
13993)]
13994#[cfg_attr(
13995    target_arch = "arm",
13996    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13997)]
13998pub fn vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
13999    unsafe extern "unadjusted" {
14000        #[cfg_attr(
14001            any(target_arch = "aarch64", target_arch = "arm64ec"),
14002            link_name = "llvm.aarch64.neon.shsub.v2i32"
14003        )]
14004        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v2i32")]
14005        fn _vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
14006    }
14007    unsafe { _vhsub_s32(a, b) }
14008}
14009#[doc = "Signed halving subtract"]
14010#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s32)"]
14011#[inline]
14012#[target_feature(enable = "neon")]
14013#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14014#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))]
14015#[cfg_attr(
14016    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14017    assert_instr(shsub)
14018)]
14019#[cfg_attr(
14020    not(target_arch = "arm"),
14021    stable(feature = "neon_intrinsics", since = "1.59.0")
14022)]
14023#[cfg_attr(
14024    target_arch = "arm",
14025    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14026)]
14027pub fn vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
14028    unsafe extern "unadjusted" {
14029        #[cfg_attr(
14030            any(target_arch = "aarch64", target_arch = "arm64ec"),
14031            link_name = "llvm.aarch64.neon.shsub.v4i32"
14032        )]
14033        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i32")]
14034        fn _vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
14035    }
14036    unsafe { _vhsubq_s32(a, b) }
14037}
14038#[doc = "Signed halving subtract"]
14039#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s8)"]
14040#[inline]
14041#[target_feature(enable = "neon")]
14042#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14043#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))]
14044#[cfg_attr(
14045    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14046    assert_instr(shsub)
14047)]
14048#[cfg_attr(
14049    not(target_arch = "arm"),
14050    stable(feature = "neon_intrinsics", since = "1.59.0")
14051)]
14052#[cfg_attr(
14053    target_arch = "arm",
14054    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14055)]
14056pub fn vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
14057    unsafe extern "unadjusted" {
14058        #[cfg_attr(
14059            any(target_arch = "aarch64", target_arch = "arm64ec"),
14060            link_name = "llvm.aarch64.neon.shsub.v8i8"
14061        )]
14062        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i8")]
14063        fn _vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
14064    }
14065    unsafe { _vhsub_s8(a, b) }
14066}
14067#[doc = "Signed halving subtract"]
14068#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s8)"]
14069#[inline]
14070#[target_feature(enable = "neon")]
14071#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14072#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))]
14073#[cfg_attr(
14074    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14075    assert_instr(shsub)
14076)]
14077#[cfg_attr(
14078    not(target_arch = "arm"),
14079    stable(feature = "neon_intrinsics", since = "1.59.0")
14080)]
14081#[cfg_attr(
14082    target_arch = "arm",
14083    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14084)]
14085pub fn vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
14086    unsafe extern "unadjusted" {
14087        #[cfg_attr(
14088            any(target_arch = "aarch64", target_arch = "arm64ec"),
14089            link_name = "llvm.aarch64.neon.shsub.v16i8"
14090        )]
14091        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v16i8")]
14092        fn _vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
14093    }
14094    unsafe { _vhsubq_s8(a, b) }
14095}
14096#[doc = "Signed halving subtract"]
14097#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u8)"]
14098#[inline]
14099#[target_feature(enable = "neon")]
14100#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14101#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))]
14102#[cfg_attr(
14103    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14104    assert_instr(uhsub)
14105)]
14106#[cfg_attr(
14107    not(target_arch = "arm"),
14108    stable(feature = "neon_intrinsics", since = "1.59.0")
14109)]
14110#[cfg_attr(
14111    target_arch = "arm",
14112    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14113)]
14114pub fn vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
14115    unsafe extern "unadjusted" {
14116        #[cfg_attr(
14117            any(target_arch = "aarch64", target_arch = "arm64ec"),
14118            link_name = "llvm.aarch64.neon.uhsub.v8i8"
14119        )]
14120        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i8")]
14121        fn _vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
14122    }
14123    unsafe { _vhsub_u8(a, b) }
14124}
14125#[doc = "Signed halving subtract"]
14126#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u8)"]
14127#[inline]
14128#[target_feature(enable = "neon")]
14129#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14130#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))]
14131#[cfg_attr(
14132    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14133    assert_instr(uhsub)
14134)]
14135#[cfg_attr(
14136    not(target_arch = "arm"),
14137    stable(feature = "neon_intrinsics", since = "1.59.0")
14138)]
14139#[cfg_attr(
14140    target_arch = "arm",
14141    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14142)]
14143pub fn vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
14144    unsafe extern "unadjusted" {
14145        #[cfg_attr(
14146            any(target_arch = "aarch64", target_arch = "arm64ec"),
14147            link_name = "llvm.aarch64.neon.uhsub.v16i8"
14148        )]
14149        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v16i8")]
14150        fn _vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
14151    }
14152    unsafe { _vhsubq_u8(a, b) }
14153}
14154#[doc = "Signed halving subtract"]
14155#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u16)"]
14156#[inline]
14157#[target_feature(enable = "neon")]
14158#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14159#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))]
14160#[cfg_attr(
14161    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14162    assert_instr(uhsub)
14163)]
14164#[cfg_attr(
14165    not(target_arch = "arm"),
14166    stable(feature = "neon_intrinsics", since = "1.59.0")
14167)]
14168#[cfg_attr(
14169    target_arch = "arm",
14170    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14171)]
14172pub fn vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
14173    unsafe extern "unadjusted" {
14174        #[cfg_attr(
14175            any(target_arch = "aarch64", target_arch = "arm64ec"),
14176            link_name = "llvm.aarch64.neon.uhsub.v4i16"
14177        )]
14178        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i16")]
14179        fn _vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
14180    }
14181    unsafe { _vhsub_u16(a, b) }
14182}
14183#[doc = "Signed halving subtract"]
14184#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u16)"]
14185#[inline]
14186#[target_feature(enable = "neon")]
14187#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14188#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))]
14189#[cfg_attr(
14190    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14191    assert_instr(uhsub)
14192)]
14193#[cfg_attr(
14194    not(target_arch = "arm"),
14195    stable(feature = "neon_intrinsics", since = "1.59.0")
14196)]
14197#[cfg_attr(
14198    target_arch = "arm",
14199    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14200)]
14201pub fn vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
14202    unsafe extern "unadjusted" {
14203        #[cfg_attr(
14204            any(target_arch = "aarch64", target_arch = "arm64ec"),
14205            link_name = "llvm.aarch64.neon.uhsub.v8i16"
14206        )]
14207        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i16")]
14208        fn _vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
14209    }
14210    unsafe { _vhsubq_u16(a, b) }
14211}
14212#[doc = "Signed halving subtract"]
14213#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u32)"]
14214#[inline]
14215#[target_feature(enable = "neon")]
14216#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14217#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))]
14218#[cfg_attr(
14219    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14220    assert_instr(uhsub)
14221)]
14222#[cfg_attr(
14223    not(target_arch = "arm"),
14224    stable(feature = "neon_intrinsics", since = "1.59.0")
14225)]
14226#[cfg_attr(
14227    target_arch = "arm",
14228    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14229)]
14230pub fn vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
14231    unsafe extern "unadjusted" {
14232        #[cfg_attr(
14233            any(target_arch = "aarch64", target_arch = "arm64ec"),
14234            link_name = "llvm.aarch64.neon.uhsub.v2i32"
14235        )]
14236        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v2i32")]
14237        fn _vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
14238    }
14239    unsafe { _vhsub_u32(a, b) }
14240}
14241#[doc = "Signed halving subtract"]
14242#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u32)"]
14243#[inline]
14244#[target_feature(enable = "neon")]
14245#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14246#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))]
14247#[cfg_attr(
14248    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14249    assert_instr(uhsub)
14250)]
14251#[cfg_attr(
14252    not(target_arch = "arm"),
14253    stable(feature = "neon_intrinsics", since = "1.59.0")
14254)]
14255#[cfg_attr(
14256    target_arch = "arm",
14257    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14258)]
14259pub fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
14260    unsafe extern "unadjusted" {
14261        #[cfg_attr(
14262            any(target_arch = "aarch64", target_arch = "arm64ec"),
14263            link_name = "llvm.aarch64.neon.uhsub.v4i32"
14264        )]
14265        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i32")]
14266        fn _vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
14267    }
14268    unsafe { _vhsubq_u32(a, b) }
14269}
14270#[doc = "Load one single-element structure and replicate to all lanes of one register"]
14271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f16)"]
14272#[doc = "## Safety"]
14273#[doc = "  * Neon instrinsic unsafe"]
14274#[inline]
14275#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14276#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14277#[cfg_attr(
14278    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14279    assert_instr(ld1r)
14280)]
14281#[target_feature(enable = "neon,fp16")]
14282#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14283pub unsafe fn vld1_dup_f16(ptr: *const f16) -> float16x4_t {
14284    let x: float16x4_t = vld1_lane_f16::<0>(ptr, transmute(f16x4::splat(0.0)));
14285    simd_shuffle!(x, x, [0, 0, 0, 0])
14286}
14287#[doc = "Load one single-element structure and replicate to all lanes of one register"]
14288#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f16)"]
14289#[doc = "## Safety"]
14290#[doc = "  * Neon instrinsic unsafe"]
14291#[inline]
14292#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14293#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14294#[cfg_attr(
14295    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14296    assert_instr(ld1r)
14297)]
14298#[target_feature(enable = "neon,fp16")]
14299#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14300pub unsafe fn vld1q_dup_f16(ptr: *const f16) -> float16x8_t {
14301    let x: float16x8_t = vld1q_lane_f16::<0>(ptr, transmute(f16x8::splat(0.0)));
14302    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
14303}
14304#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14305#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f32)"]
14306#[doc = "## Safety"]
14307#[doc = "  * Neon instrinsic unsafe"]
14308#[inline]
14309#[target_feature(enable = "neon")]
14310#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14311#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14312#[cfg_attr(
14313    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14314    assert_instr(ld1r)
14315)]
14316#[cfg_attr(
14317    not(target_arch = "arm"),
14318    stable(feature = "neon_intrinsics", since = "1.59.0")
14319)]
14320#[cfg_attr(
14321    target_arch = "arm",
14322    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14323)]
14324pub unsafe fn vld1_dup_f32(ptr: *const f32) -> float32x2_t {
14325    let x = vld1_lane_f32::<0>(ptr, transmute(f32x2::splat(0.0)));
14326    simd_shuffle!(x, x, [0, 0])
14327}
14328#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p16)"]
14330#[doc = "## Safety"]
14331#[doc = "  * Neon instrinsic unsafe"]
14332#[inline]
14333#[target_feature(enable = "neon")]
14334#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14335#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14336#[cfg_attr(
14337    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14338    assert_instr(ld1r)
14339)]
14340#[cfg_attr(
14341    not(target_arch = "arm"),
14342    stable(feature = "neon_intrinsics", since = "1.59.0")
14343)]
14344#[cfg_attr(
14345    target_arch = "arm",
14346    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14347)]
14348pub unsafe fn vld1_dup_p16(ptr: *const p16) -> poly16x4_t {
14349    let x = vld1_lane_p16::<0>(ptr, transmute(u16x4::splat(0)));
14350    simd_shuffle!(x, x, [0, 0, 0, 0])
14351}
14352#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14353#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p8)"]
14354#[doc = "## Safety"]
14355#[doc = "  * Neon instrinsic unsafe"]
14356#[inline]
14357#[target_feature(enable = "neon")]
14358#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14359#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14360#[cfg_attr(
14361    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14362    assert_instr(ld1r)
14363)]
14364#[cfg_attr(
14365    not(target_arch = "arm"),
14366    stable(feature = "neon_intrinsics", since = "1.59.0")
14367)]
14368#[cfg_attr(
14369    target_arch = "arm",
14370    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14371)]
14372pub unsafe fn vld1_dup_p8(ptr: *const p8) -> poly8x8_t {
14373    let x = vld1_lane_p8::<0>(ptr, transmute(u8x8::splat(0)));
14374    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
14375}
14376#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14377#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s16)"]
14378#[doc = "## Safety"]
14379#[doc = "  * Neon instrinsic unsafe"]
14380#[inline]
14381#[target_feature(enable = "neon")]
14382#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14383#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14384#[cfg_attr(
14385    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14386    assert_instr(ld1r)
14387)]
14388#[cfg_attr(
14389    not(target_arch = "arm"),
14390    stable(feature = "neon_intrinsics", since = "1.59.0")
14391)]
14392#[cfg_attr(
14393    target_arch = "arm",
14394    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14395)]
14396pub unsafe fn vld1_dup_s16(ptr: *const i16) -> int16x4_t {
14397    let x = vld1_lane_s16::<0>(ptr, transmute(i16x4::splat(0)));
14398    simd_shuffle!(x, x, [0, 0, 0, 0])
14399}
14400#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14401#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s32)"]
14402#[doc = "## Safety"]
14403#[doc = "  * Neon instrinsic unsafe"]
14404#[inline]
14405#[target_feature(enable = "neon")]
14406#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14407#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14408#[cfg_attr(
14409    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14410    assert_instr(ld1r)
14411)]
14412#[cfg_attr(
14413    not(target_arch = "arm"),
14414    stable(feature = "neon_intrinsics", since = "1.59.0")
14415)]
14416#[cfg_attr(
14417    target_arch = "arm",
14418    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14419)]
14420pub unsafe fn vld1_dup_s32(ptr: *const i32) -> int32x2_t {
14421    let x = vld1_lane_s32::<0>(ptr, transmute(i32x2::splat(0)));
14422    simd_shuffle!(x, x, [0, 0])
14423}
14424#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14425#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s8)"]
14426#[doc = "## Safety"]
14427#[doc = "  * Neon instrinsic unsafe"]
14428#[inline]
14429#[target_feature(enable = "neon")]
14430#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14431#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14432#[cfg_attr(
14433    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14434    assert_instr(ld1r)
14435)]
14436#[cfg_attr(
14437    not(target_arch = "arm"),
14438    stable(feature = "neon_intrinsics", since = "1.59.0")
14439)]
14440#[cfg_attr(
14441    target_arch = "arm",
14442    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14443)]
14444pub unsafe fn vld1_dup_s8(ptr: *const i8) -> int8x8_t {
14445    let x = vld1_lane_s8::<0>(ptr, transmute(i8x8::splat(0)));
14446    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
14447}
14448#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14449#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u16)"]
14450#[doc = "## Safety"]
14451#[doc = "  * Neon instrinsic unsafe"]
14452#[inline]
14453#[target_feature(enable = "neon")]
14454#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14455#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14456#[cfg_attr(
14457    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14458    assert_instr(ld1r)
14459)]
14460#[cfg_attr(
14461    not(target_arch = "arm"),
14462    stable(feature = "neon_intrinsics", since = "1.59.0")
14463)]
14464#[cfg_attr(
14465    target_arch = "arm",
14466    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14467)]
14468pub unsafe fn vld1_dup_u16(ptr: *const u16) -> uint16x4_t {
14469    let x = vld1_lane_u16::<0>(ptr, transmute(u16x4::splat(0)));
14470    simd_shuffle!(x, x, [0, 0, 0, 0])
14471}
14472#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u32)"]
14474#[doc = "## Safety"]
14475#[doc = "  * Neon instrinsic unsafe"]
14476#[inline]
14477#[target_feature(enable = "neon")]
14478#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14479#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14480#[cfg_attr(
14481    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14482    assert_instr(ld1r)
14483)]
14484#[cfg_attr(
14485    not(target_arch = "arm"),
14486    stable(feature = "neon_intrinsics", since = "1.59.0")
14487)]
14488#[cfg_attr(
14489    target_arch = "arm",
14490    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14491)]
14492pub unsafe fn vld1_dup_u32(ptr: *const u32) -> uint32x2_t {
14493    let x = vld1_lane_u32::<0>(ptr, transmute(u32x2::splat(0)));
14494    simd_shuffle!(x, x, [0, 0])
14495}
14496#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u8)"]
14498#[doc = "## Safety"]
14499#[doc = "  * Neon instrinsic unsafe"]
14500#[inline]
14501#[target_feature(enable = "neon")]
14502#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14503#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14504#[cfg_attr(
14505    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14506    assert_instr(ld1r)
14507)]
14508#[cfg_attr(
14509    not(target_arch = "arm"),
14510    stable(feature = "neon_intrinsics", since = "1.59.0")
14511)]
14512#[cfg_attr(
14513    target_arch = "arm",
14514    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14515)]
14516pub unsafe fn vld1_dup_u8(ptr: *const u8) -> uint8x8_t {
14517    let x = vld1_lane_u8::<0>(ptr, transmute(u8x8::splat(0)));
14518    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
14519}
14520#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14521#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f32)"]
14522#[doc = "## Safety"]
14523#[doc = "  * Neon instrinsic unsafe"]
14524#[inline]
14525#[target_feature(enable = "neon")]
14526#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14527#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14528#[cfg_attr(
14529    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14530    assert_instr(ld1r)
14531)]
14532#[cfg_attr(
14533    not(target_arch = "arm"),
14534    stable(feature = "neon_intrinsics", since = "1.59.0")
14535)]
14536#[cfg_attr(
14537    target_arch = "arm",
14538    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14539)]
14540pub unsafe fn vld1q_dup_f32(ptr: *const f32) -> float32x4_t {
14541    let x = vld1q_lane_f32::<0>(ptr, transmute(f32x4::splat(0.0)));
14542    simd_shuffle!(x, x, [0, 0, 0, 0])
14543}
14544#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14545#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p16)"]
14546#[doc = "## Safety"]
14547#[doc = "  * Neon instrinsic unsafe"]
14548#[inline]
14549#[target_feature(enable = "neon")]
14550#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14551#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14552#[cfg_attr(
14553    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14554    assert_instr(ld1r)
14555)]
14556#[cfg_attr(
14557    not(target_arch = "arm"),
14558    stable(feature = "neon_intrinsics", since = "1.59.0")
14559)]
14560#[cfg_attr(
14561    target_arch = "arm",
14562    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14563)]
14564pub unsafe fn vld1q_dup_p16(ptr: *const p16) -> poly16x8_t {
14565    let x = vld1q_lane_p16::<0>(ptr, transmute(u16x8::splat(0)));
14566    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
14567}
14568#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14569#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p8)"]
14570#[doc = "## Safety"]
14571#[doc = "  * Neon instrinsic unsafe"]
14572#[inline]
14573#[target_feature(enable = "neon")]
14574#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14575#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14576#[cfg_attr(
14577    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14578    assert_instr(ld1r)
14579)]
14580#[cfg_attr(
14581    not(target_arch = "arm"),
14582    stable(feature = "neon_intrinsics", since = "1.59.0")
14583)]
14584#[cfg_attr(
14585    target_arch = "arm",
14586    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14587)]
14588pub unsafe fn vld1q_dup_p8(ptr: *const p8) -> poly8x16_t {
14589    let x = vld1q_lane_p8::<0>(ptr, transmute(u8x16::splat(0)));
14590    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0])
14591}
14592#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s16)"]
14594#[doc = "## Safety"]
14595#[doc = "  * Neon instrinsic unsafe"]
14596#[inline]
14597#[target_feature(enable = "neon")]
14598#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14599#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14600#[cfg_attr(
14601    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14602    assert_instr(ld1r)
14603)]
14604#[cfg_attr(
14605    not(target_arch = "arm"),
14606    stable(feature = "neon_intrinsics", since = "1.59.0")
14607)]
14608#[cfg_attr(
14609    target_arch = "arm",
14610    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14611)]
14612pub unsafe fn vld1q_dup_s16(ptr: *const i16) -> int16x8_t {
14613    let x = vld1q_lane_s16::<0>(ptr, transmute(i16x8::splat(0)));
14614    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
14615}
14616#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14617#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s32)"]
14618#[doc = "## Safety"]
14619#[doc = "  * Neon instrinsic unsafe"]
14620#[inline]
14621#[target_feature(enable = "neon")]
14622#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14623#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14624#[cfg_attr(
14625    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14626    assert_instr(ld1r)
14627)]
14628#[cfg_attr(
14629    not(target_arch = "arm"),
14630    stable(feature = "neon_intrinsics", since = "1.59.0")
14631)]
14632#[cfg_attr(
14633    target_arch = "arm",
14634    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14635)]
14636pub unsafe fn vld1q_dup_s32(ptr: *const i32) -> int32x4_t {
14637    let x = vld1q_lane_s32::<0>(ptr, transmute(i32x4::splat(0)));
14638    simd_shuffle!(x, x, [0, 0, 0, 0])
14639}
14640#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14641#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s64)"]
14642#[doc = "## Safety"]
14643#[doc = "  * Neon instrinsic unsafe"]
14644#[inline]
14645#[target_feature(enable = "neon")]
14646#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14647#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))]
14648#[cfg_attr(
14649    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14650    assert_instr(ld1)
14651)]
14652#[cfg_attr(
14653    not(target_arch = "arm"),
14654    stable(feature = "neon_intrinsics", since = "1.59.0")
14655)]
14656#[cfg_attr(
14657    target_arch = "arm",
14658    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14659)]
14660pub unsafe fn vld1q_dup_s64(ptr: *const i64) -> int64x2_t {
14661    let x = vld1q_lane_s64::<0>(ptr, transmute(i64x2::splat(0)));
14662    simd_shuffle!(x, x, [0, 0])
14663}
14664#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s8)"]
14666#[doc = "## Safety"]
14667#[doc = "  * Neon instrinsic unsafe"]
14668#[inline]
14669#[target_feature(enable = "neon")]
14670#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14671#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14672#[cfg_attr(
14673    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14674    assert_instr(ld1r)
14675)]
14676#[cfg_attr(
14677    not(target_arch = "arm"),
14678    stable(feature = "neon_intrinsics", since = "1.59.0")
14679)]
14680#[cfg_attr(
14681    target_arch = "arm",
14682    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14683)]
14684pub unsafe fn vld1q_dup_s8(ptr: *const i8) -> int8x16_t {
14685    let x = vld1q_lane_s8::<0>(ptr, transmute(i8x16::splat(0)));
14686    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0])
14687}
14688#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14689#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u16)"]
14690#[doc = "## Safety"]
14691#[doc = "  * Neon instrinsic unsafe"]
14692#[inline]
14693#[target_feature(enable = "neon")]
14694#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14695#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14696#[cfg_attr(
14697    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14698    assert_instr(ld1r)
14699)]
14700#[cfg_attr(
14701    not(target_arch = "arm"),
14702    stable(feature = "neon_intrinsics", since = "1.59.0")
14703)]
14704#[cfg_attr(
14705    target_arch = "arm",
14706    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14707)]
14708pub unsafe fn vld1q_dup_u16(ptr: *const u16) -> uint16x8_t {
14709    let x = vld1q_lane_u16::<0>(ptr, transmute(u16x8::splat(0)));
14710    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
14711}
14712#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u32)"]
14714#[doc = "## Safety"]
14715#[doc = "  * Neon instrinsic unsafe"]
14716#[inline]
14717#[target_feature(enable = "neon")]
14718#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14719#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14720#[cfg_attr(
14721    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14722    assert_instr(ld1r)
14723)]
14724#[cfg_attr(
14725    not(target_arch = "arm"),
14726    stable(feature = "neon_intrinsics", since = "1.59.0")
14727)]
14728#[cfg_attr(
14729    target_arch = "arm",
14730    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14731)]
14732pub unsafe fn vld1q_dup_u32(ptr: *const u32) -> uint32x4_t {
14733    let x = vld1q_lane_u32::<0>(ptr, transmute(u32x4::splat(0)));
14734    simd_shuffle!(x, x, [0, 0, 0, 0])
14735}
14736#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14737#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u64)"]
14738#[doc = "## Safety"]
14739#[doc = "  * Neon instrinsic unsafe"]
14740#[inline]
14741#[target_feature(enable = "neon")]
14742#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14743#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))]
14744#[cfg_attr(
14745    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14746    assert_instr(ld1)
14747)]
14748#[cfg_attr(
14749    not(target_arch = "arm"),
14750    stable(feature = "neon_intrinsics", since = "1.59.0")
14751)]
14752#[cfg_attr(
14753    target_arch = "arm",
14754    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14755)]
14756pub unsafe fn vld1q_dup_u64(ptr: *const u64) -> uint64x2_t {
14757    let x = vld1q_lane_u64::<0>(ptr, transmute(u64x2::splat(0)));
14758    simd_shuffle!(x, x, [0, 0])
14759}
14760#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14761#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u8)"]
14762#[doc = "## Safety"]
14763#[doc = "  * Neon instrinsic unsafe"]
14764#[inline]
14765#[target_feature(enable = "neon")]
14766#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14767#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14768#[cfg_attr(
14769    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14770    assert_instr(ld1r)
14771)]
14772#[cfg_attr(
14773    not(target_arch = "arm"),
14774    stable(feature = "neon_intrinsics", since = "1.59.0")
14775)]
14776#[cfg_attr(
14777    target_arch = "arm",
14778    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14779)]
14780pub unsafe fn vld1q_dup_u8(ptr: *const u8) -> uint8x16_t {
14781    let x = vld1q_lane_u8::<0>(ptr, transmute(u8x16::splat(0)));
14782    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0])
14783}
14784#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14785#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p64)"]
14786#[doc = "## Safety"]
14787#[doc = "  * Neon instrinsic unsafe"]
14788#[inline]
14789#[target_feature(enable = "neon,aes")]
14790#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14791#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
14792#[cfg_attr(
14793    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14794    assert_instr(ldr)
14795)]
14796#[cfg_attr(
14797    not(target_arch = "arm"),
14798    stable(feature = "neon_intrinsics", since = "1.59.0")
14799)]
14800#[cfg_attr(
14801    target_arch = "arm",
14802    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14803)]
14804pub unsafe fn vld1_dup_p64(ptr: *const p64) -> poly64x1_t {
14805    let x: poly64x1_t;
14806    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
14807    {
14808        x = crate::core_arch::aarch64::vld1_p64(ptr);
14809    }
14810    #[cfg(target_arch = "arm")]
14811    {
14812        x = crate::core_arch::arm::vld1_p64(ptr);
14813    };
14814    x
14815}
14816#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14817#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s64)"]
14818#[doc = "## Safety"]
14819#[doc = "  * Neon instrinsic unsafe"]
14820#[inline]
14821#[target_feature(enable = "neon")]
14822#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14823#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
14824#[cfg_attr(
14825    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14826    assert_instr(ldr)
14827)]
14828#[cfg_attr(
14829    not(target_arch = "arm"),
14830    stable(feature = "neon_intrinsics", since = "1.59.0")
14831)]
14832#[cfg_attr(
14833    target_arch = "arm",
14834    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14835)]
14836pub unsafe fn vld1_dup_s64(ptr: *const i64) -> int64x1_t {
14837    let x: int64x1_t;
14838    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
14839    {
14840        x = crate::core_arch::aarch64::vld1_s64(ptr);
14841    }
14842    #[cfg(target_arch = "arm")]
14843    {
14844        x = crate::core_arch::arm::vld1_s64(ptr);
14845    };
14846    x
14847}
14848#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14849#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u64)"]
14850#[doc = "## Safety"]
14851#[doc = "  * Neon instrinsic unsafe"]
14852#[inline]
14853#[target_feature(enable = "neon")]
14854#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14855#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
14856#[cfg_attr(
14857    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14858    assert_instr(ldr)
14859)]
14860#[cfg_attr(
14861    not(target_arch = "arm"),
14862    stable(feature = "neon_intrinsics", since = "1.59.0")
14863)]
14864#[cfg_attr(
14865    target_arch = "arm",
14866    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14867)]
14868pub unsafe fn vld1_dup_u64(ptr: *const u64) -> uint64x1_t {
14869    let x: uint64x1_t;
14870    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
14871    {
14872        x = crate::core_arch::aarch64::vld1_u64(ptr);
14873    }
14874    #[cfg(target_arch = "arm")]
14875    {
14876        x = crate::core_arch::arm::vld1_u64(ptr);
14877    };
14878    x
14879}
14880#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
14881#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
14882#[doc = "## Safety"]
14883#[doc = "  * Neon instrinsic unsafe"]
14884#[inline]
14885#[cfg(target_endian = "little")]
14886#[cfg(target_arch = "arm")]
14887#[target_feature(enable = "neon,v7")]
14888#[target_feature(enable = "neon,fp16")]
14889#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14890#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14891pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
14892    transmute(vld1_v4f16(
14893        ptr as *const i8,
14894        crate::mem::align_of::<f16>() as i32,
14895    ))
14896}
14897#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
14898#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
14899#[doc = "## Safety"]
14900#[doc = "  * Neon instrinsic unsafe"]
14901#[inline]
14902#[cfg(target_endian = "big")]
14903#[cfg(target_arch = "arm")]
14904#[target_feature(enable = "neon,v7")]
14905#[target_feature(enable = "neon,fp16")]
14906#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14907#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14908pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
14909    let ret_val: float16x4_t = transmute(vld1_v4f16(
14910        ptr as *const i8,
14911        crate::mem::align_of::<f16>() as i32,
14912    ));
14913    simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
14914}
14915#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
14916#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
14917#[doc = "## Safety"]
14918#[doc = "  * Neon instrinsic unsafe"]
14919#[inline]
14920#[cfg(target_endian = "little")]
14921#[cfg(target_arch = "arm")]
14922#[target_feature(enable = "neon,v7")]
14923#[target_feature(enable = "neon,fp16")]
14924#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14925#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14926pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
14927    transmute(vld1q_v8f16(
14928        ptr as *const i8,
14929        crate::mem::align_of::<f16>() as i32,
14930    ))
14931}
14932#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
14933#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
14934#[doc = "## Safety"]
14935#[doc = "  * Neon instrinsic unsafe"]
14936#[inline]
14937#[cfg(target_endian = "big")]
14938#[cfg(target_arch = "arm")]
14939#[target_feature(enable = "neon,v7")]
14940#[target_feature(enable = "neon,fp16")]
14941#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14942#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14943pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
14944    let ret_val: float16x8_t = transmute(vld1q_v8f16(
14945        ptr as *const i8,
14946        crate::mem::align_of::<f16>() as i32,
14947    ));
14948    simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
14949}
14950#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x2)"]
14952#[doc = "## Safety"]
14953#[doc = "  * Neon instrinsic unsafe"]
14954#[inline]
14955#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14956#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14957#[cfg_attr(
14958    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14959    assert_instr(ld1)
14960)]
14961#[target_feature(enable = "neon,fp16")]
14962#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14963pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t {
14964    unsafe extern "unadjusted" {
14965        #[cfg_attr(
14966            any(target_arch = "aarch64", target_arch = "arm64ec"),
14967            link_name = "llvm.aarch64.neon.ld1x2.v4f16.p0"
14968        )]
14969        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4f16.p0")]
14970        fn _vld1_f16_x2(a: *const f16) -> float16x4x2_t;
14971    }
14972    _vld1_f16_x2(a)
14973}
14974#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14975#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x3)"]
14976#[doc = "## Safety"]
14977#[doc = "  * Neon instrinsic unsafe"]
14978#[inline]
14979#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14980#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14981#[cfg_attr(
14982    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14983    assert_instr(ld1)
14984)]
14985#[target_feature(enable = "neon,fp16")]
14986#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14987pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t {
14988    unsafe extern "unadjusted" {
14989        #[cfg_attr(
14990            any(target_arch = "aarch64", target_arch = "arm64ec"),
14991            link_name = "llvm.aarch64.neon.ld1x3.v4f16.p0"
14992        )]
14993        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4f16.p0")]
14994        fn _vld1_f16_x3(a: *const f16) -> float16x4x3_t;
14995    }
14996    _vld1_f16_x3(a)
14997}
14998#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x4)"]
15000#[doc = "## Safety"]
15001#[doc = "  * Neon instrinsic unsafe"]
15002#[inline]
15003#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15004#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15005#[cfg_attr(
15006    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15007    assert_instr(ld1)
15008)]
15009#[target_feature(enable = "neon,fp16")]
15010#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15011pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t {
15012    unsafe extern "unadjusted" {
15013        #[cfg_attr(
15014            any(target_arch = "aarch64", target_arch = "arm64ec"),
15015            link_name = "llvm.aarch64.neon.ld1x4.v4f16.p0"
15016        )]
15017        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4f16.p0")]
15018        fn _vld1_f16_x4(a: *const f16) -> float16x4x4_t;
15019    }
15020    _vld1_f16_x4(a)
15021}
15022#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15023#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x2)"]
15024#[doc = "## Safety"]
15025#[doc = "  * Neon instrinsic unsafe"]
15026#[inline]
15027#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15028#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15029#[cfg_attr(
15030    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15031    assert_instr(ld1)
15032)]
15033#[target_feature(enable = "neon,fp16")]
15034#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15035pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t {
15036    unsafe extern "unadjusted" {
15037        #[cfg_attr(
15038            any(target_arch = "aarch64", target_arch = "arm64ec"),
15039            link_name = "llvm.aarch64.neon.ld1x2.v8f16.p0"
15040        )]
15041        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8f16.p0")]
15042        fn _vld1q_f16_x2(a: *const f16) -> float16x8x2_t;
15043    }
15044    _vld1q_f16_x2(a)
15045}
15046#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15047#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x3)"]
15048#[doc = "## Safety"]
15049#[doc = "  * Neon instrinsic unsafe"]
15050#[inline]
15051#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15052#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15053#[cfg_attr(
15054    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15055    assert_instr(ld1)
15056)]
15057#[target_feature(enable = "neon,fp16")]
15058#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15059pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t {
15060    unsafe extern "unadjusted" {
15061        #[cfg_attr(
15062            any(target_arch = "aarch64", target_arch = "arm64ec"),
15063            link_name = "llvm.aarch64.neon.ld1x3.v8f16.p0"
15064        )]
15065        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8f16.p0")]
15066        fn _vld1q_f16_x3(a: *const f16) -> float16x8x3_t;
15067    }
15068    _vld1q_f16_x3(a)
15069}
15070#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x4)"]
15072#[doc = "## Safety"]
15073#[doc = "  * Neon instrinsic unsafe"]
15074#[inline]
15075#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15076#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15077#[cfg_attr(
15078    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15079    assert_instr(ld1)
15080)]
15081#[target_feature(enable = "neon,fp16")]
15082#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15083pub unsafe fn vld1q_f16_x4(a: *const f16) -> float16x8x4_t {
15084    unsafe extern "unadjusted" {
15085        #[cfg_attr(
15086            any(target_arch = "aarch64", target_arch = "arm64ec"),
15087            link_name = "llvm.aarch64.neon.ld1x4.v8f16.p0"
15088        )]
15089        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8f16.p0")]
15090        fn _vld1q_f16_x4(a: *const f16) -> float16x8x4_t;
15091    }
15092    _vld1q_f16_x4(a)
15093}
15094#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15095#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"]
15096#[doc = "## Safety"]
15097#[doc = "  * Neon instrinsic unsafe"]
15098#[inline]
15099#[cfg(target_endian = "little")]
15100#[cfg(target_arch = "arm")]
15101#[target_feature(enable = "neon,v7")]
15102#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15103#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
15104pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t {
15105    transmute(vld1_v2f32(
15106        ptr as *const i8,
15107        crate::mem::align_of::<f32>() as i32,
15108    ))
15109}
15110#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15111#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"]
15112#[doc = "## Safety"]
15113#[doc = "  * Neon instrinsic unsafe"]
15114#[inline]
15115#[cfg(target_endian = "big")]
15116#[cfg(target_arch = "arm")]
15117#[target_feature(enable = "neon,v7")]
15118#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15119#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
15120pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t {
15121    let ret_val: float32x2_t = transmute(vld1_v2f32(
15122        ptr as *const i8,
15123        crate::mem::align_of::<f32>() as i32,
15124    ));
15125    simd_shuffle!(ret_val, ret_val, [1, 0])
15126}
15127#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15128#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"]
15129#[doc = "## Safety"]
15130#[doc = "  * Neon instrinsic unsafe"]
15131#[inline]
15132#[cfg(target_endian = "little")]
15133#[cfg(target_arch = "arm")]
15134#[target_feature(enable = "neon,v7")]
15135#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15136#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
15137pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t {
15138    transmute(vld1q_v4f32(
15139        ptr as *const i8,
15140        crate::mem::align_of::<f32>() as i32,
15141    ))
15142}
15143#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15144#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"]
15145#[doc = "## Safety"]
15146#[doc = "  * Neon instrinsic unsafe"]
15147#[inline]
15148#[cfg(target_endian = "big")]
15149#[cfg(target_arch = "arm")]
15150#[target_feature(enable = "neon,v7")]
15151#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15152#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
15153pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t {
15154    let ret_val: float32x4_t = transmute(vld1q_v4f32(
15155        ptr as *const i8,
15156        crate::mem::align_of::<f32>() as i32,
15157    ));
15158    simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15159}
15160#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15161#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"]
15162#[doc = "## Safety"]
15163#[doc = "  * Neon instrinsic unsafe"]
15164#[inline]
15165#[cfg(target_endian = "little")]
15166#[cfg(target_arch = "arm")]
15167#[target_feature(enable = "neon,v7")]
15168#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15169#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15170pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t {
15171    transmute(vld1_v8i8(
15172        ptr as *const i8,
15173        crate::mem::align_of::<u8>() as i32,
15174    ))
15175}
15176#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15177#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"]
15178#[doc = "## Safety"]
15179#[doc = "  * Neon instrinsic unsafe"]
15180#[inline]
15181#[cfg(target_endian = "big")]
15182#[cfg(target_arch = "arm")]
15183#[target_feature(enable = "neon,v7")]
15184#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15185#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15186pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t {
15187    let ret_val: uint8x8_t = transmute(vld1_v8i8(
15188        ptr as *const i8,
15189        crate::mem::align_of::<u8>() as i32,
15190    ));
15191    simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15192}
15193#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15194#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"]
15195#[doc = "## Safety"]
15196#[doc = "  * Neon instrinsic unsafe"]
15197#[inline]
15198#[cfg(target_endian = "little")]
15199#[cfg(target_arch = "arm")]
15200#[target_feature(enable = "neon,v7")]
15201#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15202#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15203pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t {
15204    transmute(vld1q_v16i8(
15205        ptr as *const i8,
15206        crate::mem::align_of::<u8>() as i32,
15207    ))
15208}
15209#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15210#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"]
15211#[doc = "## Safety"]
15212#[doc = "  * Neon instrinsic unsafe"]
15213#[inline]
15214#[cfg(target_endian = "big")]
15215#[cfg(target_arch = "arm")]
15216#[target_feature(enable = "neon,v7")]
15217#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15218#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15219pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t {
15220    let ret_val: uint8x16_t = transmute(vld1q_v16i8(
15221        ptr as *const i8,
15222        crate::mem::align_of::<u8>() as i32,
15223    ));
15224    simd_shuffle!(
15225        ret_val,
15226        ret_val,
15227        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
15228    )
15229}
15230#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15231#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"]
15232#[doc = "## Safety"]
15233#[doc = "  * Neon instrinsic unsafe"]
15234#[inline]
15235#[cfg(target_endian = "little")]
15236#[cfg(target_arch = "arm")]
15237#[target_feature(enable = "neon,v7")]
15238#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15239#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15240pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t {
15241    transmute(vld1_v4i16(
15242        ptr as *const i8,
15243        crate::mem::align_of::<u16>() as i32,
15244    ))
15245}
15246#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15247#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"]
15248#[doc = "## Safety"]
15249#[doc = "  * Neon instrinsic unsafe"]
15250#[inline]
15251#[cfg(target_endian = "big")]
15252#[cfg(target_arch = "arm")]
15253#[target_feature(enable = "neon,v7")]
15254#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15255#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15256pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t {
15257    let ret_val: uint16x4_t = transmute(vld1_v4i16(
15258        ptr as *const i8,
15259        crate::mem::align_of::<u16>() as i32,
15260    ));
15261    simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15262}
15263#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15264#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"]
15265#[doc = "## Safety"]
15266#[doc = "  * Neon instrinsic unsafe"]
15267#[inline]
15268#[cfg(target_endian = "little")]
15269#[cfg(target_arch = "arm")]
15270#[target_feature(enable = "neon,v7")]
15271#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15272#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15273pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t {
15274    transmute(vld1q_v8i16(
15275        ptr as *const i8,
15276        crate::mem::align_of::<u16>() as i32,
15277    ))
15278}
15279#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15280#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"]
15281#[doc = "## Safety"]
15282#[doc = "  * Neon instrinsic unsafe"]
15283#[inline]
15284#[cfg(target_endian = "big")]
15285#[cfg(target_arch = "arm")]
15286#[target_feature(enable = "neon,v7")]
15287#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15288#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15289pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t {
15290    let ret_val: uint16x8_t = transmute(vld1q_v8i16(
15291        ptr as *const i8,
15292        crate::mem::align_of::<u16>() as i32,
15293    ));
15294    simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15295}
15296#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15297#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"]
15298#[doc = "## Safety"]
15299#[doc = "  * Neon instrinsic unsafe"]
15300#[inline]
15301#[cfg(target_endian = "little")]
15302#[cfg(target_arch = "arm")]
15303#[target_feature(enable = "neon,v7")]
15304#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15305#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
15306pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t {
15307    transmute(vld1_v2i32(
15308        ptr as *const i8,
15309        crate::mem::align_of::<u32>() as i32,
15310    ))
15311}
15312#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"]
15314#[doc = "## Safety"]
15315#[doc = "  * Neon instrinsic unsafe"]
15316#[inline]
15317#[cfg(target_endian = "big")]
15318#[cfg(target_arch = "arm")]
15319#[target_feature(enable = "neon,v7")]
15320#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15321#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
15322pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t {
15323    let ret_val: uint32x2_t = transmute(vld1_v2i32(
15324        ptr as *const i8,
15325        crate::mem::align_of::<u32>() as i32,
15326    ));
15327    simd_shuffle!(ret_val, ret_val, [1, 0])
15328}
15329#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15330#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"]
15331#[doc = "## Safety"]
15332#[doc = "  * Neon instrinsic unsafe"]
15333#[inline]
15334#[cfg(target_endian = "little")]
15335#[cfg(target_arch = "arm")]
15336#[target_feature(enable = "neon,v7")]
15337#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15338#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
15339pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
15340    transmute(vld1q_v4i32(
15341        ptr as *const i8,
15342        crate::mem::align_of::<u32>() as i32,
15343    ))
15344}
15345#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15346#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"]
15347#[doc = "## Safety"]
15348#[doc = "  * Neon instrinsic unsafe"]
15349#[inline]
15350#[cfg(target_endian = "big")]
15351#[cfg(target_arch = "arm")]
15352#[target_feature(enable = "neon,v7")]
15353#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15354#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
15355pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
15356    let ret_val: uint32x4_t = transmute(vld1q_v4i32(
15357        ptr as *const i8,
15358        crate::mem::align_of::<u32>() as i32,
15359    ));
15360    simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15361}
15362#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15363#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"]
15364#[doc = "## Safety"]
15365#[doc = "  * Neon instrinsic unsafe"]
15366#[inline]
15367#[cfg(target_arch = "arm")]
15368#[target_feature(enable = "neon,v7")]
15369#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15370#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
15371pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t {
15372    transmute(vld1_v1i64(
15373        ptr as *const i8,
15374        crate::mem::align_of::<u64>() as i32,
15375    ))
15376}
15377#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"]
15379#[doc = "## Safety"]
15380#[doc = "  * Neon instrinsic unsafe"]
15381#[inline]
15382#[cfg(target_endian = "little")]
15383#[cfg(target_arch = "arm")]
15384#[target_feature(enable = "neon,v7")]
15385#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15386#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
15387pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t {
15388    transmute(vld1q_v2i64(
15389        ptr as *const i8,
15390        crate::mem::align_of::<u64>() as i32,
15391    ))
15392}
15393#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"]
15395#[doc = "## Safety"]
15396#[doc = "  * Neon instrinsic unsafe"]
15397#[inline]
15398#[cfg(target_endian = "big")]
15399#[cfg(target_arch = "arm")]
15400#[target_feature(enable = "neon,v7")]
15401#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15402#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
15403pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t {
15404    let ret_val: uint64x2_t = transmute(vld1q_v2i64(
15405        ptr as *const i8,
15406        crate::mem::align_of::<u64>() as i32,
15407    ));
15408    simd_shuffle!(ret_val, ret_val, [1, 0])
15409}
15410#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15411#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"]
15412#[doc = "## Safety"]
15413#[doc = "  * Neon instrinsic unsafe"]
15414#[inline]
15415#[cfg(target_endian = "little")]
15416#[cfg(target_arch = "arm")]
15417#[target_feature(enable = "neon,v7")]
15418#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15419#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15420pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t {
15421    transmute(vld1_v8i8(
15422        ptr as *const i8,
15423        crate::mem::align_of::<p8>() as i32,
15424    ))
15425}
15426#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15427#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"]
15428#[doc = "## Safety"]
15429#[doc = "  * Neon instrinsic unsafe"]
15430#[inline]
15431#[cfg(target_endian = "big")]
15432#[cfg(target_arch = "arm")]
15433#[target_feature(enable = "neon,v7")]
15434#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15435#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15436pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t {
15437    let ret_val: poly8x8_t = transmute(vld1_v8i8(
15438        ptr as *const i8,
15439        crate::mem::align_of::<p8>() as i32,
15440    ));
15441    simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15442}
15443#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15444#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"]
15445#[doc = "## Safety"]
15446#[doc = "  * Neon instrinsic unsafe"]
15447#[inline]
15448#[cfg(target_endian = "little")]
15449#[cfg(target_arch = "arm")]
15450#[target_feature(enable = "neon,v7")]
15451#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15452#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15453pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t {
15454    transmute(vld1q_v16i8(
15455        ptr as *const i8,
15456        crate::mem::align_of::<p8>() as i32,
15457    ))
15458}
15459#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"]
15461#[doc = "## Safety"]
15462#[doc = "  * Neon instrinsic unsafe"]
15463#[inline]
15464#[cfg(target_endian = "big")]
15465#[cfg(target_arch = "arm")]
15466#[target_feature(enable = "neon,v7")]
15467#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15468#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15469pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t {
15470    let ret_val: poly8x16_t = transmute(vld1q_v16i8(
15471        ptr as *const i8,
15472        crate::mem::align_of::<p8>() as i32,
15473    ));
15474    simd_shuffle!(
15475        ret_val,
15476        ret_val,
15477        [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
15478    )
15479}
15480#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15481#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"]
15482#[doc = "## Safety"]
15483#[doc = "  * Neon instrinsic unsafe"]
15484#[inline]
15485#[cfg(target_endian = "little")]
15486#[cfg(target_arch = "arm")]
15487#[target_feature(enable = "neon,v7")]
15488#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15489#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15490pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t {
15491    transmute(vld1_v4i16(
15492        ptr as *const i8,
15493        crate::mem::align_of::<p16>() as i32,
15494    ))
15495}
15496#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"]
15498#[doc = "## Safety"]
15499#[doc = "  * Neon instrinsic unsafe"]
15500#[inline]
15501#[cfg(target_endian = "big")]
15502#[cfg(target_arch = "arm")]
15503#[target_feature(enable = "neon,v7")]
15504#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15505#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15506pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t {
15507    let ret_val: poly16x4_t = transmute(vld1_v4i16(
15508        ptr as *const i8,
15509        crate::mem::align_of::<p16>() as i32,
15510    ));
15511    simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15512}
15513#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15514#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"]
15515#[doc = "## Safety"]
15516#[doc = "  * Neon instrinsic unsafe"]
15517#[inline]
15518#[cfg(target_endian = "little")]
15519#[cfg(target_arch = "arm")]
15520#[target_feature(enable = "neon,v7")]
15521#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15522#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15523pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t {
15524    transmute(vld1q_v8i16(
15525        ptr as *const i8,
15526        crate::mem::align_of::<p16>() as i32,
15527    ))
15528}
15529#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15530#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"]
15531#[doc = "## Safety"]
15532#[doc = "  * Neon instrinsic unsafe"]
15533#[inline]
15534#[cfg(target_endian = "big")]
15535#[cfg(target_arch = "arm")]
15536#[target_feature(enable = "neon,v7")]
15537#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15538#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15539pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t {
15540    let ret_val: poly16x8_t = transmute(vld1q_v8i16(
15541        ptr as *const i8,
15542        crate::mem::align_of::<p16>() as i32,
15543    ));
15544    simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15545}
15546#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15547#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"]
15548#[doc = "## Safety"]
15549#[doc = "  * Neon instrinsic unsafe"]
15550#[inline]
15551#[cfg(target_endian = "little")]
15552#[cfg(target_arch = "arm")]
15553#[target_feature(enable = "neon,aes")]
15554#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15555#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
15556pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
15557    transmute(vld1q_v2i64(
15558        ptr as *const i8,
15559        crate::mem::align_of::<p64>() as i32,
15560    ))
15561}
15562#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15563#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"]
15564#[doc = "## Safety"]
15565#[doc = "  * Neon instrinsic unsafe"]
15566#[inline]
15567#[cfg(target_endian = "big")]
15568#[cfg(target_arch = "arm")]
15569#[target_feature(enable = "neon,aes")]
15570#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15571#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
15572pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
15573    let ret_val: poly64x2_t = transmute(vld1q_v2i64(
15574        ptr as *const i8,
15575        crate::mem::align_of::<p64>() as i32,
15576    ));
15577    simd_shuffle!(ret_val, ret_val, [1, 0])
15578}
15579#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x2)"]
15581#[doc = "## Safety"]
15582#[doc = "  * Neon instrinsic unsafe"]
15583#[inline]
15584#[target_feature(enable = "neon")]
15585#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15586#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15587#[cfg_attr(
15588    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15589    assert_instr(ld1)
15590)]
15591#[cfg_attr(
15592    not(target_arch = "arm"),
15593    stable(feature = "neon_intrinsics", since = "1.59.0")
15594)]
15595#[cfg_attr(
15596    target_arch = "arm",
15597    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15598)]
15599pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t {
15600    unsafe extern "unadjusted" {
15601        #[cfg_attr(
15602            any(target_arch = "aarch64", target_arch = "arm64ec"),
15603            link_name = "llvm.aarch64.neon.ld1x2.v2f32.p0"
15604        )]
15605        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2f32.p0")]
15606        fn _vld1_f32_x2(a: *const f32) -> float32x2x2_t;
15607    }
15608    _vld1_f32_x2(a)
15609}
15610#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15611#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x3)"]
15612#[doc = "## Safety"]
15613#[doc = "  * Neon instrinsic unsafe"]
15614#[inline]
15615#[target_feature(enable = "neon")]
15616#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15617#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15618#[cfg_attr(
15619    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15620    assert_instr(ld1)
15621)]
15622#[cfg_attr(
15623    not(target_arch = "arm"),
15624    stable(feature = "neon_intrinsics", since = "1.59.0")
15625)]
15626#[cfg_attr(
15627    target_arch = "arm",
15628    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15629)]
15630pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t {
15631    unsafe extern "unadjusted" {
15632        #[cfg_attr(
15633            any(target_arch = "aarch64", target_arch = "arm64ec"),
15634            link_name = "llvm.aarch64.neon.ld1x3.v2f32.p0"
15635        )]
15636        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2f32.p0")]
15637        fn _vld1_f32_x3(a: *const f32) -> float32x2x3_t;
15638    }
15639    _vld1_f32_x3(a)
15640}
15641#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15642#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x4)"]
15643#[doc = "## Safety"]
15644#[doc = "  * Neon instrinsic unsafe"]
15645#[inline]
15646#[target_feature(enable = "neon")]
15647#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15648#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15649#[cfg_attr(
15650    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15651    assert_instr(ld1)
15652)]
15653#[cfg_attr(
15654    not(target_arch = "arm"),
15655    stable(feature = "neon_intrinsics", since = "1.59.0")
15656)]
15657#[cfg_attr(
15658    target_arch = "arm",
15659    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15660)]
15661pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t {
15662    unsafe extern "unadjusted" {
15663        #[cfg_attr(
15664            any(target_arch = "aarch64", target_arch = "arm64ec"),
15665            link_name = "llvm.aarch64.neon.ld1x4.v2f32.p0"
15666        )]
15667        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2f32.p0")]
15668        fn _vld1_f32_x4(a: *const f32) -> float32x2x4_t;
15669    }
15670    _vld1_f32_x4(a)
15671}
15672#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15673#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x2)"]
15674#[doc = "## Safety"]
15675#[doc = "  * Neon instrinsic unsafe"]
15676#[inline]
15677#[target_feature(enable = "neon")]
15678#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15679#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15680#[cfg_attr(
15681    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15682    assert_instr(ld1)
15683)]
15684#[cfg_attr(
15685    not(target_arch = "arm"),
15686    stable(feature = "neon_intrinsics", since = "1.59.0")
15687)]
15688#[cfg_attr(
15689    target_arch = "arm",
15690    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15691)]
15692pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t {
15693    unsafe extern "unadjusted" {
15694        #[cfg_attr(
15695            any(target_arch = "aarch64", target_arch = "arm64ec"),
15696            link_name = "llvm.aarch64.neon.ld1x2.v4f32.p0"
15697        )]
15698        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4f32.p0")]
15699        fn _vld1q_f32_x2(a: *const f32) -> float32x4x2_t;
15700    }
15701    _vld1q_f32_x2(a)
15702}
15703#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15704#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x3)"]
15705#[doc = "## Safety"]
15706#[doc = "  * Neon instrinsic unsafe"]
15707#[inline]
15708#[target_feature(enable = "neon")]
15709#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15710#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15711#[cfg_attr(
15712    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15713    assert_instr(ld1)
15714)]
15715#[cfg_attr(
15716    not(target_arch = "arm"),
15717    stable(feature = "neon_intrinsics", since = "1.59.0")
15718)]
15719#[cfg_attr(
15720    target_arch = "arm",
15721    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15722)]
15723pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t {
15724    unsafe extern "unadjusted" {
15725        #[cfg_attr(
15726            any(target_arch = "aarch64", target_arch = "arm64ec"),
15727            link_name = "llvm.aarch64.neon.ld1x3.v4f32.p0"
15728        )]
15729        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4f32.p0")]
15730        fn _vld1q_f32_x3(a: *const f32) -> float32x4x3_t;
15731    }
15732    _vld1q_f32_x3(a)
15733}
15734#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15735#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x4)"]
15736#[doc = "## Safety"]
15737#[doc = "  * Neon instrinsic unsafe"]
15738#[inline]
15739#[target_feature(enable = "neon")]
15740#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15741#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15742#[cfg_attr(
15743    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15744    assert_instr(ld1)
15745)]
15746#[cfg_attr(
15747    not(target_arch = "arm"),
15748    stable(feature = "neon_intrinsics", since = "1.59.0")
15749)]
15750#[cfg_attr(
15751    target_arch = "arm",
15752    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15753)]
15754pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t {
15755    unsafe extern "unadjusted" {
15756        #[cfg_attr(
15757            any(target_arch = "aarch64", target_arch = "arm64ec"),
15758            link_name = "llvm.aarch64.neon.ld1x4.v4f32.p0"
15759        )]
15760        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4f32.p0")]
15761        fn _vld1q_f32_x4(a: *const f32) -> float32x4x4_t;
15762    }
15763    _vld1q_f32_x4(a)
15764}
15765#[doc = "Load one single-element structure to one lane of one register"]
15766#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f16)"]
15767#[doc = "## Safety"]
15768#[doc = "  * Neon instrinsic unsafe"]
15769#[inline]
15770#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15771#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))]
15772#[cfg_attr(
15773    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15774    assert_instr(ld1, LANE = 0)
15775)]
15776#[rustc_legacy_const_generics(2)]
15777#[target_feature(enable = "neon,fp16")]
15778#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15779pub unsafe fn vld1_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x4_t) -> float16x4_t {
15780    static_assert_uimm_bits!(LANE, 2);
15781    simd_insert!(src, LANE as u32, *ptr)
15782}
15783#[doc = "Load one single-element structure to one lane of one register"]
15784#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f16)"]
15785#[doc = "## Safety"]
15786#[doc = "  * Neon instrinsic unsafe"]
15787#[inline]
15788#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15789#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))]
15790#[cfg_attr(
15791    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15792    assert_instr(ld1, LANE = 0)
15793)]
15794#[rustc_legacy_const_generics(2)]
15795#[target_feature(enable = "neon,fp16")]
15796#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15797pub unsafe fn vld1q_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x8_t) -> float16x8_t {
15798    static_assert_uimm_bits!(LANE, 3);
15799    simd_insert!(src, LANE as u32, *ptr)
15800}
15801#[doc = "Load one single-element structure to one lane of one register."]
15802#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f32)"]
15803#[doc = "## Safety"]
15804#[doc = "  * Neon instrinsic unsafe"]
15805#[inline]
15806#[target_feature(enable = "neon")]
15807#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15808#[rustc_legacy_const_generics(2)]
15809#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))]
15810#[cfg_attr(
15811    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15812    assert_instr(ld1, LANE = 1)
15813)]
15814#[cfg_attr(
15815    not(target_arch = "arm"),
15816    stable(feature = "neon_intrinsics", since = "1.59.0")
15817)]
15818#[cfg_attr(
15819    target_arch = "arm",
15820    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15821)]
15822pub unsafe fn vld1_lane_f32<const LANE: i32>(ptr: *const f32, src: float32x2_t) -> float32x2_t {
15823    static_assert_uimm_bits!(LANE, 1);
15824    simd_insert!(src, LANE as u32, *ptr)
15825}
15826#[doc = "Load one single-element structure to one lane of one register."]
15827#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p16)"]
15828#[doc = "## Safety"]
15829#[doc = "  * Neon instrinsic unsafe"]
15830#[inline]
15831#[target_feature(enable = "neon")]
15832#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15833#[rustc_legacy_const_generics(2)]
15834#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))]
15835#[cfg_attr(
15836    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15837    assert_instr(ld1, LANE = 3)
15838)]
15839#[cfg_attr(
15840    not(target_arch = "arm"),
15841    stable(feature = "neon_intrinsics", since = "1.59.0")
15842)]
15843#[cfg_attr(
15844    target_arch = "arm",
15845    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15846)]
15847pub unsafe fn vld1_lane_p16<const LANE: i32>(ptr: *const p16, src: poly16x4_t) -> poly16x4_t {
15848    static_assert_uimm_bits!(LANE, 2);
15849    simd_insert!(src, LANE as u32, *ptr)
15850}
15851#[doc = "Load one single-element structure to one lane of one register."]
15852#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p8)"]
15853#[doc = "## Safety"]
15854#[doc = "  * Neon instrinsic unsafe"]
15855#[inline]
15856#[target_feature(enable = "neon")]
15857#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15858#[rustc_legacy_const_generics(2)]
15859#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))]
15860#[cfg_attr(
15861    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15862    assert_instr(ld1, LANE = 7)
15863)]
15864#[cfg_attr(
15865    not(target_arch = "arm"),
15866    stable(feature = "neon_intrinsics", since = "1.59.0")
15867)]
15868#[cfg_attr(
15869    target_arch = "arm",
15870    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15871)]
15872pub unsafe fn vld1_lane_p8<const LANE: i32>(ptr: *const p8, src: poly8x8_t) -> poly8x8_t {
15873    static_assert_uimm_bits!(LANE, 3);
15874    simd_insert!(src, LANE as u32, *ptr)
15875}
15876#[doc = "Load one single-element structure to one lane of one register."]
15877#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s16)"]
15878#[doc = "## Safety"]
15879#[doc = "  * Neon instrinsic unsafe"]
15880#[inline]
15881#[target_feature(enable = "neon")]
15882#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15883#[rustc_legacy_const_generics(2)]
15884#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))]
15885#[cfg_attr(
15886    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15887    assert_instr(ld1, LANE = 3)
15888)]
15889#[cfg_attr(
15890    not(target_arch = "arm"),
15891    stable(feature = "neon_intrinsics", since = "1.59.0")
15892)]
15893#[cfg_attr(
15894    target_arch = "arm",
15895    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15896)]
15897pub unsafe fn vld1_lane_s16<const LANE: i32>(ptr: *const i16, src: int16x4_t) -> int16x4_t {
15898    static_assert_uimm_bits!(LANE, 2);
15899    simd_insert!(src, LANE as u32, *ptr)
15900}
15901#[doc = "Load one single-element structure to one lane of one register."]
15902#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s32)"]
15903#[doc = "## Safety"]
15904#[doc = "  * Neon instrinsic unsafe"]
15905#[inline]
15906#[target_feature(enable = "neon")]
15907#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15908#[rustc_legacy_const_generics(2)]
15909#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))]
15910#[cfg_attr(
15911    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15912    assert_instr(ld1, LANE = 1)
15913)]
15914#[cfg_attr(
15915    not(target_arch = "arm"),
15916    stable(feature = "neon_intrinsics", since = "1.59.0")
15917)]
15918#[cfg_attr(
15919    target_arch = "arm",
15920    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15921)]
15922pub unsafe fn vld1_lane_s32<const LANE: i32>(ptr: *const i32, src: int32x2_t) -> int32x2_t {
15923    static_assert_uimm_bits!(LANE, 1);
15924    simd_insert!(src, LANE as u32, *ptr)
15925}
15926#[doc = "Load one single-element structure to one lane of one register."]
15927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s64)"]
15928#[doc = "## Safety"]
15929#[doc = "  * Neon instrinsic unsafe"]
15930#[inline]
15931#[target_feature(enable = "neon")]
15932#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15933#[rustc_legacy_const_generics(2)]
15934#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))]
15935#[cfg_attr(
15936    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15937    assert_instr(ldr, LANE = 0)
15938)]
15939#[cfg_attr(
15940    not(target_arch = "arm"),
15941    stable(feature = "neon_intrinsics", since = "1.59.0")
15942)]
15943#[cfg_attr(
15944    target_arch = "arm",
15945    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15946)]
15947pub unsafe fn vld1_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x1_t) -> int64x1_t {
15948    static_assert!(LANE == 0);
15949    simd_insert!(src, LANE as u32, *ptr)
15950}
15951#[doc = "Load one single-element structure to one lane of one register."]
15952#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s8)"]
15953#[doc = "## Safety"]
15954#[doc = "  * Neon instrinsic unsafe"]
15955#[inline]
15956#[target_feature(enable = "neon")]
15957#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15958#[rustc_legacy_const_generics(2)]
15959#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))]
15960#[cfg_attr(
15961    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15962    assert_instr(ld1, LANE = 7)
15963)]
15964#[cfg_attr(
15965    not(target_arch = "arm"),
15966    stable(feature = "neon_intrinsics", since = "1.59.0")
15967)]
15968#[cfg_attr(
15969    target_arch = "arm",
15970    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15971)]
15972pub unsafe fn vld1_lane_s8<const LANE: i32>(ptr: *const i8, src: int8x8_t) -> int8x8_t {
15973    static_assert_uimm_bits!(LANE, 3);
15974    simd_insert!(src, LANE as u32, *ptr)
15975}
15976#[doc = "Load one single-element structure to one lane of one register."]
15977#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u16)"]
15978#[doc = "## Safety"]
15979#[doc = "  * Neon instrinsic unsafe"]
15980#[inline]
15981#[target_feature(enable = "neon")]
15982#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15983#[rustc_legacy_const_generics(2)]
15984#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))]
15985#[cfg_attr(
15986    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15987    assert_instr(ld1, LANE = 3)
15988)]
15989#[cfg_attr(
15990    not(target_arch = "arm"),
15991    stable(feature = "neon_intrinsics", since = "1.59.0")
15992)]
15993#[cfg_attr(
15994    target_arch = "arm",
15995    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15996)]
15997pub unsafe fn vld1_lane_u16<const LANE: i32>(ptr: *const u16, src: uint16x4_t) -> uint16x4_t {
15998    static_assert_uimm_bits!(LANE, 2);
15999    simd_insert!(src, LANE as u32, *ptr)
16000}
16001#[doc = "Load one single-element structure to one lane of one register."]
16002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u32)"]
16003#[doc = "## Safety"]
16004#[doc = "  * Neon instrinsic unsafe"]
16005#[inline]
16006#[target_feature(enable = "neon")]
16007#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16008#[rustc_legacy_const_generics(2)]
16009#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))]
16010#[cfg_attr(
16011    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16012    assert_instr(ld1, LANE = 1)
16013)]
16014#[cfg_attr(
16015    not(target_arch = "arm"),
16016    stable(feature = "neon_intrinsics", since = "1.59.0")
16017)]
16018#[cfg_attr(
16019    target_arch = "arm",
16020    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16021)]
16022pub unsafe fn vld1_lane_u32<const LANE: i32>(ptr: *const u32, src: uint32x2_t) -> uint32x2_t {
16023    static_assert_uimm_bits!(LANE, 1);
16024    simd_insert!(src, LANE as u32, *ptr)
16025}
16026#[doc = "Load one single-element structure to one lane of one register."]
16027#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u64)"]
16028#[doc = "## Safety"]
16029#[doc = "  * Neon instrinsic unsafe"]
16030#[inline]
16031#[target_feature(enable = "neon")]
16032#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16033#[rustc_legacy_const_generics(2)]
16034#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))]
16035#[cfg_attr(
16036    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16037    assert_instr(ldr, LANE = 0)
16038)]
16039#[cfg_attr(
16040    not(target_arch = "arm"),
16041    stable(feature = "neon_intrinsics", since = "1.59.0")
16042)]
16043#[cfg_attr(
16044    target_arch = "arm",
16045    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16046)]
16047pub unsafe fn vld1_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x1_t) -> uint64x1_t {
16048    static_assert!(LANE == 0);
16049    simd_insert!(src, LANE as u32, *ptr)
16050}
16051#[doc = "Load one single-element structure to one lane of one register."]
16052#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u8)"]
16053#[doc = "## Safety"]
16054#[doc = "  * Neon instrinsic unsafe"]
16055#[inline]
16056#[target_feature(enable = "neon")]
16057#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16058#[rustc_legacy_const_generics(2)]
16059#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))]
16060#[cfg_attr(
16061    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16062    assert_instr(ld1, LANE = 7)
16063)]
16064#[cfg_attr(
16065    not(target_arch = "arm"),
16066    stable(feature = "neon_intrinsics", since = "1.59.0")
16067)]
16068#[cfg_attr(
16069    target_arch = "arm",
16070    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16071)]
16072pub unsafe fn vld1_lane_u8<const LANE: i32>(ptr: *const u8, src: uint8x8_t) -> uint8x8_t {
16073    static_assert_uimm_bits!(LANE, 3);
16074    simd_insert!(src, LANE as u32, *ptr)
16075}
16076#[doc = "Load one single-element structure to one lane of one register."]
16077#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f32)"]
16078#[doc = "## Safety"]
16079#[doc = "  * Neon instrinsic unsafe"]
16080#[inline]
16081#[target_feature(enable = "neon")]
16082#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16083#[rustc_legacy_const_generics(2)]
16084#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))]
16085#[cfg_attr(
16086    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16087    assert_instr(ld1, LANE = 3)
16088)]
16089#[cfg_attr(
16090    not(target_arch = "arm"),
16091    stable(feature = "neon_intrinsics", since = "1.59.0")
16092)]
16093#[cfg_attr(
16094    target_arch = "arm",
16095    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16096)]
16097pub unsafe fn vld1q_lane_f32<const LANE: i32>(ptr: *const f32, src: float32x4_t) -> float32x4_t {
16098    static_assert_uimm_bits!(LANE, 2);
16099    simd_insert!(src, LANE as u32, *ptr)
16100}
16101#[doc = "Load one single-element structure to one lane of one register."]
16102#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p16)"]
16103#[doc = "## Safety"]
16104#[doc = "  * Neon instrinsic unsafe"]
16105#[inline]
16106#[target_feature(enable = "neon")]
16107#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16108#[rustc_legacy_const_generics(2)]
16109#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))]
16110#[cfg_attr(
16111    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16112    assert_instr(ld1, LANE = 7)
16113)]
16114#[cfg_attr(
16115    not(target_arch = "arm"),
16116    stable(feature = "neon_intrinsics", since = "1.59.0")
16117)]
16118#[cfg_attr(
16119    target_arch = "arm",
16120    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16121)]
16122pub unsafe fn vld1q_lane_p16<const LANE: i32>(ptr: *const p16, src: poly16x8_t) -> poly16x8_t {
16123    static_assert_uimm_bits!(LANE, 3);
16124    simd_insert!(src, LANE as u32, *ptr)
16125}
16126#[doc = "Load one single-element structure to one lane of one register."]
16127#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p8)"]
16128#[doc = "## Safety"]
16129#[doc = "  * Neon instrinsic unsafe"]
16130#[inline]
16131#[target_feature(enable = "neon")]
16132#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16133#[rustc_legacy_const_generics(2)]
16134#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))]
16135#[cfg_attr(
16136    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16137    assert_instr(ld1, LANE = 15)
16138)]
16139#[cfg_attr(
16140    not(target_arch = "arm"),
16141    stable(feature = "neon_intrinsics", since = "1.59.0")
16142)]
16143#[cfg_attr(
16144    target_arch = "arm",
16145    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16146)]
16147pub unsafe fn vld1q_lane_p8<const LANE: i32>(ptr: *const p8, src: poly8x16_t) -> poly8x16_t {
16148    static_assert_uimm_bits!(LANE, 4);
16149    simd_insert!(src, LANE as u32, *ptr)
16150}
16151#[doc = "Load one single-element structure to one lane of one register."]
16152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s16)"]
16153#[doc = "## Safety"]
16154#[doc = "  * Neon instrinsic unsafe"]
16155#[inline]
16156#[target_feature(enable = "neon")]
16157#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16158#[rustc_legacy_const_generics(2)]
16159#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))]
16160#[cfg_attr(
16161    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16162    assert_instr(ld1, LANE = 7)
16163)]
16164#[cfg_attr(
16165    not(target_arch = "arm"),
16166    stable(feature = "neon_intrinsics", since = "1.59.0")
16167)]
16168#[cfg_attr(
16169    target_arch = "arm",
16170    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16171)]
16172pub unsafe fn vld1q_lane_s16<const LANE: i32>(ptr: *const i16, src: int16x8_t) -> int16x8_t {
16173    static_assert_uimm_bits!(LANE, 3);
16174    simd_insert!(src, LANE as u32, *ptr)
16175}
16176#[doc = "Load one single-element structure to one lane of one register."]
16177#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s32)"]
16178#[doc = "## Safety"]
16179#[doc = "  * Neon instrinsic unsafe"]
16180#[inline]
16181#[target_feature(enable = "neon")]
16182#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16183#[rustc_legacy_const_generics(2)]
16184#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))]
16185#[cfg_attr(
16186    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16187    assert_instr(ld1, LANE = 3)
16188)]
16189#[cfg_attr(
16190    not(target_arch = "arm"),
16191    stable(feature = "neon_intrinsics", since = "1.59.0")
16192)]
16193#[cfg_attr(
16194    target_arch = "arm",
16195    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16196)]
16197pub unsafe fn vld1q_lane_s32<const LANE: i32>(ptr: *const i32, src: int32x4_t) -> int32x4_t {
16198    static_assert_uimm_bits!(LANE, 2);
16199    simd_insert!(src, LANE as u32, *ptr)
16200}
16201#[doc = "Load one single-element structure to one lane of one register."]
16202#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s64)"]
16203#[doc = "## Safety"]
16204#[doc = "  * Neon instrinsic unsafe"]
16205#[inline]
16206#[target_feature(enable = "neon")]
16207#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16208#[rustc_legacy_const_generics(2)]
16209#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))]
16210#[cfg_attr(
16211    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16212    assert_instr(ld1, LANE = 1)
16213)]
16214#[cfg_attr(
16215    not(target_arch = "arm"),
16216    stable(feature = "neon_intrinsics", since = "1.59.0")
16217)]
16218#[cfg_attr(
16219    target_arch = "arm",
16220    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16221)]
16222pub unsafe fn vld1q_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x2_t) -> int64x2_t {
16223    static_assert_uimm_bits!(LANE, 1);
16224    simd_insert!(src, LANE as u32, *ptr)
16225}
16226#[doc = "Load one single-element structure to one lane of one register."]
16227#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s8)"]
16228#[doc = "## Safety"]
16229#[doc = "  * Neon instrinsic unsafe"]
16230#[inline]
16231#[target_feature(enable = "neon")]
16232#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16233#[rustc_legacy_const_generics(2)]
16234#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))]
16235#[cfg_attr(
16236    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16237    assert_instr(ld1, LANE = 15)
16238)]
16239#[cfg_attr(
16240    not(target_arch = "arm"),
16241    stable(feature = "neon_intrinsics", since = "1.59.0")
16242)]
16243#[cfg_attr(
16244    target_arch = "arm",
16245    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16246)]
16247pub unsafe fn vld1q_lane_s8<const LANE: i32>(ptr: *const i8, src: int8x16_t) -> int8x16_t {
16248    static_assert_uimm_bits!(LANE, 4);
16249    simd_insert!(src, LANE as u32, *ptr)
16250}
16251#[doc = "Load one single-element structure to one lane of one register."]
16252#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u16)"]
16253#[doc = "## Safety"]
16254#[doc = "  * Neon instrinsic unsafe"]
16255#[inline]
16256#[target_feature(enable = "neon")]
16257#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16258#[rustc_legacy_const_generics(2)]
16259#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))]
16260#[cfg_attr(
16261    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16262    assert_instr(ld1, LANE = 7)
16263)]
16264#[cfg_attr(
16265    not(target_arch = "arm"),
16266    stable(feature = "neon_intrinsics", since = "1.59.0")
16267)]
16268#[cfg_attr(
16269    target_arch = "arm",
16270    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16271)]
16272pub unsafe fn vld1q_lane_u16<const LANE: i32>(ptr: *const u16, src: uint16x8_t) -> uint16x8_t {
16273    static_assert_uimm_bits!(LANE, 3);
16274    simd_insert!(src, LANE as u32, *ptr)
16275}
16276#[doc = "Load one single-element structure to one lane of one register."]
16277#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u32)"]
16278#[doc = "## Safety"]
16279#[doc = "  * Neon instrinsic unsafe"]
16280#[inline]
16281#[target_feature(enable = "neon")]
16282#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16283#[rustc_legacy_const_generics(2)]
16284#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))]
16285#[cfg_attr(
16286    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16287    assert_instr(ld1, LANE = 3)
16288)]
16289#[cfg_attr(
16290    not(target_arch = "arm"),
16291    stable(feature = "neon_intrinsics", since = "1.59.0")
16292)]
16293#[cfg_attr(
16294    target_arch = "arm",
16295    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16296)]
16297pub unsafe fn vld1q_lane_u32<const LANE: i32>(ptr: *const u32, src: uint32x4_t) -> uint32x4_t {
16298    static_assert_uimm_bits!(LANE, 2);
16299    simd_insert!(src, LANE as u32, *ptr)
16300}
16301#[doc = "Load one single-element structure to one lane of one register."]
16302#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u64)"]
16303#[doc = "## Safety"]
16304#[doc = "  * Neon instrinsic unsafe"]
16305#[inline]
16306#[target_feature(enable = "neon")]
16307#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16308#[rustc_legacy_const_generics(2)]
16309#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))]
16310#[cfg_attr(
16311    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16312    assert_instr(ld1, LANE = 1)
16313)]
16314#[cfg_attr(
16315    not(target_arch = "arm"),
16316    stable(feature = "neon_intrinsics", since = "1.59.0")
16317)]
16318#[cfg_attr(
16319    target_arch = "arm",
16320    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16321)]
16322pub unsafe fn vld1q_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x2_t) -> uint64x2_t {
16323    static_assert_uimm_bits!(LANE, 1);
16324    simd_insert!(src, LANE as u32, *ptr)
16325}
16326#[doc = "Load one single-element structure to one lane of one register."]
16327#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u8)"]
16328#[doc = "## Safety"]
16329#[doc = "  * Neon instrinsic unsafe"]
16330#[inline]
16331#[target_feature(enable = "neon")]
16332#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16333#[rustc_legacy_const_generics(2)]
16334#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))]
16335#[cfg_attr(
16336    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16337    assert_instr(ld1, LANE = 15)
16338)]
16339#[cfg_attr(
16340    not(target_arch = "arm"),
16341    stable(feature = "neon_intrinsics", since = "1.59.0")
16342)]
16343#[cfg_attr(
16344    target_arch = "arm",
16345    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16346)]
16347pub unsafe fn vld1q_lane_u8<const LANE: i32>(ptr: *const u8, src: uint8x16_t) -> uint8x16_t {
16348    static_assert_uimm_bits!(LANE, 4);
16349    simd_insert!(src, LANE as u32, *ptr)
16350}
16351#[doc = "Load one single-element structure to one lane of one register."]
16352#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p64)"]
16353#[doc = "## Safety"]
16354#[doc = "  * Neon instrinsic unsafe"]
16355#[inline]
16356#[target_feature(enable = "neon,aes")]
16357#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16358#[rustc_legacy_const_generics(2)]
16359#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))]
16360#[cfg_attr(
16361    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16362    assert_instr(ldr, LANE = 0)
16363)]
16364#[cfg_attr(
16365    not(target_arch = "arm"),
16366    stable(feature = "neon_intrinsics", since = "1.59.0")
16367)]
16368#[cfg_attr(
16369    target_arch = "arm",
16370    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16371)]
16372pub unsafe fn vld1_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x1_t) -> poly64x1_t {
16373    static_assert!(LANE == 0);
16374    simd_insert!(src, LANE as u32, *ptr)
16375}
16376#[doc = "Load one single-element structure to one lane of one register."]
16377#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p64)"]
16378#[doc = "## Safety"]
16379#[doc = "  * Neon instrinsic unsafe"]
16380#[inline]
16381#[target_feature(enable = "neon,aes")]
16382#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16383#[rustc_legacy_const_generics(2)]
16384#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))]
16385#[cfg_attr(
16386    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16387    assert_instr(ld1, LANE = 1)
16388)]
16389#[cfg_attr(
16390    not(target_arch = "arm"),
16391    stable(feature = "neon_intrinsics", since = "1.59.0")
16392)]
16393#[cfg_attr(
16394    target_arch = "arm",
16395    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16396)]
16397pub unsafe fn vld1q_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x2_t) -> poly64x2_t {
16398    static_assert_uimm_bits!(LANE, 1);
16399    simd_insert!(src, LANE as u32, *ptr)
16400}
16401#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16402#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"]
16403#[doc = "## Safety"]
16404#[doc = "  * Neon instrinsic unsafe"]
16405#[inline]
16406#[cfg(target_arch = "arm")]
16407#[target_feature(enable = "neon,aes")]
16408#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16409#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
16410pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t {
16411    let a: *const i8 = ptr as *const i8;
16412    let b: i32 = crate::mem::align_of::<p64>() as i32;
16413    unsafe extern "unadjusted" {
16414        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v1i64")]
16415        fn _vld1_v1i64(a: *const i8, b: i32) -> int64x1_t;
16416    }
16417    transmute(_vld1_v1i64(a, b))
16418}
16419#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16420#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x2)"]
16421#[doc = "## Safety"]
16422#[doc = "  * Neon instrinsic unsafe"]
16423#[inline]
16424#[target_feature(enable = "neon,aes")]
16425#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16426#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16427#[cfg_attr(
16428    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16429    assert_instr(ld1)
16430)]
16431#[cfg_attr(
16432    not(target_arch = "arm"),
16433    stable(feature = "neon_intrinsics", since = "1.59.0")
16434)]
16435#[cfg_attr(
16436    target_arch = "arm",
16437    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16438)]
16439pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t {
16440    transmute(vld1_s64_x2(transmute(a)))
16441}
16442#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16443#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x3)"]
16444#[doc = "## Safety"]
16445#[doc = "  * Neon instrinsic unsafe"]
16446#[inline]
16447#[target_feature(enable = "neon,aes")]
16448#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16449#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16450#[cfg_attr(
16451    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16452    assert_instr(ld1)
16453)]
16454#[cfg_attr(
16455    not(target_arch = "arm"),
16456    stable(feature = "neon_intrinsics", since = "1.59.0")
16457)]
16458#[cfg_attr(
16459    target_arch = "arm",
16460    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16461)]
16462pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t {
16463    transmute(vld1_s64_x3(transmute(a)))
16464}
16465#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16466#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x4)"]
16467#[doc = "## Safety"]
16468#[doc = "  * Neon instrinsic unsafe"]
16469#[inline]
16470#[target_feature(enable = "neon,aes")]
16471#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16472#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16473#[cfg_attr(
16474    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16475    assert_instr(ld1)
16476)]
16477#[cfg_attr(
16478    not(target_arch = "arm"),
16479    stable(feature = "neon_intrinsics", since = "1.59.0")
16480)]
16481#[cfg_attr(
16482    target_arch = "arm",
16483    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16484)]
16485pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t {
16486    transmute(vld1_s64_x4(transmute(a)))
16487}
16488#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16489#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"]
16490#[doc = "## Safety"]
16491#[doc = "  * Neon instrinsic unsafe"]
16492#[inline]
16493#[cfg(target_endian = "little")]
16494#[target_feature(enable = "neon,aes")]
16495#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16496#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16497#[cfg_attr(
16498    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16499    assert_instr(ld1)
16500)]
16501#[cfg_attr(
16502    not(target_arch = "arm"),
16503    stable(feature = "neon_intrinsics", since = "1.59.0")
16504)]
16505#[cfg_attr(
16506    target_arch = "arm",
16507    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16508)]
16509pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
16510    transmute(vld1q_s64_x2(transmute(a)))
16511}
16512#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16513#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"]
16514#[doc = "## Safety"]
16515#[doc = "  * Neon instrinsic unsafe"]
16516#[inline]
16517#[cfg(target_endian = "big")]
16518#[target_feature(enable = "neon,aes")]
16519#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16520#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16521#[cfg_attr(
16522    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16523    assert_instr(ld1)
16524)]
16525#[cfg_attr(
16526    not(target_arch = "arm"),
16527    stable(feature = "neon_intrinsics", since = "1.59.0")
16528)]
16529#[cfg_attr(
16530    target_arch = "arm",
16531    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16532)]
16533pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
16534    let mut ret_val: poly64x2x2_t = transmute(vld1q_s64_x2(transmute(a)));
16535    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
16536    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
16537    ret_val
16538}
16539#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16540#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"]
16541#[doc = "## Safety"]
16542#[doc = "  * Neon instrinsic unsafe"]
16543#[inline]
16544#[cfg(target_endian = "little")]
16545#[target_feature(enable = "neon,aes")]
16546#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16547#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16548#[cfg_attr(
16549    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16550    assert_instr(ld1)
16551)]
16552#[cfg_attr(
16553    not(target_arch = "arm"),
16554    stable(feature = "neon_intrinsics", since = "1.59.0")
16555)]
16556#[cfg_attr(
16557    target_arch = "arm",
16558    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16559)]
16560pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
16561    transmute(vld1q_s64_x3(transmute(a)))
16562}
16563#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16564#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"]
16565#[doc = "## Safety"]
16566#[doc = "  * Neon instrinsic unsafe"]
16567#[inline]
16568#[cfg(target_endian = "big")]
16569#[target_feature(enable = "neon,aes")]
16570#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16571#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16572#[cfg_attr(
16573    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16574    assert_instr(ld1)
16575)]
16576#[cfg_attr(
16577    not(target_arch = "arm"),
16578    stable(feature = "neon_intrinsics", since = "1.59.0")
16579)]
16580#[cfg_attr(
16581    target_arch = "arm",
16582    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16583)]
16584pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
16585    let mut ret_val: poly64x2x3_t = transmute(vld1q_s64_x3(transmute(a)));
16586    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
16587    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
16588    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
16589    ret_val
16590}
16591#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16592#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"]
16593#[doc = "## Safety"]
16594#[doc = "  * Neon instrinsic unsafe"]
16595#[inline]
16596#[cfg(target_endian = "little")]
16597#[target_feature(enable = "neon,aes")]
16598#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16599#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16600#[cfg_attr(
16601    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16602    assert_instr(ld1)
16603)]
16604#[cfg_attr(
16605    not(target_arch = "arm"),
16606    stable(feature = "neon_intrinsics", since = "1.59.0")
16607)]
16608#[cfg_attr(
16609    target_arch = "arm",
16610    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16611)]
16612pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t {
16613    transmute(vld1q_s64_x4(transmute(a)))
16614}
16615#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16616#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"]
16617#[doc = "## Safety"]
16618#[doc = "  * Neon instrinsic unsafe"]
16619#[inline]
16620#[cfg(target_endian = "big")]
16621#[target_feature(enable = "neon,aes")]
16622#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16623#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16624#[cfg_attr(
16625    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16626    assert_instr(ld1)
16627)]
16628#[cfg_attr(
16629    not(target_arch = "arm"),
16630    stable(feature = "neon_intrinsics", since = "1.59.0")
16631)]
16632#[cfg_attr(
16633    target_arch = "arm",
16634    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16635)]
16636pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t {
16637    let mut ret_val: poly64x2x4_t = transmute(vld1q_s64_x4(transmute(a)));
16638    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
16639    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
16640    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
16641    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
16642    ret_val
16643}
16644#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16645#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"]
16646#[doc = "## Safety"]
16647#[doc = "  * Neon instrinsic unsafe"]
16648#[inline]
16649#[cfg(target_arch = "arm")]
16650#[target_feature(enable = "neon,v7")]
16651#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16652#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
16653pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t {
16654    vld1_v8i8(ptr as *const i8, crate::mem::align_of::<i8>() as i32)
16655}
16656#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"]
16658#[doc = "## Safety"]
16659#[doc = "  * Neon instrinsic unsafe"]
16660#[inline]
16661#[cfg(target_arch = "arm")]
16662#[target_feature(enable = "neon,v7")]
16663#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16664#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
16665pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t {
16666    vld1q_v16i8(ptr as *const i8, crate::mem::align_of::<i8>() as i32)
16667}
16668#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16669#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"]
16670#[doc = "## Safety"]
16671#[doc = "  * Neon instrinsic unsafe"]
16672#[inline]
16673#[cfg(target_arch = "arm")]
16674#[target_feature(enable = "neon,v7")]
16675#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16676#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
16677pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t {
16678    vld1_v4i16(ptr as *const i8, crate::mem::align_of::<i16>() as i32)
16679}
16680#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16681#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"]
16682#[doc = "## Safety"]
16683#[doc = "  * Neon instrinsic unsafe"]
16684#[inline]
16685#[cfg(target_arch = "arm")]
16686#[target_feature(enable = "neon,v7")]
16687#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16688#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
16689pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t {
16690    vld1q_v8i16(ptr as *const i8, crate::mem::align_of::<i16>() as i32)
16691}
16692#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16693#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"]
16694#[doc = "## Safety"]
16695#[doc = "  * Neon instrinsic unsafe"]
16696#[inline]
16697#[cfg(target_arch = "arm")]
16698#[target_feature(enable = "neon,v7")]
16699#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16700#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
16701pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t {
16702    vld1_v2i32(ptr as *const i8, crate::mem::align_of::<i32>() as i32)
16703}
16704#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16705#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"]
16706#[doc = "## Safety"]
16707#[doc = "  * Neon instrinsic unsafe"]
16708#[inline]
16709#[cfg(target_arch = "arm")]
16710#[target_feature(enable = "neon,v7")]
16711#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16712#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
16713pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t {
16714    vld1q_v4i32(ptr as *const i8, crate::mem::align_of::<i32>() as i32)
16715}
16716#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16717#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"]
16718#[doc = "## Safety"]
16719#[doc = "  * Neon instrinsic unsafe"]
16720#[inline]
16721#[cfg(target_arch = "arm")]
16722#[target_feature(enable = "neon,v7")]
16723#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16724#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
16725pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t {
16726    vld1_v1i64(ptr as *const i8, crate::mem::align_of::<i64>() as i32)
16727}
16728#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16729#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"]
16730#[doc = "## Safety"]
16731#[doc = "  * Neon instrinsic unsafe"]
16732#[inline]
16733#[cfg(target_arch = "arm")]
16734#[target_feature(enable = "neon,v7")]
16735#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16736#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
16737pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t {
16738    vld1q_v2i64(ptr as *const i8, crate::mem::align_of::<i64>() as i32)
16739}
16740#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x2)"]
16742#[doc = "## Safety"]
16743#[doc = "  * Neon instrinsic unsafe"]
16744#[inline]
16745#[target_feature(enable = "neon")]
16746#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16747#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16748#[cfg_attr(
16749    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16750    assert_instr(ld1)
16751)]
16752#[cfg_attr(
16753    not(target_arch = "arm"),
16754    stable(feature = "neon_intrinsics", since = "1.59.0")
16755)]
16756#[cfg_attr(
16757    target_arch = "arm",
16758    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16759)]
16760pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t {
16761    unsafe extern "unadjusted" {
16762        #[cfg_attr(
16763            any(target_arch = "aarch64", target_arch = "arm64ec"),
16764            link_name = "llvm.aarch64.neon.ld1x2.v8i8.p0"
16765        )]
16766        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8i8.p0")]
16767        fn _vld1_s8_x2(a: *const i8) -> int8x8x2_t;
16768    }
16769    _vld1_s8_x2(a)
16770}
16771#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16772#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x3)"]
16773#[doc = "## Safety"]
16774#[doc = "  * Neon instrinsic unsafe"]
16775#[inline]
16776#[target_feature(enable = "neon")]
16777#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16778#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16779#[cfg_attr(
16780    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16781    assert_instr(ld1)
16782)]
16783#[cfg_attr(
16784    not(target_arch = "arm"),
16785    stable(feature = "neon_intrinsics", since = "1.59.0")
16786)]
16787#[cfg_attr(
16788    target_arch = "arm",
16789    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16790)]
16791pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t {
16792    unsafe extern "unadjusted" {
16793        #[cfg_attr(
16794            any(target_arch = "aarch64", target_arch = "arm64ec"),
16795            link_name = "llvm.aarch64.neon.ld1x3.v8i8.p0"
16796        )]
16797        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8i8.p0")]
16798        fn _vld1_s8_x3(a: *const i8) -> int8x8x3_t;
16799    }
16800    _vld1_s8_x3(a)
16801}
16802#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16803#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x4)"]
16804#[doc = "## Safety"]
16805#[doc = "  * Neon instrinsic unsafe"]
16806#[inline]
16807#[target_feature(enable = "neon")]
16808#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16809#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16810#[cfg_attr(
16811    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16812    assert_instr(ld1)
16813)]
16814#[cfg_attr(
16815    not(target_arch = "arm"),
16816    stable(feature = "neon_intrinsics", since = "1.59.0")
16817)]
16818#[cfg_attr(
16819    target_arch = "arm",
16820    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16821)]
16822pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t {
16823    unsafe extern "unadjusted" {
16824        #[cfg_attr(
16825            any(target_arch = "aarch64", target_arch = "arm64ec"),
16826            link_name = "llvm.aarch64.neon.ld1x4.v8i8.p0"
16827        )]
16828        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8i8.p0")]
16829        fn _vld1_s8_x4(a: *const i8) -> int8x8x4_t;
16830    }
16831    _vld1_s8_x4(a)
16832}
16833#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16834#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x2)"]
16835#[doc = "## Safety"]
16836#[doc = "  * Neon instrinsic unsafe"]
16837#[inline]
16838#[target_feature(enable = "neon")]
16839#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16840#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16841#[cfg_attr(
16842    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16843    assert_instr(ld1)
16844)]
16845#[cfg_attr(
16846    not(target_arch = "arm"),
16847    stable(feature = "neon_intrinsics", since = "1.59.0")
16848)]
16849#[cfg_attr(
16850    target_arch = "arm",
16851    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16852)]
16853pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t {
16854    unsafe extern "unadjusted" {
16855        #[cfg_attr(
16856            any(target_arch = "aarch64", target_arch = "arm64ec"),
16857            link_name = "llvm.aarch64.neon.ld1x2.v16i8.p0"
16858        )]
16859        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v16i8.p0")]
16860        fn _vld1q_s8_x2(a: *const i8) -> int8x16x2_t;
16861    }
16862    _vld1q_s8_x2(a)
16863}
16864#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16865#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x3)"]
16866#[doc = "## Safety"]
16867#[doc = "  * Neon instrinsic unsafe"]
16868#[inline]
16869#[target_feature(enable = "neon")]
16870#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16871#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16872#[cfg_attr(
16873    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16874    assert_instr(ld1)
16875)]
16876#[cfg_attr(
16877    not(target_arch = "arm"),
16878    stable(feature = "neon_intrinsics", since = "1.59.0")
16879)]
16880#[cfg_attr(
16881    target_arch = "arm",
16882    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16883)]
16884pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t {
16885    unsafe extern "unadjusted" {
16886        #[cfg_attr(
16887            any(target_arch = "aarch64", target_arch = "arm64ec"),
16888            link_name = "llvm.aarch64.neon.ld1x3.v16i8.p0"
16889        )]
16890        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v16i8.p0")]
16891        fn _vld1q_s8_x3(a: *const i8) -> int8x16x3_t;
16892    }
16893    _vld1q_s8_x3(a)
16894}
16895#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16896#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x4)"]
16897#[doc = "## Safety"]
16898#[doc = "  * Neon instrinsic unsafe"]
16899#[inline]
16900#[target_feature(enable = "neon")]
16901#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16902#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16903#[cfg_attr(
16904    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16905    assert_instr(ld1)
16906)]
16907#[cfg_attr(
16908    not(target_arch = "arm"),
16909    stable(feature = "neon_intrinsics", since = "1.59.0")
16910)]
16911#[cfg_attr(
16912    target_arch = "arm",
16913    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16914)]
16915pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t {
16916    unsafe extern "unadjusted" {
16917        #[cfg_attr(
16918            any(target_arch = "aarch64", target_arch = "arm64ec"),
16919            link_name = "llvm.aarch64.neon.ld1x4.v16i8.p0"
16920        )]
16921        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v16i8.p0")]
16922        fn _vld1q_s8_x4(a: *const i8) -> int8x16x4_t;
16923    }
16924    _vld1q_s8_x4(a)
16925}
16926#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x2)"]
16928#[doc = "## Safety"]
16929#[doc = "  * Neon instrinsic unsafe"]
16930#[inline]
16931#[target_feature(enable = "neon")]
16932#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16933#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16934#[cfg_attr(
16935    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16936    assert_instr(ld1)
16937)]
16938#[cfg_attr(
16939    not(target_arch = "arm"),
16940    stable(feature = "neon_intrinsics", since = "1.59.0")
16941)]
16942#[cfg_attr(
16943    target_arch = "arm",
16944    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16945)]
16946pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t {
16947    unsafe extern "unadjusted" {
16948        #[cfg_attr(
16949            any(target_arch = "aarch64", target_arch = "arm64ec"),
16950            link_name = "llvm.aarch64.neon.ld1x2.v4i16.p0"
16951        )]
16952        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4i16.p0")]
16953        fn _vld1_s16_x2(a: *const i16) -> int16x4x2_t;
16954    }
16955    _vld1_s16_x2(a)
16956}
16957#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16958#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x3)"]
16959#[doc = "## Safety"]
16960#[doc = "  * Neon instrinsic unsafe"]
16961#[inline]
16962#[target_feature(enable = "neon")]
16963#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16964#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16965#[cfg_attr(
16966    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16967    assert_instr(ld1)
16968)]
16969#[cfg_attr(
16970    not(target_arch = "arm"),
16971    stable(feature = "neon_intrinsics", since = "1.59.0")
16972)]
16973#[cfg_attr(
16974    target_arch = "arm",
16975    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16976)]
16977pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t {
16978    unsafe extern "unadjusted" {
16979        #[cfg_attr(
16980            any(target_arch = "aarch64", target_arch = "arm64ec"),
16981            link_name = "llvm.aarch64.neon.ld1x3.v4i16.p0"
16982        )]
16983        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4i16.p0")]
16984        fn _vld1_s16_x3(a: *const i16) -> int16x4x3_t;
16985    }
16986    _vld1_s16_x3(a)
16987}
16988#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16989#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x4)"]
16990#[doc = "## Safety"]
16991#[doc = "  * Neon instrinsic unsafe"]
16992#[inline]
16993#[target_feature(enable = "neon")]
16994#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16995#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16996#[cfg_attr(
16997    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16998    assert_instr(ld1)
16999)]
17000#[cfg_attr(
17001    not(target_arch = "arm"),
17002    stable(feature = "neon_intrinsics", since = "1.59.0")
17003)]
17004#[cfg_attr(
17005    target_arch = "arm",
17006    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17007)]
17008pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t {
17009    unsafe extern "unadjusted" {
17010        #[cfg_attr(
17011            any(target_arch = "aarch64", target_arch = "arm64ec"),
17012            link_name = "llvm.aarch64.neon.ld1x4.v4i16.p0"
17013        )]
17014        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4i16.p0")]
17015        fn _vld1_s16_x4(a: *const i16) -> int16x4x4_t;
17016    }
17017    _vld1_s16_x4(a)
17018}
17019#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17020#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x2)"]
17021#[doc = "## Safety"]
17022#[doc = "  * Neon instrinsic unsafe"]
17023#[inline]
17024#[target_feature(enable = "neon")]
17025#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17026#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17027#[cfg_attr(
17028    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17029    assert_instr(ld1)
17030)]
17031#[cfg_attr(
17032    not(target_arch = "arm"),
17033    stable(feature = "neon_intrinsics", since = "1.59.0")
17034)]
17035#[cfg_attr(
17036    target_arch = "arm",
17037    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17038)]
17039pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t {
17040    unsafe extern "unadjusted" {
17041        #[cfg_attr(
17042            any(target_arch = "aarch64", target_arch = "arm64ec"),
17043            link_name = "llvm.aarch64.neon.ld1x2.v8i16.p0"
17044        )]
17045        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8i16.p0")]
17046        fn _vld1q_s16_x2(a: *const i16) -> int16x8x2_t;
17047    }
17048    _vld1q_s16_x2(a)
17049}
17050#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17051#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x3)"]
17052#[doc = "## Safety"]
17053#[doc = "  * Neon instrinsic unsafe"]
17054#[inline]
17055#[target_feature(enable = "neon")]
17056#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17057#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17058#[cfg_attr(
17059    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17060    assert_instr(ld1)
17061)]
17062#[cfg_attr(
17063    not(target_arch = "arm"),
17064    stable(feature = "neon_intrinsics", since = "1.59.0")
17065)]
17066#[cfg_attr(
17067    target_arch = "arm",
17068    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17069)]
17070pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t {
17071    unsafe extern "unadjusted" {
17072        #[cfg_attr(
17073            any(target_arch = "aarch64", target_arch = "arm64ec"),
17074            link_name = "llvm.aarch64.neon.ld1x3.v8i16.p0"
17075        )]
17076        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8i16.p0")]
17077        fn _vld1q_s16_x3(a: *const i16) -> int16x8x3_t;
17078    }
17079    _vld1q_s16_x3(a)
17080}
17081#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17082#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x4)"]
17083#[doc = "## Safety"]
17084#[doc = "  * Neon instrinsic unsafe"]
17085#[inline]
17086#[target_feature(enable = "neon")]
17087#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17088#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17089#[cfg_attr(
17090    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17091    assert_instr(ld1)
17092)]
17093#[cfg_attr(
17094    not(target_arch = "arm"),
17095    stable(feature = "neon_intrinsics", since = "1.59.0")
17096)]
17097#[cfg_attr(
17098    target_arch = "arm",
17099    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17100)]
17101pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t {
17102    unsafe extern "unadjusted" {
17103        #[cfg_attr(
17104            any(target_arch = "aarch64", target_arch = "arm64ec"),
17105            link_name = "llvm.aarch64.neon.ld1x4.v8i16.p0"
17106        )]
17107        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8i16.p0")]
17108        fn _vld1q_s16_x4(a: *const i16) -> int16x8x4_t;
17109    }
17110    _vld1q_s16_x4(a)
17111}
17112#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17113#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x2)"]
17114#[doc = "## Safety"]
17115#[doc = "  * Neon instrinsic unsafe"]
17116#[inline]
17117#[target_feature(enable = "neon")]
17118#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17119#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17120#[cfg_attr(
17121    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17122    assert_instr(ld1)
17123)]
17124#[cfg_attr(
17125    not(target_arch = "arm"),
17126    stable(feature = "neon_intrinsics", since = "1.59.0")
17127)]
17128#[cfg_attr(
17129    target_arch = "arm",
17130    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17131)]
17132pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t {
17133    unsafe extern "unadjusted" {
17134        #[cfg_attr(
17135            any(target_arch = "aarch64", target_arch = "arm64ec"),
17136            link_name = "llvm.aarch64.neon.ld1x2.v2i32.p0"
17137        )]
17138        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2i32.p0")]
17139        fn _vld1_s32_x2(a: *const i32) -> int32x2x2_t;
17140    }
17141    _vld1_s32_x2(a)
17142}
17143#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17144#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x3)"]
17145#[doc = "## Safety"]
17146#[doc = "  * Neon instrinsic unsafe"]
17147#[inline]
17148#[target_feature(enable = "neon")]
17149#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17150#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17151#[cfg_attr(
17152    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17153    assert_instr(ld1)
17154)]
17155#[cfg_attr(
17156    not(target_arch = "arm"),
17157    stable(feature = "neon_intrinsics", since = "1.59.0")
17158)]
17159#[cfg_attr(
17160    target_arch = "arm",
17161    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17162)]
17163pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t {
17164    unsafe extern "unadjusted" {
17165        #[cfg_attr(
17166            any(target_arch = "aarch64", target_arch = "arm64ec"),
17167            link_name = "llvm.aarch64.neon.ld1x3.v2i32.p0"
17168        )]
17169        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2i32.p0")]
17170        fn _vld1_s32_x3(a: *const i32) -> int32x2x3_t;
17171    }
17172    _vld1_s32_x3(a)
17173}
17174#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17175#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x4)"]
17176#[doc = "## Safety"]
17177#[doc = "  * Neon instrinsic unsafe"]
17178#[inline]
17179#[target_feature(enable = "neon")]
17180#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17181#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17182#[cfg_attr(
17183    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17184    assert_instr(ld1)
17185)]
17186#[cfg_attr(
17187    not(target_arch = "arm"),
17188    stable(feature = "neon_intrinsics", since = "1.59.0")
17189)]
17190#[cfg_attr(
17191    target_arch = "arm",
17192    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17193)]
17194pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t {
17195    unsafe extern "unadjusted" {
17196        #[cfg_attr(
17197            any(target_arch = "aarch64", target_arch = "arm64ec"),
17198            link_name = "llvm.aarch64.neon.ld1x4.v2i32.p0"
17199        )]
17200        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2i32.p0")]
17201        fn _vld1_s32_x4(a: *const i32) -> int32x2x4_t;
17202    }
17203    _vld1_s32_x4(a)
17204}
17205#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17206#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x2)"]
17207#[doc = "## Safety"]
17208#[doc = "  * Neon instrinsic unsafe"]
17209#[inline]
17210#[target_feature(enable = "neon")]
17211#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17212#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17213#[cfg_attr(
17214    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17215    assert_instr(ld1)
17216)]
17217#[cfg_attr(
17218    not(target_arch = "arm"),
17219    stable(feature = "neon_intrinsics", since = "1.59.0")
17220)]
17221#[cfg_attr(
17222    target_arch = "arm",
17223    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17224)]
17225pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t {
17226    unsafe extern "unadjusted" {
17227        #[cfg_attr(
17228            any(target_arch = "aarch64", target_arch = "arm64ec"),
17229            link_name = "llvm.aarch64.neon.ld1x2.v4i32.p0"
17230        )]
17231        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4i32.p0")]
17232        fn _vld1q_s32_x2(a: *const i32) -> int32x4x2_t;
17233    }
17234    _vld1q_s32_x2(a)
17235}
17236#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17237#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x3)"]
17238#[doc = "## Safety"]
17239#[doc = "  * Neon instrinsic unsafe"]
17240#[inline]
17241#[target_feature(enable = "neon")]
17242#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17243#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17244#[cfg_attr(
17245    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17246    assert_instr(ld1)
17247)]
17248#[cfg_attr(
17249    not(target_arch = "arm"),
17250    stable(feature = "neon_intrinsics", since = "1.59.0")
17251)]
17252#[cfg_attr(
17253    target_arch = "arm",
17254    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17255)]
17256pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t {
17257    unsafe extern "unadjusted" {
17258        #[cfg_attr(
17259            any(target_arch = "aarch64", target_arch = "arm64ec"),
17260            link_name = "llvm.aarch64.neon.ld1x3.v4i32.p0"
17261        )]
17262        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4i32.p0")]
17263        fn _vld1q_s32_x3(a: *const i32) -> int32x4x3_t;
17264    }
17265    _vld1q_s32_x3(a)
17266}
17267#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17268#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x4)"]
17269#[doc = "## Safety"]
17270#[doc = "  * Neon instrinsic unsafe"]
17271#[inline]
17272#[target_feature(enable = "neon")]
17273#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17274#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17275#[cfg_attr(
17276    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17277    assert_instr(ld1)
17278)]
17279#[cfg_attr(
17280    not(target_arch = "arm"),
17281    stable(feature = "neon_intrinsics", since = "1.59.0")
17282)]
17283#[cfg_attr(
17284    target_arch = "arm",
17285    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17286)]
17287pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t {
17288    unsafe extern "unadjusted" {
17289        #[cfg_attr(
17290            any(target_arch = "aarch64", target_arch = "arm64ec"),
17291            link_name = "llvm.aarch64.neon.ld1x4.v4i32.p0"
17292        )]
17293        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4i32.p0")]
17294        fn _vld1q_s32_x4(a: *const i32) -> int32x4x4_t;
17295    }
17296    _vld1q_s32_x4(a)
17297}
17298#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x2)"]
17300#[doc = "## Safety"]
17301#[doc = "  * Neon instrinsic unsafe"]
17302#[inline]
17303#[target_feature(enable = "neon")]
17304#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17305#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17306#[cfg_attr(
17307    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17308    assert_instr(ld1)
17309)]
17310#[cfg_attr(
17311    not(target_arch = "arm"),
17312    stable(feature = "neon_intrinsics", since = "1.59.0")
17313)]
17314#[cfg_attr(
17315    target_arch = "arm",
17316    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17317)]
17318pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t {
17319    unsafe extern "unadjusted" {
17320        #[cfg_attr(
17321            any(target_arch = "aarch64", target_arch = "arm64ec"),
17322            link_name = "llvm.aarch64.neon.ld1x2.v1i64.p0"
17323        )]
17324        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v1i64.p0")]
17325        fn _vld1_s64_x2(a: *const i64) -> int64x1x2_t;
17326    }
17327    _vld1_s64_x2(a)
17328}
17329#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17330#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x3)"]
17331#[doc = "## Safety"]
17332#[doc = "  * Neon instrinsic unsafe"]
17333#[inline]
17334#[target_feature(enable = "neon")]
17335#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17336#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17337#[cfg_attr(
17338    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17339    assert_instr(ld1)
17340)]
17341#[cfg_attr(
17342    not(target_arch = "arm"),
17343    stable(feature = "neon_intrinsics", since = "1.59.0")
17344)]
17345#[cfg_attr(
17346    target_arch = "arm",
17347    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17348)]
17349pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t {
17350    unsafe extern "unadjusted" {
17351        #[cfg_attr(
17352            any(target_arch = "aarch64", target_arch = "arm64ec"),
17353            link_name = "llvm.aarch64.neon.ld1x3.v1i64.p0"
17354        )]
17355        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v1i64.p0")]
17356        fn _vld1_s64_x3(a: *const i64) -> int64x1x3_t;
17357    }
17358    _vld1_s64_x3(a)
17359}
17360#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17361#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x4)"]
17362#[doc = "## Safety"]
17363#[doc = "  * Neon instrinsic unsafe"]
17364#[inline]
17365#[target_feature(enable = "neon")]
17366#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17367#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17368#[cfg_attr(
17369    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17370    assert_instr(ld1)
17371)]
17372#[cfg_attr(
17373    not(target_arch = "arm"),
17374    stable(feature = "neon_intrinsics", since = "1.59.0")
17375)]
17376#[cfg_attr(
17377    target_arch = "arm",
17378    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17379)]
17380pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t {
17381    unsafe extern "unadjusted" {
17382        #[cfg_attr(
17383            any(target_arch = "aarch64", target_arch = "arm64ec"),
17384            link_name = "llvm.aarch64.neon.ld1x4.v1i64.p0"
17385        )]
17386        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v1i64.p0")]
17387        fn _vld1_s64_x4(a: *const i64) -> int64x1x4_t;
17388    }
17389    _vld1_s64_x4(a)
17390}
17391#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x2)"]
17393#[doc = "## Safety"]
17394#[doc = "  * Neon instrinsic unsafe"]
17395#[inline]
17396#[target_feature(enable = "neon")]
17397#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17398#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17399#[cfg_attr(
17400    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17401    assert_instr(ld1)
17402)]
17403#[cfg_attr(
17404    not(target_arch = "arm"),
17405    stable(feature = "neon_intrinsics", since = "1.59.0")
17406)]
17407#[cfg_attr(
17408    target_arch = "arm",
17409    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17410)]
17411pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t {
17412    unsafe extern "unadjusted" {
17413        #[cfg_attr(
17414            any(target_arch = "aarch64", target_arch = "arm64ec"),
17415            link_name = "llvm.aarch64.neon.ld1x2.v2i64.p0"
17416        )]
17417        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2i64.p0")]
17418        fn _vld1q_s64_x2(a: *const i64) -> int64x2x2_t;
17419    }
17420    _vld1q_s64_x2(a)
17421}
17422#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17423#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x3)"]
17424#[doc = "## Safety"]
17425#[doc = "  * Neon instrinsic unsafe"]
17426#[inline]
17427#[target_feature(enable = "neon")]
17428#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17429#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17430#[cfg_attr(
17431    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17432    assert_instr(ld1)
17433)]
17434#[cfg_attr(
17435    not(target_arch = "arm"),
17436    stable(feature = "neon_intrinsics", since = "1.59.0")
17437)]
17438#[cfg_attr(
17439    target_arch = "arm",
17440    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17441)]
17442pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t {
17443    unsafe extern "unadjusted" {
17444        #[cfg_attr(
17445            any(target_arch = "aarch64", target_arch = "arm64ec"),
17446            link_name = "llvm.aarch64.neon.ld1x3.v2i64.p0"
17447        )]
17448        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2i64.p0")]
17449        fn _vld1q_s64_x3(a: *const i64) -> int64x2x3_t;
17450    }
17451    _vld1q_s64_x3(a)
17452}
17453#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17454#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x4)"]
17455#[doc = "## Safety"]
17456#[doc = "  * Neon instrinsic unsafe"]
17457#[inline]
17458#[target_feature(enable = "neon")]
17459#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17460#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17461#[cfg_attr(
17462    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17463    assert_instr(ld1)
17464)]
17465#[cfg_attr(
17466    not(target_arch = "arm"),
17467    stable(feature = "neon_intrinsics", since = "1.59.0")
17468)]
17469#[cfg_attr(
17470    target_arch = "arm",
17471    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17472)]
17473pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t {
17474    unsafe extern "unadjusted" {
17475        #[cfg_attr(
17476            any(target_arch = "aarch64", target_arch = "arm64ec"),
17477            link_name = "llvm.aarch64.neon.ld1x4.v2i64.p0"
17478        )]
17479        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2i64.p0")]
17480        fn _vld1q_s64_x4(a: *const i64) -> int64x2x4_t;
17481    }
17482    _vld1q_s64_x4(a)
17483}
17484#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17485#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"]
17486#[doc = "## Safety"]
17487#[doc = "  * Neon instrinsic unsafe"]
17488#[inline]
17489#[cfg(target_endian = "little")]
17490#[target_feature(enable = "neon")]
17491#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17492#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17493#[cfg_attr(
17494    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17495    assert_instr(ld1)
17496)]
17497#[cfg_attr(
17498    not(target_arch = "arm"),
17499    stable(feature = "neon_intrinsics", since = "1.59.0")
17500)]
17501#[cfg_attr(
17502    target_arch = "arm",
17503    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17504)]
17505pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
17506    transmute(vld1_s8_x2(transmute(a)))
17507}
17508#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17509#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"]
17510#[doc = "## Safety"]
17511#[doc = "  * Neon instrinsic unsafe"]
17512#[inline]
17513#[cfg(target_endian = "big")]
17514#[target_feature(enable = "neon")]
17515#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17516#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17517#[cfg_attr(
17518    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17519    assert_instr(ld1)
17520)]
17521#[cfg_attr(
17522    not(target_arch = "arm"),
17523    stable(feature = "neon_intrinsics", since = "1.59.0")
17524)]
17525#[cfg_attr(
17526    target_arch = "arm",
17527    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17528)]
17529pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
17530    let mut ret_val: uint8x8x2_t = transmute(vld1_s8_x2(transmute(a)));
17531    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
17532    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
17533    ret_val
17534}
17535#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17536#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"]
17537#[doc = "## Safety"]
17538#[doc = "  * Neon instrinsic unsafe"]
17539#[inline]
17540#[cfg(target_endian = "little")]
17541#[target_feature(enable = "neon")]
17542#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17543#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17544#[cfg_attr(
17545    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17546    assert_instr(ld1)
17547)]
17548#[cfg_attr(
17549    not(target_arch = "arm"),
17550    stable(feature = "neon_intrinsics", since = "1.59.0")
17551)]
17552#[cfg_attr(
17553    target_arch = "arm",
17554    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17555)]
17556pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
17557    transmute(vld1_s8_x3(transmute(a)))
17558}
17559#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17560#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"]
17561#[doc = "## Safety"]
17562#[doc = "  * Neon instrinsic unsafe"]
17563#[inline]
17564#[cfg(target_endian = "big")]
17565#[target_feature(enable = "neon")]
17566#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17567#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17568#[cfg_attr(
17569    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17570    assert_instr(ld1)
17571)]
17572#[cfg_attr(
17573    not(target_arch = "arm"),
17574    stable(feature = "neon_intrinsics", since = "1.59.0")
17575)]
17576#[cfg_attr(
17577    target_arch = "arm",
17578    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17579)]
17580pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
17581    let mut ret_val: uint8x8x3_t = transmute(vld1_s8_x3(transmute(a)));
17582    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
17583    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
17584    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
17585    ret_val
17586}
17587#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17588#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"]
17589#[doc = "## Safety"]
17590#[doc = "  * Neon instrinsic unsafe"]
17591#[inline]
17592#[cfg(target_endian = "little")]
17593#[target_feature(enable = "neon")]
17594#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17595#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17596#[cfg_attr(
17597    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17598    assert_instr(ld1)
17599)]
17600#[cfg_attr(
17601    not(target_arch = "arm"),
17602    stable(feature = "neon_intrinsics", since = "1.59.0")
17603)]
17604#[cfg_attr(
17605    target_arch = "arm",
17606    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17607)]
17608pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
17609    transmute(vld1_s8_x4(transmute(a)))
17610}
17611#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17612#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"]
17613#[doc = "## Safety"]
17614#[doc = "  * Neon instrinsic unsafe"]
17615#[inline]
17616#[cfg(target_endian = "big")]
17617#[target_feature(enable = "neon")]
17618#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17619#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17620#[cfg_attr(
17621    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17622    assert_instr(ld1)
17623)]
17624#[cfg_attr(
17625    not(target_arch = "arm"),
17626    stable(feature = "neon_intrinsics", since = "1.59.0")
17627)]
17628#[cfg_attr(
17629    target_arch = "arm",
17630    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17631)]
17632pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
17633    let mut ret_val: uint8x8x4_t = transmute(vld1_s8_x4(transmute(a)));
17634    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
17635    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
17636    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
17637    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
17638    ret_val
17639}
17640#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17641#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"]
17642#[doc = "## Safety"]
17643#[doc = "  * Neon instrinsic unsafe"]
17644#[inline]
17645#[cfg(target_endian = "little")]
17646#[target_feature(enable = "neon")]
17647#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17648#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17649#[cfg_attr(
17650    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17651    assert_instr(ld1)
17652)]
17653#[cfg_attr(
17654    not(target_arch = "arm"),
17655    stable(feature = "neon_intrinsics", since = "1.59.0")
17656)]
17657#[cfg_attr(
17658    target_arch = "arm",
17659    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17660)]
17661pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
17662    transmute(vld1q_s8_x2(transmute(a)))
17663}
17664#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"]
17666#[doc = "## Safety"]
17667#[doc = "  * Neon instrinsic unsafe"]
17668#[inline]
17669#[cfg(target_endian = "big")]
17670#[target_feature(enable = "neon")]
17671#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17672#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17673#[cfg_attr(
17674    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17675    assert_instr(ld1)
17676)]
17677#[cfg_attr(
17678    not(target_arch = "arm"),
17679    stable(feature = "neon_intrinsics", since = "1.59.0")
17680)]
17681#[cfg_attr(
17682    target_arch = "arm",
17683    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17684)]
17685pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
17686    let mut ret_val: uint8x16x2_t = transmute(vld1q_s8_x2(transmute(a)));
17687    ret_val.0 = unsafe {
17688        simd_shuffle!(
17689            ret_val.0,
17690            ret_val.0,
17691            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17692        )
17693    };
17694    ret_val.1 = unsafe {
17695        simd_shuffle!(
17696            ret_val.1,
17697            ret_val.1,
17698            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17699        )
17700    };
17701    ret_val
17702}
17703#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17704#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"]
17705#[doc = "## Safety"]
17706#[doc = "  * Neon instrinsic unsafe"]
17707#[inline]
17708#[cfg(target_endian = "little")]
17709#[target_feature(enable = "neon")]
17710#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17711#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17712#[cfg_attr(
17713    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17714    assert_instr(ld1)
17715)]
17716#[cfg_attr(
17717    not(target_arch = "arm"),
17718    stable(feature = "neon_intrinsics", since = "1.59.0")
17719)]
17720#[cfg_attr(
17721    target_arch = "arm",
17722    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17723)]
17724pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
17725    transmute(vld1q_s8_x3(transmute(a)))
17726}
17727#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17728#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"]
17729#[doc = "## Safety"]
17730#[doc = "  * Neon instrinsic unsafe"]
17731#[inline]
17732#[cfg(target_endian = "big")]
17733#[target_feature(enable = "neon")]
17734#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17735#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17736#[cfg_attr(
17737    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17738    assert_instr(ld1)
17739)]
17740#[cfg_attr(
17741    not(target_arch = "arm"),
17742    stable(feature = "neon_intrinsics", since = "1.59.0")
17743)]
17744#[cfg_attr(
17745    target_arch = "arm",
17746    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17747)]
17748pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
17749    let mut ret_val: uint8x16x3_t = transmute(vld1q_s8_x3(transmute(a)));
17750    ret_val.0 = unsafe {
17751        simd_shuffle!(
17752            ret_val.0,
17753            ret_val.0,
17754            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17755        )
17756    };
17757    ret_val.1 = unsafe {
17758        simd_shuffle!(
17759            ret_val.1,
17760            ret_val.1,
17761            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17762        )
17763    };
17764    ret_val.2 = unsafe {
17765        simd_shuffle!(
17766            ret_val.2,
17767            ret_val.2,
17768            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17769        )
17770    };
17771    ret_val
17772}
17773#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"]
17775#[doc = "## Safety"]
17776#[doc = "  * Neon instrinsic unsafe"]
17777#[inline]
17778#[cfg(target_endian = "little")]
17779#[target_feature(enable = "neon")]
17780#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17781#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17782#[cfg_attr(
17783    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17784    assert_instr(ld1)
17785)]
17786#[cfg_attr(
17787    not(target_arch = "arm"),
17788    stable(feature = "neon_intrinsics", since = "1.59.0")
17789)]
17790#[cfg_attr(
17791    target_arch = "arm",
17792    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17793)]
17794pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
17795    transmute(vld1q_s8_x4(transmute(a)))
17796}
17797#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"]
17799#[doc = "## Safety"]
17800#[doc = "  * Neon instrinsic unsafe"]
17801#[inline]
17802#[cfg(target_endian = "big")]
17803#[target_feature(enable = "neon")]
17804#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17805#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17806#[cfg_attr(
17807    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17808    assert_instr(ld1)
17809)]
17810#[cfg_attr(
17811    not(target_arch = "arm"),
17812    stable(feature = "neon_intrinsics", since = "1.59.0")
17813)]
17814#[cfg_attr(
17815    target_arch = "arm",
17816    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17817)]
17818pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
17819    let mut ret_val: uint8x16x4_t = transmute(vld1q_s8_x4(transmute(a)));
17820    ret_val.0 = unsafe {
17821        simd_shuffle!(
17822            ret_val.0,
17823            ret_val.0,
17824            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17825        )
17826    };
17827    ret_val.1 = unsafe {
17828        simd_shuffle!(
17829            ret_val.1,
17830            ret_val.1,
17831            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17832        )
17833    };
17834    ret_val.2 = unsafe {
17835        simd_shuffle!(
17836            ret_val.2,
17837            ret_val.2,
17838            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17839        )
17840    };
17841    ret_val.3 = unsafe {
17842        simd_shuffle!(
17843            ret_val.3,
17844            ret_val.3,
17845            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17846        )
17847    };
17848    ret_val
17849}
17850#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17851#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"]
17852#[doc = "## Safety"]
17853#[doc = "  * Neon instrinsic unsafe"]
17854#[inline]
17855#[cfg(target_endian = "little")]
17856#[target_feature(enable = "neon")]
17857#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17858#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17859#[cfg_attr(
17860    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17861    assert_instr(ld1)
17862)]
17863#[cfg_attr(
17864    not(target_arch = "arm"),
17865    stable(feature = "neon_intrinsics", since = "1.59.0")
17866)]
17867#[cfg_attr(
17868    target_arch = "arm",
17869    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17870)]
17871pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
17872    transmute(vld1_s16_x2(transmute(a)))
17873}
17874#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17875#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"]
17876#[doc = "## Safety"]
17877#[doc = "  * Neon instrinsic unsafe"]
17878#[inline]
17879#[cfg(target_endian = "big")]
17880#[target_feature(enable = "neon")]
17881#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17882#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17883#[cfg_attr(
17884    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17885    assert_instr(ld1)
17886)]
17887#[cfg_attr(
17888    not(target_arch = "arm"),
17889    stable(feature = "neon_intrinsics", since = "1.59.0")
17890)]
17891#[cfg_attr(
17892    target_arch = "arm",
17893    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17894)]
17895pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
17896    let mut ret_val: uint16x4x2_t = transmute(vld1_s16_x2(transmute(a)));
17897    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
17898    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
17899    ret_val
17900}
17901#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17902#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"]
17903#[doc = "## Safety"]
17904#[doc = "  * Neon instrinsic unsafe"]
17905#[inline]
17906#[cfg(target_endian = "little")]
17907#[target_feature(enable = "neon")]
17908#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17909#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17910#[cfg_attr(
17911    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17912    assert_instr(ld1)
17913)]
17914#[cfg_attr(
17915    not(target_arch = "arm"),
17916    stable(feature = "neon_intrinsics", since = "1.59.0")
17917)]
17918#[cfg_attr(
17919    target_arch = "arm",
17920    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17921)]
17922pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
17923    transmute(vld1_s16_x3(transmute(a)))
17924}
17925#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17926#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"]
17927#[doc = "## Safety"]
17928#[doc = "  * Neon instrinsic unsafe"]
17929#[inline]
17930#[cfg(target_endian = "big")]
17931#[target_feature(enable = "neon")]
17932#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17933#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17934#[cfg_attr(
17935    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17936    assert_instr(ld1)
17937)]
17938#[cfg_attr(
17939    not(target_arch = "arm"),
17940    stable(feature = "neon_intrinsics", since = "1.59.0")
17941)]
17942#[cfg_attr(
17943    target_arch = "arm",
17944    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17945)]
17946pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
17947    let mut ret_val: uint16x4x3_t = transmute(vld1_s16_x3(transmute(a)));
17948    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
17949    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
17950    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
17951    ret_val
17952}
17953#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17954#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"]
17955#[doc = "## Safety"]
17956#[doc = "  * Neon instrinsic unsafe"]
17957#[inline]
17958#[cfg(target_endian = "little")]
17959#[target_feature(enable = "neon")]
17960#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17961#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17962#[cfg_attr(
17963    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17964    assert_instr(ld1)
17965)]
17966#[cfg_attr(
17967    not(target_arch = "arm"),
17968    stable(feature = "neon_intrinsics", since = "1.59.0")
17969)]
17970#[cfg_attr(
17971    target_arch = "arm",
17972    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17973)]
17974pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
17975    transmute(vld1_s16_x4(transmute(a)))
17976}
17977#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17978#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"]
17979#[doc = "## Safety"]
17980#[doc = "  * Neon instrinsic unsafe"]
17981#[inline]
17982#[cfg(target_endian = "big")]
17983#[target_feature(enable = "neon")]
17984#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17985#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17986#[cfg_attr(
17987    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17988    assert_instr(ld1)
17989)]
17990#[cfg_attr(
17991    not(target_arch = "arm"),
17992    stable(feature = "neon_intrinsics", since = "1.59.0")
17993)]
17994#[cfg_attr(
17995    target_arch = "arm",
17996    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17997)]
17998pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
17999    let mut ret_val: uint16x4x4_t = transmute(vld1_s16_x4(transmute(a)));
18000    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
18001    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
18002    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
18003    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
18004    ret_val
18005}
18006#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"]
18008#[doc = "## Safety"]
18009#[doc = "  * Neon instrinsic unsafe"]
18010#[inline]
18011#[cfg(target_endian = "little")]
18012#[target_feature(enable = "neon")]
18013#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18014#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18015#[cfg_attr(
18016    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18017    assert_instr(ld1)
18018)]
18019#[cfg_attr(
18020    not(target_arch = "arm"),
18021    stable(feature = "neon_intrinsics", since = "1.59.0")
18022)]
18023#[cfg_attr(
18024    target_arch = "arm",
18025    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18026)]
18027pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
18028    transmute(vld1q_s16_x2(transmute(a)))
18029}
18030#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18031#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"]
18032#[doc = "## Safety"]
18033#[doc = "  * Neon instrinsic unsafe"]
18034#[inline]
18035#[cfg(target_endian = "big")]
18036#[target_feature(enable = "neon")]
18037#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18038#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18039#[cfg_attr(
18040    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18041    assert_instr(ld1)
18042)]
18043#[cfg_attr(
18044    not(target_arch = "arm"),
18045    stable(feature = "neon_intrinsics", since = "1.59.0")
18046)]
18047#[cfg_attr(
18048    target_arch = "arm",
18049    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18050)]
18051pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
18052    let mut ret_val: uint16x8x2_t = transmute(vld1q_s16_x2(transmute(a)));
18053    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18054    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18055    ret_val
18056}
18057#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18058#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"]
18059#[doc = "## Safety"]
18060#[doc = "  * Neon instrinsic unsafe"]
18061#[inline]
18062#[cfg(target_endian = "little")]
18063#[target_feature(enable = "neon")]
18064#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18065#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18066#[cfg_attr(
18067    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18068    assert_instr(ld1)
18069)]
18070#[cfg_attr(
18071    not(target_arch = "arm"),
18072    stable(feature = "neon_intrinsics", since = "1.59.0")
18073)]
18074#[cfg_attr(
18075    target_arch = "arm",
18076    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18077)]
18078pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
18079    transmute(vld1q_s16_x3(transmute(a)))
18080}
18081#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18082#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"]
18083#[doc = "## Safety"]
18084#[doc = "  * Neon instrinsic unsafe"]
18085#[inline]
18086#[cfg(target_endian = "big")]
18087#[target_feature(enable = "neon")]
18088#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18089#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18090#[cfg_attr(
18091    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18092    assert_instr(ld1)
18093)]
18094#[cfg_attr(
18095    not(target_arch = "arm"),
18096    stable(feature = "neon_intrinsics", since = "1.59.0")
18097)]
18098#[cfg_attr(
18099    target_arch = "arm",
18100    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18101)]
18102pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
18103    let mut ret_val: uint16x8x3_t = transmute(vld1q_s16_x3(transmute(a)));
18104    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18105    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18106    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
18107    ret_val
18108}
18109#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18110#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"]
18111#[doc = "## Safety"]
18112#[doc = "  * Neon instrinsic unsafe"]
18113#[inline]
18114#[cfg(target_endian = "little")]
18115#[target_feature(enable = "neon")]
18116#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18117#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18118#[cfg_attr(
18119    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18120    assert_instr(ld1)
18121)]
18122#[cfg_attr(
18123    not(target_arch = "arm"),
18124    stable(feature = "neon_intrinsics", since = "1.59.0")
18125)]
18126#[cfg_attr(
18127    target_arch = "arm",
18128    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18129)]
18130pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
18131    transmute(vld1q_s16_x4(transmute(a)))
18132}
18133#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18134#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"]
18135#[doc = "## Safety"]
18136#[doc = "  * Neon instrinsic unsafe"]
18137#[inline]
18138#[cfg(target_endian = "big")]
18139#[target_feature(enable = "neon")]
18140#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18141#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18142#[cfg_attr(
18143    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18144    assert_instr(ld1)
18145)]
18146#[cfg_attr(
18147    not(target_arch = "arm"),
18148    stable(feature = "neon_intrinsics", since = "1.59.0")
18149)]
18150#[cfg_attr(
18151    target_arch = "arm",
18152    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18153)]
18154pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
18155    let mut ret_val: uint16x8x4_t = transmute(vld1q_s16_x4(transmute(a)));
18156    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18157    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18158    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
18159    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
18160    ret_val
18161}
18162#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18163#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"]
18164#[doc = "## Safety"]
18165#[doc = "  * Neon instrinsic unsafe"]
18166#[inline]
18167#[cfg(target_endian = "little")]
18168#[target_feature(enable = "neon")]
18169#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18170#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18171#[cfg_attr(
18172    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18173    assert_instr(ld1)
18174)]
18175#[cfg_attr(
18176    not(target_arch = "arm"),
18177    stable(feature = "neon_intrinsics", since = "1.59.0")
18178)]
18179#[cfg_attr(
18180    target_arch = "arm",
18181    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18182)]
18183pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
18184    transmute(vld1_s32_x2(transmute(a)))
18185}
18186#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18187#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"]
18188#[doc = "## Safety"]
18189#[doc = "  * Neon instrinsic unsafe"]
18190#[inline]
18191#[cfg(target_endian = "big")]
18192#[target_feature(enable = "neon")]
18193#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18194#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18195#[cfg_attr(
18196    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18197    assert_instr(ld1)
18198)]
18199#[cfg_attr(
18200    not(target_arch = "arm"),
18201    stable(feature = "neon_intrinsics", since = "1.59.0")
18202)]
18203#[cfg_attr(
18204    target_arch = "arm",
18205    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18206)]
18207pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
18208    let mut ret_val: uint32x2x2_t = transmute(vld1_s32_x2(transmute(a)));
18209    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18210    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18211    ret_val
18212}
18213#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18214#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"]
18215#[doc = "## Safety"]
18216#[doc = "  * Neon instrinsic unsafe"]
18217#[inline]
18218#[cfg(target_endian = "little")]
18219#[target_feature(enable = "neon")]
18220#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18221#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18222#[cfg_attr(
18223    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18224    assert_instr(ld1)
18225)]
18226#[cfg_attr(
18227    not(target_arch = "arm"),
18228    stable(feature = "neon_intrinsics", since = "1.59.0")
18229)]
18230#[cfg_attr(
18231    target_arch = "arm",
18232    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18233)]
18234pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
18235    transmute(vld1_s32_x3(transmute(a)))
18236}
18237#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"]
18239#[doc = "## Safety"]
18240#[doc = "  * Neon instrinsic unsafe"]
18241#[inline]
18242#[cfg(target_endian = "big")]
18243#[target_feature(enable = "neon")]
18244#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18245#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18246#[cfg_attr(
18247    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18248    assert_instr(ld1)
18249)]
18250#[cfg_attr(
18251    not(target_arch = "arm"),
18252    stable(feature = "neon_intrinsics", since = "1.59.0")
18253)]
18254#[cfg_attr(
18255    target_arch = "arm",
18256    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18257)]
18258pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
18259    let mut ret_val: uint32x2x3_t = transmute(vld1_s32_x3(transmute(a)));
18260    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18261    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18262    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
18263    ret_val
18264}
18265#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18266#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"]
18267#[doc = "## Safety"]
18268#[doc = "  * Neon instrinsic unsafe"]
18269#[inline]
18270#[cfg(target_endian = "little")]
18271#[target_feature(enable = "neon")]
18272#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18273#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18274#[cfg_attr(
18275    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18276    assert_instr(ld1)
18277)]
18278#[cfg_attr(
18279    not(target_arch = "arm"),
18280    stable(feature = "neon_intrinsics", since = "1.59.0")
18281)]
18282#[cfg_attr(
18283    target_arch = "arm",
18284    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18285)]
18286pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
18287    transmute(vld1_s32_x4(transmute(a)))
18288}
18289#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18290#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"]
18291#[doc = "## Safety"]
18292#[doc = "  * Neon instrinsic unsafe"]
18293#[inline]
18294#[cfg(target_endian = "big")]
18295#[target_feature(enable = "neon")]
18296#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18297#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18298#[cfg_attr(
18299    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18300    assert_instr(ld1)
18301)]
18302#[cfg_attr(
18303    not(target_arch = "arm"),
18304    stable(feature = "neon_intrinsics", since = "1.59.0")
18305)]
18306#[cfg_attr(
18307    target_arch = "arm",
18308    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18309)]
18310pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
18311    let mut ret_val: uint32x2x4_t = transmute(vld1_s32_x4(transmute(a)));
18312    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18313    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18314    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
18315    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
18316    ret_val
18317}
18318#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18319#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"]
18320#[doc = "## Safety"]
18321#[doc = "  * Neon instrinsic unsafe"]
18322#[inline]
18323#[cfg(target_endian = "little")]
18324#[target_feature(enable = "neon")]
18325#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18326#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18327#[cfg_attr(
18328    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18329    assert_instr(ld1)
18330)]
18331#[cfg_attr(
18332    not(target_arch = "arm"),
18333    stable(feature = "neon_intrinsics", since = "1.59.0")
18334)]
18335#[cfg_attr(
18336    target_arch = "arm",
18337    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18338)]
18339pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
18340    transmute(vld1q_s32_x2(transmute(a)))
18341}
18342#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18343#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"]
18344#[doc = "## Safety"]
18345#[doc = "  * Neon instrinsic unsafe"]
18346#[inline]
18347#[cfg(target_endian = "big")]
18348#[target_feature(enable = "neon")]
18349#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18350#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18351#[cfg_attr(
18352    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18353    assert_instr(ld1)
18354)]
18355#[cfg_attr(
18356    not(target_arch = "arm"),
18357    stable(feature = "neon_intrinsics", since = "1.59.0")
18358)]
18359#[cfg_attr(
18360    target_arch = "arm",
18361    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18362)]
18363pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
18364    let mut ret_val: uint32x4x2_t = transmute(vld1q_s32_x2(transmute(a)));
18365    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
18366    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
18367    ret_val
18368}
18369#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18370#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"]
18371#[doc = "## Safety"]
18372#[doc = "  * Neon instrinsic unsafe"]
18373#[inline]
18374#[cfg(target_endian = "little")]
18375#[target_feature(enable = "neon")]
18376#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18377#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18378#[cfg_attr(
18379    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18380    assert_instr(ld1)
18381)]
18382#[cfg_attr(
18383    not(target_arch = "arm"),
18384    stable(feature = "neon_intrinsics", since = "1.59.0")
18385)]
18386#[cfg_attr(
18387    target_arch = "arm",
18388    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18389)]
18390pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
18391    transmute(vld1q_s32_x3(transmute(a)))
18392}
18393#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"]
18395#[doc = "## Safety"]
18396#[doc = "  * Neon instrinsic unsafe"]
18397#[inline]
18398#[cfg(target_endian = "big")]
18399#[target_feature(enable = "neon")]
18400#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18401#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18402#[cfg_attr(
18403    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18404    assert_instr(ld1)
18405)]
18406#[cfg_attr(
18407    not(target_arch = "arm"),
18408    stable(feature = "neon_intrinsics", since = "1.59.0")
18409)]
18410#[cfg_attr(
18411    target_arch = "arm",
18412    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18413)]
18414pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
18415    let mut ret_val: uint32x4x3_t = transmute(vld1q_s32_x3(transmute(a)));
18416    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
18417    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
18418    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
18419    ret_val
18420}
18421#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18422#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"]
18423#[doc = "## Safety"]
18424#[doc = "  * Neon instrinsic unsafe"]
18425#[inline]
18426#[cfg(target_endian = "little")]
18427#[target_feature(enable = "neon")]
18428#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18429#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18430#[cfg_attr(
18431    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18432    assert_instr(ld1)
18433)]
18434#[cfg_attr(
18435    not(target_arch = "arm"),
18436    stable(feature = "neon_intrinsics", since = "1.59.0")
18437)]
18438#[cfg_attr(
18439    target_arch = "arm",
18440    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18441)]
18442pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
18443    transmute(vld1q_s32_x4(transmute(a)))
18444}
18445#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18446#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"]
18447#[doc = "## Safety"]
18448#[doc = "  * Neon instrinsic unsafe"]
18449#[inline]
18450#[cfg(target_endian = "big")]
18451#[target_feature(enable = "neon")]
18452#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18453#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18454#[cfg_attr(
18455    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18456    assert_instr(ld1)
18457)]
18458#[cfg_attr(
18459    not(target_arch = "arm"),
18460    stable(feature = "neon_intrinsics", since = "1.59.0")
18461)]
18462#[cfg_attr(
18463    target_arch = "arm",
18464    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18465)]
18466pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
18467    let mut ret_val: uint32x4x4_t = transmute(vld1q_s32_x4(transmute(a)));
18468    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
18469    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
18470    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
18471    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
18472    ret_val
18473}
18474#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18475#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"]
18476#[doc = "## Safety"]
18477#[doc = "  * Neon instrinsic unsafe"]
18478#[inline]
18479#[target_feature(enable = "neon")]
18480#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18481#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18482#[cfg_attr(
18483    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18484    assert_instr(ld1)
18485)]
18486#[cfg_attr(
18487    not(target_arch = "arm"),
18488    stable(feature = "neon_intrinsics", since = "1.59.0")
18489)]
18490#[cfg_attr(
18491    target_arch = "arm",
18492    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18493)]
18494pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t {
18495    transmute(vld1_s64_x2(transmute(a)))
18496}
18497#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18498#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"]
18499#[doc = "## Safety"]
18500#[doc = "  * Neon instrinsic unsafe"]
18501#[inline]
18502#[target_feature(enable = "neon")]
18503#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18504#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18505#[cfg_attr(
18506    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18507    assert_instr(ld1)
18508)]
18509#[cfg_attr(
18510    not(target_arch = "arm"),
18511    stable(feature = "neon_intrinsics", since = "1.59.0")
18512)]
18513#[cfg_attr(
18514    target_arch = "arm",
18515    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18516)]
18517pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t {
18518    transmute(vld1_s64_x3(transmute(a)))
18519}
18520#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18521#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"]
18522#[doc = "## Safety"]
18523#[doc = "  * Neon instrinsic unsafe"]
18524#[inline]
18525#[target_feature(enable = "neon")]
18526#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18527#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18528#[cfg_attr(
18529    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18530    assert_instr(ld1)
18531)]
18532#[cfg_attr(
18533    not(target_arch = "arm"),
18534    stable(feature = "neon_intrinsics", since = "1.59.0")
18535)]
18536#[cfg_attr(
18537    target_arch = "arm",
18538    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18539)]
18540pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t {
18541    transmute(vld1_s64_x4(transmute(a)))
18542}
18543#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18544#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"]
18545#[doc = "## Safety"]
18546#[doc = "  * Neon instrinsic unsafe"]
18547#[inline]
18548#[cfg(target_endian = "little")]
18549#[target_feature(enable = "neon")]
18550#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18551#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18552#[cfg_attr(
18553    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18554    assert_instr(ld1)
18555)]
18556#[cfg_attr(
18557    not(target_arch = "arm"),
18558    stable(feature = "neon_intrinsics", since = "1.59.0")
18559)]
18560#[cfg_attr(
18561    target_arch = "arm",
18562    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18563)]
18564pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
18565    transmute(vld1q_s64_x2(transmute(a)))
18566}
18567#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"]
18569#[doc = "## Safety"]
18570#[doc = "  * Neon instrinsic unsafe"]
18571#[inline]
18572#[cfg(target_endian = "big")]
18573#[target_feature(enable = "neon")]
18574#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18575#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18576#[cfg_attr(
18577    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18578    assert_instr(ld1)
18579)]
18580#[cfg_attr(
18581    not(target_arch = "arm"),
18582    stable(feature = "neon_intrinsics", since = "1.59.0")
18583)]
18584#[cfg_attr(
18585    target_arch = "arm",
18586    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18587)]
18588pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
18589    let mut ret_val: uint64x2x2_t = transmute(vld1q_s64_x2(transmute(a)));
18590    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18591    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18592    ret_val
18593}
18594#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18595#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"]
18596#[doc = "## Safety"]
18597#[doc = "  * Neon instrinsic unsafe"]
18598#[inline]
18599#[cfg(target_endian = "little")]
18600#[target_feature(enable = "neon")]
18601#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18602#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18603#[cfg_attr(
18604    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18605    assert_instr(ld1)
18606)]
18607#[cfg_attr(
18608    not(target_arch = "arm"),
18609    stable(feature = "neon_intrinsics", since = "1.59.0")
18610)]
18611#[cfg_attr(
18612    target_arch = "arm",
18613    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18614)]
18615pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
18616    transmute(vld1q_s64_x3(transmute(a)))
18617}
18618#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18619#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"]
18620#[doc = "## Safety"]
18621#[doc = "  * Neon instrinsic unsafe"]
18622#[inline]
18623#[cfg(target_endian = "big")]
18624#[target_feature(enable = "neon")]
18625#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18626#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18627#[cfg_attr(
18628    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18629    assert_instr(ld1)
18630)]
18631#[cfg_attr(
18632    not(target_arch = "arm"),
18633    stable(feature = "neon_intrinsics", since = "1.59.0")
18634)]
18635#[cfg_attr(
18636    target_arch = "arm",
18637    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18638)]
18639pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
18640    let mut ret_val: uint64x2x3_t = transmute(vld1q_s64_x3(transmute(a)));
18641    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18642    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18643    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
18644    ret_val
18645}
18646#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18647#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"]
18648#[doc = "## Safety"]
18649#[doc = "  * Neon instrinsic unsafe"]
18650#[inline]
18651#[cfg(target_endian = "little")]
18652#[target_feature(enable = "neon")]
18653#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18654#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18655#[cfg_attr(
18656    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18657    assert_instr(ld1)
18658)]
18659#[cfg_attr(
18660    not(target_arch = "arm"),
18661    stable(feature = "neon_intrinsics", since = "1.59.0")
18662)]
18663#[cfg_attr(
18664    target_arch = "arm",
18665    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18666)]
18667pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
18668    transmute(vld1q_s64_x4(transmute(a)))
18669}
18670#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18671#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"]
18672#[doc = "## Safety"]
18673#[doc = "  * Neon instrinsic unsafe"]
18674#[inline]
18675#[cfg(target_endian = "big")]
18676#[target_feature(enable = "neon")]
18677#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18678#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18679#[cfg_attr(
18680    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18681    assert_instr(ld1)
18682)]
18683#[cfg_attr(
18684    not(target_arch = "arm"),
18685    stable(feature = "neon_intrinsics", since = "1.59.0")
18686)]
18687#[cfg_attr(
18688    target_arch = "arm",
18689    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18690)]
18691pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
18692    let mut ret_val: uint64x2x4_t = transmute(vld1q_s64_x4(transmute(a)));
18693    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18694    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18695    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
18696    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
18697    ret_val
18698}
18699#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18700#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"]
18701#[doc = "## Safety"]
18702#[doc = "  * Neon instrinsic unsafe"]
18703#[inline]
18704#[cfg(target_endian = "little")]
18705#[target_feature(enable = "neon")]
18706#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18707#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18708#[cfg_attr(
18709    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18710    assert_instr(ld1)
18711)]
18712#[cfg_attr(
18713    not(target_arch = "arm"),
18714    stable(feature = "neon_intrinsics", since = "1.59.0")
18715)]
18716#[cfg_attr(
18717    target_arch = "arm",
18718    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18719)]
18720pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
18721    transmute(vld1_s8_x2(transmute(a)))
18722}
18723#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18724#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"]
18725#[doc = "## Safety"]
18726#[doc = "  * Neon instrinsic unsafe"]
18727#[inline]
18728#[cfg(target_endian = "big")]
18729#[target_feature(enable = "neon")]
18730#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18731#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18732#[cfg_attr(
18733    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18734    assert_instr(ld1)
18735)]
18736#[cfg_attr(
18737    not(target_arch = "arm"),
18738    stable(feature = "neon_intrinsics", since = "1.59.0")
18739)]
18740#[cfg_attr(
18741    target_arch = "arm",
18742    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18743)]
18744pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
18745    let mut ret_val: poly8x8x2_t = transmute(vld1_s8_x2(transmute(a)));
18746    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18747    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18748    ret_val
18749}
18750#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"]
18752#[doc = "## Safety"]
18753#[doc = "  * Neon instrinsic unsafe"]
18754#[inline]
18755#[cfg(target_endian = "little")]
18756#[target_feature(enable = "neon")]
18757#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18758#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18759#[cfg_attr(
18760    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18761    assert_instr(ld1)
18762)]
18763#[cfg_attr(
18764    not(target_arch = "arm"),
18765    stable(feature = "neon_intrinsics", since = "1.59.0")
18766)]
18767#[cfg_attr(
18768    target_arch = "arm",
18769    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18770)]
18771pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
18772    transmute(vld1_s8_x3(transmute(a)))
18773}
18774#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18775#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"]
18776#[doc = "## Safety"]
18777#[doc = "  * Neon instrinsic unsafe"]
18778#[inline]
18779#[cfg(target_endian = "big")]
18780#[target_feature(enable = "neon")]
18781#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18782#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18783#[cfg_attr(
18784    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18785    assert_instr(ld1)
18786)]
18787#[cfg_attr(
18788    not(target_arch = "arm"),
18789    stable(feature = "neon_intrinsics", since = "1.59.0")
18790)]
18791#[cfg_attr(
18792    target_arch = "arm",
18793    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18794)]
18795pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
18796    let mut ret_val: poly8x8x3_t = transmute(vld1_s8_x3(transmute(a)));
18797    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18798    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18799    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
18800    ret_val
18801}
18802#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18803#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"]
18804#[doc = "## Safety"]
18805#[doc = "  * Neon instrinsic unsafe"]
18806#[inline]
18807#[cfg(target_endian = "little")]
18808#[target_feature(enable = "neon")]
18809#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18810#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18811#[cfg_attr(
18812    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18813    assert_instr(ld1)
18814)]
18815#[cfg_attr(
18816    not(target_arch = "arm"),
18817    stable(feature = "neon_intrinsics", since = "1.59.0")
18818)]
18819#[cfg_attr(
18820    target_arch = "arm",
18821    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18822)]
18823pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
18824    transmute(vld1_s8_x4(transmute(a)))
18825}
18826#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18827#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"]
18828#[doc = "## Safety"]
18829#[doc = "  * Neon instrinsic unsafe"]
18830#[inline]
18831#[cfg(target_endian = "big")]
18832#[target_feature(enable = "neon")]
18833#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18834#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18835#[cfg_attr(
18836    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18837    assert_instr(ld1)
18838)]
18839#[cfg_attr(
18840    not(target_arch = "arm"),
18841    stable(feature = "neon_intrinsics", since = "1.59.0")
18842)]
18843#[cfg_attr(
18844    target_arch = "arm",
18845    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18846)]
18847pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
18848    let mut ret_val: poly8x8x4_t = transmute(vld1_s8_x4(transmute(a)));
18849    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18850    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18851    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
18852    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
18853    ret_val
18854}
18855#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18856#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"]
18857#[doc = "## Safety"]
18858#[doc = "  * Neon instrinsic unsafe"]
18859#[inline]
18860#[cfg(target_endian = "little")]
18861#[target_feature(enable = "neon")]
18862#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18863#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18864#[cfg_attr(
18865    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18866    assert_instr(ld1)
18867)]
18868#[cfg_attr(
18869    not(target_arch = "arm"),
18870    stable(feature = "neon_intrinsics", since = "1.59.0")
18871)]
18872#[cfg_attr(
18873    target_arch = "arm",
18874    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18875)]
18876pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
18877    transmute(vld1q_s8_x2(transmute(a)))
18878}
18879#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"]
18881#[doc = "## Safety"]
18882#[doc = "  * Neon instrinsic unsafe"]
18883#[inline]
18884#[cfg(target_endian = "big")]
18885#[target_feature(enable = "neon")]
18886#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18887#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18888#[cfg_attr(
18889    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18890    assert_instr(ld1)
18891)]
18892#[cfg_attr(
18893    not(target_arch = "arm"),
18894    stable(feature = "neon_intrinsics", since = "1.59.0")
18895)]
18896#[cfg_attr(
18897    target_arch = "arm",
18898    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18899)]
18900pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
18901    let mut ret_val: poly8x16x2_t = transmute(vld1q_s8_x2(transmute(a)));
18902    ret_val.0 = unsafe {
18903        simd_shuffle!(
18904            ret_val.0,
18905            ret_val.0,
18906            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18907        )
18908    };
18909    ret_val.1 = unsafe {
18910        simd_shuffle!(
18911            ret_val.1,
18912            ret_val.1,
18913            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18914        )
18915    };
18916    ret_val
18917}
18918#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18919#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"]
18920#[doc = "## Safety"]
18921#[doc = "  * Neon instrinsic unsafe"]
18922#[inline]
18923#[cfg(target_endian = "little")]
18924#[target_feature(enable = "neon")]
18925#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18926#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18927#[cfg_attr(
18928    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18929    assert_instr(ld1)
18930)]
18931#[cfg_attr(
18932    not(target_arch = "arm"),
18933    stable(feature = "neon_intrinsics", since = "1.59.0")
18934)]
18935#[cfg_attr(
18936    target_arch = "arm",
18937    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18938)]
18939pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
18940    transmute(vld1q_s8_x3(transmute(a)))
18941}
18942#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18943#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"]
18944#[doc = "## Safety"]
18945#[doc = "  * Neon instrinsic unsafe"]
18946#[inline]
18947#[cfg(target_endian = "big")]
18948#[target_feature(enable = "neon")]
18949#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18950#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18951#[cfg_attr(
18952    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18953    assert_instr(ld1)
18954)]
18955#[cfg_attr(
18956    not(target_arch = "arm"),
18957    stable(feature = "neon_intrinsics", since = "1.59.0")
18958)]
18959#[cfg_attr(
18960    target_arch = "arm",
18961    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18962)]
18963pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
18964    let mut ret_val: poly8x16x3_t = transmute(vld1q_s8_x3(transmute(a)));
18965    ret_val.0 = unsafe {
18966        simd_shuffle!(
18967            ret_val.0,
18968            ret_val.0,
18969            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18970        )
18971    };
18972    ret_val.1 = unsafe {
18973        simd_shuffle!(
18974            ret_val.1,
18975            ret_val.1,
18976            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18977        )
18978    };
18979    ret_val.2 = unsafe {
18980        simd_shuffle!(
18981            ret_val.2,
18982            ret_val.2,
18983            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18984        )
18985    };
18986    ret_val
18987}
18988#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18989#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"]
18990#[doc = "## Safety"]
18991#[doc = "  * Neon instrinsic unsafe"]
18992#[inline]
18993#[cfg(target_endian = "little")]
18994#[target_feature(enable = "neon")]
18995#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18996#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18997#[cfg_attr(
18998    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18999    assert_instr(ld1)
19000)]
19001#[cfg_attr(
19002    not(target_arch = "arm"),
19003    stable(feature = "neon_intrinsics", since = "1.59.0")
19004)]
19005#[cfg_attr(
19006    target_arch = "arm",
19007    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19008)]
19009pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
19010    transmute(vld1q_s8_x4(transmute(a)))
19011}
19012#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"]
19014#[doc = "## Safety"]
19015#[doc = "  * Neon instrinsic unsafe"]
19016#[inline]
19017#[cfg(target_endian = "big")]
19018#[target_feature(enable = "neon")]
19019#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19020#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19021#[cfg_attr(
19022    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19023    assert_instr(ld1)
19024)]
19025#[cfg_attr(
19026    not(target_arch = "arm"),
19027    stable(feature = "neon_intrinsics", since = "1.59.0")
19028)]
19029#[cfg_attr(
19030    target_arch = "arm",
19031    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19032)]
19033pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
19034    let mut ret_val: poly8x16x4_t = transmute(vld1q_s8_x4(transmute(a)));
19035    ret_val.0 = unsafe {
19036        simd_shuffle!(
19037            ret_val.0,
19038            ret_val.0,
19039            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19040        )
19041    };
19042    ret_val.1 = unsafe {
19043        simd_shuffle!(
19044            ret_val.1,
19045            ret_val.1,
19046            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19047        )
19048    };
19049    ret_val.2 = unsafe {
19050        simd_shuffle!(
19051            ret_val.2,
19052            ret_val.2,
19053            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19054        )
19055    };
19056    ret_val.3 = unsafe {
19057        simd_shuffle!(
19058            ret_val.3,
19059            ret_val.3,
19060            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19061        )
19062    };
19063    ret_val
19064}
19065#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19066#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"]
19067#[doc = "## Safety"]
19068#[doc = "  * Neon instrinsic unsafe"]
19069#[inline]
19070#[cfg(target_endian = "little")]
19071#[target_feature(enable = "neon")]
19072#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19073#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19074#[cfg_attr(
19075    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19076    assert_instr(ld1)
19077)]
19078#[cfg_attr(
19079    not(target_arch = "arm"),
19080    stable(feature = "neon_intrinsics", since = "1.59.0")
19081)]
19082#[cfg_attr(
19083    target_arch = "arm",
19084    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19085)]
19086pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
19087    transmute(vld1_s16_x2(transmute(a)))
19088}
19089#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19090#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"]
19091#[doc = "## Safety"]
19092#[doc = "  * Neon instrinsic unsafe"]
19093#[inline]
19094#[cfg(target_endian = "big")]
19095#[target_feature(enable = "neon")]
19096#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19097#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19098#[cfg_attr(
19099    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19100    assert_instr(ld1)
19101)]
19102#[cfg_attr(
19103    not(target_arch = "arm"),
19104    stable(feature = "neon_intrinsics", since = "1.59.0")
19105)]
19106#[cfg_attr(
19107    target_arch = "arm",
19108    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19109)]
19110pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
19111    let mut ret_val: poly16x4x2_t = transmute(vld1_s16_x2(transmute(a)));
19112    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
19113    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
19114    ret_val
19115}
19116#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"]
19118#[doc = "## Safety"]
19119#[doc = "  * Neon instrinsic unsafe"]
19120#[inline]
19121#[cfg(target_endian = "little")]
19122#[target_feature(enable = "neon")]
19123#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19124#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19125#[cfg_attr(
19126    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19127    assert_instr(ld1)
19128)]
19129#[cfg_attr(
19130    not(target_arch = "arm"),
19131    stable(feature = "neon_intrinsics", since = "1.59.0")
19132)]
19133#[cfg_attr(
19134    target_arch = "arm",
19135    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19136)]
19137pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
19138    transmute(vld1_s16_x3(transmute(a)))
19139}
19140#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19141#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"]
19142#[doc = "## Safety"]
19143#[doc = "  * Neon instrinsic unsafe"]
19144#[inline]
19145#[cfg(target_endian = "big")]
19146#[target_feature(enable = "neon")]
19147#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19148#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19149#[cfg_attr(
19150    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19151    assert_instr(ld1)
19152)]
19153#[cfg_attr(
19154    not(target_arch = "arm"),
19155    stable(feature = "neon_intrinsics", since = "1.59.0")
19156)]
19157#[cfg_attr(
19158    target_arch = "arm",
19159    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19160)]
19161pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
19162    let mut ret_val: poly16x4x3_t = transmute(vld1_s16_x3(transmute(a)));
19163    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
19164    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
19165    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
19166    ret_val
19167}
19168#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19169#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"]
19170#[doc = "## Safety"]
19171#[doc = "  * Neon instrinsic unsafe"]
19172#[inline]
19173#[cfg(target_endian = "little")]
19174#[target_feature(enable = "neon")]
19175#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19176#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19177#[cfg_attr(
19178    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19179    assert_instr(ld1)
19180)]
19181#[cfg_attr(
19182    not(target_arch = "arm"),
19183    stable(feature = "neon_intrinsics", since = "1.59.0")
19184)]
19185#[cfg_attr(
19186    target_arch = "arm",
19187    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19188)]
19189pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
19190    transmute(vld1_s16_x4(transmute(a)))
19191}
19192#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19193#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"]
19194#[doc = "## Safety"]
19195#[doc = "  * Neon instrinsic unsafe"]
19196#[inline]
19197#[cfg(target_endian = "big")]
19198#[target_feature(enable = "neon")]
19199#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19200#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19201#[cfg_attr(
19202    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19203    assert_instr(ld1)
19204)]
19205#[cfg_attr(
19206    not(target_arch = "arm"),
19207    stable(feature = "neon_intrinsics", since = "1.59.0")
19208)]
19209#[cfg_attr(
19210    target_arch = "arm",
19211    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19212)]
19213pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
19214    let mut ret_val: poly16x4x4_t = transmute(vld1_s16_x4(transmute(a)));
19215    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
19216    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
19217    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
19218    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
19219    ret_val
19220}
19221#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19222#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"]
19223#[doc = "## Safety"]
19224#[doc = "  * Neon instrinsic unsafe"]
19225#[inline]
19226#[cfg(target_endian = "little")]
19227#[target_feature(enable = "neon")]
19228#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19229#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19230#[cfg_attr(
19231    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19232    assert_instr(ld1)
19233)]
19234#[cfg_attr(
19235    not(target_arch = "arm"),
19236    stable(feature = "neon_intrinsics", since = "1.59.0")
19237)]
19238#[cfg_attr(
19239    target_arch = "arm",
19240    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19241)]
19242pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
19243    transmute(vld1q_s16_x2(transmute(a)))
19244}
19245#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19246#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"]
19247#[doc = "## Safety"]
19248#[doc = "  * Neon instrinsic unsafe"]
19249#[inline]
19250#[cfg(target_endian = "big")]
19251#[target_feature(enable = "neon")]
19252#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19253#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19254#[cfg_attr(
19255    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19256    assert_instr(ld1)
19257)]
19258#[cfg_attr(
19259    not(target_arch = "arm"),
19260    stable(feature = "neon_intrinsics", since = "1.59.0")
19261)]
19262#[cfg_attr(
19263    target_arch = "arm",
19264    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19265)]
19266pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
19267    let mut ret_val: poly16x8x2_t = transmute(vld1q_s16_x2(transmute(a)));
19268    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
19269    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
19270    ret_val
19271}
19272#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19273#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"]
19274#[doc = "## Safety"]
19275#[doc = "  * Neon instrinsic unsafe"]
19276#[inline]
19277#[cfg(target_endian = "little")]
19278#[target_feature(enable = "neon")]
19279#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19280#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19281#[cfg_attr(
19282    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19283    assert_instr(ld1)
19284)]
19285#[cfg_attr(
19286    not(target_arch = "arm"),
19287    stable(feature = "neon_intrinsics", since = "1.59.0")
19288)]
19289#[cfg_attr(
19290    target_arch = "arm",
19291    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19292)]
19293pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
19294    transmute(vld1q_s16_x3(transmute(a)))
19295}
19296#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19297#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"]
19298#[doc = "## Safety"]
19299#[doc = "  * Neon instrinsic unsafe"]
19300#[inline]
19301#[cfg(target_endian = "big")]
19302#[target_feature(enable = "neon")]
19303#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19304#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19305#[cfg_attr(
19306    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19307    assert_instr(ld1)
19308)]
19309#[cfg_attr(
19310    not(target_arch = "arm"),
19311    stable(feature = "neon_intrinsics", since = "1.59.0")
19312)]
19313#[cfg_attr(
19314    target_arch = "arm",
19315    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19316)]
19317pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
19318    let mut ret_val: poly16x8x3_t = transmute(vld1q_s16_x3(transmute(a)));
19319    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
19320    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
19321    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
19322    ret_val
19323}
19324#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19325#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"]
19326#[doc = "## Safety"]
19327#[doc = "  * Neon instrinsic unsafe"]
19328#[inline]
19329#[cfg(target_endian = "little")]
19330#[target_feature(enable = "neon")]
19331#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19332#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19333#[cfg_attr(
19334    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19335    assert_instr(ld1)
19336)]
19337#[cfg_attr(
19338    not(target_arch = "arm"),
19339    stable(feature = "neon_intrinsics", since = "1.59.0")
19340)]
19341#[cfg_attr(
19342    target_arch = "arm",
19343    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19344)]
19345pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t {
19346    transmute(vld1q_s16_x4(transmute(a)))
19347}
19348#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19349#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"]
19350#[doc = "## Safety"]
19351#[doc = "  * Neon instrinsic unsafe"]
19352#[inline]
19353#[cfg(target_endian = "big")]
19354#[target_feature(enable = "neon")]
19355#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19356#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19357#[cfg_attr(
19358    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19359    assert_instr(ld1)
19360)]
19361#[cfg_attr(
19362    not(target_arch = "arm"),
19363    stable(feature = "neon_intrinsics", since = "1.59.0")
19364)]
19365#[cfg_attr(
19366    target_arch = "arm",
19367    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19368)]
19369pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t {
19370    let mut ret_val: poly16x8x4_t = transmute(vld1q_s16_x4(transmute(a)));
19371    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
19372    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
19373    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
19374    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
19375    ret_val
19376}
19377#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v1i64)"]
19379#[doc = "## Safety"]
19380#[doc = "  * Neon instrinsic unsafe"]
19381#[inline]
19382#[cfg(target_arch = "arm")]
19383#[target_feature(enable = "neon,v7")]
19384#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19385unsafe fn vld1_v1i64(a: *const i8, b: i32) -> int64x1_t {
19386    unsafe extern "unadjusted" {
19387        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v1i64")]
19388        fn _vld1_v1i64(a: *const i8, b: i32) -> int64x1_t;
19389    }
19390    _vld1_v1i64(a, b)
19391}
19392#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19393#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v2f32)"]
19394#[doc = "## Safety"]
19395#[doc = "  * Neon instrinsic unsafe"]
19396#[inline]
19397#[cfg(target_arch = "arm")]
19398#[target_feature(enable = "neon,v7")]
19399#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19400unsafe fn vld1_v2f32(a: *const i8, b: i32) -> float32x2_t {
19401    unsafe extern "unadjusted" {
19402        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2f32")]
19403        fn _vld1_v2f32(a: *const i8, b: i32) -> float32x2_t;
19404    }
19405    _vld1_v2f32(a, b)
19406}
19407#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19408#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v2i32)"]
19409#[doc = "## Safety"]
19410#[doc = "  * Neon instrinsic unsafe"]
19411#[inline]
19412#[cfg(target_arch = "arm")]
19413#[target_feature(enable = "neon,v7")]
19414#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19415unsafe fn vld1_v2i32(a: *const i8, b: i32) -> int32x2_t {
19416    unsafe extern "unadjusted" {
19417        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2i32")]
19418        fn _vld1_v2i32(a: *const i8, b: i32) -> int32x2_t;
19419    }
19420    _vld1_v2i32(a, b)
19421}
19422#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19423#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v4i16)"]
19424#[doc = "## Safety"]
19425#[doc = "  * Neon instrinsic unsafe"]
19426#[inline]
19427#[cfg(target_arch = "arm")]
19428#[target_feature(enable = "neon,v7")]
19429#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19430unsafe fn vld1_v4i16(a: *const i8, b: i32) -> int16x4_t {
19431    unsafe extern "unadjusted" {
19432        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4i16")]
19433        fn _vld1_v4i16(a: *const i8, b: i32) -> int16x4_t;
19434    }
19435    _vld1_v4i16(a, b)
19436}
19437#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19438#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v8i8)"]
19439#[doc = "## Safety"]
19440#[doc = "  * Neon instrinsic unsafe"]
19441#[inline]
19442#[cfg(target_arch = "arm")]
19443#[target_feature(enable = "neon,v7")]
19444#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19445unsafe fn vld1_v8i8(a: *const i8, b: i32) -> int8x8_t {
19446    unsafe extern "unadjusted" {
19447        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8i8")]
19448        fn _vld1_v8i8(a: *const i8, b: i32) -> int8x8_t;
19449    }
19450    _vld1_v8i8(a, b)
19451}
19452#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19453#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v16i8)"]
19454#[doc = "## Safety"]
19455#[doc = "  * Neon instrinsic unsafe"]
19456#[inline]
19457#[cfg(target_arch = "arm")]
19458#[target_feature(enable = "neon,v7")]
19459#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19460unsafe fn vld1q_v16i8(a: *const i8, b: i32) -> int8x16_t {
19461    unsafe extern "unadjusted" {
19462        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v16i8")]
19463        fn _vld1q_v16i8(a: *const i8, b: i32) -> int8x16_t;
19464    }
19465    _vld1q_v16i8(a, b)
19466}
19467#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v2i64)"]
19469#[doc = "## Safety"]
19470#[doc = "  * Neon instrinsic unsafe"]
19471#[inline]
19472#[cfg(target_arch = "arm")]
19473#[target_feature(enable = "neon,v7")]
19474#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19475unsafe fn vld1q_v2i64(a: *const i8, b: i32) -> int64x2_t {
19476    unsafe extern "unadjusted" {
19477        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2i64")]
19478        fn _vld1q_v2i64(a: *const i8, b: i32) -> int64x2_t;
19479    }
19480    _vld1q_v2i64(a, b)
19481}
19482#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v4f32)"]
19484#[doc = "## Safety"]
19485#[doc = "  * Neon instrinsic unsafe"]
19486#[inline]
19487#[cfg(target_arch = "arm")]
19488#[target_feature(enable = "neon,v7")]
19489#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19490unsafe fn vld1q_v4f32(a: *const i8, b: i32) -> float32x4_t {
19491    unsafe extern "unadjusted" {
19492        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4f32")]
19493        fn _vld1q_v4f32(a: *const i8, b: i32) -> float32x4_t;
19494    }
19495    _vld1q_v4f32(a, b)
19496}
19497#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19498#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v4i32)"]
19499#[doc = "## Safety"]
19500#[doc = "  * Neon instrinsic unsafe"]
19501#[inline]
19502#[cfg(target_arch = "arm")]
19503#[target_feature(enable = "neon,v7")]
19504#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19505unsafe fn vld1q_v4i32(a: *const i8, b: i32) -> int32x4_t {
19506    unsafe extern "unadjusted" {
19507        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4i32")]
19508        fn _vld1q_v4i32(a: *const i8, b: i32) -> int32x4_t;
19509    }
19510    _vld1q_v4i32(a, b)
19511}
19512#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19513#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v8i16)"]
19514#[doc = "## Safety"]
19515#[doc = "  * Neon instrinsic unsafe"]
19516#[inline]
19517#[cfg(target_arch = "arm")]
19518#[target_feature(enable = "neon,v7")]
19519#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19520unsafe fn vld1q_v8i16(a: *const i8, b: i32) -> int16x8_t {
19521    unsafe extern "unadjusted" {
19522        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8i16")]
19523        fn _vld1q_v8i16(a: *const i8, b: i32) -> int16x8_t;
19524    }
19525    _vld1q_v8i16(a, b)
19526}
19527#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19528#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v4f16)"]
19529#[doc = "## Safety"]
19530#[doc = "  * Neon instrinsic unsafe"]
19531#[inline]
19532#[cfg(target_arch = "arm")]
19533#[target_feature(enable = "neon,v7")]
19534#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
19535#[target_feature(enable = "neon,fp16")]
19536#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19537unsafe fn vld1_v4f16(a: *const i8, b: i32) -> float16x4_t {
19538    unsafe extern "unadjusted" {
19539        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4f16")]
19540        fn _vld1_v4f16(a: *const i8, b: i32) -> float16x4_t;
19541    }
19542    _vld1_v4f16(a, b)
19543}
19544#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19545#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v8f16)"]
19546#[doc = "## Safety"]
19547#[doc = "  * Neon instrinsic unsafe"]
19548#[inline]
19549#[cfg(target_arch = "arm")]
19550#[target_feature(enable = "neon,v7")]
19551#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
19552#[target_feature(enable = "neon,fp16")]
19553#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19554unsafe fn vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t {
19555    unsafe extern "unadjusted" {
19556        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8f16")]
19557        fn _vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t;
19558    }
19559    _vld1q_v8f16(a, b)
19560}
19561#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
19562#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p64)"]
19563#[doc = "## Safety"]
19564#[doc = "  * Neon instrinsic unsafe"]
19565#[inline]
19566#[target_feature(enable = "neon,aes")]
19567#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19568#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
19569#[cfg_attr(
19570    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19571    assert_instr(ld1r)
19572)]
19573#[cfg_attr(
19574    not(target_arch = "arm"),
19575    stable(feature = "neon_intrinsics", since = "1.59.0")
19576)]
19577#[cfg_attr(
19578    target_arch = "arm",
19579    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19580)]
19581pub unsafe fn vld1q_dup_p64(ptr: *const p64) -> poly64x2_t {
19582    let x = vld1q_lane_p64::<0>(ptr, transmute(u64x2::splat(0)));
19583    simd_shuffle!(x, x, [0, 0])
19584}
19585#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19586#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"]
19587#[doc = "## Safety"]
19588#[doc = "  * Neon instrinsic unsafe"]
19589#[inline]
19590#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19591#[cfg(target_arch = "arm")]
19592#[target_feature(enable = "neon,fp16")]
19593#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
19594#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19595pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t {
19596    unsafe extern "unadjusted" {
19597        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4f16.p0")]
19598        fn _vld2_dup_f16(ptr: *const f16, size: i32) -> float16x4x2_t;
19599    }
19600    _vld2_dup_f16(a as _, 2)
19601}
19602#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19603#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"]
19604#[doc = "## Safety"]
19605#[doc = "  * Neon instrinsic unsafe"]
19606#[inline]
19607#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19608#[cfg(target_arch = "arm")]
19609#[target_feature(enable = "neon,fp16")]
19610#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
19611#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19612pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t {
19613    unsafe extern "unadjusted" {
19614        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8f16.p0")]
19615        fn _vld2q_dup_f16(ptr: *const f16, size: i32) -> float16x8x2_t;
19616    }
19617    _vld2q_dup_f16(a as _, 2)
19618}
19619#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19620#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"]
19621#[doc = "## Safety"]
19622#[doc = "  * Neon instrinsic unsafe"]
19623#[inline]
19624#[cfg(not(target_arch = "arm"))]
19625#[cfg_attr(
19626    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19627    assert_instr(ld2r)
19628)]
19629#[target_feature(enable = "neon,fp16")]
19630#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19631pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t {
19632    unsafe extern "unadjusted" {
19633        #[cfg_attr(
19634            any(target_arch = "aarch64", target_arch = "arm64ec"),
19635            link_name = "llvm.aarch64.neon.ld2r.v4f16.p0"
19636        )]
19637        fn _vld2_dup_f16(ptr: *const f16) -> float16x4x2_t;
19638    }
19639    _vld2_dup_f16(a as _)
19640}
19641#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19642#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"]
19643#[doc = "## Safety"]
19644#[doc = "  * Neon instrinsic unsafe"]
19645#[inline]
19646#[cfg(not(target_arch = "arm"))]
19647#[cfg_attr(
19648    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19649    assert_instr(ld2r)
19650)]
19651#[target_feature(enable = "neon,fp16")]
19652#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19653pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t {
19654    unsafe extern "unadjusted" {
19655        #[cfg_attr(
19656            any(target_arch = "aarch64", target_arch = "arm64ec"),
19657            link_name = "llvm.aarch64.neon.ld2r.v8f16.p0"
19658        )]
19659        fn _vld2q_dup_f16(ptr: *const f16) -> float16x8x2_t;
19660    }
19661    _vld2q_dup_f16(a as _)
19662}
19663#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19664#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"]
19665#[doc = "## Safety"]
19666#[doc = "  * Neon instrinsic unsafe"]
19667#[inline]
19668#[target_feature(enable = "neon,v7")]
19669#[cfg(target_arch = "arm")]
19670#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19671#[cfg_attr(test, assert_instr(vld2))]
19672pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t {
19673    unsafe extern "unadjusted" {
19674        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v2f32.p0")]
19675        fn _vld2_dup_f32(ptr: *const i8, size: i32) -> float32x2x2_t;
19676    }
19677    _vld2_dup_f32(a as *const i8, 4)
19678}
19679#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19680#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"]
19681#[doc = "## Safety"]
19682#[doc = "  * Neon instrinsic unsafe"]
19683#[inline]
19684#[target_feature(enable = "neon,v7")]
19685#[cfg(target_arch = "arm")]
19686#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19687#[cfg_attr(test, assert_instr(vld2))]
19688pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t {
19689    unsafe extern "unadjusted" {
19690        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4f32.p0")]
19691        fn _vld2q_dup_f32(ptr: *const i8, size: i32) -> float32x4x2_t;
19692    }
19693    _vld2q_dup_f32(a as *const i8, 4)
19694}
19695#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19696#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"]
19697#[doc = "## Safety"]
19698#[doc = "  * Neon instrinsic unsafe"]
19699#[inline]
19700#[target_feature(enable = "neon,v7")]
19701#[cfg(target_arch = "arm")]
19702#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19703#[cfg_attr(test, assert_instr(vld2))]
19704pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t {
19705    unsafe extern "unadjusted" {
19706        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8i8.p0")]
19707        fn _vld2_dup_s8(ptr: *const i8, size: i32) -> int8x8x2_t;
19708    }
19709    _vld2_dup_s8(a as *const i8, 1)
19710}
19711#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19712#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"]
19713#[doc = "## Safety"]
19714#[doc = "  * Neon instrinsic unsafe"]
19715#[inline]
19716#[target_feature(enable = "neon,v7")]
19717#[cfg(target_arch = "arm")]
19718#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19719#[cfg_attr(test, assert_instr(vld2))]
19720pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t {
19721    unsafe extern "unadjusted" {
19722        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v16i8.p0")]
19723        fn _vld2q_dup_s8(ptr: *const i8, size: i32) -> int8x16x2_t;
19724    }
19725    _vld2q_dup_s8(a as *const i8, 1)
19726}
19727#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19728#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"]
19729#[doc = "## Safety"]
19730#[doc = "  * Neon instrinsic unsafe"]
19731#[inline]
19732#[target_feature(enable = "neon,v7")]
19733#[cfg(target_arch = "arm")]
19734#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19735#[cfg_attr(test, assert_instr(vld2))]
19736pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t {
19737    unsafe extern "unadjusted" {
19738        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4i16.p0")]
19739        fn _vld2_dup_s16(ptr: *const i8, size: i32) -> int16x4x2_t;
19740    }
19741    _vld2_dup_s16(a as *const i8, 2)
19742}
19743#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19744#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"]
19745#[doc = "## Safety"]
19746#[doc = "  * Neon instrinsic unsafe"]
19747#[inline]
19748#[target_feature(enable = "neon,v7")]
19749#[cfg(target_arch = "arm")]
19750#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19751#[cfg_attr(test, assert_instr(vld2))]
19752pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t {
19753    unsafe extern "unadjusted" {
19754        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8i16.p0")]
19755        fn _vld2q_dup_s16(ptr: *const i8, size: i32) -> int16x8x2_t;
19756    }
19757    _vld2q_dup_s16(a as *const i8, 2)
19758}
19759#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19760#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"]
19761#[doc = "## Safety"]
19762#[doc = "  * Neon instrinsic unsafe"]
19763#[inline]
19764#[target_feature(enable = "neon,v7")]
19765#[cfg(target_arch = "arm")]
19766#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19767#[cfg_attr(test, assert_instr(vld2))]
19768pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t {
19769    unsafe extern "unadjusted" {
19770        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v2i32.p0")]
19771        fn _vld2_dup_s32(ptr: *const i8, size: i32) -> int32x2x2_t;
19772    }
19773    _vld2_dup_s32(a as *const i8, 4)
19774}
19775#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19776#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"]
19777#[doc = "## Safety"]
19778#[doc = "  * Neon instrinsic unsafe"]
19779#[inline]
19780#[target_feature(enable = "neon,v7")]
19781#[cfg(target_arch = "arm")]
19782#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19783#[cfg_attr(test, assert_instr(vld2))]
19784pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t {
19785    unsafe extern "unadjusted" {
19786        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4i32.p0")]
19787        fn _vld2q_dup_s32(ptr: *const i8, size: i32) -> int32x4x2_t;
19788    }
19789    _vld2q_dup_s32(a as *const i8, 4)
19790}
19791#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19792#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"]
19793#[doc = "## Safety"]
19794#[doc = "  * Neon instrinsic unsafe"]
19795#[inline]
19796#[target_feature(enable = "neon")]
19797#[cfg(not(target_arch = "arm"))]
19798#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19799#[cfg_attr(test, assert_instr(ld2r))]
19800pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t {
19801    unsafe extern "unadjusted" {
19802        #[cfg_attr(
19803            any(target_arch = "aarch64", target_arch = "arm64ec"),
19804            link_name = "llvm.aarch64.neon.ld2r.v2f32.p0"
19805        )]
19806        fn _vld2_dup_f32(ptr: *const f32) -> float32x2x2_t;
19807    }
19808    _vld2_dup_f32(a as _)
19809}
19810#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"]
19812#[doc = "## Safety"]
19813#[doc = "  * Neon instrinsic unsafe"]
19814#[inline]
19815#[target_feature(enable = "neon")]
19816#[cfg(not(target_arch = "arm"))]
19817#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19818#[cfg_attr(test, assert_instr(ld2r))]
19819pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t {
19820    unsafe extern "unadjusted" {
19821        #[cfg_attr(
19822            any(target_arch = "aarch64", target_arch = "arm64ec"),
19823            link_name = "llvm.aarch64.neon.ld2r.v4f32.p0"
19824        )]
19825        fn _vld2q_dup_f32(ptr: *const f32) -> float32x4x2_t;
19826    }
19827    _vld2q_dup_f32(a as _)
19828}
19829#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"]
19831#[doc = "## Safety"]
19832#[doc = "  * Neon instrinsic unsafe"]
19833#[inline]
19834#[target_feature(enable = "neon")]
19835#[cfg(not(target_arch = "arm"))]
19836#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19837#[cfg_attr(test, assert_instr(ld2r))]
19838pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t {
19839    unsafe extern "unadjusted" {
19840        #[cfg_attr(
19841            any(target_arch = "aarch64", target_arch = "arm64ec"),
19842            link_name = "llvm.aarch64.neon.ld2r.v8i8.p0"
19843        )]
19844        fn _vld2_dup_s8(ptr: *const i8) -> int8x8x2_t;
19845    }
19846    _vld2_dup_s8(a as _)
19847}
19848#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19849#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"]
19850#[doc = "## Safety"]
19851#[doc = "  * Neon instrinsic unsafe"]
19852#[inline]
19853#[target_feature(enable = "neon")]
19854#[cfg(not(target_arch = "arm"))]
19855#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19856#[cfg_attr(test, assert_instr(ld2r))]
19857pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t {
19858    unsafe extern "unadjusted" {
19859        #[cfg_attr(
19860            any(target_arch = "aarch64", target_arch = "arm64ec"),
19861            link_name = "llvm.aarch64.neon.ld2r.v16i8.p0"
19862        )]
19863        fn _vld2q_dup_s8(ptr: *const i8) -> int8x16x2_t;
19864    }
19865    _vld2q_dup_s8(a as _)
19866}
19867#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19868#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"]
19869#[doc = "## Safety"]
19870#[doc = "  * Neon instrinsic unsafe"]
19871#[inline]
19872#[target_feature(enable = "neon")]
19873#[cfg(not(target_arch = "arm"))]
19874#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19875#[cfg_attr(test, assert_instr(ld2r))]
19876pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t {
19877    unsafe extern "unadjusted" {
19878        #[cfg_attr(
19879            any(target_arch = "aarch64", target_arch = "arm64ec"),
19880            link_name = "llvm.aarch64.neon.ld2r.v4i16.p0"
19881        )]
19882        fn _vld2_dup_s16(ptr: *const i16) -> int16x4x2_t;
19883    }
19884    _vld2_dup_s16(a as _)
19885}
19886#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"]
19888#[doc = "## Safety"]
19889#[doc = "  * Neon instrinsic unsafe"]
19890#[inline]
19891#[target_feature(enable = "neon")]
19892#[cfg(not(target_arch = "arm"))]
19893#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19894#[cfg_attr(test, assert_instr(ld2r))]
19895pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t {
19896    unsafe extern "unadjusted" {
19897        #[cfg_attr(
19898            any(target_arch = "aarch64", target_arch = "arm64ec"),
19899            link_name = "llvm.aarch64.neon.ld2r.v8i16.p0"
19900        )]
19901        fn _vld2q_dup_s16(ptr: *const i16) -> int16x8x2_t;
19902    }
19903    _vld2q_dup_s16(a as _)
19904}
19905#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19906#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"]
19907#[doc = "## Safety"]
19908#[doc = "  * Neon instrinsic unsafe"]
19909#[inline]
19910#[target_feature(enable = "neon")]
19911#[cfg(not(target_arch = "arm"))]
19912#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19913#[cfg_attr(test, assert_instr(ld2r))]
19914pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t {
19915    unsafe extern "unadjusted" {
19916        #[cfg_attr(
19917            any(target_arch = "aarch64", target_arch = "arm64ec"),
19918            link_name = "llvm.aarch64.neon.ld2r.v2i32.p0"
19919        )]
19920        fn _vld2_dup_s32(ptr: *const i32) -> int32x2x2_t;
19921    }
19922    _vld2_dup_s32(a as _)
19923}
19924#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19925#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"]
19926#[doc = "## Safety"]
19927#[doc = "  * Neon instrinsic unsafe"]
19928#[inline]
19929#[target_feature(enable = "neon")]
19930#[cfg(not(target_arch = "arm"))]
19931#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19932#[cfg_attr(test, assert_instr(ld2r))]
19933pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t {
19934    unsafe extern "unadjusted" {
19935        #[cfg_attr(
19936            any(target_arch = "aarch64", target_arch = "arm64ec"),
19937            link_name = "llvm.aarch64.neon.ld2r.v4i32.p0"
19938        )]
19939        fn _vld2q_dup_s32(ptr: *const i32) -> int32x4x2_t;
19940    }
19941    _vld2q_dup_s32(a as _)
19942}
19943#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19944#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p64)"]
19945#[doc = "## Safety"]
19946#[doc = "  * Neon instrinsic unsafe"]
19947#[inline]
19948#[target_feature(enable = "neon,aes")]
19949#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
19950#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
19951#[cfg_attr(
19952    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19953    assert_instr(ld2r)
19954)]
19955#[cfg_attr(
19956    not(target_arch = "arm"),
19957    stable(feature = "neon_intrinsics", since = "1.59.0")
19958)]
19959#[cfg_attr(
19960    target_arch = "arm",
19961    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19962)]
19963pub unsafe fn vld2_dup_p64(a: *const p64) -> poly64x1x2_t {
19964    transmute(vld2_dup_s64(transmute(a)))
19965}
19966#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19967#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"]
19968#[doc = "## Safety"]
19969#[doc = "  * Neon instrinsic unsafe"]
19970#[inline]
19971#[target_feature(enable = "neon,v7")]
19972#[cfg(target_arch = "arm")]
19973#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19974#[cfg_attr(test, assert_instr(nop))]
19975pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t {
19976    unsafe extern "unadjusted" {
19977        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v1i64.p0")]
19978        fn _vld2_dup_s64(ptr: *const i8, size: i32) -> int64x1x2_t;
19979    }
19980    _vld2_dup_s64(a as *const i8, 8)
19981}
19982#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19983#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"]
19984#[doc = "## Safety"]
19985#[doc = "  * Neon instrinsic unsafe"]
19986#[inline]
19987#[target_feature(enable = "neon")]
19988#[cfg(not(target_arch = "arm"))]
19989#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19990#[cfg_attr(test, assert_instr(ld2r))]
19991pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t {
19992    unsafe extern "unadjusted" {
19993        #[cfg_attr(
19994            any(target_arch = "aarch64", target_arch = "arm64ec"),
19995            link_name = "llvm.aarch64.neon.ld2r.v1i64.p0"
19996        )]
19997        fn _vld2_dup_s64(ptr: *const i64) -> int64x1x2_t;
19998    }
19999    _vld2_dup_s64(a as _)
20000}
20001#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u64)"]
20003#[doc = "## Safety"]
20004#[doc = "  * Neon instrinsic unsafe"]
20005#[inline]
20006#[target_feature(enable = "neon")]
20007#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20008#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
20009#[cfg_attr(
20010    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20011    assert_instr(ld2r)
20012)]
20013#[cfg_attr(
20014    not(target_arch = "arm"),
20015    stable(feature = "neon_intrinsics", since = "1.59.0")
20016)]
20017#[cfg_attr(
20018    target_arch = "arm",
20019    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20020)]
20021pub unsafe fn vld2_dup_u64(a: *const u64) -> uint64x1x2_t {
20022    transmute(vld2_dup_s64(transmute(a)))
20023}
20024#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20025#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"]
20026#[doc = "## Safety"]
20027#[doc = "  * Neon instrinsic unsafe"]
20028#[inline]
20029#[cfg(target_endian = "little")]
20030#[target_feature(enable = "neon")]
20031#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20032#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20033#[cfg_attr(
20034    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20035    assert_instr(ld2r)
20036)]
20037#[cfg_attr(
20038    not(target_arch = "arm"),
20039    stable(feature = "neon_intrinsics", since = "1.59.0")
20040)]
20041#[cfg_attr(
20042    target_arch = "arm",
20043    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20044)]
20045pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
20046    transmute(vld2_dup_s8(transmute(a)))
20047}
20048#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20049#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"]
20050#[doc = "## Safety"]
20051#[doc = "  * Neon instrinsic unsafe"]
20052#[inline]
20053#[cfg(target_endian = "big")]
20054#[target_feature(enable = "neon")]
20055#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20056#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20057#[cfg_attr(
20058    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20059    assert_instr(ld2r)
20060)]
20061#[cfg_attr(
20062    not(target_arch = "arm"),
20063    stable(feature = "neon_intrinsics", since = "1.59.0")
20064)]
20065#[cfg_attr(
20066    target_arch = "arm",
20067    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20068)]
20069pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
20070    let mut ret_val: uint8x8x2_t = transmute(vld2_dup_s8(transmute(a)));
20071    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
20072    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
20073    ret_val
20074}
20075#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20076#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"]
20077#[doc = "## Safety"]
20078#[doc = "  * Neon instrinsic unsafe"]
20079#[inline]
20080#[cfg(target_endian = "little")]
20081#[target_feature(enable = "neon")]
20082#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20083#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20084#[cfg_attr(
20085    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20086    assert_instr(ld2r)
20087)]
20088#[cfg_attr(
20089    not(target_arch = "arm"),
20090    stable(feature = "neon_intrinsics", since = "1.59.0")
20091)]
20092#[cfg_attr(
20093    target_arch = "arm",
20094    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20095)]
20096pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
20097    transmute(vld2q_dup_s8(transmute(a)))
20098}
20099#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20100#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"]
20101#[doc = "## Safety"]
20102#[doc = "  * Neon instrinsic unsafe"]
20103#[inline]
20104#[cfg(target_endian = "big")]
20105#[target_feature(enable = "neon")]
20106#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20107#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20108#[cfg_attr(
20109    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20110    assert_instr(ld2r)
20111)]
20112#[cfg_attr(
20113    not(target_arch = "arm"),
20114    stable(feature = "neon_intrinsics", since = "1.59.0")
20115)]
20116#[cfg_attr(
20117    target_arch = "arm",
20118    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20119)]
20120pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
20121    let mut ret_val: uint8x16x2_t = transmute(vld2q_dup_s8(transmute(a)));
20122    ret_val.0 = unsafe {
20123        simd_shuffle!(
20124            ret_val.0,
20125            ret_val.0,
20126            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20127        )
20128    };
20129    ret_val.1 = unsafe {
20130        simd_shuffle!(
20131            ret_val.1,
20132            ret_val.1,
20133            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20134        )
20135    };
20136    ret_val
20137}
20138#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20139#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"]
20140#[doc = "## Safety"]
20141#[doc = "  * Neon instrinsic unsafe"]
20142#[inline]
20143#[cfg(target_endian = "little")]
20144#[target_feature(enable = "neon")]
20145#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20146#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20147#[cfg_attr(
20148    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20149    assert_instr(ld2r)
20150)]
20151#[cfg_attr(
20152    not(target_arch = "arm"),
20153    stable(feature = "neon_intrinsics", since = "1.59.0")
20154)]
20155#[cfg_attr(
20156    target_arch = "arm",
20157    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20158)]
20159pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
20160    transmute(vld2_dup_s16(transmute(a)))
20161}
20162#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20163#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"]
20164#[doc = "## Safety"]
20165#[doc = "  * Neon instrinsic unsafe"]
20166#[inline]
20167#[cfg(target_endian = "big")]
20168#[target_feature(enable = "neon")]
20169#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20170#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20171#[cfg_attr(
20172    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20173    assert_instr(ld2r)
20174)]
20175#[cfg_attr(
20176    not(target_arch = "arm"),
20177    stable(feature = "neon_intrinsics", since = "1.59.0")
20178)]
20179#[cfg_attr(
20180    target_arch = "arm",
20181    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20182)]
20183pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
20184    let mut ret_val: uint16x4x2_t = transmute(vld2_dup_s16(transmute(a)));
20185    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
20186    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
20187    ret_val
20188}
20189#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20190#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"]
20191#[doc = "## Safety"]
20192#[doc = "  * Neon instrinsic unsafe"]
20193#[inline]
20194#[cfg(target_endian = "little")]
20195#[target_feature(enable = "neon")]
20196#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20197#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20198#[cfg_attr(
20199    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20200    assert_instr(ld2r)
20201)]
20202#[cfg_attr(
20203    not(target_arch = "arm"),
20204    stable(feature = "neon_intrinsics", since = "1.59.0")
20205)]
20206#[cfg_attr(
20207    target_arch = "arm",
20208    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20209)]
20210pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
20211    transmute(vld2q_dup_s16(transmute(a)))
20212}
20213#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20214#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"]
20215#[doc = "## Safety"]
20216#[doc = "  * Neon instrinsic unsafe"]
20217#[inline]
20218#[cfg(target_endian = "big")]
20219#[target_feature(enable = "neon")]
20220#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20221#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20222#[cfg_attr(
20223    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20224    assert_instr(ld2r)
20225)]
20226#[cfg_attr(
20227    not(target_arch = "arm"),
20228    stable(feature = "neon_intrinsics", since = "1.59.0")
20229)]
20230#[cfg_attr(
20231    target_arch = "arm",
20232    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20233)]
20234pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
20235    let mut ret_val: uint16x8x2_t = transmute(vld2q_dup_s16(transmute(a)));
20236    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
20237    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
20238    ret_val
20239}
20240#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20241#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"]
20242#[doc = "## Safety"]
20243#[doc = "  * Neon instrinsic unsafe"]
20244#[inline]
20245#[cfg(target_endian = "little")]
20246#[target_feature(enable = "neon")]
20247#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20248#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20249#[cfg_attr(
20250    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20251    assert_instr(ld2r)
20252)]
20253#[cfg_attr(
20254    not(target_arch = "arm"),
20255    stable(feature = "neon_intrinsics", since = "1.59.0")
20256)]
20257#[cfg_attr(
20258    target_arch = "arm",
20259    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20260)]
20261pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
20262    transmute(vld2_dup_s32(transmute(a)))
20263}
20264#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20265#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"]
20266#[doc = "## Safety"]
20267#[doc = "  * Neon instrinsic unsafe"]
20268#[inline]
20269#[cfg(target_endian = "big")]
20270#[target_feature(enable = "neon")]
20271#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20272#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20273#[cfg_attr(
20274    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20275    assert_instr(ld2r)
20276)]
20277#[cfg_attr(
20278    not(target_arch = "arm"),
20279    stable(feature = "neon_intrinsics", since = "1.59.0")
20280)]
20281#[cfg_attr(
20282    target_arch = "arm",
20283    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20284)]
20285pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
20286    let mut ret_val: uint32x2x2_t = transmute(vld2_dup_s32(transmute(a)));
20287    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
20288    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
20289    ret_val
20290}
20291#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20292#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"]
20293#[doc = "## Safety"]
20294#[doc = "  * Neon instrinsic unsafe"]
20295#[inline]
20296#[cfg(target_endian = "little")]
20297#[target_feature(enable = "neon")]
20298#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20299#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20300#[cfg_attr(
20301    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20302    assert_instr(ld2r)
20303)]
20304#[cfg_attr(
20305    not(target_arch = "arm"),
20306    stable(feature = "neon_intrinsics", since = "1.59.0")
20307)]
20308#[cfg_attr(
20309    target_arch = "arm",
20310    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20311)]
20312pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
20313    transmute(vld2q_dup_s32(transmute(a)))
20314}
20315#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20316#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"]
20317#[doc = "## Safety"]
20318#[doc = "  * Neon instrinsic unsafe"]
20319#[inline]
20320#[cfg(target_endian = "big")]
20321#[target_feature(enable = "neon")]
20322#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20323#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20324#[cfg_attr(
20325    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20326    assert_instr(ld2r)
20327)]
20328#[cfg_attr(
20329    not(target_arch = "arm"),
20330    stable(feature = "neon_intrinsics", since = "1.59.0")
20331)]
20332#[cfg_attr(
20333    target_arch = "arm",
20334    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20335)]
20336pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
20337    let mut ret_val: uint32x4x2_t = transmute(vld2q_dup_s32(transmute(a)));
20338    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
20339    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
20340    ret_val
20341}
20342#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20343#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"]
20344#[doc = "## Safety"]
20345#[doc = "  * Neon instrinsic unsafe"]
20346#[inline]
20347#[cfg(target_endian = "little")]
20348#[target_feature(enable = "neon")]
20349#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20350#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20351#[cfg_attr(
20352    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20353    assert_instr(ld2r)
20354)]
20355#[cfg_attr(
20356    not(target_arch = "arm"),
20357    stable(feature = "neon_intrinsics", since = "1.59.0")
20358)]
20359#[cfg_attr(
20360    target_arch = "arm",
20361    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20362)]
20363pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
20364    transmute(vld2_dup_s8(transmute(a)))
20365}
20366#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20367#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"]
20368#[doc = "## Safety"]
20369#[doc = "  * Neon instrinsic unsafe"]
20370#[inline]
20371#[cfg(target_endian = "big")]
20372#[target_feature(enable = "neon")]
20373#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20374#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20375#[cfg_attr(
20376    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20377    assert_instr(ld2r)
20378)]
20379#[cfg_attr(
20380    not(target_arch = "arm"),
20381    stable(feature = "neon_intrinsics", since = "1.59.0")
20382)]
20383#[cfg_attr(
20384    target_arch = "arm",
20385    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20386)]
20387pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
20388    let mut ret_val: poly8x8x2_t = transmute(vld2_dup_s8(transmute(a)));
20389    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
20390    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
20391    ret_val
20392}
20393#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"]
20395#[doc = "## Safety"]
20396#[doc = "  * Neon instrinsic unsafe"]
20397#[inline]
20398#[cfg(target_endian = "little")]
20399#[target_feature(enable = "neon")]
20400#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20401#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20402#[cfg_attr(
20403    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20404    assert_instr(ld2r)
20405)]
20406#[cfg_attr(
20407    not(target_arch = "arm"),
20408    stable(feature = "neon_intrinsics", since = "1.59.0")
20409)]
20410#[cfg_attr(
20411    target_arch = "arm",
20412    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20413)]
20414pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
20415    transmute(vld2q_dup_s8(transmute(a)))
20416}
20417#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"]
20419#[doc = "## Safety"]
20420#[doc = "  * Neon instrinsic unsafe"]
20421#[inline]
20422#[cfg(target_endian = "big")]
20423#[target_feature(enable = "neon")]
20424#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20425#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20426#[cfg_attr(
20427    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20428    assert_instr(ld2r)
20429)]
20430#[cfg_attr(
20431    not(target_arch = "arm"),
20432    stable(feature = "neon_intrinsics", since = "1.59.0")
20433)]
20434#[cfg_attr(
20435    target_arch = "arm",
20436    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20437)]
20438pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
20439    let mut ret_val: poly8x16x2_t = transmute(vld2q_dup_s8(transmute(a)));
20440    ret_val.0 = unsafe {
20441        simd_shuffle!(
20442            ret_val.0,
20443            ret_val.0,
20444            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20445        )
20446    };
20447    ret_val.1 = unsafe {
20448        simd_shuffle!(
20449            ret_val.1,
20450            ret_val.1,
20451            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20452        )
20453    };
20454    ret_val
20455}
20456#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20457#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"]
20458#[doc = "## Safety"]
20459#[doc = "  * Neon instrinsic unsafe"]
20460#[inline]
20461#[cfg(target_endian = "little")]
20462#[target_feature(enable = "neon")]
20463#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20464#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20465#[cfg_attr(
20466    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20467    assert_instr(ld2r)
20468)]
20469#[cfg_attr(
20470    not(target_arch = "arm"),
20471    stable(feature = "neon_intrinsics", since = "1.59.0")
20472)]
20473#[cfg_attr(
20474    target_arch = "arm",
20475    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20476)]
20477pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
20478    transmute(vld2_dup_s16(transmute(a)))
20479}
20480#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20481#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"]
20482#[doc = "## Safety"]
20483#[doc = "  * Neon instrinsic unsafe"]
20484#[inline]
20485#[cfg(target_endian = "big")]
20486#[target_feature(enable = "neon")]
20487#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20488#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20489#[cfg_attr(
20490    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20491    assert_instr(ld2r)
20492)]
20493#[cfg_attr(
20494    not(target_arch = "arm"),
20495    stable(feature = "neon_intrinsics", since = "1.59.0")
20496)]
20497#[cfg_attr(
20498    target_arch = "arm",
20499    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20500)]
20501pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
20502    let mut ret_val: poly16x4x2_t = transmute(vld2_dup_s16(transmute(a)));
20503    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
20504    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
20505    ret_val
20506}
20507#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"]
20509#[doc = "## Safety"]
20510#[doc = "  * Neon instrinsic unsafe"]
20511#[inline]
20512#[cfg(target_endian = "little")]
20513#[target_feature(enable = "neon")]
20514#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20515#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20516#[cfg_attr(
20517    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20518    assert_instr(ld2r)
20519)]
20520#[cfg_attr(
20521    not(target_arch = "arm"),
20522    stable(feature = "neon_intrinsics", since = "1.59.0")
20523)]
20524#[cfg_attr(
20525    target_arch = "arm",
20526    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20527)]
20528pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
20529    transmute(vld2q_dup_s16(transmute(a)))
20530}
20531#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20532#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"]
20533#[doc = "## Safety"]
20534#[doc = "  * Neon instrinsic unsafe"]
20535#[inline]
20536#[cfg(target_endian = "big")]
20537#[target_feature(enable = "neon")]
20538#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20539#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20540#[cfg_attr(
20541    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20542    assert_instr(ld2r)
20543)]
20544#[cfg_attr(
20545    not(target_arch = "arm"),
20546    stable(feature = "neon_intrinsics", since = "1.59.0")
20547)]
20548#[cfg_attr(
20549    target_arch = "arm",
20550    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20551)]
20552pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
20553    let mut ret_val: poly16x8x2_t = transmute(vld2q_dup_s16(transmute(a)));
20554    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
20555    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
20556    ret_val
20557}
20558#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"]
20560#[doc = "## Safety"]
20561#[doc = "  * Neon instrinsic unsafe"]
20562#[inline]
20563#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20564#[cfg(target_arch = "arm")]
20565#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20566#[target_feature(enable = "neon,fp16")]
20567#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20568pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
20569    unsafe extern "unadjusted" {
20570        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4f16.p0")]
20571        fn _vld2_f16(ptr: *const f16, size: i32) -> float16x4x2_t;
20572    }
20573    _vld2_f16(a as _, 2)
20574}
20575#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"]
20577#[doc = "## Safety"]
20578#[doc = "  * Neon instrinsic unsafe"]
20579#[inline]
20580#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20581#[cfg(target_arch = "arm")]
20582#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20583#[target_feature(enable = "neon,fp16")]
20584#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20585pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t {
20586    unsafe extern "unadjusted" {
20587        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8f16.p0")]
20588        fn _vld2q_f16(ptr: *const f16, size: i32) -> float16x8x2_t;
20589    }
20590    _vld2q_f16(a as _, 2)
20591}
20592#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"]
20594#[doc = "## Safety"]
20595#[doc = "  * Neon instrinsic unsafe"]
20596#[inline]
20597#[cfg(not(target_arch = "arm"))]
20598#[cfg_attr(
20599    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20600    assert_instr(ld2)
20601)]
20602#[target_feature(enable = "neon,fp16")]
20603#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20604pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
20605    unsafe extern "unadjusted" {
20606        #[cfg_attr(
20607            any(target_arch = "aarch64", target_arch = "arm64ec"),
20608            link_name = "llvm.aarch64.neon.ld2.v4f16.p0"
20609        )]
20610        fn _vld2_f16(ptr: *const f16) -> float16x4x2_t;
20611    }
20612    _vld2_f16(a as _)
20613}
20614#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20615#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"]
20616#[doc = "## Safety"]
20617#[doc = "  * Neon instrinsic unsafe"]
20618#[inline]
20619#[cfg(not(target_arch = "arm"))]
20620#[cfg_attr(
20621    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20622    assert_instr(ld2)
20623)]
20624#[target_feature(enable = "neon,fp16")]
20625#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20626pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t {
20627    unsafe extern "unadjusted" {
20628        #[cfg_attr(
20629            any(target_arch = "aarch64", target_arch = "arm64ec"),
20630            link_name = "llvm.aarch64.neon.ld2.v8f16.p0"
20631        )]
20632        fn _vld2q_f16(ptr: *const f16) -> float16x8x2_t;
20633    }
20634    _vld2q_f16(a as _)
20635}
20636#[doc = "Load multiple 2-element structures to two registers"]
20637#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"]
20638#[doc = "## Safety"]
20639#[doc = "  * Neon instrinsic unsafe"]
20640#[inline]
20641#[target_feature(enable = "neon,v7")]
20642#[cfg(target_arch = "arm")]
20643#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20644#[cfg_attr(test, assert_instr(vld2))]
20645pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t {
20646    unsafe extern "unadjusted" {
20647        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v2f32")]
20648        fn _vld2_f32(ptr: *const i8, size: i32) -> float32x2x2_t;
20649    }
20650    _vld2_f32(a as *const i8, 4)
20651}
20652#[doc = "Load multiple 2-element structures to two registers"]
20653#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"]
20654#[doc = "## Safety"]
20655#[doc = "  * Neon instrinsic unsafe"]
20656#[inline]
20657#[target_feature(enable = "neon,v7")]
20658#[cfg(target_arch = "arm")]
20659#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20660#[cfg_attr(test, assert_instr(vld2))]
20661pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t {
20662    unsafe extern "unadjusted" {
20663        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4f32")]
20664        fn _vld2q_f32(ptr: *const i8, size: i32) -> float32x4x2_t;
20665    }
20666    _vld2q_f32(a as *const i8, 4)
20667}
20668#[doc = "Load multiple 2-element structures to two registers"]
20669#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"]
20670#[doc = "## Safety"]
20671#[doc = "  * Neon instrinsic unsafe"]
20672#[inline]
20673#[target_feature(enable = "neon,v7")]
20674#[cfg(target_arch = "arm")]
20675#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20676#[cfg_attr(test, assert_instr(vld2))]
20677pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t {
20678    unsafe extern "unadjusted" {
20679        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8i8")]
20680        fn _vld2_s8(ptr: *const i8, size: i32) -> int8x8x2_t;
20681    }
20682    _vld2_s8(a as *const i8, 1)
20683}
20684#[doc = "Load multiple 2-element structures to two registers"]
20685#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"]
20686#[doc = "## Safety"]
20687#[doc = "  * Neon instrinsic unsafe"]
20688#[inline]
20689#[target_feature(enable = "neon,v7")]
20690#[cfg(target_arch = "arm")]
20691#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20692#[cfg_attr(test, assert_instr(vld2))]
20693pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t {
20694    unsafe extern "unadjusted" {
20695        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v16i8")]
20696        fn _vld2q_s8(ptr: *const i8, size: i32) -> int8x16x2_t;
20697    }
20698    _vld2q_s8(a as *const i8, 1)
20699}
20700#[doc = "Load multiple 2-element structures to two registers"]
20701#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"]
20702#[doc = "## Safety"]
20703#[doc = "  * Neon instrinsic unsafe"]
20704#[inline]
20705#[target_feature(enable = "neon,v7")]
20706#[cfg(target_arch = "arm")]
20707#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20708#[cfg_attr(test, assert_instr(vld2))]
20709pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t {
20710    unsafe extern "unadjusted" {
20711        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4i16")]
20712        fn _vld2_s16(ptr: *const i8, size: i32) -> int16x4x2_t;
20713    }
20714    _vld2_s16(a as *const i8, 2)
20715}
20716#[doc = "Load multiple 2-element structures to two registers"]
20717#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"]
20718#[doc = "## Safety"]
20719#[doc = "  * Neon instrinsic unsafe"]
20720#[inline]
20721#[target_feature(enable = "neon,v7")]
20722#[cfg(target_arch = "arm")]
20723#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20724#[cfg_attr(test, assert_instr(vld2))]
20725pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t {
20726    unsafe extern "unadjusted" {
20727        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8i16")]
20728        fn _vld2q_s16(ptr: *const i8, size: i32) -> int16x8x2_t;
20729    }
20730    _vld2q_s16(a as *const i8, 2)
20731}
20732#[doc = "Load multiple 2-element structures to two registers"]
20733#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"]
20734#[doc = "## Safety"]
20735#[doc = "  * Neon instrinsic unsafe"]
20736#[inline]
20737#[target_feature(enable = "neon,v7")]
20738#[cfg(target_arch = "arm")]
20739#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20740#[cfg_attr(test, assert_instr(vld2))]
20741pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t {
20742    unsafe extern "unadjusted" {
20743        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v2i32")]
20744        fn _vld2_s32(ptr: *const i8, size: i32) -> int32x2x2_t;
20745    }
20746    _vld2_s32(a as *const i8, 4)
20747}
20748#[doc = "Load multiple 2-element structures to two registers"]
20749#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"]
20750#[doc = "## Safety"]
20751#[doc = "  * Neon instrinsic unsafe"]
20752#[inline]
20753#[target_feature(enable = "neon,v7")]
20754#[cfg(target_arch = "arm")]
20755#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20756#[cfg_attr(test, assert_instr(vld2))]
20757pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t {
20758    unsafe extern "unadjusted" {
20759        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4i32")]
20760        fn _vld2q_s32(ptr: *const i8, size: i32) -> int32x4x2_t;
20761    }
20762    _vld2q_s32(a as *const i8, 4)
20763}
20764#[doc = "Load multiple 2-element structures to two registers"]
20765#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"]
20766#[doc = "## Safety"]
20767#[doc = "  * Neon instrinsic unsafe"]
20768#[inline]
20769#[target_feature(enable = "neon")]
20770#[cfg(not(target_arch = "arm"))]
20771#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20772#[cfg_attr(test, assert_instr(ld2))]
20773pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t {
20774    unsafe extern "unadjusted" {
20775        #[cfg_attr(
20776            any(target_arch = "aarch64", target_arch = "arm64ec"),
20777            link_name = "llvm.aarch64.neon.ld2.v2f32.p0"
20778        )]
20779        fn _vld2_f32(ptr: *const float32x2_t) -> float32x2x2_t;
20780    }
20781    _vld2_f32(a as _)
20782}
20783#[doc = "Load multiple 2-element structures to two registers"]
20784#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"]
20785#[doc = "## Safety"]
20786#[doc = "  * Neon instrinsic unsafe"]
20787#[inline]
20788#[target_feature(enable = "neon")]
20789#[cfg(not(target_arch = "arm"))]
20790#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20791#[cfg_attr(test, assert_instr(ld2))]
20792pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t {
20793    unsafe extern "unadjusted" {
20794        #[cfg_attr(
20795            any(target_arch = "aarch64", target_arch = "arm64ec"),
20796            link_name = "llvm.aarch64.neon.ld2.v4f32.p0"
20797        )]
20798        fn _vld2q_f32(ptr: *const float32x4_t) -> float32x4x2_t;
20799    }
20800    _vld2q_f32(a as _)
20801}
20802#[doc = "Load multiple 2-element structures to two registers"]
20803#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"]
20804#[doc = "## Safety"]
20805#[doc = "  * Neon instrinsic unsafe"]
20806#[inline]
20807#[target_feature(enable = "neon")]
20808#[cfg(not(target_arch = "arm"))]
20809#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20810#[cfg_attr(test, assert_instr(ld2))]
20811pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t {
20812    unsafe extern "unadjusted" {
20813        #[cfg_attr(
20814            any(target_arch = "aarch64", target_arch = "arm64ec"),
20815            link_name = "llvm.aarch64.neon.ld2.v8i8.p0"
20816        )]
20817        fn _vld2_s8(ptr: *const int8x8_t) -> int8x8x2_t;
20818    }
20819    _vld2_s8(a as _)
20820}
20821#[doc = "Load multiple 2-element structures to two registers"]
20822#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"]
20823#[doc = "## Safety"]
20824#[doc = "  * Neon instrinsic unsafe"]
20825#[inline]
20826#[target_feature(enable = "neon")]
20827#[cfg(not(target_arch = "arm"))]
20828#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20829#[cfg_attr(test, assert_instr(ld2))]
20830pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t {
20831    unsafe extern "unadjusted" {
20832        #[cfg_attr(
20833            any(target_arch = "aarch64", target_arch = "arm64ec"),
20834            link_name = "llvm.aarch64.neon.ld2.v16i8.p0"
20835        )]
20836        fn _vld2q_s8(ptr: *const int8x16_t) -> int8x16x2_t;
20837    }
20838    _vld2q_s8(a as _)
20839}
20840#[doc = "Load multiple 2-element structures to two registers"]
20841#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"]
20842#[doc = "## Safety"]
20843#[doc = "  * Neon instrinsic unsafe"]
20844#[inline]
20845#[target_feature(enable = "neon")]
20846#[cfg(not(target_arch = "arm"))]
20847#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20848#[cfg_attr(test, assert_instr(ld2))]
20849pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t {
20850    unsafe extern "unadjusted" {
20851        #[cfg_attr(
20852            any(target_arch = "aarch64", target_arch = "arm64ec"),
20853            link_name = "llvm.aarch64.neon.ld2.v4i16.p0"
20854        )]
20855        fn _vld2_s16(ptr: *const int16x4_t) -> int16x4x2_t;
20856    }
20857    _vld2_s16(a as _)
20858}
20859#[doc = "Load multiple 2-element structures to two registers"]
20860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"]
20861#[doc = "## Safety"]
20862#[doc = "  * Neon instrinsic unsafe"]
20863#[inline]
20864#[target_feature(enable = "neon")]
20865#[cfg(not(target_arch = "arm"))]
20866#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20867#[cfg_attr(test, assert_instr(ld2))]
20868pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t {
20869    unsafe extern "unadjusted" {
20870        #[cfg_attr(
20871            any(target_arch = "aarch64", target_arch = "arm64ec"),
20872            link_name = "llvm.aarch64.neon.ld2.v8i16.p0"
20873        )]
20874        fn _vld2q_s16(ptr: *const int16x8_t) -> int16x8x2_t;
20875    }
20876    _vld2q_s16(a as _)
20877}
20878#[doc = "Load multiple 2-element structures to two registers"]
20879#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"]
20880#[doc = "## Safety"]
20881#[doc = "  * Neon instrinsic unsafe"]
20882#[inline]
20883#[target_feature(enable = "neon")]
20884#[cfg(not(target_arch = "arm"))]
20885#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20886#[cfg_attr(test, assert_instr(ld2))]
20887pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t {
20888    unsafe extern "unadjusted" {
20889        #[cfg_attr(
20890            any(target_arch = "aarch64", target_arch = "arm64ec"),
20891            link_name = "llvm.aarch64.neon.ld2.v2i32.p0"
20892        )]
20893        fn _vld2_s32(ptr: *const int32x2_t) -> int32x2x2_t;
20894    }
20895    _vld2_s32(a as _)
20896}
20897#[doc = "Load multiple 2-element structures to two registers"]
20898#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"]
20899#[doc = "## Safety"]
20900#[doc = "  * Neon instrinsic unsafe"]
20901#[inline]
20902#[target_feature(enable = "neon")]
20903#[cfg(not(target_arch = "arm"))]
20904#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20905#[cfg_attr(test, assert_instr(ld2))]
20906pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t {
20907    unsafe extern "unadjusted" {
20908        #[cfg_attr(
20909            any(target_arch = "aarch64", target_arch = "arm64ec"),
20910            link_name = "llvm.aarch64.neon.ld2.v4i32.p0"
20911        )]
20912        fn _vld2q_s32(ptr: *const int32x4_t) -> int32x4x2_t;
20913    }
20914    _vld2q_s32(a as _)
20915}
20916#[doc = "Load multiple 2-element structures to two registers"]
20917#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"]
20918#[doc = "## Safety"]
20919#[doc = "  * Neon instrinsic unsafe"]
20920#[inline]
20921#[target_feature(enable = "neon,v7")]
20922#[cfg(target_arch = "arm")]
20923#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
20924#[rustc_legacy_const_generics(2)]
20925#[target_feature(enable = "neon,fp16")]
20926#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20927pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) -> float16x4x2_t {
20928    static_assert_uimm_bits!(LANE, 2);
20929    unsafe extern "unadjusted" {
20930        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4f16.p0")]
20931        fn _vld2_lane_f16(
20932            ptr: *const f16,
20933            a: float16x4_t,
20934            b: float16x4_t,
20935            n: i32,
20936            size: i32,
20937        ) -> float16x4x2_t;
20938    }
20939    _vld2_lane_f16(a as _, b.0, b.1, LANE, 2)
20940}
20941#[doc = "Load multiple 2-element structures to two registers"]
20942#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"]
20943#[doc = "## Safety"]
20944#[doc = "  * Neon instrinsic unsafe"]
20945#[inline]
20946#[target_feature(enable = "neon,v7")]
20947#[cfg(target_arch = "arm")]
20948#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
20949#[rustc_legacy_const_generics(2)]
20950#[target_feature(enable = "neon,fp16")]
20951#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20952pub unsafe fn vld2q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x2_t) -> float16x8x2_t {
20953    static_assert_uimm_bits!(LANE, 3);
20954    unsafe extern "unadjusted" {
20955        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8f16.p0")]
20956        fn _vld2q_lane_f16(
20957            ptr: *const f16,
20958            a: float16x8_t,
20959            b: float16x8_t,
20960            n: i32,
20961            size: i32,
20962        ) -> float16x8x2_t;
20963    }
20964    _vld2q_lane_f16(a as _, b.0, b.1, LANE, 2)
20965}
20966#[doc = "Load multiple 2-element structures to two registers"]
20967#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"]
20968#[doc = "## Safety"]
20969#[doc = "  * Neon instrinsic unsafe"]
20970#[inline]
20971#[cfg(not(target_arch = "arm"))]
20972#[cfg_attr(
20973    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20974    assert_instr(ld2, LANE = 0)
20975)]
20976#[rustc_legacy_const_generics(2)]
20977#[target_feature(enable = "neon,fp16")]
20978#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20979pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) -> float16x4x2_t {
20980    static_assert_uimm_bits!(LANE, 2);
20981    unsafe extern "unadjusted" {
20982        #[cfg_attr(
20983            any(target_arch = "aarch64", target_arch = "arm64ec"),
20984            link_name = "llvm.aarch64.neon.ld2lane.v4f16.p0"
20985        )]
20986        fn _vld2_lane_f16(a: float16x4_t, b: float16x4_t, n: i64, ptr: *const f16)
20987            -> float16x4x2_t;
20988    }
20989    _vld2_lane_f16(b.0, b.1, LANE as i64, a as _)
20990}
20991#[doc = "Load multiple 2-element structures to two registers"]
20992#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"]
20993#[doc = "## Safety"]
20994#[doc = "  * Neon instrinsic unsafe"]
20995#[inline]
20996#[cfg(not(target_arch = "arm"))]
20997#[cfg_attr(
20998    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20999    assert_instr(ld2, LANE = 0)
21000)]
21001#[rustc_legacy_const_generics(2)]
21002#[target_feature(enable = "neon,fp16")]
21003#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
21004pub unsafe fn vld2q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x2_t) -> float16x8x2_t {
21005    static_assert_uimm_bits!(LANE, 3);
21006    unsafe extern "unadjusted" {
21007        #[cfg_attr(
21008            any(target_arch = "aarch64", target_arch = "arm64ec"),
21009            link_name = "llvm.aarch64.neon.ld2lane.v8f16.p0"
21010        )]
21011        fn _vld2q_lane_f16(
21012            a: float16x8_t,
21013            b: float16x8_t,
21014            n: i64,
21015            ptr: *const f16,
21016        ) -> float16x8x2_t;
21017    }
21018    _vld2q_lane_f16(b.0, b.1, LANE as i64, a as _)
21019}
21020#[doc = "Load multiple 2-element structures to two registers"]
21021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"]
21022#[doc = "## Safety"]
21023#[doc = "  * Neon instrinsic unsafe"]
21024#[inline]
21025#[target_feature(enable = "neon")]
21026#[cfg(not(target_arch = "arm"))]
21027#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21028#[rustc_legacy_const_generics(2)]
21029#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21030pub unsafe fn vld2_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x2_t) -> float32x2x2_t {
21031    static_assert_uimm_bits!(LANE, 2);
21032    unsafe extern "unadjusted" {
21033        #[cfg_attr(
21034            any(target_arch = "aarch64", target_arch = "arm64ec"),
21035            link_name = "llvm.aarch64.neon.ld2lane.v2f32.p0"
21036        )]
21037        fn _vld2_lane_f32(a: float32x2_t, b: float32x2_t, n: i64, ptr: *const i8) -> float32x2x2_t;
21038    }
21039    _vld2_lane_f32(b.0, b.1, LANE as i64, a as _)
21040}
21041#[doc = "Load multiple 2-element structures to two registers"]
21042#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"]
21043#[doc = "## Safety"]
21044#[doc = "  * Neon instrinsic unsafe"]
21045#[inline]
21046#[target_feature(enable = "neon")]
21047#[cfg(not(target_arch = "arm"))]
21048#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21049#[rustc_legacy_const_generics(2)]
21050#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21051pub unsafe fn vld2q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x2_t) -> float32x4x2_t {
21052    static_assert_uimm_bits!(LANE, 2);
21053    unsafe extern "unadjusted" {
21054        #[cfg_attr(
21055            any(target_arch = "aarch64", target_arch = "arm64ec"),
21056            link_name = "llvm.aarch64.neon.ld2lane.v4f32.p0"
21057        )]
21058        fn _vld2q_lane_f32(a: float32x4_t, b: float32x4_t, n: i64, ptr: *const i8)
21059            -> float32x4x2_t;
21060    }
21061    _vld2q_lane_f32(b.0, b.1, LANE as i64, a as _)
21062}
21063#[doc = "Load multiple 2-element structures to two registers"]
21064#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"]
21065#[doc = "## Safety"]
21066#[doc = "  * Neon instrinsic unsafe"]
21067#[inline]
21068#[target_feature(enable = "neon")]
21069#[cfg(not(target_arch = "arm"))]
21070#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21071#[rustc_legacy_const_generics(2)]
21072#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21073pub unsafe fn vld2_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x2_t) -> int8x8x2_t {
21074    static_assert_uimm_bits!(LANE, 3);
21075    unsafe extern "unadjusted" {
21076        #[cfg_attr(
21077            any(target_arch = "aarch64", target_arch = "arm64ec"),
21078            link_name = "llvm.aarch64.neon.ld2lane.v8i8.p0"
21079        )]
21080        fn _vld2_lane_s8(a: int8x8_t, b: int8x8_t, n: i64, ptr: *const i8) -> int8x8x2_t;
21081    }
21082    _vld2_lane_s8(b.0, b.1, LANE as i64, a as _)
21083}
21084#[doc = "Load multiple 2-element structures to two registers"]
21085#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"]
21086#[doc = "## Safety"]
21087#[doc = "  * Neon instrinsic unsafe"]
21088#[inline]
21089#[target_feature(enable = "neon")]
21090#[cfg(not(target_arch = "arm"))]
21091#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21092#[rustc_legacy_const_generics(2)]
21093#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21094pub unsafe fn vld2_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x2_t) -> int16x4x2_t {
21095    static_assert_uimm_bits!(LANE, 2);
21096    unsafe extern "unadjusted" {
21097        #[cfg_attr(
21098            any(target_arch = "aarch64", target_arch = "arm64ec"),
21099            link_name = "llvm.aarch64.neon.ld2lane.v4i16.p0"
21100        )]
21101        fn _vld2_lane_s16(a: int16x4_t, b: int16x4_t, n: i64, ptr: *const i8) -> int16x4x2_t;
21102    }
21103    _vld2_lane_s16(b.0, b.1, LANE as i64, a as _)
21104}
21105#[doc = "Load multiple 2-element structures to two registers"]
21106#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"]
21107#[doc = "## Safety"]
21108#[doc = "  * Neon instrinsic unsafe"]
21109#[inline]
21110#[target_feature(enable = "neon")]
21111#[cfg(not(target_arch = "arm"))]
21112#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21113#[rustc_legacy_const_generics(2)]
21114#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21115pub unsafe fn vld2q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x2_t) -> int16x8x2_t {
21116    static_assert_uimm_bits!(LANE, 3);
21117    unsafe extern "unadjusted" {
21118        #[cfg_attr(
21119            any(target_arch = "aarch64", target_arch = "arm64ec"),
21120            link_name = "llvm.aarch64.neon.ld2lane.v8i16.p0"
21121        )]
21122        fn _vld2q_lane_s16(a: int16x8_t, b: int16x8_t, n: i64, ptr: *const i8) -> int16x8x2_t;
21123    }
21124    _vld2q_lane_s16(b.0, b.1, LANE as i64, a as _)
21125}
21126#[doc = "Load multiple 2-element structures to two registers"]
21127#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"]
21128#[doc = "## Safety"]
21129#[doc = "  * Neon instrinsic unsafe"]
21130#[inline]
21131#[target_feature(enable = "neon")]
21132#[cfg(not(target_arch = "arm"))]
21133#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21134#[rustc_legacy_const_generics(2)]
21135#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21136pub unsafe fn vld2_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x2_t) -> int32x2x2_t {
21137    static_assert_uimm_bits!(LANE, 1);
21138    unsafe extern "unadjusted" {
21139        #[cfg_attr(
21140            any(target_arch = "aarch64", target_arch = "arm64ec"),
21141            link_name = "llvm.aarch64.neon.ld2lane.v2i32.p0"
21142        )]
21143        fn _vld2_lane_s32(a: int32x2_t, b: int32x2_t, n: i64, ptr: *const i8) -> int32x2x2_t;
21144    }
21145    _vld2_lane_s32(b.0, b.1, LANE as i64, a as _)
21146}
21147#[doc = "Load multiple 2-element structures to two registers"]
21148#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"]
21149#[doc = "## Safety"]
21150#[doc = "  * Neon instrinsic unsafe"]
21151#[inline]
21152#[target_feature(enable = "neon")]
21153#[cfg(not(target_arch = "arm"))]
21154#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21155#[rustc_legacy_const_generics(2)]
21156#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21157pub unsafe fn vld2q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x2_t) -> int32x4x2_t {
21158    static_assert_uimm_bits!(LANE, 2);
21159    unsafe extern "unadjusted" {
21160        #[cfg_attr(
21161            any(target_arch = "aarch64", target_arch = "arm64ec"),
21162            link_name = "llvm.aarch64.neon.ld2lane.v4i32.p0"
21163        )]
21164        fn _vld2q_lane_s32(a: int32x4_t, b: int32x4_t, n: i64, ptr: *const i8) -> int32x4x2_t;
21165    }
21166    _vld2q_lane_s32(b.0, b.1, LANE as i64, a as _)
21167}
21168#[doc = "Load multiple 2-element structures to two registers"]
21169#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"]
21170#[doc = "## Safety"]
21171#[doc = "  * Neon instrinsic unsafe"]
21172#[inline]
21173#[target_feature(enable = "neon,v7")]
21174#[cfg(target_arch = "arm")]
21175#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21176#[rustc_legacy_const_generics(2)]
21177#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21178pub unsafe fn vld2_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x2_t) -> float32x2x2_t {
21179    static_assert_uimm_bits!(LANE, 1);
21180    unsafe extern "unadjusted" {
21181        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v2f32.p0")]
21182        fn _vld2_lane_f32(
21183            ptr: *const i8,
21184            a: float32x2_t,
21185            b: float32x2_t,
21186            n: i32,
21187            size: i32,
21188        ) -> float32x2x2_t;
21189    }
21190    _vld2_lane_f32(a as _, b.0, b.1, LANE, 4)
21191}
21192#[doc = "Load multiple 2-element structures to two registers"]
21193#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"]
21194#[doc = "## Safety"]
21195#[doc = "  * Neon instrinsic unsafe"]
21196#[inline]
21197#[target_feature(enable = "neon,v7")]
21198#[cfg(target_arch = "arm")]
21199#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21200#[rustc_legacy_const_generics(2)]
21201#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21202pub unsafe fn vld2q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x2_t) -> float32x4x2_t {
21203    static_assert_uimm_bits!(LANE, 2);
21204    unsafe extern "unadjusted" {
21205        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4f32.p0")]
21206        fn _vld2q_lane_f32(
21207            ptr: *const i8,
21208            a: float32x4_t,
21209            b: float32x4_t,
21210            n: i32,
21211            size: i32,
21212        ) -> float32x4x2_t;
21213    }
21214    _vld2q_lane_f32(a as _, b.0, b.1, LANE, 4)
21215}
21216#[doc = "Load multiple 2-element structures to two registers"]
21217#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"]
21218#[doc = "## Safety"]
21219#[doc = "  * Neon instrinsic unsafe"]
21220#[inline]
21221#[target_feature(enable = "neon,v7")]
21222#[cfg(target_arch = "arm")]
21223#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21224#[rustc_legacy_const_generics(2)]
21225#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21226pub unsafe fn vld2q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x2_t) -> int16x8x2_t {
21227    static_assert_uimm_bits!(LANE, 3);
21228    unsafe extern "unadjusted" {
21229        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8i16.p0")]
21230        fn _vld2q_lane_s16(
21231            ptr: *const i8,
21232            a: int16x8_t,
21233            b: int16x8_t,
21234            n: i32,
21235            size: i32,
21236        ) -> int16x8x2_t;
21237    }
21238    _vld2q_lane_s16(a as _, b.0, b.1, LANE, 2)
21239}
21240#[doc = "Load multiple 2-element structures to two registers"]
21241#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"]
21242#[doc = "## Safety"]
21243#[doc = "  * Neon instrinsic unsafe"]
21244#[inline]
21245#[target_feature(enable = "neon,v7")]
21246#[cfg(target_arch = "arm")]
21247#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21248#[rustc_legacy_const_generics(2)]
21249#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21250pub unsafe fn vld2q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x2_t) -> int32x4x2_t {
21251    static_assert_uimm_bits!(LANE, 2);
21252    unsafe extern "unadjusted" {
21253        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4i32.p0")]
21254        fn _vld2q_lane_s32(
21255            ptr: *const i8,
21256            a: int32x4_t,
21257            b: int32x4_t,
21258            n: i32,
21259            size: i32,
21260        ) -> int32x4x2_t;
21261    }
21262    _vld2q_lane_s32(a as _, b.0, b.1, LANE, 4)
21263}
21264#[doc = "Load multiple 2-element structures to two registers"]
21265#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"]
21266#[doc = "## Safety"]
21267#[doc = "  * Neon instrinsic unsafe"]
21268#[inline]
21269#[target_feature(enable = "neon,v7")]
21270#[cfg(target_arch = "arm")]
21271#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21272#[rustc_legacy_const_generics(2)]
21273#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21274pub unsafe fn vld2_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x2_t) -> int8x8x2_t {
21275    static_assert_uimm_bits!(LANE, 3);
21276    unsafe extern "unadjusted" {
21277        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8i8.p0")]
21278        fn _vld2_lane_s8(ptr: *const i8, a: int8x8_t, b: int8x8_t, n: i32, size: i32)
21279            -> int8x8x2_t;
21280    }
21281    _vld2_lane_s8(a as _, b.0, b.1, LANE, 1)
21282}
21283#[doc = "Load multiple 2-element structures to two registers"]
21284#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"]
21285#[doc = "## Safety"]
21286#[doc = "  * Neon instrinsic unsafe"]
21287#[inline]
21288#[target_feature(enable = "neon,v7")]
21289#[cfg(target_arch = "arm")]
21290#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21291#[rustc_legacy_const_generics(2)]
21292#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21293pub unsafe fn vld2_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x2_t) -> int16x4x2_t {
21294    static_assert_uimm_bits!(LANE, 2);
21295    unsafe extern "unadjusted" {
21296        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4i16.p0")]
21297        fn _vld2_lane_s16(
21298            ptr: *const i8,
21299            a: int16x4_t,
21300            b: int16x4_t,
21301            n: i32,
21302            size: i32,
21303        ) -> int16x4x2_t;
21304    }
21305    _vld2_lane_s16(a as _, b.0, b.1, LANE, 2)
21306}
21307#[doc = "Load multiple 2-element structures to two registers"]
21308#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"]
21309#[doc = "## Safety"]
21310#[doc = "  * Neon instrinsic unsafe"]
21311#[inline]
21312#[target_feature(enable = "neon,v7")]
21313#[cfg(target_arch = "arm")]
21314#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21315#[rustc_legacy_const_generics(2)]
21316#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21317pub unsafe fn vld2_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x2_t) -> int32x2x2_t {
21318    static_assert_uimm_bits!(LANE, 1);
21319    unsafe extern "unadjusted" {
21320        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v2i32.p0")]
21321        fn _vld2_lane_s32(
21322            ptr: *const i8,
21323            a: int32x2_t,
21324            b: int32x2_t,
21325            n: i32,
21326            size: i32,
21327        ) -> int32x2x2_t;
21328    }
21329    _vld2_lane_s32(a as _, b.0, b.1, LANE, 4)
21330}
21331#[doc = "Load multiple 2-element structures to two registers"]
21332#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u8)"]
21333#[doc = "## Safety"]
21334#[doc = "  * Neon instrinsic unsafe"]
21335#[inline]
21336#[target_feature(enable = "neon")]
21337#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21338#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21339#[cfg_attr(
21340    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21341    assert_instr(ld2, LANE = 0)
21342)]
21343#[rustc_legacy_const_generics(2)]
21344#[cfg_attr(
21345    not(target_arch = "arm"),
21346    stable(feature = "neon_intrinsics", since = "1.59.0")
21347)]
21348#[cfg_attr(
21349    target_arch = "arm",
21350    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21351)]
21352pub unsafe fn vld2_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x2_t) -> uint8x8x2_t {
21353    static_assert_uimm_bits!(LANE, 3);
21354    transmute(vld2_lane_s8::<LANE>(transmute(a), transmute(b)))
21355}
21356#[doc = "Load multiple 2-element structures to two registers"]
21357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u16)"]
21358#[doc = "## Safety"]
21359#[doc = "  * Neon instrinsic unsafe"]
21360#[inline]
21361#[target_feature(enable = "neon")]
21362#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21363#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21364#[cfg_attr(
21365    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21366    assert_instr(ld2, LANE = 0)
21367)]
21368#[rustc_legacy_const_generics(2)]
21369#[cfg_attr(
21370    not(target_arch = "arm"),
21371    stable(feature = "neon_intrinsics", since = "1.59.0")
21372)]
21373#[cfg_attr(
21374    target_arch = "arm",
21375    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21376)]
21377pub unsafe fn vld2_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x2_t) -> uint16x4x2_t {
21378    static_assert_uimm_bits!(LANE, 2);
21379    transmute(vld2_lane_s16::<LANE>(transmute(a), transmute(b)))
21380}
21381#[doc = "Load multiple 2-element structures to two registers"]
21382#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u16)"]
21383#[doc = "## Safety"]
21384#[doc = "  * Neon instrinsic unsafe"]
21385#[inline]
21386#[target_feature(enable = "neon")]
21387#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21388#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21389#[cfg_attr(
21390    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21391    assert_instr(ld2, LANE = 0)
21392)]
21393#[rustc_legacy_const_generics(2)]
21394#[cfg_attr(
21395    not(target_arch = "arm"),
21396    stable(feature = "neon_intrinsics", since = "1.59.0")
21397)]
21398#[cfg_attr(
21399    target_arch = "arm",
21400    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21401)]
21402pub unsafe fn vld2q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x2_t) -> uint16x8x2_t {
21403    static_assert_uimm_bits!(LANE, 3);
21404    transmute(vld2q_lane_s16::<LANE>(transmute(a), transmute(b)))
21405}
21406#[doc = "Load multiple 2-element structures to two registers"]
21407#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u32)"]
21408#[doc = "## Safety"]
21409#[doc = "  * Neon instrinsic unsafe"]
21410#[inline]
21411#[target_feature(enable = "neon")]
21412#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21413#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21414#[cfg_attr(
21415    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21416    assert_instr(ld2, LANE = 0)
21417)]
21418#[rustc_legacy_const_generics(2)]
21419#[cfg_attr(
21420    not(target_arch = "arm"),
21421    stable(feature = "neon_intrinsics", since = "1.59.0")
21422)]
21423#[cfg_attr(
21424    target_arch = "arm",
21425    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21426)]
21427pub unsafe fn vld2_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x2_t) -> uint32x2x2_t {
21428    static_assert_uimm_bits!(LANE, 1);
21429    transmute(vld2_lane_s32::<LANE>(transmute(a), transmute(b)))
21430}
21431#[doc = "Load multiple 2-element structures to two registers"]
21432#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u32)"]
21433#[doc = "## Safety"]
21434#[doc = "  * Neon instrinsic unsafe"]
21435#[inline]
21436#[target_feature(enable = "neon")]
21437#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21438#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21439#[cfg_attr(
21440    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21441    assert_instr(ld2, LANE = 0)
21442)]
21443#[rustc_legacy_const_generics(2)]
21444#[cfg_attr(
21445    not(target_arch = "arm"),
21446    stable(feature = "neon_intrinsics", since = "1.59.0")
21447)]
21448#[cfg_attr(
21449    target_arch = "arm",
21450    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21451)]
21452pub unsafe fn vld2q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x2_t) -> uint32x4x2_t {
21453    static_assert_uimm_bits!(LANE, 2);
21454    transmute(vld2q_lane_s32::<LANE>(transmute(a), transmute(b)))
21455}
21456#[doc = "Load multiple 2-element structures to two registers"]
21457#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p8)"]
21458#[doc = "## Safety"]
21459#[doc = "  * Neon instrinsic unsafe"]
21460#[inline]
21461#[target_feature(enable = "neon")]
21462#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21463#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21464#[cfg_attr(
21465    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21466    assert_instr(ld2, LANE = 0)
21467)]
21468#[rustc_legacy_const_generics(2)]
21469#[cfg_attr(
21470    not(target_arch = "arm"),
21471    stable(feature = "neon_intrinsics", since = "1.59.0")
21472)]
21473#[cfg_attr(
21474    target_arch = "arm",
21475    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21476)]
21477pub unsafe fn vld2_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x2_t) -> poly8x8x2_t {
21478    static_assert_uimm_bits!(LANE, 3);
21479    transmute(vld2_lane_s8::<LANE>(transmute(a), transmute(b)))
21480}
21481#[doc = "Load multiple 2-element structures to two registers"]
21482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p16)"]
21483#[doc = "## Safety"]
21484#[doc = "  * Neon instrinsic unsafe"]
21485#[inline]
21486#[target_feature(enable = "neon")]
21487#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21488#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21489#[cfg_attr(
21490    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21491    assert_instr(ld2, LANE = 0)
21492)]
21493#[rustc_legacy_const_generics(2)]
21494#[cfg_attr(
21495    not(target_arch = "arm"),
21496    stable(feature = "neon_intrinsics", since = "1.59.0")
21497)]
21498#[cfg_attr(
21499    target_arch = "arm",
21500    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21501)]
21502pub unsafe fn vld2_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x2_t) -> poly16x4x2_t {
21503    static_assert_uimm_bits!(LANE, 2);
21504    transmute(vld2_lane_s16::<LANE>(transmute(a), transmute(b)))
21505}
21506#[doc = "Load multiple 2-element structures to two registers"]
21507#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p16)"]
21508#[doc = "## Safety"]
21509#[doc = "  * Neon instrinsic unsafe"]
21510#[inline]
21511#[target_feature(enable = "neon")]
21512#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21513#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21514#[cfg_attr(
21515    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21516    assert_instr(ld2, LANE = 0)
21517)]
21518#[rustc_legacy_const_generics(2)]
21519#[cfg_attr(
21520    not(target_arch = "arm"),
21521    stable(feature = "neon_intrinsics", since = "1.59.0")
21522)]
21523#[cfg_attr(
21524    target_arch = "arm",
21525    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21526)]
21527pub unsafe fn vld2q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x2_t) -> poly16x8x2_t {
21528    static_assert_uimm_bits!(LANE, 3);
21529    transmute(vld2q_lane_s16::<LANE>(transmute(a), transmute(b)))
21530}
21531#[doc = "Load multiple 2-element structures to two registers"]
21532#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p64)"]
21533#[doc = "## Safety"]
21534#[doc = "  * Neon instrinsic unsafe"]
21535#[inline]
21536#[target_feature(enable = "neon,aes")]
21537#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
21538#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
21539#[cfg_attr(
21540    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21541    assert_instr(nop)
21542)]
21543#[cfg_attr(
21544    not(target_arch = "arm"),
21545    stable(feature = "neon_intrinsics", since = "1.59.0")
21546)]
21547#[cfg_attr(
21548    target_arch = "arm",
21549    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21550)]
21551pub unsafe fn vld2_p64(a: *const p64) -> poly64x1x2_t {
21552    transmute(vld2_s64(transmute(a)))
21553}
21554#[doc = "Load multiple 2-element structures to two registers"]
21555#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"]
21556#[doc = "## Safety"]
21557#[doc = "  * Neon instrinsic unsafe"]
21558#[inline]
21559#[target_feature(enable = "neon,v7")]
21560#[cfg(target_arch = "arm")]
21561#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21562#[cfg_attr(test, assert_instr(nop))]
21563pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t {
21564    unsafe extern "unadjusted" {
21565        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v1i64")]
21566        fn _vld2_s64(ptr: *const i8, size: i32) -> int64x1x2_t;
21567    }
21568    _vld2_s64(a as *const i8, 8)
21569}
21570#[doc = "Load multiple 2-element structures to two registers"]
21571#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"]
21572#[doc = "## Safety"]
21573#[doc = "  * Neon instrinsic unsafe"]
21574#[inline]
21575#[target_feature(enable = "neon")]
21576#[cfg(not(target_arch = "arm"))]
21577#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21578#[cfg_attr(test, assert_instr(nop))]
21579pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t {
21580    unsafe extern "unadjusted" {
21581        #[cfg_attr(
21582            any(target_arch = "aarch64", target_arch = "arm64ec"),
21583            link_name = "llvm.aarch64.neon.ld2.v1i64.p0"
21584        )]
21585        fn _vld2_s64(ptr: *const int64x1_t) -> int64x1x2_t;
21586    }
21587    _vld2_s64(a as _)
21588}
21589#[doc = "Load multiple 2-element structures to two registers"]
21590#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u64)"]
21591#[doc = "## Safety"]
21592#[doc = "  * Neon instrinsic unsafe"]
21593#[inline]
21594#[target_feature(enable = "neon")]
21595#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21596#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
21597#[cfg_attr(
21598    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21599    assert_instr(nop)
21600)]
21601#[cfg_attr(
21602    not(target_arch = "arm"),
21603    stable(feature = "neon_intrinsics", since = "1.59.0")
21604)]
21605#[cfg_attr(
21606    target_arch = "arm",
21607    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21608)]
21609pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t {
21610    transmute(vld2_s64(transmute(a)))
21611}
21612#[doc = "Load multiple 2-element structures to two registers"]
21613#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"]
21614#[doc = "## Safety"]
21615#[doc = "  * Neon instrinsic unsafe"]
21616#[inline]
21617#[cfg(target_endian = "little")]
21618#[target_feature(enable = "neon")]
21619#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21620#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21621#[cfg_attr(
21622    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21623    assert_instr(ld2)
21624)]
21625#[cfg_attr(
21626    not(target_arch = "arm"),
21627    stable(feature = "neon_intrinsics", since = "1.59.0")
21628)]
21629#[cfg_attr(
21630    target_arch = "arm",
21631    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21632)]
21633pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t {
21634    transmute(vld2_s8(transmute(a)))
21635}
21636#[doc = "Load multiple 2-element structures to two registers"]
21637#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"]
21638#[doc = "## Safety"]
21639#[doc = "  * Neon instrinsic unsafe"]
21640#[inline]
21641#[cfg(target_endian = "big")]
21642#[target_feature(enable = "neon")]
21643#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21644#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21645#[cfg_attr(
21646    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21647    assert_instr(ld2)
21648)]
21649#[cfg_attr(
21650    not(target_arch = "arm"),
21651    stable(feature = "neon_intrinsics", since = "1.59.0")
21652)]
21653#[cfg_attr(
21654    target_arch = "arm",
21655    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21656)]
21657pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t {
21658    let mut ret_val: uint8x8x2_t = transmute(vld2_s8(transmute(a)));
21659    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
21660    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
21661    ret_val
21662}
21663#[doc = "Load multiple 2-element structures to two registers"]
21664#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"]
21665#[doc = "## Safety"]
21666#[doc = "  * Neon instrinsic unsafe"]
21667#[inline]
21668#[cfg(target_endian = "little")]
21669#[target_feature(enable = "neon")]
21670#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21671#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21672#[cfg_attr(
21673    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21674    assert_instr(ld2)
21675)]
21676#[cfg_attr(
21677    not(target_arch = "arm"),
21678    stable(feature = "neon_intrinsics", since = "1.59.0")
21679)]
21680#[cfg_attr(
21681    target_arch = "arm",
21682    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21683)]
21684pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
21685    transmute(vld2q_s8(transmute(a)))
21686}
21687#[doc = "Load multiple 2-element structures to two registers"]
21688#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"]
21689#[doc = "## Safety"]
21690#[doc = "  * Neon instrinsic unsafe"]
21691#[inline]
21692#[cfg(target_endian = "big")]
21693#[target_feature(enable = "neon")]
21694#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21695#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21696#[cfg_attr(
21697    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21698    assert_instr(ld2)
21699)]
21700#[cfg_attr(
21701    not(target_arch = "arm"),
21702    stable(feature = "neon_intrinsics", since = "1.59.0")
21703)]
21704#[cfg_attr(
21705    target_arch = "arm",
21706    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21707)]
21708pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
21709    let mut ret_val: uint8x16x2_t = transmute(vld2q_s8(transmute(a)));
21710    ret_val.0 = unsafe {
21711        simd_shuffle!(
21712            ret_val.0,
21713            ret_val.0,
21714            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
21715        )
21716    };
21717    ret_val.1 = unsafe {
21718        simd_shuffle!(
21719            ret_val.1,
21720            ret_val.1,
21721            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
21722        )
21723    };
21724    ret_val
21725}
21726#[doc = "Load multiple 2-element structures to two registers"]
21727#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"]
21728#[doc = "## Safety"]
21729#[doc = "  * Neon instrinsic unsafe"]
21730#[inline]
21731#[cfg(target_endian = "little")]
21732#[target_feature(enable = "neon")]
21733#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21734#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21735#[cfg_attr(
21736    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21737    assert_instr(ld2)
21738)]
21739#[cfg_attr(
21740    not(target_arch = "arm"),
21741    stable(feature = "neon_intrinsics", since = "1.59.0")
21742)]
21743#[cfg_attr(
21744    target_arch = "arm",
21745    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21746)]
21747pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
21748    transmute(vld2_s16(transmute(a)))
21749}
21750#[doc = "Load multiple 2-element structures to two registers"]
21751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"]
21752#[doc = "## Safety"]
21753#[doc = "  * Neon instrinsic unsafe"]
21754#[inline]
21755#[cfg(target_endian = "big")]
21756#[target_feature(enable = "neon")]
21757#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21758#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21759#[cfg_attr(
21760    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21761    assert_instr(ld2)
21762)]
21763#[cfg_attr(
21764    not(target_arch = "arm"),
21765    stable(feature = "neon_intrinsics", since = "1.59.0")
21766)]
21767#[cfg_attr(
21768    target_arch = "arm",
21769    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21770)]
21771pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
21772    let mut ret_val: uint16x4x2_t = transmute(vld2_s16(transmute(a)));
21773    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
21774    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
21775    ret_val
21776}
21777#[doc = "Load multiple 2-element structures to two registers"]
21778#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"]
21779#[doc = "## Safety"]
21780#[doc = "  * Neon instrinsic unsafe"]
21781#[inline]
21782#[cfg(target_endian = "little")]
21783#[target_feature(enable = "neon")]
21784#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21785#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21786#[cfg_attr(
21787    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21788    assert_instr(ld2)
21789)]
21790#[cfg_attr(
21791    not(target_arch = "arm"),
21792    stable(feature = "neon_intrinsics", since = "1.59.0")
21793)]
21794#[cfg_attr(
21795    target_arch = "arm",
21796    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21797)]
21798pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
21799    transmute(vld2q_s16(transmute(a)))
21800}
21801#[doc = "Load multiple 2-element structures to two registers"]
21802#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"]
21803#[doc = "## Safety"]
21804#[doc = "  * Neon instrinsic unsafe"]
21805#[inline]
21806#[cfg(target_endian = "big")]
21807#[target_feature(enable = "neon")]
21808#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21809#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21810#[cfg_attr(
21811    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21812    assert_instr(ld2)
21813)]
21814#[cfg_attr(
21815    not(target_arch = "arm"),
21816    stable(feature = "neon_intrinsics", since = "1.59.0")
21817)]
21818#[cfg_attr(
21819    target_arch = "arm",
21820    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21821)]
21822pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
21823    let mut ret_val: uint16x8x2_t = transmute(vld2q_s16(transmute(a)));
21824    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
21825    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
21826    ret_val
21827}
21828#[doc = "Load multiple 2-element structures to two registers"]
21829#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"]
21830#[doc = "## Safety"]
21831#[doc = "  * Neon instrinsic unsafe"]
21832#[inline]
21833#[cfg(target_endian = "little")]
21834#[target_feature(enable = "neon")]
21835#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21836#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21837#[cfg_attr(
21838    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21839    assert_instr(ld2)
21840)]
21841#[cfg_attr(
21842    not(target_arch = "arm"),
21843    stable(feature = "neon_intrinsics", since = "1.59.0")
21844)]
21845#[cfg_attr(
21846    target_arch = "arm",
21847    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21848)]
21849pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t {
21850    transmute(vld2_s32(transmute(a)))
21851}
21852#[doc = "Load multiple 2-element structures to two registers"]
21853#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"]
21854#[doc = "## Safety"]
21855#[doc = "  * Neon instrinsic unsafe"]
21856#[inline]
21857#[cfg(target_endian = "big")]
21858#[target_feature(enable = "neon")]
21859#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21860#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21861#[cfg_attr(
21862    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21863    assert_instr(ld2)
21864)]
21865#[cfg_attr(
21866    not(target_arch = "arm"),
21867    stable(feature = "neon_intrinsics", since = "1.59.0")
21868)]
21869#[cfg_attr(
21870    target_arch = "arm",
21871    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21872)]
21873pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t {
21874    let mut ret_val: uint32x2x2_t = transmute(vld2_s32(transmute(a)));
21875    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
21876    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
21877    ret_val
21878}
21879#[doc = "Load multiple 2-element structures to two registers"]
21880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"]
21881#[doc = "## Safety"]
21882#[doc = "  * Neon instrinsic unsafe"]
21883#[inline]
21884#[cfg(target_endian = "little")]
21885#[target_feature(enable = "neon")]
21886#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21887#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21888#[cfg_attr(
21889    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21890    assert_instr(ld2)
21891)]
21892#[cfg_attr(
21893    not(target_arch = "arm"),
21894    stable(feature = "neon_intrinsics", since = "1.59.0")
21895)]
21896#[cfg_attr(
21897    target_arch = "arm",
21898    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21899)]
21900pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t {
21901    transmute(vld2q_s32(transmute(a)))
21902}
21903#[doc = "Load multiple 2-element structures to two registers"]
21904#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"]
21905#[doc = "## Safety"]
21906#[doc = "  * Neon instrinsic unsafe"]
21907#[inline]
21908#[cfg(target_endian = "big")]
21909#[target_feature(enable = "neon")]
21910#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21911#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21912#[cfg_attr(
21913    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21914    assert_instr(ld2)
21915)]
21916#[cfg_attr(
21917    not(target_arch = "arm"),
21918    stable(feature = "neon_intrinsics", since = "1.59.0")
21919)]
21920#[cfg_attr(
21921    target_arch = "arm",
21922    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21923)]
21924pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t {
21925    let mut ret_val: uint32x4x2_t = transmute(vld2q_s32(transmute(a)));
21926    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
21927    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
21928    ret_val
21929}
21930#[doc = "Load multiple 2-element structures to two registers"]
21931#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"]
21932#[doc = "## Safety"]
21933#[doc = "  * Neon instrinsic unsafe"]
21934#[inline]
21935#[cfg(target_endian = "little")]
21936#[target_feature(enable = "neon")]
21937#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21938#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21939#[cfg_attr(
21940    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21941    assert_instr(ld2)
21942)]
21943#[cfg_attr(
21944    not(target_arch = "arm"),
21945    stable(feature = "neon_intrinsics", since = "1.59.0")
21946)]
21947#[cfg_attr(
21948    target_arch = "arm",
21949    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21950)]
21951pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t {
21952    transmute(vld2_s8(transmute(a)))
21953}
21954#[doc = "Load multiple 2-element structures to two registers"]
21955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"]
21956#[doc = "## Safety"]
21957#[doc = "  * Neon instrinsic unsafe"]
21958#[inline]
21959#[cfg(target_endian = "big")]
21960#[target_feature(enable = "neon")]
21961#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21962#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21963#[cfg_attr(
21964    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21965    assert_instr(ld2)
21966)]
21967#[cfg_attr(
21968    not(target_arch = "arm"),
21969    stable(feature = "neon_intrinsics", since = "1.59.0")
21970)]
21971#[cfg_attr(
21972    target_arch = "arm",
21973    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21974)]
21975pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t {
21976    let mut ret_val: poly8x8x2_t = transmute(vld2_s8(transmute(a)));
21977    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
21978    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
21979    ret_val
21980}
21981#[doc = "Load multiple 2-element structures to two registers"]
21982#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"]
21983#[doc = "## Safety"]
21984#[doc = "  * Neon instrinsic unsafe"]
21985#[inline]
21986#[cfg(target_endian = "little")]
21987#[target_feature(enable = "neon")]
21988#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21989#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21990#[cfg_attr(
21991    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21992    assert_instr(ld2)
21993)]
21994#[cfg_attr(
21995    not(target_arch = "arm"),
21996    stable(feature = "neon_intrinsics", since = "1.59.0")
21997)]
21998#[cfg_attr(
21999    target_arch = "arm",
22000    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22001)]
22002pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t {
22003    transmute(vld2q_s8(transmute(a)))
22004}
22005#[doc = "Load multiple 2-element structures to two registers"]
22006#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"]
22007#[doc = "## Safety"]
22008#[doc = "  * Neon instrinsic unsafe"]
22009#[inline]
22010#[cfg(target_endian = "big")]
22011#[target_feature(enable = "neon")]
22012#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22013#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22014#[cfg_attr(
22015    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22016    assert_instr(ld2)
22017)]
22018#[cfg_attr(
22019    not(target_arch = "arm"),
22020    stable(feature = "neon_intrinsics", since = "1.59.0")
22021)]
22022#[cfg_attr(
22023    target_arch = "arm",
22024    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22025)]
22026pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t {
22027    let mut ret_val: poly8x16x2_t = transmute(vld2q_s8(transmute(a)));
22028    ret_val.0 = unsafe {
22029        simd_shuffle!(
22030            ret_val.0,
22031            ret_val.0,
22032            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22033        )
22034    };
22035    ret_val.1 = unsafe {
22036        simd_shuffle!(
22037            ret_val.1,
22038            ret_val.1,
22039            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22040        )
22041    };
22042    ret_val
22043}
22044#[doc = "Load multiple 2-element structures to two registers"]
22045#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"]
22046#[doc = "## Safety"]
22047#[doc = "  * Neon instrinsic unsafe"]
22048#[inline]
22049#[cfg(target_endian = "little")]
22050#[target_feature(enable = "neon")]
22051#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22052#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22053#[cfg_attr(
22054    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22055    assert_instr(ld2)
22056)]
22057#[cfg_attr(
22058    not(target_arch = "arm"),
22059    stable(feature = "neon_intrinsics", since = "1.59.0")
22060)]
22061#[cfg_attr(
22062    target_arch = "arm",
22063    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22064)]
22065pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t {
22066    transmute(vld2_s16(transmute(a)))
22067}
22068#[doc = "Load multiple 2-element structures to two registers"]
22069#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"]
22070#[doc = "## Safety"]
22071#[doc = "  * Neon instrinsic unsafe"]
22072#[inline]
22073#[cfg(target_endian = "big")]
22074#[target_feature(enable = "neon")]
22075#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22076#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22077#[cfg_attr(
22078    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22079    assert_instr(ld2)
22080)]
22081#[cfg_attr(
22082    not(target_arch = "arm"),
22083    stable(feature = "neon_intrinsics", since = "1.59.0")
22084)]
22085#[cfg_attr(
22086    target_arch = "arm",
22087    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22088)]
22089pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t {
22090    let mut ret_val: poly16x4x2_t = transmute(vld2_s16(transmute(a)));
22091    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
22092    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
22093    ret_val
22094}
22095#[doc = "Load multiple 2-element structures to two registers"]
22096#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"]
22097#[doc = "## Safety"]
22098#[doc = "  * Neon instrinsic unsafe"]
22099#[inline]
22100#[cfg(target_endian = "little")]
22101#[target_feature(enable = "neon")]
22102#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22103#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22104#[cfg_attr(
22105    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22106    assert_instr(ld2)
22107)]
22108#[cfg_attr(
22109    not(target_arch = "arm"),
22110    stable(feature = "neon_intrinsics", since = "1.59.0")
22111)]
22112#[cfg_attr(
22113    target_arch = "arm",
22114    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22115)]
22116pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t {
22117    transmute(vld2q_s16(transmute(a)))
22118}
22119#[doc = "Load multiple 2-element structures to two registers"]
22120#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"]
22121#[doc = "## Safety"]
22122#[doc = "  * Neon instrinsic unsafe"]
22123#[inline]
22124#[cfg(target_endian = "big")]
22125#[target_feature(enable = "neon")]
22126#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22127#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22128#[cfg_attr(
22129    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22130    assert_instr(ld2)
22131)]
22132#[cfg_attr(
22133    not(target_arch = "arm"),
22134    stable(feature = "neon_intrinsics", since = "1.59.0")
22135)]
22136#[cfg_attr(
22137    target_arch = "arm",
22138    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22139)]
22140pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t {
22141    let mut ret_val: poly16x8x2_t = transmute(vld2q_s16(transmute(a)));
22142    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
22143    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
22144    ret_val
22145}
22146#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
22147#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
22148#[doc = "## Safety"]
22149#[doc = "  * Neon instrinsic unsafe"]
22150#[inline]
22151#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22152#[cfg(target_arch = "arm")]
22153#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22154#[target_feature(enable = "neon,fp16")]
22155#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22156pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
22157    unsafe extern "unadjusted" {
22158        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4f16.p0")]
22159        fn _vld3_dup_f16(ptr: *const f16, size: i32) -> float16x4x3_t;
22160    }
22161    _vld3_dup_f16(a as _, 2)
22162}
22163#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
22164#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
22165#[doc = "## Safety"]
22166#[doc = "  * Neon instrinsic unsafe"]
22167#[inline]
22168#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22169#[cfg(target_arch = "arm")]
22170#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22171#[target_feature(enable = "neon,fp16")]
22172#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22173pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
22174    unsafe extern "unadjusted" {
22175        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8f16.p0")]
22176        fn _vld3q_dup_f16(ptr: *const f16, size: i32) -> float16x8x3_t;
22177    }
22178    _vld3q_dup_f16(a as _, 2)
22179}
22180#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
22181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
22182#[doc = "## Safety"]
22183#[doc = "  * Neon instrinsic unsafe"]
22184#[inline]
22185#[cfg(not(target_arch = "arm"))]
22186#[cfg_attr(
22187    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22188    assert_instr(ld3r)
22189)]
22190#[target_feature(enable = "neon,fp16")]
22191#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22192pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
22193    unsafe extern "unadjusted" {
22194        #[cfg_attr(
22195            any(target_arch = "aarch64", target_arch = "arm64ec"),
22196            link_name = "llvm.aarch64.neon.ld3r.v4f16.p0"
22197        )]
22198        fn _vld3_dup_f16(ptr: *const f16) -> float16x4x3_t;
22199    }
22200    _vld3_dup_f16(a as _)
22201}
22202#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
22203#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
22204#[doc = "## Safety"]
22205#[doc = "  * Neon instrinsic unsafe"]
22206#[inline]
22207#[cfg(not(target_arch = "arm"))]
22208#[cfg_attr(
22209    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22210    assert_instr(ld3r)
22211)]
22212#[target_feature(enable = "neon,fp16")]
22213#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22214pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
22215    unsafe extern "unadjusted" {
22216        #[cfg_attr(
22217            any(target_arch = "aarch64", target_arch = "arm64ec"),
22218            link_name = "llvm.aarch64.neon.ld3r.v8f16.p0"
22219        )]
22220        fn _vld3q_dup_f16(ptr: *const f16) -> float16x8x3_t;
22221    }
22222    _vld3q_dup_f16(a as _)
22223}
22224#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22225#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"]
22226#[doc = "## Safety"]
22227#[doc = "  * Neon instrinsic unsafe"]
22228#[inline]
22229#[target_feature(enable = "neon")]
22230#[cfg(not(target_arch = "arm"))]
22231#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22232#[cfg_attr(test, assert_instr(ld3r))]
22233pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t {
22234    unsafe extern "unadjusted" {
22235        #[cfg_attr(
22236            any(target_arch = "aarch64", target_arch = "arm64ec"),
22237            link_name = "llvm.aarch64.neon.ld3r.v2f32.p0"
22238        )]
22239        fn _vld3_dup_f32(ptr: *const f32) -> float32x2x3_t;
22240    }
22241    _vld3_dup_f32(a as _)
22242}
22243#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22244#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"]
22245#[doc = "## Safety"]
22246#[doc = "  * Neon instrinsic unsafe"]
22247#[inline]
22248#[target_feature(enable = "neon")]
22249#[cfg(not(target_arch = "arm"))]
22250#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22251#[cfg_attr(test, assert_instr(ld3r))]
22252pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t {
22253    unsafe extern "unadjusted" {
22254        #[cfg_attr(
22255            any(target_arch = "aarch64", target_arch = "arm64ec"),
22256            link_name = "llvm.aarch64.neon.ld3r.v4f32.p0"
22257        )]
22258        fn _vld3q_dup_f32(ptr: *const f32) -> float32x4x3_t;
22259    }
22260    _vld3q_dup_f32(a as _)
22261}
22262#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22263#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"]
22264#[doc = "## Safety"]
22265#[doc = "  * Neon instrinsic unsafe"]
22266#[inline]
22267#[target_feature(enable = "neon")]
22268#[cfg(not(target_arch = "arm"))]
22269#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22270#[cfg_attr(test, assert_instr(ld3r))]
22271pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t {
22272    unsafe extern "unadjusted" {
22273        #[cfg_attr(
22274            any(target_arch = "aarch64", target_arch = "arm64ec"),
22275            link_name = "llvm.aarch64.neon.ld3r.v8i8.p0"
22276        )]
22277        fn _vld3_dup_s8(ptr: *const i8) -> int8x8x3_t;
22278    }
22279    _vld3_dup_s8(a as _)
22280}
22281#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22282#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"]
22283#[doc = "## Safety"]
22284#[doc = "  * Neon instrinsic unsafe"]
22285#[inline]
22286#[target_feature(enable = "neon")]
22287#[cfg(not(target_arch = "arm"))]
22288#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22289#[cfg_attr(test, assert_instr(ld3r))]
22290pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t {
22291    unsafe extern "unadjusted" {
22292        #[cfg_attr(
22293            any(target_arch = "aarch64", target_arch = "arm64ec"),
22294            link_name = "llvm.aarch64.neon.ld3r.v16i8.p0"
22295        )]
22296        fn _vld3q_dup_s8(ptr: *const i8) -> int8x16x3_t;
22297    }
22298    _vld3q_dup_s8(a as _)
22299}
22300#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22301#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"]
22302#[doc = "## Safety"]
22303#[doc = "  * Neon instrinsic unsafe"]
22304#[inline]
22305#[target_feature(enable = "neon")]
22306#[cfg(not(target_arch = "arm"))]
22307#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22308#[cfg_attr(test, assert_instr(ld3r))]
22309pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t {
22310    unsafe extern "unadjusted" {
22311        #[cfg_attr(
22312            any(target_arch = "aarch64", target_arch = "arm64ec"),
22313            link_name = "llvm.aarch64.neon.ld3r.v4i16.p0"
22314        )]
22315        fn _vld3_dup_s16(ptr: *const i16) -> int16x4x3_t;
22316    }
22317    _vld3_dup_s16(a as _)
22318}
22319#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22320#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"]
22321#[doc = "## Safety"]
22322#[doc = "  * Neon instrinsic unsafe"]
22323#[inline]
22324#[target_feature(enable = "neon")]
22325#[cfg(not(target_arch = "arm"))]
22326#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22327#[cfg_attr(test, assert_instr(ld3r))]
22328pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t {
22329    unsafe extern "unadjusted" {
22330        #[cfg_attr(
22331            any(target_arch = "aarch64", target_arch = "arm64ec"),
22332            link_name = "llvm.aarch64.neon.ld3r.v8i16.p0"
22333        )]
22334        fn _vld3q_dup_s16(ptr: *const i16) -> int16x8x3_t;
22335    }
22336    _vld3q_dup_s16(a as _)
22337}
22338#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22339#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"]
22340#[doc = "## Safety"]
22341#[doc = "  * Neon instrinsic unsafe"]
22342#[inline]
22343#[target_feature(enable = "neon")]
22344#[cfg(not(target_arch = "arm"))]
22345#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22346#[cfg_attr(test, assert_instr(ld3r))]
22347pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t {
22348    unsafe extern "unadjusted" {
22349        #[cfg_attr(
22350            any(target_arch = "aarch64", target_arch = "arm64ec"),
22351            link_name = "llvm.aarch64.neon.ld3r.v2i32.p0"
22352        )]
22353        fn _vld3_dup_s32(ptr: *const i32) -> int32x2x3_t;
22354    }
22355    _vld3_dup_s32(a as _)
22356}
22357#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22358#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"]
22359#[doc = "## Safety"]
22360#[doc = "  * Neon instrinsic unsafe"]
22361#[inline]
22362#[target_feature(enable = "neon")]
22363#[cfg(not(target_arch = "arm"))]
22364#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22365#[cfg_attr(test, assert_instr(ld3r))]
22366pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t {
22367    unsafe extern "unadjusted" {
22368        #[cfg_attr(
22369            any(target_arch = "aarch64", target_arch = "arm64ec"),
22370            link_name = "llvm.aarch64.neon.ld3r.v4i32.p0"
22371        )]
22372        fn _vld3q_dup_s32(ptr: *const i32) -> int32x4x3_t;
22373    }
22374    _vld3q_dup_s32(a as _)
22375}
22376#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22377#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"]
22378#[doc = "## Safety"]
22379#[doc = "  * Neon instrinsic unsafe"]
22380#[inline]
22381#[target_feature(enable = "neon")]
22382#[cfg(not(target_arch = "arm"))]
22383#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22384#[cfg_attr(test, assert_instr(ld3r))]
22385pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t {
22386    unsafe extern "unadjusted" {
22387        #[cfg_attr(
22388            any(target_arch = "aarch64", target_arch = "arm64ec"),
22389            link_name = "llvm.aarch64.neon.ld3r.v1i64.p0"
22390        )]
22391        fn _vld3_dup_s64(ptr: *const i64) -> int64x1x3_t;
22392    }
22393    _vld3_dup_s64(a as _)
22394}
22395#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22396#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"]
22397#[doc = "## Safety"]
22398#[doc = "  * Neon instrinsic unsafe"]
22399#[inline]
22400#[target_feature(enable = "neon,v7")]
22401#[cfg(target_arch = "arm")]
22402#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22403#[cfg_attr(test, assert_instr(vld3))]
22404pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t {
22405    unsafe extern "unadjusted" {
22406        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v2f32.p0")]
22407        fn _vld3_dup_f32(ptr: *const i8, size: i32) -> float32x2x3_t;
22408    }
22409    _vld3_dup_f32(a as *const i8, 4)
22410}
22411#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22412#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"]
22413#[doc = "## Safety"]
22414#[doc = "  * Neon instrinsic unsafe"]
22415#[inline]
22416#[target_feature(enable = "neon,v7")]
22417#[cfg(target_arch = "arm")]
22418#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22419#[cfg_attr(test, assert_instr(vld3))]
22420pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t {
22421    unsafe extern "unadjusted" {
22422        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4f32.p0")]
22423        fn _vld3q_dup_f32(ptr: *const i8, size: i32) -> float32x4x3_t;
22424    }
22425    _vld3q_dup_f32(a as *const i8, 4)
22426}
22427#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22428#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"]
22429#[doc = "## Safety"]
22430#[doc = "  * Neon instrinsic unsafe"]
22431#[inline]
22432#[target_feature(enable = "neon,v7")]
22433#[cfg(target_arch = "arm")]
22434#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22435#[cfg_attr(test, assert_instr(vld3))]
22436pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t {
22437    unsafe extern "unadjusted" {
22438        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8i8.p0")]
22439        fn _vld3_dup_s8(ptr: *const i8, size: i32) -> int8x8x3_t;
22440    }
22441    _vld3_dup_s8(a as *const i8, 1)
22442}
22443#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22444#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"]
22445#[doc = "## Safety"]
22446#[doc = "  * Neon instrinsic unsafe"]
22447#[inline]
22448#[target_feature(enable = "neon,v7")]
22449#[cfg(target_arch = "arm")]
22450#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22451#[cfg_attr(test, assert_instr(vld3))]
22452pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t {
22453    unsafe extern "unadjusted" {
22454        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v16i8.p0")]
22455        fn _vld3q_dup_s8(ptr: *const i8, size: i32) -> int8x16x3_t;
22456    }
22457    _vld3q_dup_s8(a as *const i8, 1)
22458}
22459#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"]
22461#[doc = "## Safety"]
22462#[doc = "  * Neon instrinsic unsafe"]
22463#[inline]
22464#[target_feature(enable = "neon,v7")]
22465#[cfg(target_arch = "arm")]
22466#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22467#[cfg_attr(test, assert_instr(vld3))]
22468pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t {
22469    unsafe extern "unadjusted" {
22470        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4i16.p0")]
22471        fn _vld3_dup_s16(ptr: *const i8, size: i32) -> int16x4x3_t;
22472    }
22473    _vld3_dup_s16(a as *const i8, 2)
22474}
22475#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22476#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"]
22477#[doc = "## Safety"]
22478#[doc = "  * Neon instrinsic unsafe"]
22479#[inline]
22480#[target_feature(enable = "neon,v7")]
22481#[cfg(target_arch = "arm")]
22482#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22483#[cfg_attr(test, assert_instr(vld3))]
22484pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t {
22485    unsafe extern "unadjusted" {
22486        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8i16.p0")]
22487        fn _vld3q_dup_s16(ptr: *const i8, size: i32) -> int16x8x3_t;
22488    }
22489    _vld3q_dup_s16(a as *const i8, 2)
22490}
22491#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22492#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"]
22493#[doc = "## Safety"]
22494#[doc = "  * Neon instrinsic unsafe"]
22495#[inline]
22496#[target_feature(enable = "neon,v7")]
22497#[cfg(target_arch = "arm")]
22498#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22499#[cfg_attr(test, assert_instr(vld3))]
22500pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t {
22501    unsafe extern "unadjusted" {
22502        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v2i32.p0")]
22503        fn _vld3_dup_s32(ptr: *const i8, size: i32) -> int32x2x3_t;
22504    }
22505    _vld3_dup_s32(a as *const i8, 4)
22506}
22507#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"]
22509#[doc = "## Safety"]
22510#[doc = "  * Neon instrinsic unsafe"]
22511#[inline]
22512#[target_feature(enable = "neon,v7")]
22513#[cfg(target_arch = "arm")]
22514#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22515#[cfg_attr(test, assert_instr(vld3))]
22516pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t {
22517    unsafe extern "unadjusted" {
22518        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4i32.p0")]
22519        fn _vld3q_dup_s32(ptr: *const i8, size: i32) -> int32x4x3_t;
22520    }
22521    _vld3q_dup_s32(a as *const i8, 4)
22522}
22523#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22524#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p64)"]
22525#[doc = "## Safety"]
22526#[doc = "  * Neon instrinsic unsafe"]
22527#[inline]
22528#[target_feature(enable = "neon,aes")]
22529#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
22530#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
22531#[cfg_attr(
22532    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22533    assert_instr(ld3r)
22534)]
22535#[cfg_attr(
22536    not(target_arch = "arm"),
22537    stable(feature = "neon_intrinsics", since = "1.59.0")
22538)]
22539#[cfg_attr(
22540    target_arch = "arm",
22541    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22542)]
22543pub unsafe fn vld3_dup_p64(a: *const p64) -> poly64x1x3_t {
22544    transmute(vld3_dup_s64(transmute(a)))
22545}
22546#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22547#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"]
22548#[doc = "## Safety"]
22549#[doc = "  * Neon instrinsic unsafe"]
22550#[inline]
22551#[cfg(target_arch = "arm")]
22552#[target_feature(enable = "neon,v7")]
22553#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22554#[cfg_attr(test, assert_instr(nop))]
22555pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t {
22556    unsafe extern "unadjusted" {
22557        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v1i64.p0")]
22558        fn _vld3_dup_s64(ptr: *const i8, size: i32) -> int64x1x3_t;
22559    }
22560    _vld3_dup_s64(a as *const i8, 8)
22561}
22562#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22563#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u64)"]
22564#[doc = "## Safety"]
22565#[doc = "  * Neon instrinsic unsafe"]
22566#[inline]
22567#[target_feature(enable = "neon")]
22568#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22569#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
22570#[cfg_attr(
22571    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22572    assert_instr(ld3r)
22573)]
22574#[cfg_attr(
22575    not(target_arch = "arm"),
22576    stable(feature = "neon_intrinsics", since = "1.59.0")
22577)]
22578#[cfg_attr(
22579    target_arch = "arm",
22580    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22581)]
22582pub unsafe fn vld3_dup_u64(a: *const u64) -> uint64x1x3_t {
22583    transmute(vld3_dup_s64(transmute(a)))
22584}
22585#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22586#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"]
22587#[doc = "## Safety"]
22588#[doc = "  * Neon instrinsic unsafe"]
22589#[inline]
22590#[cfg(target_endian = "little")]
22591#[target_feature(enable = "neon")]
22592#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22593#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22594#[cfg_attr(
22595    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22596    assert_instr(ld3r)
22597)]
22598#[cfg_attr(
22599    not(target_arch = "arm"),
22600    stable(feature = "neon_intrinsics", since = "1.59.0")
22601)]
22602#[cfg_attr(
22603    target_arch = "arm",
22604    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22605)]
22606pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
22607    transmute(vld3_dup_s8(transmute(a)))
22608}
22609#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22610#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"]
22611#[doc = "## Safety"]
22612#[doc = "  * Neon instrinsic unsafe"]
22613#[inline]
22614#[cfg(target_endian = "big")]
22615#[target_feature(enable = "neon")]
22616#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22617#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22618#[cfg_attr(
22619    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22620    assert_instr(ld3r)
22621)]
22622#[cfg_attr(
22623    not(target_arch = "arm"),
22624    stable(feature = "neon_intrinsics", since = "1.59.0")
22625)]
22626#[cfg_attr(
22627    target_arch = "arm",
22628    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22629)]
22630pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
22631    let mut ret_val: uint8x8x3_t = transmute(vld3_dup_s8(transmute(a)));
22632    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
22633    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
22634    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
22635    ret_val
22636}
22637#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22638#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"]
22639#[doc = "## Safety"]
22640#[doc = "  * Neon instrinsic unsafe"]
22641#[inline]
22642#[cfg(target_endian = "little")]
22643#[target_feature(enable = "neon")]
22644#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22645#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22646#[cfg_attr(
22647    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22648    assert_instr(ld3r)
22649)]
22650#[cfg_attr(
22651    not(target_arch = "arm"),
22652    stable(feature = "neon_intrinsics", since = "1.59.0")
22653)]
22654#[cfg_attr(
22655    target_arch = "arm",
22656    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22657)]
22658pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
22659    transmute(vld3q_dup_s8(transmute(a)))
22660}
22661#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22662#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"]
22663#[doc = "## Safety"]
22664#[doc = "  * Neon instrinsic unsafe"]
22665#[inline]
22666#[cfg(target_endian = "big")]
22667#[target_feature(enable = "neon")]
22668#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22669#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22670#[cfg_attr(
22671    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22672    assert_instr(ld3r)
22673)]
22674#[cfg_attr(
22675    not(target_arch = "arm"),
22676    stable(feature = "neon_intrinsics", since = "1.59.0")
22677)]
22678#[cfg_attr(
22679    target_arch = "arm",
22680    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22681)]
22682pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
22683    let mut ret_val: uint8x16x3_t = transmute(vld3q_dup_s8(transmute(a)));
22684    ret_val.0 = unsafe {
22685        simd_shuffle!(
22686            ret_val.0,
22687            ret_val.0,
22688            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22689        )
22690    };
22691    ret_val.1 = unsafe {
22692        simd_shuffle!(
22693            ret_val.1,
22694            ret_val.1,
22695            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22696        )
22697    };
22698    ret_val.2 = unsafe {
22699        simd_shuffle!(
22700            ret_val.2,
22701            ret_val.2,
22702            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22703        )
22704    };
22705    ret_val
22706}
22707#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22708#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"]
22709#[doc = "## Safety"]
22710#[doc = "  * Neon instrinsic unsafe"]
22711#[inline]
22712#[cfg(target_endian = "little")]
22713#[target_feature(enable = "neon")]
22714#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22715#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22716#[cfg_attr(
22717    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22718    assert_instr(ld3r)
22719)]
22720#[cfg_attr(
22721    not(target_arch = "arm"),
22722    stable(feature = "neon_intrinsics", since = "1.59.0")
22723)]
22724#[cfg_attr(
22725    target_arch = "arm",
22726    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22727)]
22728pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
22729    transmute(vld3_dup_s16(transmute(a)))
22730}
22731#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"]
22733#[doc = "## Safety"]
22734#[doc = "  * Neon instrinsic unsafe"]
22735#[inline]
22736#[cfg(target_endian = "big")]
22737#[target_feature(enable = "neon")]
22738#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22739#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22740#[cfg_attr(
22741    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22742    assert_instr(ld3r)
22743)]
22744#[cfg_attr(
22745    not(target_arch = "arm"),
22746    stable(feature = "neon_intrinsics", since = "1.59.0")
22747)]
22748#[cfg_attr(
22749    target_arch = "arm",
22750    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22751)]
22752pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
22753    let mut ret_val: uint16x4x3_t = transmute(vld3_dup_s16(transmute(a)));
22754    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
22755    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
22756    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
22757    ret_val
22758}
22759#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22760#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"]
22761#[doc = "## Safety"]
22762#[doc = "  * Neon instrinsic unsafe"]
22763#[inline]
22764#[cfg(target_endian = "little")]
22765#[target_feature(enable = "neon")]
22766#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22767#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22768#[cfg_attr(
22769    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22770    assert_instr(ld3r)
22771)]
22772#[cfg_attr(
22773    not(target_arch = "arm"),
22774    stable(feature = "neon_intrinsics", since = "1.59.0")
22775)]
22776#[cfg_attr(
22777    target_arch = "arm",
22778    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22779)]
22780pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
22781    transmute(vld3q_dup_s16(transmute(a)))
22782}
22783#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22784#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"]
22785#[doc = "## Safety"]
22786#[doc = "  * Neon instrinsic unsafe"]
22787#[inline]
22788#[cfg(target_endian = "big")]
22789#[target_feature(enable = "neon")]
22790#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22791#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22792#[cfg_attr(
22793    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22794    assert_instr(ld3r)
22795)]
22796#[cfg_attr(
22797    not(target_arch = "arm"),
22798    stable(feature = "neon_intrinsics", since = "1.59.0")
22799)]
22800#[cfg_attr(
22801    target_arch = "arm",
22802    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22803)]
22804pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
22805    let mut ret_val: uint16x8x3_t = transmute(vld3q_dup_s16(transmute(a)));
22806    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
22807    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
22808    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
22809    ret_val
22810}
22811#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22812#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"]
22813#[doc = "## Safety"]
22814#[doc = "  * Neon instrinsic unsafe"]
22815#[inline]
22816#[cfg(target_endian = "little")]
22817#[target_feature(enable = "neon")]
22818#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22819#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22820#[cfg_attr(
22821    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22822    assert_instr(ld3r)
22823)]
22824#[cfg_attr(
22825    not(target_arch = "arm"),
22826    stable(feature = "neon_intrinsics", since = "1.59.0")
22827)]
22828#[cfg_attr(
22829    target_arch = "arm",
22830    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22831)]
22832pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
22833    transmute(vld3_dup_s32(transmute(a)))
22834}
22835#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22836#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"]
22837#[doc = "## Safety"]
22838#[doc = "  * Neon instrinsic unsafe"]
22839#[inline]
22840#[cfg(target_endian = "big")]
22841#[target_feature(enable = "neon")]
22842#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22843#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22844#[cfg_attr(
22845    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22846    assert_instr(ld3r)
22847)]
22848#[cfg_attr(
22849    not(target_arch = "arm"),
22850    stable(feature = "neon_intrinsics", since = "1.59.0")
22851)]
22852#[cfg_attr(
22853    target_arch = "arm",
22854    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22855)]
22856pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
22857    let mut ret_val: uint32x2x3_t = transmute(vld3_dup_s32(transmute(a)));
22858    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
22859    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
22860    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
22861    ret_val
22862}
22863#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22864#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"]
22865#[doc = "## Safety"]
22866#[doc = "  * Neon instrinsic unsafe"]
22867#[inline]
22868#[cfg(target_endian = "little")]
22869#[target_feature(enable = "neon")]
22870#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22871#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22872#[cfg_attr(
22873    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22874    assert_instr(ld3r)
22875)]
22876#[cfg_attr(
22877    not(target_arch = "arm"),
22878    stable(feature = "neon_intrinsics", since = "1.59.0")
22879)]
22880#[cfg_attr(
22881    target_arch = "arm",
22882    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22883)]
22884pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
22885    transmute(vld3q_dup_s32(transmute(a)))
22886}
22887#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22888#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"]
22889#[doc = "## Safety"]
22890#[doc = "  * Neon instrinsic unsafe"]
22891#[inline]
22892#[cfg(target_endian = "big")]
22893#[target_feature(enable = "neon")]
22894#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22895#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22896#[cfg_attr(
22897    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22898    assert_instr(ld3r)
22899)]
22900#[cfg_attr(
22901    not(target_arch = "arm"),
22902    stable(feature = "neon_intrinsics", since = "1.59.0")
22903)]
22904#[cfg_attr(
22905    target_arch = "arm",
22906    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22907)]
22908pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
22909    let mut ret_val: uint32x4x3_t = transmute(vld3q_dup_s32(transmute(a)));
22910    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
22911    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
22912    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
22913    ret_val
22914}
22915#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22916#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"]
22917#[doc = "## Safety"]
22918#[doc = "  * Neon instrinsic unsafe"]
22919#[inline]
22920#[cfg(target_endian = "little")]
22921#[target_feature(enable = "neon")]
22922#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22923#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22924#[cfg_attr(
22925    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22926    assert_instr(ld3r)
22927)]
22928#[cfg_attr(
22929    not(target_arch = "arm"),
22930    stable(feature = "neon_intrinsics", since = "1.59.0")
22931)]
22932#[cfg_attr(
22933    target_arch = "arm",
22934    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22935)]
22936pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
22937    transmute(vld3_dup_s8(transmute(a)))
22938}
22939#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22940#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"]
22941#[doc = "## Safety"]
22942#[doc = "  * Neon instrinsic unsafe"]
22943#[inline]
22944#[cfg(target_endian = "big")]
22945#[target_feature(enable = "neon")]
22946#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22947#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22948#[cfg_attr(
22949    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22950    assert_instr(ld3r)
22951)]
22952#[cfg_attr(
22953    not(target_arch = "arm"),
22954    stable(feature = "neon_intrinsics", since = "1.59.0")
22955)]
22956#[cfg_attr(
22957    target_arch = "arm",
22958    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22959)]
22960pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
22961    let mut ret_val: poly8x8x3_t = transmute(vld3_dup_s8(transmute(a)));
22962    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
22963    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
22964    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
22965    ret_val
22966}
22967#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22968#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"]
22969#[doc = "## Safety"]
22970#[doc = "  * Neon instrinsic unsafe"]
22971#[inline]
22972#[cfg(target_endian = "little")]
22973#[target_feature(enable = "neon")]
22974#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22975#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22976#[cfg_attr(
22977    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22978    assert_instr(ld3r)
22979)]
22980#[cfg_attr(
22981    not(target_arch = "arm"),
22982    stable(feature = "neon_intrinsics", since = "1.59.0")
22983)]
22984#[cfg_attr(
22985    target_arch = "arm",
22986    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22987)]
22988pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
22989    transmute(vld3q_dup_s8(transmute(a)))
22990}
22991#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22992#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"]
22993#[doc = "## Safety"]
22994#[doc = "  * Neon instrinsic unsafe"]
22995#[inline]
22996#[cfg(target_endian = "big")]
22997#[target_feature(enable = "neon")]
22998#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22999#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23000#[cfg_attr(
23001    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23002    assert_instr(ld3r)
23003)]
23004#[cfg_attr(
23005    not(target_arch = "arm"),
23006    stable(feature = "neon_intrinsics", since = "1.59.0")
23007)]
23008#[cfg_attr(
23009    target_arch = "arm",
23010    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23011)]
23012pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
23013    let mut ret_val: poly8x16x3_t = transmute(vld3q_dup_s8(transmute(a)));
23014    ret_val.0 = unsafe {
23015        simd_shuffle!(
23016            ret_val.0,
23017            ret_val.0,
23018            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
23019        )
23020    };
23021    ret_val.1 = unsafe {
23022        simd_shuffle!(
23023            ret_val.1,
23024            ret_val.1,
23025            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
23026        )
23027    };
23028    ret_val.2 = unsafe {
23029        simd_shuffle!(
23030            ret_val.2,
23031            ret_val.2,
23032            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
23033        )
23034    };
23035    ret_val
23036}
23037#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
23038#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"]
23039#[doc = "## Safety"]
23040#[doc = "  * Neon instrinsic unsafe"]
23041#[inline]
23042#[cfg(target_endian = "little")]
23043#[target_feature(enable = "neon")]
23044#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23045#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23046#[cfg_attr(
23047    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23048    assert_instr(ld3r)
23049)]
23050#[cfg_attr(
23051    not(target_arch = "arm"),
23052    stable(feature = "neon_intrinsics", since = "1.59.0")
23053)]
23054#[cfg_attr(
23055    target_arch = "arm",
23056    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23057)]
23058pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
23059    transmute(vld3_dup_s16(transmute(a)))
23060}
23061#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
23062#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"]
23063#[doc = "## Safety"]
23064#[doc = "  * Neon instrinsic unsafe"]
23065#[inline]
23066#[cfg(target_endian = "big")]
23067#[target_feature(enable = "neon")]
23068#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23069#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23070#[cfg_attr(
23071    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23072    assert_instr(ld3r)
23073)]
23074#[cfg_attr(
23075    not(target_arch = "arm"),
23076    stable(feature = "neon_intrinsics", since = "1.59.0")
23077)]
23078#[cfg_attr(
23079    target_arch = "arm",
23080    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23081)]
23082pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
23083    let mut ret_val: poly16x4x3_t = transmute(vld3_dup_s16(transmute(a)));
23084    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
23085    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
23086    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
23087    ret_val
23088}
23089#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
23090#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"]
23091#[doc = "## Safety"]
23092#[doc = "  * Neon instrinsic unsafe"]
23093#[inline]
23094#[cfg(target_endian = "little")]
23095#[target_feature(enable = "neon")]
23096#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23097#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23098#[cfg_attr(
23099    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23100    assert_instr(ld3r)
23101)]
23102#[cfg_attr(
23103    not(target_arch = "arm"),
23104    stable(feature = "neon_intrinsics", since = "1.59.0")
23105)]
23106#[cfg_attr(
23107    target_arch = "arm",
23108    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23109)]
23110pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
23111    transmute(vld3q_dup_s16(transmute(a)))
23112}
23113#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
23114#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"]
23115#[doc = "## Safety"]
23116#[doc = "  * Neon instrinsic unsafe"]
23117#[inline]
23118#[cfg(target_endian = "big")]
23119#[target_feature(enable = "neon")]
23120#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23121#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23122#[cfg_attr(
23123    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23124    assert_instr(ld3r)
23125)]
23126#[cfg_attr(
23127    not(target_arch = "arm"),
23128    stable(feature = "neon_intrinsics", since = "1.59.0")
23129)]
23130#[cfg_attr(
23131    target_arch = "arm",
23132    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23133)]
23134pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
23135    let mut ret_val: poly16x8x3_t = transmute(vld3q_dup_s16(transmute(a)));
23136    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
23137    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
23138    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
23139    ret_val
23140}
23141#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
23142#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"]
23143#[doc = "## Safety"]
23144#[doc = "  * Neon instrinsic unsafe"]
23145#[inline]
23146#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23147#[cfg(target_arch = "arm")]
23148#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23149#[target_feature(enable = "neon,fp16")]
23150#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23151pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
23152    unsafe extern "unadjusted" {
23153        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4f16.p0")]
23154        fn _vld3_f16(ptr: *const f16, size: i32) -> float16x4x3_t;
23155    }
23156    _vld3_f16(a as _, 2)
23157}
23158#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
23159#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"]
23160#[doc = "## Safety"]
23161#[doc = "  * Neon instrinsic unsafe"]
23162#[inline]
23163#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23164#[cfg(target_arch = "arm")]
23165#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23166#[target_feature(enable = "neon,fp16")]
23167#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23168pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
23169    unsafe extern "unadjusted" {
23170        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8f16.p0")]
23171        fn _vld3q_f16(ptr: *const f16, size: i32) -> float16x8x3_t;
23172    }
23173    _vld3q_f16(a as _, 2)
23174}
23175#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
23176#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"]
23177#[doc = "## Safety"]
23178#[doc = "  * Neon instrinsic unsafe"]
23179#[inline]
23180#[cfg(not(target_arch = "arm"))]
23181#[cfg_attr(
23182    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23183    assert_instr(ld3)
23184)]
23185#[target_feature(enable = "neon,fp16")]
23186#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23187pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
23188    unsafe extern "unadjusted" {
23189        #[cfg_attr(
23190            any(target_arch = "aarch64", target_arch = "arm64ec"),
23191            link_name = "llvm.aarch64.neon.ld3.v4f16.p0"
23192        )]
23193        fn _vld3_f16(ptr: *const f16) -> float16x4x3_t;
23194    }
23195    _vld3_f16(a as _)
23196}
23197#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
23198#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"]
23199#[doc = "## Safety"]
23200#[doc = "  * Neon instrinsic unsafe"]
23201#[inline]
23202#[cfg(not(target_arch = "arm"))]
23203#[cfg_attr(
23204    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23205    assert_instr(ld3)
23206)]
23207#[target_feature(enable = "neon,fp16")]
23208#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23209pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
23210    unsafe extern "unadjusted" {
23211        #[cfg_attr(
23212            any(target_arch = "aarch64", target_arch = "arm64ec"),
23213            link_name = "llvm.aarch64.neon.ld3.v8f16.p0"
23214        )]
23215        fn _vld3q_f16(ptr: *const f16) -> float16x8x3_t;
23216    }
23217    _vld3q_f16(a as _)
23218}
23219#[doc = "Load multiple 3-element structures to three registers"]
23220#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
23221#[doc = "## Safety"]
23222#[doc = "  * Neon instrinsic unsafe"]
23223#[inline]
23224#[target_feature(enable = "neon")]
23225#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23226#[cfg(not(target_arch = "arm"))]
23227#[cfg_attr(test, assert_instr(ld3))]
23228pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
23229    unsafe extern "unadjusted" {
23230        #[cfg_attr(
23231            any(target_arch = "aarch64", target_arch = "arm64ec"),
23232            link_name = "llvm.aarch64.neon.ld3.v2f32.p0"
23233        )]
23234        fn _vld3_f32(ptr: *const float32x2_t) -> float32x2x3_t;
23235    }
23236    _vld3_f32(a as _)
23237}
23238#[doc = "Load multiple 3-element structures to three registers"]
23239#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"]
23240#[doc = "## Safety"]
23241#[doc = "  * Neon instrinsic unsafe"]
23242#[inline]
23243#[target_feature(enable = "neon")]
23244#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23245#[cfg(not(target_arch = "arm"))]
23246#[cfg_attr(test, assert_instr(ld3))]
23247pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
23248    unsafe extern "unadjusted" {
23249        #[cfg_attr(
23250            any(target_arch = "aarch64", target_arch = "arm64ec"),
23251            link_name = "llvm.aarch64.neon.ld3.v4f32.p0"
23252        )]
23253        fn _vld3q_f32(ptr: *const float32x4_t) -> float32x4x3_t;
23254    }
23255    _vld3q_f32(a as _)
23256}
23257#[doc = "Load multiple 3-element structures to three registers"]
23258#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"]
23259#[doc = "## Safety"]
23260#[doc = "  * Neon instrinsic unsafe"]
23261#[inline]
23262#[target_feature(enable = "neon")]
23263#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23264#[cfg(not(target_arch = "arm"))]
23265#[cfg_attr(test, assert_instr(ld3))]
23266pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
23267    unsafe extern "unadjusted" {
23268        #[cfg_attr(
23269            any(target_arch = "aarch64", target_arch = "arm64ec"),
23270            link_name = "llvm.aarch64.neon.ld3.v8i8.p0"
23271        )]
23272        fn _vld3_s8(ptr: *const int8x8_t) -> int8x8x3_t;
23273    }
23274    _vld3_s8(a as _)
23275}
23276#[doc = "Load multiple 3-element structures to three registers"]
23277#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"]
23278#[doc = "## Safety"]
23279#[doc = "  * Neon instrinsic unsafe"]
23280#[inline]
23281#[target_feature(enable = "neon")]
23282#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23283#[cfg(not(target_arch = "arm"))]
23284#[cfg_attr(test, assert_instr(ld3))]
23285pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
23286    unsafe extern "unadjusted" {
23287        #[cfg_attr(
23288            any(target_arch = "aarch64", target_arch = "arm64ec"),
23289            link_name = "llvm.aarch64.neon.ld3.v16i8.p0"
23290        )]
23291        fn _vld3q_s8(ptr: *const int8x16_t) -> int8x16x3_t;
23292    }
23293    _vld3q_s8(a as _)
23294}
23295#[doc = "Load multiple 3-element structures to three registers"]
23296#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"]
23297#[doc = "## Safety"]
23298#[doc = "  * Neon instrinsic unsafe"]
23299#[inline]
23300#[target_feature(enable = "neon")]
23301#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23302#[cfg(not(target_arch = "arm"))]
23303#[cfg_attr(test, assert_instr(ld3))]
23304pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
23305    unsafe extern "unadjusted" {
23306        #[cfg_attr(
23307            any(target_arch = "aarch64", target_arch = "arm64ec"),
23308            link_name = "llvm.aarch64.neon.ld3.v4i16.p0"
23309        )]
23310        fn _vld3_s16(ptr: *const int16x4_t) -> int16x4x3_t;
23311    }
23312    _vld3_s16(a as _)
23313}
23314#[doc = "Load multiple 3-element structures to three registers"]
23315#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"]
23316#[doc = "## Safety"]
23317#[doc = "  * Neon instrinsic unsafe"]
23318#[inline]
23319#[target_feature(enable = "neon")]
23320#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23321#[cfg(not(target_arch = "arm"))]
23322#[cfg_attr(test, assert_instr(ld3))]
23323pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
23324    unsafe extern "unadjusted" {
23325        #[cfg_attr(
23326            any(target_arch = "aarch64", target_arch = "arm64ec"),
23327            link_name = "llvm.aarch64.neon.ld3.v8i16.p0"
23328        )]
23329        fn _vld3q_s16(ptr: *const int16x8_t) -> int16x8x3_t;
23330    }
23331    _vld3q_s16(a as _)
23332}
23333#[doc = "Load multiple 3-element structures to three registers"]
23334#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"]
23335#[doc = "## Safety"]
23336#[doc = "  * Neon instrinsic unsafe"]
23337#[inline]
23338#[target_feature(enable = "neon")]
23339#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23340#[cfg(not(target_arch = "arm"))]
23341#[cfg_attr(test, assert_instr(ld3))]
23342pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
23343    unsafe extern "unadjusted" {
23344        #[cfg_attr(
23345            any(target_arch = "aarch64", target_arch = "arm64ec"),
23346            link_name = "llvm.aarch64.neon.ld3.v2i32.p0"
23347        )]
23348        fn _vld3_s32(ptr: *const int32x2_t) -> int32x2x3_t;
23349    }
23350    _vld3_s32(a as _)
23351}
23352#[doc = "Load multiple 3-element structures to three registers"]
23353#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"]
23354#[doc = "## Safety"]
23355#[doc = "  * Neon instrinsic unsafe"]
23356#[inline]
23357#[target_feature(enable = "neon")]
23358#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23359#[cfg(not(target_arch = "arm"))]
23360#[cfg_attr(test, assert_instr(ld3))]
23361pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t {
23362    unsafe extern "unadjusted" {
23363        #[cfg_attr(
23364            any(target_arch = "aarch64", target_arch = "arm64ec"),
23365            link_name = "llvm.aarch64.neon.ld3.v4i32.p0"
23366        )]
23367        fn _vld3q_s32(ptr: *const int32x4_t) -> int32x4x3_t;
23368    }
23369    _vld3q_s32(a as _)
23370}
23371#[doc = "Load multiple 3-element structures to three registers"]
23372#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
23373#[doc = "## Safety"]
23374#[doc = "  * Neon instrinsic unsafe"]
23375#[inline]
23376#[cfg(target_arch = "arm")]
23377#[target_feature(enable = "neon,v7")]
23378#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23379#[cfg_attr(test, assert_instr(vld3))]
23380pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
23381    unsafe extern "unadjusted" {
23382        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v2f32.p0")]
23383        fn _vld3_f32(ptr: *const i8, size: i32) -> float32x2x3_t;
23384    }
23385    _vld3_f32(a as *const i8, 4)
23386}
23387#[doc = "Load multiple 3-element structures to three registers"]
23388#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"]
23389#[doc = "## Safety"]
23390#[doc = "  * Neon instrinsic unsafe"]
23391#[inline]
23392#[cfg(target_arch = "arm")]
23393#[target_feature(enable = "neon,v7")]
23394#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23395#[cfg_attr(test, assert_instr(vld3))]
23396pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
23397    unsafe extern "unadjusted" {
23398        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4f32.p0")]
23399        fn _vld3q_f32(ptr: *const i8, size: i32) -> float32x4x3_t;
23400    }
23401    _vld3q_f32(a as *const i8, 4)
23402}
23403#[doc = "Load multiple 3-element structures to three registers"]
23404#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"]
23405#[doc = "## Safety"]
23406#[doc = "  * Neon instrinsic unsafe"]
23407#[inline]
23408#[cfg(target_arch = "arm")]
23409#[target_feature(enable = "neon,v7")]
23410#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23411#[cfg_attr(test, assert_instr(vld3))]
23412pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
23413    unsafe extern "unadjusted" {
23414        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8i8.p0")]
23415        fn _vld3_s8(ptr: *const i8, size: i32) -> int8x8x3_t;
23416    }
23417    _vld3_s8(a as *const i8, 1)
23418}
23419#[doc = "Load multiple 3-element structures to three registers"]
23420#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"]
23421#[doc = "## Safety"]
23422#[doc = "  * Neon instrinsic unsafe"]
23423#[inline]
23424#[cfg(target_arch = "arm")]
23425#[target_feature(enable = "neon,v7")]
23426#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23427#[cfg_attr(test, assert_instr(vld3))]
23428pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
23429    unsafe extern "unadjusted" {
23430        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v16i8.p0")]
23431        fn _vld3q_s8(ptr: *const i8, size: i32) -> int8x16x3_t;
23432    }
23433    _vld3q_s8(a as *const i8, 1)
23434}
23435#[doc = "Load multiple 3-element structures to three registers"]
23436#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"]
23437#[doc = "## Safety"]
23438#[doc = "  * Neon instrinsic unsafe"]
23439#[inline]
23440#[cfg(target_arch = "arm")]
23441#[target_feature(enable = "neon,v7")]
23442#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23443#[cfg_attr(test, assert_instr(vld3))]
23444pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
23445    unsafe extern "unadjusted" {
23446        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4i16.p0")]
23447        fn _vld3_s16(ptr: *const i8, size: i32) -> int16x4x3_t;
23448    }
23449    _vld3_s16(a as *const i8, 2)
23450}
23451#[doc = "Load multiple 3-element structures to three registers"]
23452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"]
23453#[doc = "## Safety"]
23454#[doc = "  * Neon instrinsic unsafe"]
23455#[inline]
23456#[cfg(target_arch = "arm")]
23457#[target_feature(enable = "neon,v7")]
23458#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23459#[cfg_attr(test, assert_instr(vld3))]
23460pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
23461    unsafe extern "unadjusted" {
23462        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8i16.p0")]
23463        fn _vld3q_s16(ptr: *const i8, size: i32) -> int16x8x3_t;
23464    }
23465    _vld3q_s16(a as *const i8, 2)
23466}
23467#[doc = "Load multiple 3-element structures to three registers"]
23468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"]
23469#[doc = "## Safety"]
23470#[doc = "  * Neon instrinsic unsafe"]
23471#[inline]
23472#[cfg(target_arch = "arm")]
23473#[target_feature(enable = "neon,v7")]
23474#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23475#[cfg_attr(test, assert_instr(vld3))]
23476pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
23477    unsafe extern "unadjusted" {
23478        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v2i32.p0")]
23479        fn _vld3_s32(ptr: *const i8, size: i32) -> int32x2x3_t;
23480    }
23481    _vld3_s32(a as *const i8, 4)
23482}
23483#[doc = "Load multiple 3-element structures to three registers"]
23484#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"]
23485#[doc = "## Safety"]
23486#[doc = "  * Neon instrinsic unsafe"]
23487#[inline]
23488#[cfg(target_arch = "arm")]
23489#[target_feature(enable = "neon,v7")]
23490#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23491#[cfg_attr(test, assert_instr(vld3))]
23492pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t {
23493    unsafe extern "unadjusted" {
23494        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4i32.p0")]
23495        fn _vld3q_s32(ptr: *const i8, size: i32) -> int32x4x3_t;
23496    }
23497    _vld3q_s32(a as *const i8, 4)
23498}
23499#[doc = "Load multiple 3-element structures to two registers"]
23500#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"]
23501#[doc = "## Safety"]
23502#[doc = "  * Neon instrinsic unsafe"]
23503#[inline]
23504#[target_feature(enable = "neon,v7")]
23505#[cfg(target_arch = "arm")]
23506#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
23507#[rustc_legacy_const_generics(2)]
23508#[target_feature(enable = "neon,fp16")]
23509#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23510pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) -> float16x4x3_t {
23511    static_assert_uimm_bits!(LANE, 2);
23512    unsafe extern "unadjusted" {
23513        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4f16.p0")]
23514        fn _vld3_lane_f16(
23515            ptr: *const f16,
23516            a: float16x4_t,
23517            b: float16x4_t,
23518            c: float16x4_t,
23519            n: i32,
23520            size: i32,
23521        ) -> float16x4x3_t;
23522    }
23523    _vld3_lane_f16(a as _, b.0, b.1, b.2, LANE, 2)
23524}
23525#[doc = "Load multiple 3-element structures to two registers"]
23526#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"]
23527#[doc = "## Safety"]
23528#[doc = "  * Neon instrinsic unsafe"]
23529#[inline]
23530#[target_feature(enable = "neon,v7")]
23531#[cfg(target_arch = "arm")]
23532#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
23533#[rustc_legacy_const_generics(2)]
23534#[target_feature(enable = "neon,fp16")]
23535#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23536pub unsafe fn vld3q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x3_t) -> float16x8x3_t {
23537    static_assert_uimm_bits!(LANE, 3);
23538    unsafe extern "unadjusted" {
23539        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8f16.p0")]
23540        fn _vld3q_lane_f16(
23541            ptr: *const f16,
23542            a: float16x8_t,
23543            b: float16x8_t,
23544            c: float16x8_t,
23545            n: i32,
23546            size: i32,
23547        ) -> float16x8x3_t;
23548    }
23549    _vld3q_lane_f16(a as _, b.0, b.1, b.2, LANE, 2)
23550}
23551#[doc = "Load multiple 3-element structures to two registers"]
23552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"]
23553#[doc = "## Safety"]
23554#[doc = "  * Neon instrinsic unsafe"]
23555#[inline]
23556#[cfg(not(target_arch = "arm"))]
23557#[cfg_attr(
23558    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23559    assert_instr(ld3, LANE = 0)
23560)]
23561#[rustc_legacy_const_generics(2)]
23562#[target_feature(enable = "neon,fp16")]
23563#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23564pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) -> float16x4x3_t {
23565    static_assert_uimm_bits!(LANE, 2);
23566    unsafe extern "unadjusted" {
23567        #[cfg_attr(
23568            any(target_arch = "aarch64", target_arch = "arm64ec"),
23569            link_name = "llvm.aarch64.neon.ld3lane.v4f16.p0"
23570        )]
23571        fn _vld3_lane_f16(
23572            a: float16x4_t,
23573            b: float16x4_t,
23574            c: float16x4_t,
23575            n: i64,
23576            ptr: *const f16,
23577        ) -> float16x4x3_t;
23578    }
23579    _vld3_lane_f16(b.0, b.1, b.2, LANE as i64, a as _)
23580}
23581#[doc = "Load multiple 3-element structures to two registers"]
23582#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"]
23583#[doc = "## Safety"]
23584#[doc = "  * Neon instrinsic unsafe"]
23585#[inline]
23586#[cfg(not(target_arch = "arm"))]
23587#[cfg_attr(
23588    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23589    assert_instr(ld3, LANE = 0)
23590)]
23591#[rustc_legacy_const_generics(2)]
23592#[target_feature(enable = "neon,fp16")]
23593#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23594pub unsafe fn vld3q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x3_t) -> float16x8x3_t {
23595    static_assert_uimm_bits!(LANE, 3);
23596    unsafe extern "unadjusted" {
23597        #[cfg_attr(
23598            any(target_arch = "aarch64", target_arch = "arm64ec"),
23599            link_name = "llvm.aarch64.neon.ld3lane.v8f16.p0"
23600        )]
23601        fn _vld3q_lane_f16(
23602            a: float16x8_t,
23603            b: float16x8_t,
23604            c: float16x8_t,
23605            n: i64,
23606            ptr: *const f16,
23607        ) -> float16x8x3_t;
23608    }
23609    _vld3q_lane_f16(b.0, b.1, b.2, LANE as i64, a as _)
23610}
23611#[doc = "Load multiple 3-element structures to three registers"]
23612#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"]
23613#[doc = "## Safety"]
23614#[doc = "  * Neon instrinsic unsafe"]
23615#[inline]
23616#[target_feature(enable = "neon")]
23617#[cfg(not(target_arch = "arm"))]
23618#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23619#[rustc_legacy_const_generics(2)]
23620#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23621pub unsafe fn vld3_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x3_t) -> float32x2x3_t {
23622    static_assert_uimm_bits!(LANE, 1);
23623    unsafe extern "unadjusted" {
23624        #[cfg_attr(
23625            any(target_arch = "aarch64", target_arch = "arm64ec"),
23626            link_name = "llvm.aarch64.neon.ld3lane.v2f32.p0"
23627        )]
23628        fn _vld3_lane_f32(
23629            a: float32x2_t,
23630            b: float32x2_t,
23631            c: float32x2_t,
23632            n: i64,
23633            ptr: *const i8,
23634        ) -> float32x2x3_t;
23635    }
23636    _vld3_lane_f32(b.0, b.1, b.2, LANE as i64, a as _)
23637}
23638#[doc = "Load multiple 3-element structures to three registers"]
23639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"]
23640#[doc = "## Safety"]
23641#[doc = "  * Neon instrinsic unsafe"]
23642#[inline]
23643#[target_feature(enable = "neon")]
23644#[cfg(not(target_arch = "arm"))]
23645#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23646#[rustc_legacy_const_generics(2)]
23647#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23648pub unsafe fn vld3q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x3_t) -> float32x4x3_t {
23649    static_assert_uimm_bits!(LANE, 2);
23650    unsafe extern "unadjusted" {
23651        #[cfg_attr(
23652            any(target_arch = "aarch64", target_arch = "arm64ec"),
23653            link_name = "llvm.aarch64.neon.ld3lane.v4f32.p0"
23654        )]
23655        fn _vld3q_lane_f32(
23656            a: float32x4_t,
23657            b: float32x4_t,
23658            c: float32x4_t,
23659            n: i64,
23660            ptr: *const i8,
23661        ) -> float32x4x3_t;
23662    }
23663    _vld3q_lane_f32(b.0, b.1, b.2, LANE as i64, a as _)
23664}
23665#[doc = "Load multiple 3-element structures to three registers"]
23666#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"]
23667#[doc = "## Safety"]
23668#[doc = "  * Neon instrinsic unsafe"]
23669#[inline]
23670#[cfg(target_arch = "arm")]
23671#[target_feature(enable = "neon,v7")]
23672#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
23673#[rustc_legacy_const_generics(2)]
23674#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23675pub unsafe fn vld3_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x3_t) -> float32x2x3_t {
23676    static_assert_uimm_bits!(LANE, 1);
23677    unsafe extern "unadjusted" {
23678        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v2f32.p0")]
23679        fn _vld3_lane_f32(
23680            ptr: *const i8,
23681            a: float32x2_t,
23682            b: float32x2_t,
23683            c: float32x2_t,
23684            n: i32,
23685            size: i32,
23686        ) -> float32x2x3_t;
23687    }
23688    _vld3_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
23689}
23690#[doc = "Load multiple 3-element structures to two registers"]
23691#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"]
23692#[doc = "## Safety"]
23693#[doc = "  * Neon instrinsic unsafe"]
23694#[inline]
23695#[target_feature(enable = "neon")]
23696#[cfg(not(target_arch = "arm"))]
23697#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23698#[rustc_legacy_const_generics(2)]
23699#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23700pub unsafe fn vld3_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x3_t) -> int8x8x3_t {
23701    static_assert_uimm_bits!(LANE, 3);
23702    unsafe extern "unadjusted" {
23703        #[cfg_attr(
23704            any(target_arch = "aarch64", target_arch = "arm64ec"),
23705            link_name = "llvm.aarch64.neon.ld3lane.v8i8.p0"
23706        )]
23707        fn _vld3_lane_s8(
23708            a: int8x8_t,
23709            b: int8x8_t,
23710            c: int8x8_t,
23711            n: i64,
23712            ptr: *const i8,
23713        ) -> int8x8x3_t;
23714    }
23715    _vld3_lane_s8(b.0, b.1, b.2, LANE as i64, a as _)
23716}
23717#[doc = "Load multiple 3-element structures to two registers"]
23718#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"]
23719#[doc = "## Safety"]
23720#[doc = "  * Neon instrinsic unsafe"]
23721#[inline]
23722#[target_feature(enable = "neon")]
23723#[cfg(not(target_arch = "arm"))]
23724#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23725#[rustc_legacy_const_generics(2)]
23726#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23727pub unsafe fn vld3_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x3_t) -> int16x4x3_t {
23728    static_assert_uimm_bits!(LANE, 2);
23729    unsafe extern "unadjusted" {
23730        #[cfg_attr(
23731            any(target_arch = "aarch64", target_arch = "arm64ec"),
23732            link_name = "llvm.aarch64.neon.ld3lane.v4i16.p0"
23733        )]
23734        fn _vld3_lane_s16(
23735            a: int16x4_t,
23736            b: int16x4_t,
23737            c: int16x4_t,
23738            n: i64,
23739            ptr: *const i8,
23740        ) -> int16x4x3_t;
23741    }
23742    _vld3_lane_s16(b.0, b.1, b.2, LANE as i64, a as _)
23743}
23744#[doc = "Load multiple 3-element structures to two registers"]
23745#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"]
23746#[doc = "## Safety"]
23747#[doc = "  * Neon instrinsic unsafe"]
23748#[inline]
23749#[target_feature(enable = "neon")]
23750#[cfg(not(target_arch = "arm"))]
23751#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23752#[rustc_legacy_const_generics(2)]
23753#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23754pub unsafe fn vld3q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x3_t) -> int16x8x3_t {
23755    static_assert_uimm_bits!(LANE, 4);
23756    unsafe extern "unadjusted" {
23757        #[cfg_attr(
23758            any(target_arch = "aarch64", target_arch = "arm64ec"),
23759            link_name = "llvm.aarch64.neon.ld3lane.v8i16.p0"
23760        )]
23761        fn _vld3q_lane_s16(
23762            a: int16x8_t,
23763            b: int16x8_t,
23764            c: int16x8_t,
23765            n: i64,
23766            ptr: *const i8,
23767        ) -> int16x8x3_t;
23768    }
23769    _vld3q_lane_s16(b.0, b.1, b.2, LANE as i64, a as _)
23770}
23771#[doc = "Load multiple 3-element structures to two registers"]
23772#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"]
23773#[doc = "## Safety"]
23774#[doc = "  * Neon instrinsic unsafe"]
23775#[inline]
23776#[target_feature(enable = "neon")]
23777#[cfg(not(target_arch = "arm"))]
23778#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23779#[rustc_legacy_const_generics(2)]
23780#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23781pub unsafe fn vld3_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x3_t) -> int32x2x3_t {
23782    static_assert_uimm_bits!(LANE, 1);
23783    unsafe extern "unadjusted" {
23784        #[cfg_attr(
23785            any(target_arch = "aarch64", target_arch = "arm64ec"),
23786            link_name = "llvm.aarch64.neon.ld3lane.v2i32.p0"
23787        )]
23788        fn _vld3_lane_s32(
23789            a: int32x2_t,
23790            b: int32x2_t,
23791            c: int32x2_t,
23792            n: i64,
23793            ptr: *const i8,
23794        ) -> int32x2x3_t;
23795    }
23796    _vld3_lane_s32(b.0, b.1, b.2, LANE as i64, a as _)
23797}
23798#[doc = "Load multiple 3-element structures to two registers"]
23799#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"]
23800#[doc = "## Safety"]
23801#[doc = "  * Neon instrinsic unsafe"]
23802#[inline]
23803#[target_feature(enable = "neon")]
23804#[cfg(not(target_arch = "arm"))]
23805#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23806#[rustc_legacy_const_generics(2)]
23807#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23808pub unsafe fn vld3q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x3_t) -> int32x4x3_t {
23809    static_assert_uimm_bits!(LANE, 2);
23810    unsafe extern "unadjusted" {
23811        #[cfg_attr(
23812            any(target_arch = "aarch64", target_arch = "arm64ec"),
23813            link_name = "llvm.aarch64.neon.ld3lane.v4i32.p0"
23814        )]
23815        fn _vld3q_lane_s32(
23816            a: int32x4_t,
23817            b: int32x4_t,
23818            c: int32x4_t,
23819            n: i64,
23820            ptr: *const i8,
23821        ) -> int32x4x3_t;
23822    }
23823    _vld3q_lane_s32(b.0, b.1, b.2, LANE as i64, a as _)
23824}
23825#[doc = "Load multiple 3-element structures to two registers"]
23826#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"]
23827#[doc = "## Safety"]
23828#[doc = "  * Neon instrinsic unsafe"]
23829#[inline]
23830#[cfg(target_arch = "arm")]
23831#[target_feature(enable = "neon,v7")]
23832#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
23833#[rustc_legacy_const_generics(2)]
23834#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23835pub unsafe fn vld3_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x3_t) -> int8x8x3_t {
23836    static_assert_uimm_bits!(LANE, 3);
23837    unsafe extern "unadjusted" {
23838        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8i8.p0")]
23839        fn _vld3_lane_s8(
23840            ptr: *const i8,
23841            a: int8x8_t,
23842            b: int8x8_t,
23843            c: int8x8_t,
23844            n: i32,
23845            size: i32,
23846        ) -> int8x8x3_t;
23847    }
23848    _vld3_lane_s8(a as _, b.0, b.1, b.2, LANE, 1)
23849}
23850#[doc = "Load multiple 3-element structures to two registers"]
23851#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"]
23852#[doc = "## Safety"]
23853#[doc = "  * Neon instrinsic unsafe"]
23854#[inline]
23855#[cfg(target_arch = "arm")]
23856#[target_feature(enable = "neon,v7")]
23857#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
23858#[rustc_legacy_const_generics(2)]
23859#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23860pub unsafe fn vld3_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x3_t) -> int16x4x3_t {
23861    static_assert_uimm_bits!(LANE, 2);
23862    unsafe extern "unadjusted" {
23863        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4i16.p0")]
23864        fn _vld3_lane_s16(
23865            ptr: *const i8,
23866            a: int16x4_t,
23867            b: int16x4_t,
23868            c: int16x4_t,
23869            n: i32,
23870            size: i32,
23871        ) -> int16x4x3_t;
23872    }
23873    _vld3_lane_s16(a as _, b.0, b.1, b.2, LANE, 2)
23874}
23875#[doc = "Load multiple 3-element structures to two registers"]
23876#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"]
23877#[doc = "## Safety"]
23878#[doc = "  * Neon instrinsic unsafe"]
23879#[inline]
23880#[cfg(target_arch = "arm")]
23881#[target_feature(enable = "neon,v7")]
23882#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
23883#[rustc_legacy_const_generics(2)]
23884#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23885pub unsafe fn vld3q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x3_t) -> int16x8x3_t {
23886    static_assert_uimm_bits!(LANE, 3);
23887    unsafe extern "unadjusted" {
23888        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8i16.p0")]
23889        fn _vld3q_lane_s16(
23890            ptr: *const i8,
23891            a: int16x8_t,
23892            b: int16x8_t,
23893            c: int16x8_t,
23894            n: i32,
23895            size: i32,
23896        ) -> int16x8x3_t;
23897    }
23898    _vld3q_lane_s16(a as _, b.0, b.1, b.2, LANE, 2)
23899}
23900#[doc = "Load multiple 3-element structures to two registers"]
23901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"]
23902#[doc = "## Safety"]
23903#[doc = "  * Neon instrinsic unsafe"]
23904#[inline]
23905#[cfg(target_arch = "arm")]
23906#[target_feature(enable = "neon,v7")]
23907#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
23908#[rustc_legacy_const_generics(2)]
23909#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23910pub unsafe fn vld3_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x3_t) -> int32x2x3_t {
23911    static_assert_uimm_bits!(LANE, 1);
23912    unsafe extern "unadjusted" {
23913        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v2i32.p0")]
23914        fn _vld3_lane_s32(
23915            ptr: *const i8,
23916            a: int32x2_t,
23917            b: int32x2_t,
23918            c: int32x2_t,
23919            n: i32,
23920            size: i32,
23921        ) -> int32x2x3_t;
23922    }
23923    _vld3_lane_s32(a as _, b.0, b.1, b.2, LANE, 4)
23924}
23925#[doc = "Load multiple 3-element structures to two registers"]
23926#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"]
23927#[doc = "## Safety"]
23928#[doc = "  * Neon instrinsic unsafe"]
23929#[inline]
23930#[cfg(target_arch = "arm")]
23931#[target_feature(enable = "neon,v7")]
23932#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
23933#[rustc_legacy_const_generics(2)]
23934#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23935pub unsafe fn vld3q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x3_t) -> int32x4x3_t {
23936    static_assert_uimm_bits!(LANE, 2);
23937    unsafe extern "unadjusted" {
23938        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4i32.p0")]
23939        fn _vld3q_lane_s32(
23940            ptr: *const i8,
23941            a: int32x4_t,
23942            b: int32x4_t,
23943            c: int32x4_t,
23944            n: i32,
23945            size: i32,
23946        ) -> int32x4x3_t;
23947    }
23948    _vld3q_lane_s32(a as _, b.0, b.1, b.2, LANE, 4)
23949}
23950#[doc = "Load multiple 3-element structures to three registers"]
23951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u8)"]
23952#[doc = "## Safety"]
23953#[doc = "  * Neon instrinsic unsafe"]
23954#[inline]
23955#[target_feature(enable = "neon")]
23956#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23957#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
23958#[cfg_attr(
23959    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23960    assert_instr(ld3, LANE = 0)
23961)]
23962#[rustc_legacy_const_generics(2)]
23963#[cfg_attr(
23964    not(target_arch = "arm"),
23965    stable(feature = "neon_intrinsics", since = "1.59.0")
23966)]
23967#[cfg_attr(
23968    target_arch = "arm",
23969    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23970)]
23971pub unsafe fn vld3_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x3_t) -> uint8x8x3_t {
23972    static_assert_uimm_bits!(LANE, 3);
23973    transmute(vld3_lane_s8::<LANE>(transmute(a), transmute(b)))
23974}
23975#[doc = "Load multiple 3-element structures to three registers"]
23976#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u16)"]
23977#[doc = "## Safety"]
23978#[doc = "  * Neon instrinsic unsafe"]
23979#[inline]
23980#[target_feature(enable = "neon")]
23981#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23982#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
23983#[cfg_attr(
23984    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23985    assert_instr(ld3, LANE = 0)
23986)]
23987#[rustc_legacy_const_generics(2)]
23988#[cfg_attr(
23989    not(target_arch = "arm"),
23990    stable(feature = "neon_intrinsics", since = "1.59.0")
23991)]
23992#[cfg_attr(
23993    target_arch = "arm",
23994    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23995)]
23996pub unsafe fn vld3_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x3_t) -> uint16x4x3_t {
23997    static_assert_uimm_bits!(LANE, 2);
23998    transmute(vld3_lane_s16::<LANE>(transmute(a), transmute(b)))
23999}
24000#[doc = "Load multiple 3-element structures to three registers"]
24001#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u16)"]
24002#[doc = "## Safety"]
24003#[doc = "  * Neon instrinsic unsafe"]
24004#[inline]
24005#[target_feature(enable = "neon")]
24006#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24007#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24008#[cfg_attr(
24009    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24010    assert_instr(ld3, LANE = 0)
24011)]
24012#[rustc_legacy_const_generics(2)]
24013#[cfg_attr(
24014    not(target_arch = "arm"),
24015    stable(feature = "neon_intrinsics", since = "1.59.0")
24016)]
24017#[cfg_attr(
24018    target_arch = "arm",
24019    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24020)]
24021pub unsafe fn vld3q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x3_t) -> uint16x8x3_t {
24022    static_assert_uimm_bits!(LANE, 3);
24023    transmute(vld3q_lane_s16::<LANE>(transmute(a), transmute(b)))
24024}
24025#[doc = "Load multiple 3-element structures to three registers"]
24026#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u32)"]
24027#[doc = "## Safety"]
24028#[doc = "  * Neon instrinsic unsafe"]
24029#[inline]
24030#[target_feature(enable = "neon")]
24031#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24032#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24033#[cfg_attr(
24034    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24035    assert_instr(ld3, LANE = 0)
24036)]
24037#[rustc_legacy_const_generics(2)]
24038#[cfg_attr(
24039    not(target_arch = "arm"),
24040    stable(feature = "neon_intrinsics", since = "1.59.0")
24041)]
24042#[cfg_attr(
24043    target_arch = "arm",
24044    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24045)]
24046pub unsafe fn vld3_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x3_t) -> uint32x2x3_t {
24047    static_assert_uimm_bits!(LANE, 1);
24048    transmute(vld3_lane_s32::<LANE>(transmute(a), transmute(b)))
24049}
24050#[doc = "Load multiple 3-element structures to three registers"]
24051#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u32)"]
24052#[doc = "## Safety"]
24053#[doc = "  * Neon instrinsic unsafe"]
24054#[inline]
24055#[target_feature(enable = "neon")]
24056#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24057#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24058#[cfg_attr(
24059    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24060    assert_instr(ld3, LANE = 0)
24061)]
24062#[rustc_legacy_const_generics(2)]
24063#[cfg_attr(
24064    not(target_arch = "arm"),
24065    stable(feature = "neon_intrinsics", since = "1.59.0")
24066)]
24067#[cfg_attr(
24068    target_arch = "arm",
24069    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24070)]
24071pub unsafe fn vld3q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x3_t) -> uint32x4x3_t {
24072    static_assert_uimm_bits!(LANE, 2);
24073    transmute(vld3q_lane_s32::<LANE>(transmute(a), transmute(b)))
24074}
24075#[doc = "Load multiple 3-element structures to three registers"]
24076#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p8)"]
24077#[doc = "## Safety"]
24078#[doc = "  * Neon instrinsic unsafe"]
24079#[inline]
24080#[target_feature(enable = "neon")]
24081#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24082#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24083#[cfg_attr(
24084    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24085    assert_instr(ld3, LANE = 0)
24086)]
24087#[rustc_legacy_const_generics(2)]
24088#[cfg_attr(
24089    not(target_arch = "arm"),
24090    stable(feature = "neon_intrinsics", since = "1.59.0")
24091)]
24092#[cfg_attr(
24093    target_arch = "arm",
24094    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24095)]
24096pub unsafe fn vld3_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x3_t) -> poly8x8x3_t {
24097    static_assert_uimm_bits!(LANE, 3);
24098    transmute(vld3_lane_s8::<LANE>(transmute(a), transmute(b)))
24099}
24100#[doc = "Load multiple 3-element structures to three registers"]
24101#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p16)"]
24102#[doc = "## Safety"]
24103#[doc = "  * Neon instrinsic unsafe"]
24104#[inline]
24105#[target_feature(enable = "neon")]
24106#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24107#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24108#[cfg_attr(
24109    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24110    assert_instr(ld3, LANE = 0)
24111)]
24112#[rustc_legacy_const_generics(2)]
24113#[cfg_attr(
24114    not(target_arch = "arm"),
24115    stable(feature = "neon_intrinsics", since = "1.59.0")
24116)]
24117#[cfg_attr(
24118    target_arch = "arm",
24119    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24120)]
24121pub unsafe fn vld3_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x3_t) -> poly16x4x3_t {
24122    static_assert_uimm_bits!(LANE, 2);
24123    transmute(vld3_lane_s16::<LANE>(transmute(a), transmute(b)))
24124}
24125#[doc = "Load multiple 3-element structures to three registers"]
24126#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p16)"]
24127#[doc = "## Safety"]
24128#[doc = "  * Neon instrinsic unsafe"]
24129#[inline]
24130#[target_feature(enable = "neon")]
24131#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24132#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24133#[cfg_attr(
24134    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24135    assert_instr(ld3, LANE = 0)
24136)]
24137#[rustc_legacy_const_generics(2)]
24138#[cfg_attr(
24139    not(target_arch = "arm"),
24140    stable(feature = "neon_intrinsics", since = "1.59.0")
24141)]
24142#[cfg_attr(
24143    target_arch = "arm",
24144    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24145)]
24146pub unsafe fn vld3q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x3_t) -> poly16x8x3_t {
24147    static_assert_uimm_bits!(LANE, 3);
24148    transmute(vld3q_lane_s16::<LANE>(transmute(a), transmute(b)))
24149}
24150#[doc = "Load multiple 3-element structures to three registers"]
24151#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p64)"]
24152#[doc = "## Safety"]
24153#[doc = "  * Neon instrinsic unsafe"]
24154#[inline]
24155#[target_feature(enable = "neon,aes")]
24156#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
24157#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
24158#[cfg_attr(
24159    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24160    assert_instr(nop)
24161)]
24162#[cfg_attr(
24163    not(target_arch = "arm"),
24164    stable(feature = "neon_intrinsics", since = "1.59.0")
24165)]
24166#[cfg_attr(
24167    target_arch = "arm",
24168    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24169)]
24170pub unsafe fn vld3_p64(a: *const p64) -> poly64x1x3_t {
24171    transmute(vld3_s64(transmute(a)))
24172}
24173#[doc = "Load multiple 3-element structures to three registers"]
24174#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"]
24175#[doc = "## Safety"]
24176#[doc = "  * Neon instrinsic unsafe"]
24177#[inline]
24178#[target_feature(enable = "neon")]
24179#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24180#[cfg(not(target_arch = "arm"))]
24181#[cfg_attr(test, assert_instr(nop))]
24182pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t {
24183    unsafe extern "unadjusted" {
24184        #[cfg_attr(
24185            any(target_arch = "aarch64", target_arch = "arm64ec"),
24186            link_name = "llvm.aarch64.neon.ld3.v1i64.p0"
24187        )]
24188        fn _vld3_s64(ptr: *const int64x1_t) -> int64x1x3_t;
24189    }
24190    _vld3_s64(a as _)
24191}
24192#[doc = "Load multiple 3-element structures to three registers"]
24193#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"]
24194#[doc = "## Safety"]
24195#[doc = "  * Neon instrinsic unsafe"]
24196#[inline]
24197#[cfg(target_arch = "arm")]
24198#[target_feature(enable = "neon,v7")]
24199#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24200#[cfg_attr(test, assert_instr(nop))]
24201pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t {
24202    unsafe extern "unadjusted" {
24203        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v1i64.p0")]
24204        fn _vld3_s64(ptr: *const i8, size: i32) -> int64x1x3_t;
24205    }
24206    _vld3_s64(a as *const i8, 8)
24207}
24208#[doc = "Load multiple 3-element structures to three registers"]
24209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u64)"]
24210#[doc = "## Safety"]
24211#[doc = "  * Neon instrinsic unsafe"]
24212#[inline]
24213#[target_feature(enable = "neon")]
24214#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24215#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
24216#[cfg_attr(
24217    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24218    assert_instr(nop)
24219)]
24220#[cfg_attr(
24221    not(target_arch = "arm"),
24222    stable(feature = "neon_intrinsics", since = "1.59.0")
24223)]
24224#[cfg_attr(
24225    target_arch = "arm",
24226    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24227)]
24228pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t {
24229    transmute(vld3_s64(transmute(a)))
24230}
24231#[doc = "Load multiple 3-element structures to three registers"]
24232#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"]
24233#[doc = "## Safety"]
24234#[doc = "  * Neon instrinsic unsafe"]
24235#[inline]
24236#[cfg(target_endian = "little")]
24237#[target_feature(enable = "neon")]
24238#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24239#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24240#[cfg_attr(
24241    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24242    assert_instr(ld3)
24243)]
24244#[cfg_attr(
24245    not(target_arch = "arm"),
24246    stable(feature = "neon_intrinsics", since = "1.59.0")
24247)]
24248#[cfg_attr(
24249    target_arch = "arm",
24250    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24251)]
24252pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t {
24253    transmute(vld3_s8(transmute(a)))
24254}
24255#[doc = "Load multiple 3-element structures to three registers"]
24256#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"]
24257#[doc = "## Safety"]
24258#[doc = "  * Neon instrinsic unsafe"]
24259#[inline]
24260#[cfg(target_endian = "big")]
24261#[target_feature(enable = "neon")]
24262#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24263#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24264#[cfg_attr(
24265    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24266    assert_instr(ld3)
24267)]
24268#[cfg_attr(
24269    not(target_arch = "arm"),
24270    stable(feature = "neon_intrinsics", since = "1.59.0")
24271)]
24272#[cfg_attr(
24273    target_arch = "arm",
24274    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24275)]
24276pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t {
24277    let mut ret_val: uint8x8x3_t = transmute(vld3_s8(transmute(a)));
24278    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
24279    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
24280    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
24281    ret_val
24282}
24283#[doc = "Load multiple 3-element structures to three registers"]
24284#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"]
24285#[doc = "## Safety"]
24286#[doc = "  * Neon instrinsic unsafe"]
24287#[inline]
24288#[cfg(target_endian = "little")]
24289#[target_feature(enable = "neon")]
24290#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24291#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24292#[cfg_attr(
24293    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24294    assert_instr(ld3)
24295)]
24296#[cfg_attr(
24297    not(target_arch = "arm"),
24298    stable(feature = "neon_intrinsics", since = "1.59.0")
24299)]
24300#[cfg_attr(
24301    target_arch = "arm",
24302    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24303)]
24304pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
24305    transmute(vld3q_s8(transmute(a)))
24306}
24307#[doc = "Load multiple 3-element structures to three registers"]
24308#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"]
24309#[doc = "## Safety"]
24310#[doc = "  * Neon instrinsic unsafe"]
24311#[inline]
24312#[cfg(target_endian = "big")]
24313#[target_feature(enable = "neon")]
24314#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24315#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24316#[cfg_attr(
24317    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24318    assert_instr(ld3)
24319)]
24320#[cfg_attr(
24321    not(target_arch = "arm"),
24322    stable(feature = "neon_intrinsics", since = "1.59.0")
24323)]
24324#[cfg_attr(
24325    target_arch = "arm",
24326    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24327)]
24328pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
24329    let mut ret_val: uint8x16x3_t = transmute(vld3q_s8(transmute(a)));
24330    ret_val.0 = unsafe {
24331        simd_shuffle!(
24332            ret_val.0,
24333            ret_val.0,
24334            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24335        )
24336    };
24337    ret_val.1 = unsafe {
24338        simd_shuffle!(
24339            ret_val.1,
24340            ret_val.1,
24341            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24342        )
24343    };
24344    ret_val.2 = unsafe {
24345        simd_shuffle!(
24346            ret_val.2,
24347            ret_val.2,
24348            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24349        )
24350    };
24351    ret_val
24352}
24353#[doc = "Load multiple 3-element structures to three registers"]
24354#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"]
24355#[doc = "## Safety"]
24356#[doc = "  * Neon instrinsic unsafe"]
24357#[inline]
24358#[cfg(target_endian = "little")]
24359#[target_feature(enable = "neon")]
24360#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24361#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24362#[cfg_attr(
24363    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24364    assert_instr(ld3)
24365)]
24366#[cfg_attr(
24367    not(target_arch = "arm"),
24368    stable(feature = "neon_intrinsics", since = "1.59.0")
24369)]
24370#[cfg_attr(
24371    target_arch = "arm",
24372    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24373)]
24374pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
24375    transmute(vld3_s16(transmute(a)))
24376}
24377#[doc = "Load multiple 3-element structures to three registers"]
24378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"]
24379#[doc = "## Safety"]
24380#[doc = "  * Neon instrinsic unsafe"]
24381#[inline]
24382#[cfg(target_endian = "big")]
24383#[target_feature(enable = "neon")]
24384#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24385#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24386#[cfg_attr(
24387    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24388    assert_instr(ld3)
24389)]
24390#[cfg_attr(
24391    not(target_arch = "arm"),
24392    stable(feature = "neon_intrinsics", since = "1.59.0")
24393)]
24394#[cfg_attr(
24395    target_arch = "arm",
24396    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24397)]
24398pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
24399    let mut ret_val: uint16x4x3_t = transmute(vld3_s16(transmute(a)));
24400    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
24401    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
24402    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
24403    ret_val
24404}
24405#[doc = "Load multiple 3-element structures to three registers"]
24406#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"]
24407#[doc = "## Safety"]
24408#[doc = "  * Neon instrinsic unsafe"]
24409#[inline]
24410#[cfg(target_endian = "little")]
24411#[target_feature(enable = "neon")]
24412#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24413#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24414#[cfg_attr(
24415    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24416    assert_instr(ld3)
24417)]
24418#[cfg_attr(
24419    not(target_arch = "arm"),
24420    stable(feature = "neon_intrinsics", since = "1.59.0")
24421)]
24422#[cfg_attr(
24423    target_arch = "arm",
24424    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24425)]
24426pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
24427    transmute(vld3q_s16(transmute(a)))
24428}
24429#[doc = "Load multiple 3-element structures to three registers"]
24430#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"]
24431#[doc = "## Safety"]
24432#[doc = "  * Neon instrinsic unsafe"]
24433#[inline]
24434#[cfg(target_endian = "big")]
24435#[target_feature(enable = "neon")]
24436#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24437#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24438#[cfg_attr(
24439    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24440    assert_instr(ld3)
24441)]
24442#[cfg_attr(
24443    not(target_arch = "arm"),
24444    stable(feature = "neon_intrinsics", since = "1.59.0")
24445)]
24446#[cfg_attr(
24447    target_arch = "arm",
24448    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24449)]
24450pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
24451    let mut ret_val: uint16x8x3_t = transmute(vld3q_s16(transmute(a)));
24452    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
24453    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
24454    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
24455    ret_val
24456}
24457#[doc = "Load multiple 3-element structures to three registers"]
24458#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"]
24459#[doc = "## Safety"]
24460#[doc = "  * Neon instrinsic unsafe"]
24461#[inline]
24462#[cfg(target_endian = "little")]
24463#[target_feature(enable = "neon")]
24464#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24465#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24466#[cfg_attr(
24467    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24468    assert_instr(ld3)
24469)]
24470#[cfg_attr(
24471    not(target_arch = "arm"),
24472    stable(feature = "neon_intrinsics", since = "1.59.0")
24473)]
24474#[cfg_attr(
24475    target_arch = "arm",
24476    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24477)]
24478pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t {
24479    transmute(vld3_s32(transmute(a)))
24480}
24481#[doc = "Load multiple 3-element structures to three registers"]
24482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"]
24483#[doc = "## Safety"]
24484#[doc = "  * Neon instrinsic unsafe"]
24485#[inline]
24486#[cfg(target_endian = "big")]
24487#[target_feature(enable = "neon")]
24488#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24489#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24490#[cfg_attr(
24491    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24492    assert_instr(ld3)
24493)]
24494#[cfg_attr(
24495    not(target_arch = "arm"),
24496    stable(feature = "neon_intrinsics", since = "1.59.0")
24497)]
24498#[cfg_attr(
24499    target_arch = "arm",
24500    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24501)]
24502pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t {
24503    let mut ret_val: uint32x2x3_t = transmute(vld3_s32(transmute(a)));
24504    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
24505    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
24506    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
24507    ret_val
24508}
24509#[doc = "Load multiple 3-element structures to three registers"]
24510#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"]
24511#[doc = "## Safety"]
24512#[doc = "  * Neon instrinsic unsafe"]
24513#[inline]
24514#[cfg(target_endian = "little")]
24515#[target_feature(enable = "neon")]
24516#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24517#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24518#[cfg_attr(
24519    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24520    assert_instr(ld3)
24521)]
24522#[cfg_attr(
24523    not(target_arch = "arm"),
24524    stable(feature = "neon_intrinsics", since = "1.59.0")
24525)]
24526#[cfg_attr(
24527    target_arch = "arm",
24528    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24529)]
24530pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t {
24531    transmute(vld3q_s32(transmute(a)))
24532}
24533#[doc = "Load multiple 3-element structures to three registers"]
24534#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"]
24535#[doc = "## Safety"]
24536#[doc = "  * Neon instrinsic unsafe"]
24537#[inline]
24538#[cfg(target_endian = "big")]
24539#[target_feature(enable = "neon")]
24540#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24541#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24542#[cfg_attr(
24543    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24544    assert_instr(ld3)
24545)]
24546#[cfg_attr(
24547    not(target_arch = "arm"),
24548    stable(feature = "neon_intrinsics", since = "1.59.0")
24549)]
24550#[cfg_attr(
24551    target_arch = "arm",
24552    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24553)]
24554pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t {
24555    let mut ret_val: uint32x4x3_t = transmute(vld3q_s32(transmute(a)));
24556    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
24557    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
24558    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
24559    ret_val
24560}
24561#[doc = "Load multiple 3-element structures to three registers"]
24562#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"]
24563#[doc = "## Safety"]
24564#[doc = "  * Neon instrinsic unsafe"]
24565#[inline]
24566#[cfg(target_endian = "little")]
24567#[target_feature(enable = "neon")]
24568#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24569#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24570#[cfg_attr(
24571    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24572    assert_instr(ld3)
24573)]
24574#[cfg_attr(
24575    not(target_arch = "arm"),
24576    stable(feature = "neon_intrinsics", since = "1.59.0")
24577)]
24578#[cfg_attr(
24579    target_arch = "arm",
24580    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24581)]
24582pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t {
24583    transmute(vld3_s8(transmute(a)))
24584}
24585#[doc = "Load multiple 3-element structures to three registers"]
24586#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"]
24587#[doc = "## Safety"]
24588#[doc = "  * Neon instrinsic unsafe"]
24589#[inline]
24590#[cfg(target_endian = "big")]
24591#[target_feature(enable = "neon")]
24592#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24593#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24594#[cfg_attr(
24595    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24596    assert_instr(ld3)
24597)]
24598#[cfg_attr(
24599    not(target_arch = "arm"),
24600    stable(feature = "neon_intrinsics", since = "1.59.0")
24601)]
24602#[cfg_attr(
24603    target_arch = "arm",
24604    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24605)]
24606pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t {
24607    let mut ret_val: poly8x8x3_t = transmute(vld3_s8(transmute(a)));
24608    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
24609    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
24610    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
24611    ret_val
24612}
24613#[doc = "Load multiple 3-element structures to three registers"]
24614#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"]
24615#[doc = "## Safety"]
24616#[doc = "  * Neon instrinsic unsafe"]
24617#[inline]
24618#[cfg(target_endian = "little")]
24619#[target_feature(enable = "neon")]
24620#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24621#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24622#[cfg_attr(
24623    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24624    assert_instr(ld3)
24625)]
24626#[cfg_attr(
24627    not(target_arch = "arm"),
24628    stable(feature = "neon_intrinsics", since = "1.59.0")
24629)]
24630#[cfg_attr(
24631    target_arch = "arm",
24632    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24633)]
24634pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t {
24635    transmute(vld3q_s8(transmute(a)))
24636}
24637#[doc = "Load multiple 3-element structures to three registers"]
24638#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"]
24639#[doc = "## Safety"]
24640#[doc = "  * Neon instrinsic unsafe"]
24641#[inline]
24642#[cfg(target_endian = "big")]
24643#[target_feature(enable = "neon")]
24644#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24645#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24646#[cfg_attr(
24647    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24648    assert_instr(ld3)
24649)]
24650#[cfg_attr(
24651    not(target_arch = "arm"),
24652    stable(feature = "neon_intrinsics", since = "1.59.0")
24653)]
24654#[cfg_attr(
24655    target_arch = "arm",
24656    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24657)]
24658pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t {
24659    let mut ret_val: poly8x16x3_t = transmute(vld3q_s8(transmute(a)));
24660    ret_val.0 = unsafe {
24661        simd_shuffle!(
24662            ret_val.0,
24663            ret_val.0,
24664            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24665        )
24666    };
24667    ret_val.1 = unsafe {
24668        simd_shuffle!(
24669            ret_val.1,
24670            ret_val.1,
24671            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24672        )
24673    };
24674    ret_val.2 = unsafe {
24675        simd_shuffle!(
24676            ret_val.2,
24677            ret_val.2,
24678            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24679        )
24680    };
24681    ret_val
24682}
24683#[doc = "Load multiple 3-element structures to three registers"]
24684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"]
24685#[doc = "## Safety"]
24686#[doc = "  * Neon instrinsic unsafe"]
24687#[inline]
24688#[cfg(target_endian = "little")]
24689#[target_feature(enable = "neon")]
24690#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24691#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24692#[cfg_attr(
24693    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24694    assert_instr(ld3)
24695)]
24696#[cfg_attr(
24697    not(target_arch = "arm"),
24698    stable(feature = "neon_intrinsics", since = "1.59.0")
24699)]
24700#[cfg_attr(
24701    target_arch = "arm",
24702    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24703)]
24704pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t {
24705    transmute(vld3_s16(transmute(a)))
24706}
24707#[doc = "Load multiple 3-element structures to three registers"]
24708#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"]
24709#[doc = "## Safety"]
24710#[doc = "  * Neon instrinsic unsafe"]
24711#[inline]
24712#[cfg(target_endian = "big")]
24713#[target_feature(enable = "neon")]
24714#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24715#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24716#[cfg_attr(
24717    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24718    assert_instr(ld3)
24719)]
24720#[cfg_attr(
24721    not(target_arch = "arm"),
24722    stable(feature = "neon_intrinsics", since = "1.59.0")
24723)]
24724#[cfg_attr(
24725    target_arch = "arm",
24726    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24727)]
24728pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t {
24729    let mut ret_val: poly16x4x3_t = transmute(vld3_s16(transmute(a)));
24730    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
24731    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
24732    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
24733    ret_val
24734}
24735#[doc = "Load multiple 3-element structures to three registers"]
24736#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"]
24737#[doc = "## Safety"]
24738#[doc = "  * Neon instrinsic unsafe"]
24739#[inline]
24740#[cfg(target_endian = "little")]
24741#[target_feature(enable = "neon")]
24742#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24743#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24744#[cfg_attr(
24745    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24746    assert_instr(ld3)
24747)]
24748#[cfg_attr(
24749    not(target_arch = "arm"),
24750    stable(feature = "neon_intrinsics", since = "1.59.0")
24751)]
24752#[cfg_attr(
24753    target_arch = "arm",
24754    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24755)]
24756pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t {
24757    transmute(vld3q_s16(transmute(a)))
24758}
24759#[doc = "Load multiple 3-element structures to three registers"]
24760#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"]
24761#[doc = "## Safety"]
24762#[doc = "  * Neon instrinsic unsafe"]
24763#[inline]
24764#[cfg(target_endian = "big")]
24765#[target_feature(enable = "neon")]
24766#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24767#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24768#[cfg_attr(
24769    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24770    assert_instr(ld3)
24771)]
24772#[cfg_attr(
24773    not(target_arch = "arm"),
24774    stable(feature = "neon_intrinsics", since = "1.59.0")
24775)]
24776#[cfg_attr(
24777    target_arch = "arm",
24778    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24779)]
24780pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t {
24781    let mut ret_val: poly16x8x3_t = transmute(vld3q_s16(transmute(a)));
24782    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
24783    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
24784    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
24785    ret_val
24786}
24787#[doc = "Load multiple 3-element structures to three registers"]
24788#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"]
24789#[doc = "## Safety"]
24790#[doc = "  * Neon instrinsic unsafe"]
24791#[inline]
24792#[cfg(target_arch = "arm")]
24793#[target_feature(enable = "neon,v7")]
24794#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
24795#[rustc_legacy_const_generics(2)]
24796#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24797pub unsafe fn vld3q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x3_t) -> float32x4x3_t {
24798    static_assert_uimm_bits!(LANE, 2);
24799    unsafe extern "unadjusted" {
24800        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4f32.p0")]
24801        fn _vld3q_lane_f32(
24802            ptr: *const i8,
24803            a: float32x4_t,
24804            b: float32x4_t,
24805            c: float32x4_t,
24806            n: i32,
24807            size: i32,
24808        ) -> float32x4x3_t;
24809    }
24810    _vld3q_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
24811}
24812#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
24813#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
24814#[doc = "## Safety"]
24815#[doc = "  * Neon instrinsic unsafe"]
24816#[inline]
24817#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24818#[cfg(target_arch = "arm")]
24819#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
24820#[target_feature(enable = "neon,fp16")]
24821#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
24822pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
24823    unsafe extern "unadjusted" {
24824        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4f16.p0")]
24825        fn _vld4_dup_f16(ptr: *const f16, size: i32) -> float16x4x4_t;
24826    }
24827    _vld4_dup_f16(a as _, 2)
24828}
24829#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
24830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
24831#[doc = "## Safety"]
24832#[doc = "  * Neon instrinsic unsafe"]
24833#[inline]
24834#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24835#[cfg(target_arch = "arm")]
24836#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
24837#[target_feature(enable = "neon,fp16")]
24838#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
24839pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
24840    unsafe extern "unadjusted" {
24841        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8f16.p0")]
24842        fn _vld4q_dup_f16(ptr: *const f16, size: i32) -> float16x8x4_t;
24843    }
24844    _vld4q_dup_f16(a as _, 2)
24845}
24846#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
24847#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
24848#[doc = "## Safety"]
24849#[doc = "  * Neon instrinsic unsafe"]
24850#[inline]
24851#[cfg(not(target_arch = "arm"))]
24852#[cfg_attr(
24853    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24854    assert_instr(ld4r)
24855)]
24856#[target_feature(enable = "neon,fp16")]
24857#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
24858pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
24859    unsafe extern "unadjusted" {
24860        #[cfg_attr(
24861            any(target_arch = "aarch64", target_arch = "arm64ec"),
24862            link_name = "llvm.aarch64.neon.ld4r.v4f16.p0"
24863        )]
24864        fn _vld4_dup_f16(ptr: *const f16) -> float16x4x4_t;
24865    }
24866    _vld4_dup_f16(a as _)
24867}
24868#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
24869#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
24870#[doc = "## Safety"]
24871#[doc = "  * Neon instrinsic unsafe"]
24872#[inline]
24873#[cfg(not(target_arch = "arm"))]
24874#[cfg_attr(
24875    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24876    assert_instr(ld4r)
24877)]
24878#[target_feature(enable = "neon,fp16")]
24879#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
24880pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
24881    unsafe extern "unadjusted" {
24882        #[cfg_attr(
24883            any(target_arch = "aarch64", target_arch = "arm64ec"),
24884            link_name = "llvm.aarch64.neon.ld4r.v8f16.p0"
24885        )]
24886        fn _vld4q_dup_f16(ptr: *const f16) -> float16x8x4_t;
24887    }
24888    _vld4q_dup_f16(a as _)
24889}
24890#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
24891#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"]
24892#[doc = "## Safety"]
24893#[doc = "  * Neon instrinsic unsafe"]
24894#[inline]
24895#[cfg(target_arch = "arm")]
24896#[target_feature(enable = "neon,v7")]
24897#[cfg_attr(test, assert_instr(vld4))]
24898#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24899pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t {
24900    unsafe extern "unadjusted" {
24901        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v2f32.p0")]
24902        fn _vld4_dup_f32(ptr: *const i8, size: i32) -> float32x2x4_t;
24903    }
24904    _vld4_dup_f32(a as *const i8, 4)
24905}
24906#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
24907#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"]
24908#[doc = "## Safety"]
24909#[doc = "  * Neon instrinsic unsafe"]
24910#[inline]
24911#[cfg(target_arch = "arm")]
24912#[target_feature(enable = "neon,v7")]
24913#[cfg_attr(test, assert_instr(vld4))]
24914#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24915pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t {
24916    unsafe extern "unadjusted" {
24917        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4f32.p0")]
24918        fn _vld4q_dup_f32(ptr: *const i8, size: i32) -> float32x4x4_t;
24919    }
24920    _vld4q_dup_f32(a as *const i8, 4)
24921}
24922#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
24923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"]
24924#[doc = "## Safety"]
24925#[doc = "  * Neon instrinsic unsafe"]
24926#[inline]
24927#[cfg(target_arch = "arm")]
24928#[target_feature(enable = "neon,v7")]
24929#[cfg_attr(test, assert_instr(vld4))]
24930#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24931pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t {
24932    unsafe extern "unadjusted" {
24933        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8i8.p0")]
24934        fn _vld4_dup_s8(ptr: *const i8, size: i32) -> int8x8x4_t;
24935    }
24936    _vld4_dup_s8(a as *const i8, 1)
24937}
24938#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
24939#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"]
24940#[doc = "## Safety"]
24941#[doc = "  * Neon instrinsic unsafe"]
24942#[inline]
24943#[cfg(target_arch = "arm")]
24944#[target_feature(enable = "neon,v7")]
24945#[cfg_attr(test, assert_instr(vld4))]
24946#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24947pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t {
24948    unsafe extern "unadjusted" {
24949        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v16i8.p0")]
24950        fn _vld4q_dup_s8(ptr: *const i8, size: i32) -> int8x16x4_t;
24951    }
24952    _vld4q_dup_s8(a as *const i8, 1)
24953}
24954#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
24955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"]
24956#[doc = "## Safety"]
24957#[doc = "  * Neon instrinsic unsafe"]
24958#[inline]
24959#[cfg(target_arch = "arm")]
24960#[target_feature(enable = "neon,v7")]
24961#[cfg_attr(test, assert_instr(vld4))]
24962#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24963pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t {
24964    unsafe extern "unadjusted" {
24965        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4i16.p0")]
24966        fn _vld4_dup_s16(ptr: *const i8, size: i32) -> int16x4x4_t;
24967    }
24968    _vld4_dup_s16(a as *const i8, 2)
24969}
24970#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
24971#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"]
24972#[doc = "## Safety"]
24973#[doc = "  * Neon instrinsic unsafe"]
24974#[inline]
24975#[cfg(target_arch = "arm")]
24976#[target_feature(enable = "neon,v7")]
24977#[cfg_attr(test, assert_instr(vld4))]
24978#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24979pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t {
24980    unsafe extern "unadjusted" {
24981        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8i16.p0")]
24982        fn _vld4q_dup_s16(ptr: *const i8, size: i32) -> int16x8x4_t;
24983    }
24984    _vld4q_dup_s16(a as *const i8, 2)
24985}
24986#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
24987#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"]
24988#[doc = "## Safety"]
24989#[doc = "  * Neon instrinsic unsafe"]
24990#[inline]
24991#[cfg(target_arch = "arm")]
24992#[target_feature(enable = "neon,v7")]
24993#[cfg_attr(test, assert_instr(vld4))]
24994#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24995pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t {
24996    unsafe extern "unadjusted" {
24997        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v2i32.p0")]
24998        fn _vld4_dup_s32(ptr: *const i8, size: i32) -> int32x2x4_t;
24999    }
25000    _vld4_dup_s32(a as *const i8, 4)
25001}
25002#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25003#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"]
25004#[doc = "## Safety"]
25005#[doc = "  * Neon instrinsic unsafe"]
25006#[inline]
25007#[cfg(target_arch = "arm")]
25008#[target_feature(enable = "neon,v7")]
25009#[cfg_attr(test, assert_instr(vld4))]
25010#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
25011pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t {
25012    unsafe extern "unadjusted" {
25013        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4i32.p0")]
25014        fn _vld4q_dup_s32(ptr: *const i8, size: i32) -> int32x4x4_t;
25015    }
25016    _vld4q_dup_s32(a as *const i8, 4)
25017}
25018#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25019#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"]
25020#[doc = "## Safety"]
25021#[doc = "  * Neon instrinsic unsafe"]
25022#[inline]
25023#[target_feature(enable = "neon")]
25024#[cfg(not(target_arch = "arm"))]
25025#[cfg_attr(test, assert_instr(ld4r))]
25026#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25027pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t {
25028    unsafe extern "unadjusted" {
25029        #[cfg_attr(
25030            any(target_arch = "aarch64", target_arch = "arm64ec"),
25031            link_name = "llvm.aarch64.neon.ld4r.v2f32.p0.p0"
25032        )]
25033        fn _vld4_dup_f32(ptr: *const f32) -> float32x2x4_t;
25034    }
25035    _vld4_dup_f32(a as _)
25036}
25037#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25038#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"]
25039#[doc = "## Safety"]
25040#[doc = "  * Neon instrinsic unsafe"]
25041#[inline]
25042#[target_feature(enable = "neon")]
25043#[cfg(not(target_arch = "arm"))]
25044#[cfg_attr(test, assert_instr(ld4r))]
25045#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25046pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t {
25047    unsafe extern "unadjusted" {
25048        #[cfg_attr(
25049            any(target_arch = "aarch64", target_arch = "arm64ec"),
25050            link_name = "llvm.aarch64.neon.ld4r.v4f32.p0.p0"
25051        )]
25052        fn _vld4q_dup_f32(ptr: *const f32) -> float32x4x4_t;
25053    }
25054    _vld4q_dup_f32(a as _)
25055}
25056#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"]
25058#[doc = "## Safety"]
25059#[doc = "  * Neon instrinsic unsafe"]
25060#[inline]
25061#[target_feature(enable = "neon")]
25062#[cfg(not(target_arch = "arm"))]
25063#[cfg_attr(test, assert_instr(ld4r))]
25064#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25065pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t {
25066    unsafe extern "unadjusted" {
25067        #[cfg_attr(
25068            any(target_arch = "aarch64", target_arch = "arm64ec"),
25069            link_name = "llvm.aarch64.neon.ld4r.v8i8.p0.p0"
25070        )]
25071        fn _vld4_dup_s8(ptr: *const i8) -> int8x8x4_t;
25072    }
25073    _vld4_dup_s8(a as _)
25074}
25075#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25076#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"]
25077#[doc = "## Safety"]
25078#[doc = "  * Neon instrinsic unsafe"]
25079#[inline]
25080#[target_feature(enable = "neon")]
25081#[cfg(not(target_arch = "arm"))]
25082#[cfg_attr(test, assert_instr(ld4r))]
25083#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25084pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t {
25085    unsafe extern "unadjusted" {
25086        #[cfg_attr(
25087            any(target_arch = "aarch64", target_arch = "arm64ec"),
25088            link_name = "llvm.aarch64.neon.ld4r.v16i8.p0.p0"
25089        )]
25090        fn _vld4q_dup_s8(ptr: *const i8) -> int8x16x4_t;
25091    }
25092    _vld4q_dup_s8(a as _)
25093}
25094#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25095#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"]
25096#[doc = "## Safety"]
25097#[doc = "  * Neon instrinsic unsafe"]
25098#[inline]
25099#[target_feature(enable = "neon")]
25100#[cfg(not(target_arch = "arm"))]
25101#[cfg_attr(test, assert_instr(ld4r))]
25102#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25103pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t {
25104    unsafe extern "unadjusted" {
25105        #[cfg_attr(
25106            any(target_arch = "aarch64", target_arch = "arm64ec"),
25107            link_name = "llvm.aarch64.neon.ld4r.v4i16.p0.p0"
25108        )]
25109        fn _vld4_dup_s16(ptr: *const i16) -> int16x4x4_t;
25110    }
25111    _vld4_dup_s16(a as _)
25112}
25113#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25114#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"]
25115#[doc = "## Safety"]
25116#[doc = "  * Neon instrinsic unsafe"]
25117#[inline]
25118#[target_feature(enable = "neon")]
25119#[cfg(not(target_arch = "arm"))]
25120#[cfg_attr(test, assert_instr(ld4r))]
25121#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25122pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t {
25123    unsafe extern "unadjusted" {
25124        #[cfg_attr(
25125            any(target_arch = "aarch64", target_arch = "arm64ec"),
25126            link_name = "llvm.aarch64.neon.ld4r.v8i16.p0.p0"
25127        )]
25128        fn _vld4q_dup_s16(ptr: *const i16) -> int16x8x4_t;
25129    }
25130    _vld4q_dup_s16(a as _)
25131}
25132#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25133#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"]
25134#[doc = "## Safety"]
25135#[doc = "  * Neon instrinsic unsafe"]
25136#[inline]
25137#[target_feature(enable = "neon")]
25138#[cfg(not(target_arch = "arm"))]
25139#[cfg_attr(test, assert_instr(ld4r))]
25140#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25141pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t {
25142    unsafe extern "unadjusted" {
25143        #[cfg_attr(
25144            any(target_arch = "aarch64", target_arch = "arm64ec"),
25145            link_name = "llvm.aarch64.neon.ld4r.v2i32.p0.p0"
25146        )]
25147        fn _vld4_dup_s32(ptr: *const i32) -> int32x2x4_t;
25148    }
25149    _vld4_dup_s32(a as _)
25150}
25151#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"]
25153#[doc = "## Safety"]
25154#[doc = "  * Neon instrinsic unsafe"]
25155#[inline]
25156#[target_feature(enable = "neon")]
25157#[cfg(not(target_arch = "arm"))]
25158#[cfg_attr(test, assert_instr(ld4r))]
25159#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25160pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t {
25161    unsafe extern "unadjusted" {
25162        #[cfg_attr(
25163            any(target_arch = "aarch64", target_arch = "arm64ec"),
25164            link_name = "llvm.aarch64.neon.ld4r.v4i32.p0.p0"
25165        )]
25166        fn _vld4q_dup_s32(ptr: *const i32) -> int32x4x4_t;
25167    }
25168    _vld4q_dup_s32(a as _)
25169}
25170#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25171#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"]
25172#[doc = "## Safety"]
25173#[doc = "  * Neon instrinsic unsafe"]
25174#[inline]
25175#[target_feature(enable = "neon")]
25176#[cfg(not(target_arch = "arm"))]
25177#[cfg_attr(test, assert_instr(ld4r))]
25178#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25179pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t {
25180    unsafe extern "unadjusted" {
25181        #[cfg_attr(
25182            any(target_arch = "aarch64", target_arch = "arm64ec"),
25183            link_name = "llvm.aarch64.neon.ld4r.v1i64.p0.p0"
25184        )]
25185        fn _vld4_dup_s64(ptr: *const i64) -> int64x1x4_t;
25186    }
25187    _vld4_dup_s64(a as _)
25188}
25189#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25190#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p64)"]
25191#[doc = "## Safety"]
25192#[doc = "  * Neon instrinsic unsafe"]
25193#[inline]
25194#[target_feature(enable = "neon,aes")]
25195#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
25196#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
25197#[cfg_attr(
25198    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25199    assert_instr(ld4r)
25200)]
25201#[cfg_attr(
25202    not(target_arch = "arm"),
25203    stable(feature = "neon_intrinsics", since = "1.59.0")
25204)]
25205#[cfg_attr(
25206    target_arch = "arm",
25207    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25208)]
25209pub unsafe fn vld4_dup_p64(a: *const p64) -> poly64x1x4_t {
25210    transmute(vld4_dup_s64(transmute(a)))
25211}
25212#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25213#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"]
25214#[doc = "## Safety"]
25215#[doc = "  * Neon instrinsic unsafe"]
25216#[inline]
25217#[cfg(target_arch = "arm")]
25218#[target_feature(enable = "neon,v7")]
25219#[cfg_attr(test, assert_instr(nop))]
25220#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
25221pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t {
25222    unsafe extern "unadjusted" {
25223        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v1i64.p0")]
25224        fn _vld4_dup_s64(ptr: *const i8, size: i32) -> int64x1x4_t;
25225    }
25226    _vld4_dup_s64(a as *const i8, 8)
25227}
25228#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25229#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u64)"]
25230#[doc = "## Safety"]
25231#[doc = "  * Neon instrinsic unsafe"]
25232#[inline]
25233#[target_feature(enable = "neon")]
25234#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25235#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
25236#[cfg_attr(
25237    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25238    assert_instr(ld4r)
25239)]
25240#[cfg_attr(
25241    not(target_arch = "arm"),
25242    stable(feature = "neon_intrinsics", since = "1.59.0")
25243)]
25244#[cfg_attr(
25245    target_arch = "arm",
25246    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25247)]
25248pub unsafe fn vld4_dup_u64(a: *const u64) -> uint64x1x4_t {
25249    transmute(vld4_dup_s64(transmute(a)))
25250}
25251#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25252#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"]
25253#[doc = "## Safety"]
25254#[doc = "  * Neon instrinsic unsafe"]
25255#[inline]
25256#[cfg(target_endian = "little")]
25257#[target_feature(enable = "neon")]
25258#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25259#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25260#[cfg_attr(
25261    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25262    assert_instr(ld4r)
25263)]
25264#[cfg_attr(
25265    not(target_arch = "arm"),
25266    stable(feature = "neon_intrinsics", since = "1.59.0")
25267)]
25268#[cfg_attr(
25269    target_arch = "arm",
25270    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25271)]
25272pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
25273    transmute(vld4_dup_s8(transmute(a)))
25274}
25275#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"]
25277#[doc = "## Safety"]
25278#[doc = "  * Neon instrinsic unsafe"]
25279#[inline]
25280#[cfg(target_endian = "big")]
25281#[target_feature(enable = "neon")]
25282#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25283#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25284#[cfg_attr(
25285    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25286    assert_instr(ld4r)
25287)]
25288#[cfg_attr(
25289    not(target_arch = "arm"),
25290    stable(feature = "neon_intrinsics", since = "1.59.0")
25291)]
25292#[cfg_attr(
25293    target_arch = "arm",
25294    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25295)]
25296pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
25297    let mut ret_val: uint8x8x4_t = transmute(vld4_dup_s8(transmute(a)));
25298    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
25299    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
25300    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
25301    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
25302    ret_val
25303}
25304#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25305#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"]
25306#[doc = "## Safety"]
25307#[doc = "  * Neon instrinsic unsafe"]
25308#[inline]
25309#[cfg(target_endian = "little")]
25310#[target_feature(enable = "neon")]
25311#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25312#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25313#[cfg_attr(
25314    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25315    assert_instr(ld4r)
25316)]
25317#[cfg_attr(
25318    not(target_arch = "arm"),
25319    stable(feature = "neon_intrinsics", since = "1.59.0")
25320)]
25321#[cfg_attr(
25322    target_arch = "arm",
25323    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25324)]
25325pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
25326    transmute(vld4q_dup_s8(transmute(a)))
25327}
25328#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"]
25330#[doc = "## Safety"]
25331#[doc = "  * Neon instrinsic unsafe"]
25332#[inline]
25333#[cfg(target_endian = "big")]
25334#[target_feature(enable = "neon")]
25335#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25336#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25337#[cfg_attr(
25338    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25339    assert_instr(ld4r)
25340)]
25341#[cfg_attr(
25342    not(target_arch = "arm"),
25343    stable(feature = "neon_intrinsics", since = "1.59.0")
25344)]
25345#[cfg_attr(
25346    target_arch = "arm",
25347    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25348)]
25349pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
25350    let mut ret_val: uint8x16x4_t = transmute(vld4q_dup_s8(transmute(a)));
25351    ret_val.0 = unsafe {
25352        simd_shuffle!(
25353            ret_val.0,
25354            ret_val.0,
25355            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25356        )
25357    };
25358    ret_val.1 = unsafe {
25359        simd_shuffle!(
25360            ret_val.1,
25361            ret_val.1,
25362            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25363        )
25364    };
25365    ret_val.2 = unsafe {
25366        simd_shuffle!(
25367            ret_val.2,
25368            ret_val.2,
25369            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25370        )
25371    };
25372    ret_val.3 = unsafe {
25373        simd_shuffle!(
25374            ret_val.3,
25375            ret_val.3,
25376            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25377        )
25378    };
25379    ret_val
25380}
25381#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25382#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"]
25383#[doc = "## Safety"]
25384#[doc = "  * Neon instrinsic unsafe"]
25385#[inline]
25386#[cfg(target_endian = "little")]
25387#[target_feature(enable = "neon")]
25388#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25389#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25390#[cfg_attr(
25391    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25392    assert_instr(ld4r)
25393)]
25394#[cfg_attr(
25395    not(target_arch = "arm"),
25396    stable(feature = "neon_intrinsics", since = "1.59.0")
25397)]
25398#[cfg_attr(
25399    target_arch = "arm",
25400    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25401)]
25402pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
25403    transmute(vld4_dup_s16(transmute(a)))
25404}
25405#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25406#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"]
25407#[doc = "## Safety"]
25408#[doc = "  * Neon instrinsic unsafe"]
25409#[inline]
25410#[cfg(target_endian = "big")]
25411#[target_feature(enable = "neon")]
25412#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25413#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25414#[cfg_attr(
25415    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25416    assert_instr(ld4r)
25417)]
25418#[cfg_attr(
25419    not(target_arch = "arm"),
25420    stable(feature = "neon_intrinsics", since = "1.59.0")
25421)]
25422#[cfg_attr(
25423    target_arch = "arm",
25424    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25425)]
25426pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
25427    let mut ret_val: uint16x4x4_t = transmute(vld4_dup_s16(transmute(a)));
25428    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
25429    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
25430    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
25431    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
25432    ret_val
25433}
25434#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25435#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"]
25436#[doc = "## Safety"]
25437#[doc = "  * Neon instrinsic unsafe"]
25438#[inline]
25439#[cfg(target_endian = "little")]
25440#[target_feature(enable = "neon")]
25441#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25442#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25443#[cfg_attr(
25444    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25445    assert_instr(ld4r)
25446)]
25447#[cfg_attr(
25448    not(target_arch = "arm"),
25449    stable(feature = "neon_intrinsics", since = "1.59.0")
25450)]
25451#[cfg_attr(
25452    target_arch = "arm",
25453    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25454)]
25455pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
25456    transmute(vld4q_dup_s16(transmute(a)))
25457}
25458#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25459#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"]
25460#[doc = "## Safety"]
25461#[doc = "  * Neon instrinsic unsafe"]
25462#[inline]
25463#[cfg(target_endian = "big")]
25464#[target_feature(enable = "neon")]
25465#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25466#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25467#[cfg_attr(
25468    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25469    assert_instr(ld4r)
25470)]
25471#[cfg_attr(
25472    not(target_arch = "arm"),
25473    stable(feature = "neon_intrinsics", since = "1.59.0")
25474)]
25475#[cfg_attr(
25476    target_arch = "arm",
25477    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25478)]
25479pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
25480    let mut ret_val: uint16x8x4_t = transmute(vld4q_dup_s16(transmute(a)));
25481    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
25482    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
25483    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
25484    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
25485    ret_val
25486}
25487#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25488#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"]
25489#[doc = "## Safety"]
25490#[doc = "  * Neon instrinsic unsafe"]
25491#[inline]
25492#[cfg(target_endian = "little")]
25493#[target_feature(enable = "neon")]
25494#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25495#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25496#[cfg_attr(
25497    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25498    assert_instr(ld4r)
25499)]
25500#[cfg_attr(
25501    not(target_arch = "arm"),
25502    stable(feature = "neon_intrinsics", since = "1.59.0")
25503)]
25504#[cfg_attr(
25505    target_arch = "arm",
25506    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25507)]
25508pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
25509    transmute(vld4_dup_s32(transmute(a)))
25510}
25511#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25512#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"]
25513#[doc = "## Safety"]
25514#[doc = "  * Neon instrinsic unsafe"]
25515#[inline]
25516#[cfg(target_endian = "big")]
25517#[target_feature(enable = "neon")]
25518#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25519#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25520#[cfg_attr(
25521    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25522    assert_instr(ld4r)
25523)]
25524#[cfg_attr(
25525    not(target_arch = "arm"),
25526    stable(feature = "neon_intrinsics", since = "1.59.0")
25527)]
25528#[cfg_attr(
25529    target_arch = "arm",
25530    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25531)]
25532pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
25533    let mut ret_val: uint32x2x4_t = transmute(vld4_dup_s32(transmute(a)));
25534    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
25535    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
25536    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
25537    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
25538    ret_val
25539}
25540#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25541#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"]
25542#[doc = "## Safety"]
25543#[doc = "  * Neon instrinsic unsafe"]
25544#[inline]
25545#[cfg(target_endian = "little")]
25546#[target_feature(enable = "neon")]
25547#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25548#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25549#[cfg_attr(
25550    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25551    assert_instr(ld4r)
25552)]
25553#[cfg_attr(
25554    not(target_arch = "arm"),
25555    stable(feature = "neon_intrinsics", since = "1.59.0")
25556)]
25557#[cfg_attr(
25558    target_arch = "arm",
25559    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25560)]
25561pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
25562    transmute(vld4q_dup_s32(transmute(a)))
25563}
25564#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25565#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"]
25566#[doc = "## Safety"]
25567#[doc = "  * Neon instrinsic unsafe"]
25568#[inline]
25569#[cfg(target_endian = "big")]
25570#[target_feature(enable = "neon")]
25571#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25572#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25573#[cfg_attr(
25574    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25575    assert_instr(ld4r)
25576)]
25577#[cfg_attr(
25578    not(target_arch = "arm"),
25579    stable(feature = "neon_intrinsics", since = "1.59.0")
25580)]
25581#[cfg_attr(
25582    target_arch = "arm",
25583    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25584)]
25585pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
25586    let mut ret_val: uint32x4x4_t = transmute(vld4q_dup_s32(transmute(a)));
25587    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
25588    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
25589    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
25590    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
25591    ret_val
25592}
25593#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25594#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"]
25595#[doc = "## Safety"]
25596#[doc = "  * Neon instrinsic unsafe"]
25597#[inline]
25598#[cfg(target_endian = "little")]
25599#[target_feature(enable = "neon")]
25600#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25601#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25602#[cfg_attr(
25603    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25604    assert_instr(ld4r)
25605)]
25606#[cfg_attr(
25607    not(target_arch = "arm"),
25608    stable(feature = "neon_intrinsics", since = "1.59.0")
25609)]
25610#[cfg_attr(
25611    target_arch = "arm",
25612    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25613)]
25614pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
25615    transmute(vld4_dup_s8(transmute(a)))
25616}
25617#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25618#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"]
25619#[doc = "## Safety"]
25620#[doc = "  * Neon instrinsic unsafe"]
25621#[inline]
25622#[cfg(target_endian = "big")]
25623#[target_feature(enable = "neon")]
25624#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25625#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25626#[cfg_attr(
25627    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25628    assert_instr(ld4r)
25629)]
25630#[cfg_attr(
25631    not(target_arch = "arm"),
25632    stable(feature = "neon_intrinsics", since = "1.59.0")
25633)]
25634#[cfg_attr(
25635    target_arch = "arm",
25636    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25637)]
25638pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
25639    let mut ret_val: poly8x8x4_t = transmute(vld4_dup_s8(transmute(a)));
25640    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
25641    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
25642    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
25643    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
25644    ret_val
25645}
25646#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25647#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"]
25648#[doc = "## Safety"]
25649#[doc = "  * Neon instrinsic unsafe"]
25650#[inline]
25651#[cfg(target_endian = "little")]
25652#[target_feature(enable = "neon")]
25653#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25654#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25655#[cfg_attr(
25656    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25657    assert_instr(ld4r)
25658)]
25659#[cfg_attr(
25660    not(target_arch = "arm"),
25661    stable(feature = "neon_intrinsics", since = "1.59.0")
25662)]
25663#[cfg_attr(
25664    target_arch = "arm",
25665    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25666)]
25667pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
25668    transmute(vld4q_dup_s8(transmute(a)))
25669}
25670#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25671#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"]
25672#[doc = "## Safety"]
25673#[doc = "  * Neon instrinsic unsafe"]
25674#[inline]
25675#[cfg(target_endian = "big")]
25676#[target_feature(enable = "neon")]
25677#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25678#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25679#[cfg_attr(
25680    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25681    assert_instr(ld4r)
25682)]
25683#[cfg_attr(
25684    not(target_arch = "arm"),
25685    stable(feature = "neon_intrinsics", since = "1.59.0")
25686)]
25687#[cfg_attr(
25688    target_arch = "arm",
25689    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25690)]
25691pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
25692    let mut ret_val: poly8x16x4_t = transmute(vld4q_dup_s8(transmute(a)));
25693    ret_val.0 = unsafe {
25694        simd_shuffle!(
25695            ret_val.0,
25696            ret_val.0,
25697            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25698        )
25699    };
25700    ret_val.1 = unsafe {
25701        simd_shuffle!(
25702            ret_val.1,
25703            ret_val.1,
25704            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25705        )
25706    };
25707    ret_val.2 = unsafe {
25708        simd_shuffle!(
25709            ret_val.2,
25710            ret_val.2,
25711            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25712        )
25713    };
25714    ret_val.3 = unsafe {
25715        simd_shuffle!(
25716            ret_val.3,
25717            ret_val.3,
25718            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25719        )
25720    };
25721    ret_val
25722}
25723#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25724#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"]
25725#[doc = "## Safety"]
25726#[doc = "  * Neon instrinsic unsafe"]
25727#[inline]
25728#[cfg(target_endian = "little")]
25729#[target_feature(enable = "neon")]
25730#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25731#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25732#[cfg_attr(
25733    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25734    assert_instr(ld4r)
25735)]
25736#[cfg_attr(
25737    not(target_arch = "arm"),
25738    stable(feature = "neon_intrinsics", since = "1.59.0")
25739)]
25740#[cfg_attr(
25741    target_arch = "arm",
25742    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25743)]
25744pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
25745    transmute(vld4_dup_s16(transmute(a)))
25746}
25747#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25748#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"]
25749#[doc = "## Safety"]
25750#[doc = "  * Neon instrinsic unsafe"]
25751#[inline]
25752#[cfg(target_endian = "big")]
25753#[target_feature(enable = "neon")]
25754#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25755#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25756#[cfg_attr(
25757    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25758    assert_instr(ld4r)
25759)]
25760#[cfg_attr(
25761    not(target_arch = "arm"),
25762    stable(feature = "neon_intrinsics", since = "1.59.0")
25763)]
25764#[cfg_attr(
25765    target_arch = "arm",
25766    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25767)]
25768pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
25769    let mut ret_val: poly16x4x4_t = transmute(vld4_dup_s16(transmute(a)));
25770    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
25771    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
25772    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
25773    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
25774    ret_val
25775}
25776#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25777#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"]
25778#[doc = "## Safety"]
25779#[doc = "  * Neon instrinsic unsafe"]
25780#[inline]
25781#[cfg(target_endian = "little")]
25782#[target_feature(enable = "neon")]
25783#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25784#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25785#[cfg_attr(
25786    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25787    assert_instr(ld4r)
25788)]
25789#[cfg_attr(
25790    not(target_arch = "arm"),
25791    stable(feature = "neon_intrinsics", since = "1.59.0")
25792)]
25793#[cfg_attr(
25794    target_arch = "arm",
25795    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25796)]
25797pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
25798    transmute(vld4q_dup_s16(transmute(a)))
25799}
25800#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25801#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"]
25802#[doc = "## Safety"]
25803#[doc = "  * Neon instrinsic unsafe"]
25804#[inline]
25805#[cfg(target_endian = "big")]
25806#[target_feature(enable = "neon")]
25807#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25808#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25809#[cfg_attr(
25810    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25811    assert_instr(ld4r)
25812)]
25813#[cfg_attr(
25814    not(target_arch = "arm"),
25815    stable(feature = "neon_intrinsics", since = "1.59.0")
25816)]
25817#[cfg_attr(
25818    target_arch = "arm",
25819    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25820)]
25821pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
25822    let mut ret_val: poly16x8x4_t = transmute(vld4q_dup_s16(transmute(a)));
25823    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
25824    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
25825    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
25826    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
25827    ret_val
25828}
25829#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
25830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"]
25831#[doc = "## Safety"]
25832#[doc = "  * Neon instrinsic unsafe"]
25833#[inline]
25834#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25835#[cfg(target_arch = "arm")]
25836#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25837#[target_feature(enable = "neon,fp16")]
25838#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
25839pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
25840    unsafe extern "unadjusted" {
25841        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4f16.p0")]
25842        fn _vld4_f16(ptr: *const f16, size: i32) -> float16x4x4_t;
25843    }
25844    _vld4_f16(a as _, 2)
25845}
25846#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
25847#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"]
25848#[doc = "## Safety"]
25849#[doc = "  * Neon instrinsic unsafe"]
25850#[inline]
25851#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25852#[cfg(target_arch = "arm")]
25853#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25854#[target_feature(enable = "neon,fp16")]
25855#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
25856pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
25857    unsafe extern "unadjusted" {
25858        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8f16.p0")]
25859        fn _vld4q_f16(ptr: *const f16, size: i32) -> float16x8x4_t;
25860    }
25861    _vld4q_f16(a as _, 2)
25862}
25863#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
25864#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"]
25865#[doc = "## Safety"]
25866#[doc = "  * Neon instrinsic unsafe"]
25867#[inline]
25868#[cfg(not(target_arch = "arm"))]
25869#[cfg_attr(
25870    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25871    assert_instr(ld4)
25872)]
25873#[target_feature(enable = "neon,fp16")]
25874#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
25875pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
25876    unsafe extern "unadjusted" {
25877        #[cfg_attr(
25878            any(target_arch = "aarch64", target_arch = "arm64ec"),
25879            link_name = "llvm.aarch64.neon.ld4.v4f16.p0"
25880        )]
25881        fn _vld4_f16(ptr: *const f16) -> float16x4x4_t;
25882    }
25883    _vld4_f16(a as _)
25884}
25885#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
25886#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"]
25887#[doc = "## Safety"]
25888#[doc = "  * Neon instrinsic unsafe"]
25889#[inline]
25890#[cfg(not(target_arch = "arm"))]
25891#[cfg_attr(
25892    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25893    assert_instr(ld4)
25894)]
25895#[target_feature(enable = "neon,fp16")]
25896#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
25897pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
25898    unsafe extern "unadjusted" {
25899        #[cfg_attr(
25900            any(target_arch = "aarch64", target_arch = "arm64ec"),
25901            link_name = "llvm.aarch64.neon.ld4.v8f16.p0"
25902        )]
25903        fn _vld4q_f16(ptr: *const f16) -> float16x8x4_t;
25904    }
25905    _vld4q_f16(a as _)
25906}
25907#[doc = "Load multiple 4-element structures to four registers"]
25908#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
25909#[doc = "## Safety"]
25910#[doc = "  * Neon instrinsic unsafe"]
25911#[inline]
25912#[target_feature(enable = "neon")]
25913#[cfg(not(target_arch = "arm"))]
25914#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25915#[cfg_attr(test, assert_instr(ld4))]
25916pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
25917    unsafe extern "unadjusted" {
25918        #[cfg_attr(
25919            any(target_arch = "aarch64", target_arch = "arm64ec"),
25920            link_name = "llvm.aarch64.neon.ld4.v2f32.p0"
25921        )]
25922        fn _vld4_f32(ptr: *const float32x2_t) -> float32x2x4_t;
25923    }
25924    _vld4_f32(a as _)
25925}
25926#[doc = "Load multiple 4-element structures to four registers"]
25927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"]
25928#[doc = "## Safety"]
25929#[doc = "  * Neon instrinsic unsafe"]
25930#[inline]
25931#[target_feature(enable = "neon")]
25932#[cfg(not(target_arch = "arm"))]
25933#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25934#[cfg_attr(test, assert_instr(ld4))]
25935pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
25936    unsafe extern "unadjusted" {
25937        #[cfg_attr(
25938            any(target_arch = "aarch64", target_arch = "arm64ec"),
25939            link_name = "llvm.aarch64.neon.ld4.v4f32.p0"
25940        )]
25941        fn _vld4q_f32(ptr: *const float32x4_t) -> float32x4x4_t;
25942    }
25943    _vld4q_f32(a as _)
25944}
25945#[doc = "Load multiple 4-element structures to four registers"]
25946#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"]
25947#[doc = "## Safety"]
25948#[doc = "  * Neon instrinsic unsafe"]
25949#[inline]
25950#[target_feature(enable = "neon")]
25951#[cfg(not(target_arch = "arm"))]
25952#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25953#[cfg_attr(test, assert_instr(ld4))]
25954pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
25955    unsafe extern "unadjusted" {
25956        #[cfg_attr(
25957            any(target_arch = "aarch64", target_arch = "arm64ec"),
25958            link_name = "llvm.aarch64.neon.ld4.v8i8.p0"
25959        )]
25960        fn _vld4_s8(ptr: *const int8x8_t) -> int8x8x4_t;
25961    }
25962    _vld4_s8(a as _)
25963}
25964#[doc = "Load multiple 4-element structures to four registers"]
25965#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"]
25966#[doc = "## Safety"]
25967#[doc = "  * Neon instrinsic unsafe"]
25968#[inline]
25969#[target_feature(enable = "neon")]
25970#[cfg(not(target_arch = "arm"))]
25971#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25972#[cfg_attr(test, assert_instr(ld4))]
25973pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
25974    unsafe extern "unadjusted" {
25975        #[cfg_attr(
25976            any(target_arch = "aarch64", target_arch = "arm64ec"),
25977            link_name = "llvm.aarch64.neon.ld4.v16i8.p0"
25978        )]
25979        fn _vld4q_s8(ptr: *const int8x16_t) -> int8x16x4_t;
25980    }
25981    _vld4q_s8(a as _)
25982}
25983#[doc = "Load multiple 4-element structures to four registers"]
25984#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"]
25985#[doc = "## Safety"]
25986#[doc = "  * Neon instrinsic unsafe"]
25987#[inline]
25988#[target_feature(enable = "neon")]
25989#[cfg(not(target_arch = "arm"))]
25990#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25991#[cfg_attr(test, assert_instr(ld4))]
25992pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
25993    unsafe extern "unadjusted" {
25994        #[cfg_attr(
25995            any(target_arch = "aarch64", target_arch = "arm64ec"),
25996            link_name = "llvm.aarch64.neon.ld4.v4i16.p0"
25997        )]
25998        fn _vld4_s16(ptr: *const int16x4_t) -> int16x4x4_t;
25999    }
26000    _vld4_s16(a as _)
26001}
26002#[doc = "Load multiple 4-element structures to four registers"]
26003#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"]
26004#[doc = "## Safety"]
26005#[doc = "  * Neon instrinsic unsafe"]
26006#[inline]
26007#[target_feature(enable = "neon")]
26008#[cfg(not(target_arch = "arm"))]
26009#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26010#[cfg_attr(test, assert_instr(ld4))]
26011pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
26012    unsafe extern "unadjusted" {
26013        #[cfg_attr(
26014            any(target_arch = "aarch64", target_arch = "arm64ec"),
26015            link_name = "llvm.aarch64.neon.ld4.v8i16.p0"
26016        )]
26017        fn _vld4q_s16(ptr: *const int16x8_t) -> int16x8x4_t;
26018    }
26019    _vld4q_s16(a as _)
26020}
26021#[doc = "Load multiple 4-element structures to four registers"]
26022#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"]
26023#[doc = "## Safety"]
26024#[doc = "  * Neon instrinsic unsafe"]
26025#[inline]
26026#[target_feature(enable = "neon")]
26027#[cfg(not(target_arch = "arm"))]
26028#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26029#[cfg_attr(test, assert_instr(ld4))]
26030pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
26031    unsafe extern "unadjusted" {
26032        #[cfg_attr(
26033            any(target_arch = "aarch64", target_arch = "arm64ec"),
26034            link_name = "llvm.aarch64.neon.ld4.v2i32.p0"
26035        )]
26036        fn _vld4_s32(ptr: *const int32x2_t) -> int32x2x4_t;
26037    }
26038    _vld4_s32(a as _)
26039}
26040#[doc = "Load multiple 4-element structures to four registers"]
26041#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"]
26042#[doc = "## Safety"]
26043#[doc = "  * Neon instrinsic unsafe"]
26044#[inline]
26045#[target_feature(enable = "neon")]
26046#[cfg(not(target_arch = "arm"))]
26047#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26048#[cfg_attr(test, assert_instr(ld4))]
26049pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t {
26050    unsafe extern "unadjusted" {
26051        #[cfg_attr(
26052            any(target_arch = "aarch64", target_arch = "arm64ec"),
26053            link_name = "llvm.aarch64.neon.ld4.v4i32.p0"
26054        )]
26055        fn _vld4q_s32(ptr: *const int32x4_t) -> int32x4x4_t;
26056    }
26057    _vld4q_s32(a as _)
26058}
26059#[doc = "Load multiple 4-element structures to four registers"]
26060#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
26061#[doc = "## Safety"]
26062#[doc = "  * Neon instrinsic unsafe"]
26063#[inline]
26064#[target_feature(enable = "neon,v7")]
26065#[cfg(target_arch = "arm")]
26066#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26067#[cfg_attr(test, assert_instr(vld4))]
26068pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
26069    unsafe extern "unadjusted" {
26070        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v2f32.p0")]
26071        fn _vld4_f32(ptr: *const i8, size: i32) -> float32x2x4_t;
26072    }
26073    _vld4_f32(a as *const i8, 4)
26074}
26075#[doc = "Load multiple 4-element structures to four registers"]
26076#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"]
26077#[doc = "## Safety"]
26078#[doc = "  * Neon instrinsic unsafe"]
26079#[inline]
26080#[target_feature(enable = "neon,v7")]
26081#[cfg(target_arch = "arm")]
26082#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26083#[cfg_attr(test, assert_instr(vld4))]
26084pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
26085    unsafe extern "unadjusted" {
26086        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4f32.p0")]
26087        fn _vld4q_f32(ptr: *const i8, size: i32) -> float32x4x4_t;
26088    }
26089    _vld4q_f32(a as *const i8, 4)
26090}
26091#[doc = "Load multiple 4-element structures to four registers"]
26092#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"]
26093#[doc = "## Safety"]
26094#[doc = "  * Neon instrinsic unsafe"]
26095#[inline]
26096#[target_feature(enable = "neon,v7")]
26097#[cfg(target_arch = "arm")]
26098#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26099#[cfg_attr(test, assert_instr(vld4))]
26100pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
26101    unsafe extern "unadjusted" {
26102        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8i8.p0")]
26103        fn _vld4_s8(ptr: *const i8, size: i32) -> int8x8x4_t;
26104    }
26105    _vld4_s8(a as *const i8, 1)
26106}
26107#[doc = "Load multiple 4-element structures to four registers"]
26108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"]
26109#[doc = "## Safety"]
26110#[doc = "  * Neon instrinsic unsafe"]
26111#[inline]
26112#[target_feature(enable = "neon,v7")]
26113#[cfg(target_arch = "arm")]
26114#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26115#[cfg_attr(test, assert_instr(vld4))]
26116pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
26117    unsafe extern "unadjusted" {
26118        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v16i8.p0")]
26119        fn _vld4q_s8(ptr: *const i8, size: i32) -> int8x16x4_t;
26120    }
26121    _vld4q_s8(a as *const i8, 1)
26122}
26123#[doc = "Load multiple 4-element structures to four registers"]
26124#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"]
26125#[doc = "## Safety"]
26126#[doc = "  * Neon instrinsic unsafe"]
26127#[inline]
26128#[target_feature(enable = "neon,v7")]
26129#[cfg(target_arch = "arm")]
26130#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26131#[cfg_attr(test, assert_instr(vld4))]
26132pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
26133    unsafe extern "unadjusted" {
26134        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4i16.p0")]
26135        fn _vld4_s16(ptr: *const i8, size: i32) -> int16x4x4_t;
26136    }
26137    _vld4_s16(a as *const i8, 2)
26138}
26139#[doc = "Load multiple 4-element structures to four registers"]
26140#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"]
26141#[doc = "## Safety"]
26142#[doc = "  * Neon instrinsic unsafe"]
26143#[inline]
26144#[target_feature(enable = "neon,v7")]
26145#[cfg(target_arch = "arm")]
26146#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26147#[cfg_attr(test, assert_instr(vld4))]
26148pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
26149    unsafe extern "unadjusted" {
26150        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8i16.p0")]
26151        fn _vld4q_s16(ptr: *const i8, size: i32) -> int16x8x4_t;
26152    }
26153    _vld4q_s16(a as *const i8, 2)
26154}
26155#[doc = "Load multiple 4-element structures to four registers"]
26156#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"]
26157#[doc = "## Safety"]
26158#[doc = "  * Neon instrinsic unsafe"]
26159#[inline]
26160#[target_feature(enable = "neon,v7")]
26161#[cfg(target_arch = "arm")]
26162#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26163#[cfg_attr(test, assert_instr(vld4))]
26164pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
26165    unsafe extern "unadjusted" {
26166        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v2i32.p0")]
26167        fn _vld4_s32(ptr: *const i8, size: i32) -> int32x2x4_t;
26168    }
26169    _vld4_s32(a as *const i8, 4)
26170}
26171#[doc = "Load multiple 4-element structures to four registers"]
26172#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"]
26173#[doc = "## Safety"]
26174#[doc = "  * Neon instrinsic unsafe"]
26175#[inline]
26176#[target_feature(enable = "neon,v7")]
26177#[cfg(target_arch = "arm")]
26178#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26179#[cfg_attr(test, assert_instr(vld4))]
26180pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t {
26181    unsafe extern "unadjusted" {
26182        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4i32.p0")]
26183        fn _vld4q_s32(ptr: *const i8, size: i32) -> int32x4x4_t;
26184    }
26185    _vld4q_s32(a as *const i8, 4)
26186}
26187#[doc = "Load multiple 4-element structures to two registers"]
26188#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"]
26189#[doc = "## Safety"]
26190#[doc = "  * Neon instrinsic unsafe"]
26191#[inline]
26192#[target_feature(enable = "neon,v7")]
26193#[cfg(target_arch = "arm")]
26194#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26195#[rustc_legacy_const_generics(2)]
26196#[target_feature(enable = "neon,fp16")]
26197#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
26198pub unsafe fn vld4_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x4_t) -> float16x4x4_t {
26199    static_assert_uimm_bits!(LANE, 2);
26200    unsafe extern "unadjusted" {
26201        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4f16.p0")]
26202        fn _vld4_lane_f16(
26203            ptr: *const f16,
26204            a: float16x4_t,
26205            b: float16x4_t,
26206            c: float16x4_t,
26207            d: float16x4_t,
26208            n: i32,
26209            size: i32,
26210        ) -> float16x4x4_t;
26211    }
26212    _vld4_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
26213}
26214#[doc = "Load multiple 4-element structures to two registers"]
26215#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"]
26216#[doc = "## Safety"]
26217#[doc = "  * Neon instrinsic unsafe"]
26218#[inline]
26219#[target_feature(enable = "neon,v7")]
26220#[cfg(target_arch = "arm")]
26221#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26222#[rustc_legacy_const_generics(2)]
26223#[target_feature(enable = "neon,fp16")]
26224#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
26225pub unsafe fn vld4q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x4_t) -> float16x8x4_t {
26226    static_assert_uimm_bits!(LANE, 3);
26227    unsafe extern "unadjusted" {
26228        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8f16.p0")]
26229        fn _vld4q_lane_f16(
26230            ptr: *const f16,
26231            a: float16x8_t,
26232            b: float16x8_t,
26233            c: float16x8_t,
26234            d: float16x8_t,
26235            n: i32,
26236            size: i32,
26237        ) -> float16x8x4_t;
26238    }
26239    _vld4q_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
26240}
26241#[doc = "Load multiple 4-element structures to two registers"]
26242#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"]
26243#[doc = "## Safety"]
26244#[doc = "  * Neon instrinsic unsafe"]
26245#[inline]
26246#[cfg(not(target_arch = "arm"))]
26247#[cfg_attr(
26248    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26249    assert_instr(ld4, LANE = 0)
26250)]
26251#[rustc_legacy_const_generics(2)]
26252#[target_feature(enable = "neon,fp16")]
26253#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
26254pub unsafe fn vld4_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x4_t) -> float16x4x4_t {
26255    static_assert_uimm_bits!(LANE, 2);
26256    unsafe extern "unadjusted" {
26257        #[cfg_attr(
26258            any(target_arch = "aarch64", target_arch = "arm64ec"),
26259            link_name = "llvm.aarch64.neon.ld4lane.v4f16.p0"
26260        )]
26261        fn _vld4_lane_f16(
26262            a: float16x4_t,
26263            b: float16x4_t,
26264            c: float16x4_t,
26265            d: float16x4_t,
26266            n: i64,
26267            ptr: *const f16,
26268        ) -> float16x4x4_t;
26269    }
26270    _vld4_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26271}
26272#[doc = "Load multiple 4-element structures to two registers"]
26273#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"]
26274#[doc = "## Safety"]
26275#[doc = "  * Neon instrinsic unsafe"]
26276#[inline]
26277#[cfg(not(target_arch = "arm"))]
26278#[cfg_attr(
26279    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26280    assert_instr(ld4, LANE = 0)
26281)]
26282#[rustc_legacy_const_generics(2)]
26283#[target_feature(enable = "neon,fp16")]
26284#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
26285pub unsafe fn vld4q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x4_t) -> float16x8x4_t {
26286    static_assert_uimm_bits!(LANE, 3);
26287    unsafe extern "unadjusted" {
26288        #[cfg_attr(
26289            any(target_arch = "aarch64", target_arch = "arm64ec"),
26290            link_name = "llvm.aarch64.neon.ld4lane.v8f16.p0"
26291        )]
26292        fn _vld4q_lane_f16(
26293            a: float16x8_t,
26294            b: float16x8_t,
26295            c: float16x8_t,
26296            d: float16x8_t,
26297            n: i64,
26298            ptr: *const f16,
26299        ) -> float16x8x4_t;
26300    }
26301    _vld4q_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26302}
26303#[doc = "Load multiple 4-element structures to four registers"]
26304#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"]
26305#[doc = "## Safety"]
26306#[doc = "  * Neon instrinsic unsafe"]
26307#[inline]
26308#[target_feature(enable = "neon")]
26309#[cfg(not(target_arch = "arm"))]
26310#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26311#[rustc_legacy_const_generics(2)]
26312#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26313pub unsafe fn vld4_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x4_t) -> float32x2x4_t {
26314    static_assert_uimm_bits!(LANE, 1);
26315    unsafe extern "unadjusted" {
26316        #[cfg_attr(
26317            any(target_arch = "aarch64", target_arch = "arm64ec"),
26318            link_name = "llvm.aarch64.neon.ld4lane.v2f32.p0"
26319        )]
26320        fn _vld4_lane_f32(
26321            a: float32x2_t,
26322            b: float32x2_t,
26323            c: float32x2_t,
26324            d: float32x2_t,
26325            n: i64,
26326            ptr: *const i8,
26327        ) -> float32x2x4_t;
26328    }
26329    _vld4_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26330}
26331#[doc = "Load multiple 4-element structures to four registers"]
26332#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"]
26333#[doc = "## Safety"]
26334#[doc = "  * Neon instrinsic unsafe"]
26335#[inline]
26336#[target_feature(enable = "neon")]
26337#[cfg(not(target_arch = "arm"))]
26338#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26339#[rustc_legacy_const_generics(2)]
26340#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26341pub unsafe fn vld4q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x4_t) -> float32x4x4_t {
26342    static_assert_uimm_bits!(LANE, 2);
26343    unsafe extern "unadjusted" {
26344        #[cfg_attr(
26345            any(target_arch = "aarch64", target_arch = "arm64ec"),
26346            link_name = "llvm.aarch64.neon.ld4lane.v4f32.p0"
26347        )]
26348        fn _vld4q_lane_f32(
26349            a: float32x4_t,
26350            b: float32x4_t,
26351            c: float32x4_t,
26352            d: float32x4_t,
26353            n: i64,
26354            ptr: *const i8,
26355        ) -> float32x4x4_t;
26356    }
26357    _vld4q_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26358}
26359#[doc = "Load multiple 4-element structures to four registers"]
26360#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"]
26361#[doc = "## Safety"]
26362#[doc = "  * Neon instrinsic unsafe"]
26363#[inline]
26364#[target_feature(enable = "neon")]
26365#[cfg(not(target_arch = "arm"))]
26366#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26367#[rustc_legacy_const_generics(2)]
26368#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26369pub unsafe fn vld4_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x4_t) -> int8x8x4_t {
26370    static_assert_uimm_bits!(LANE, 3);
26371    unsafe extern "unadjusted" {
26372        #[cfg_attr(
26373            any(target_arch = "aarch64", target_arch = "arm64ec"),
26374            link_name = "llvm.aarch64.neon.ld4lane.v8i8.p0"
26375        )]
26376        fn _vld4_lane_s8(
26377            a: int8x8_t,
26378            b: int8x8_t,
26379            c: int8x8_t,
26380            d: int8x8_t,
26381            n: i64,
26382            ptr: *const i8,
26383        ) -> int8x8x4_t;
26384    }
26385    _vld4_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26386}
26387#[doc = "Load multiple 4-element structures to four registers"]
26388#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"]
26389#[doc = "## Safety"]
26390#[doc = "  * Neon instrinsic unsafe"]
26391#[inline]
26392#[target_feature(enable = "neon")]
26393#[cfg(not(target_arch = "arm"))]
26394#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26395#[rustc_legacy_const_generics(2)]
26396#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26397pub unsafe fn vld4_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x4_t) -> int16x4x4_t {
26398    static_assert_uimm_bits!(LANE, 2);
26399    unsafe extern "unadjusted" {
26400        #[cfg_attr(
26401            any(target_arch = "aarch64", target_arch = "arm64ec"),
26402            link_name = "llvm.aarch64.neon.ld4lane.v4i16.p0"
26403        )]
26404        fn _vld4_lane_s16(
26405            a: int16x4_t,
26406            b: int16x4_t,
26407            c: int16x4_t,
26408            d: int16x4_t,
26409            n: i64,
26410            ptr: *const i8,
26411        ) -> int16x4x4_t;
26412    }
26413    _vld4_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26414}
26415#[doc = "Load multiple 4-element structures to four registers"]
26416#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"]
26417#[doc = "## Safety"]
26418#[doc = "  * Neon instrinsic unsafe"]
26419#[inline]
26420#[target_feature(enable = "neon")]
26421#[cfg(not(target_arch = "arm"))]
26422#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26423#[rustc_legacy_const_generics(2)]
26424#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26425pub unsafe fn vld4q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x4_t) -> int16x8x4_t {
26426    static_assert_uimm_bits!(LANE, 3);
26427    unsafe extern "unadjusted" {
26428        #[cfg_attr(
26429            any(target_arch = "aarch64", target_arch = "arm64ec"),
26430            link_name = "llvm.aarch64.neon.ld4lane.v8i16.p0"
26431        )]
26432        fn _vld4q_lane_s16(
26433            a: int16x8_t,
26434            b: int16x8_t,
26435            c: int16x8_t,
26436            d: int16x8_t,
26437            n: i64,
26438            ptr: *const i8,
26439        ) -> int16x8x4_t;
26440    }
26441    _vld4q_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26442}
26443#[doc = "Load multiple 4-element structures to four registers"]
26444#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"]
26445#[doc = "## Safety"]
26446#[doc = "  * Neon instrinsic unsafe"]
26447#[inline]
26448#[target_feature(enable = "neon")]
26449#[cfg(not(target_arch = "arm"))]
26450#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26451#[rustc_legacy_const_generics(2)]
26452#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26453pub unsafe fn vld4_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x4_t) -> int32x2x4_t {
26454    static_assert_uimm_bits!(LANE, 1);
26455    unsafe extern "unadjusted" {
26456        #[cfg_attr(
26457            any(target_arch = "aarch64", target_arch = "arm64ec"),
26458            link_name = "llvm.aarch64.neon.ld4lane.v2i32.p0"
26459        )]
26460        fn _vld4_lane_s32(
26461            a: int32x2_t,
26462            b: int32x2_t,
26463            c: int32x2_t,
26464            d: int32x2_t,
26465            n: i64,
26466            ptr: *const i8,
26467        ) -> int32x2x4_t;
26468    }
26469    _vld4_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26470}
26471#[doc = "Load multiple 4-element structures to four registers"]
26472#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"]
26473#[doc = "## Safety"]
26474#[doc = "  * Neon instrinsic unsafe"]
26475#[inline]
26476#[target_feature(enable = "neon")]
26477#[cfg(not(target_arch = "arm"))]
26478#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26479#[rustc_legacy_const_generics(2)]
26480#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26481pub unsafe fn vld4q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x4_t) -> int32x4x4_t {
26482    static_assert_uimm_bits!(LANE, 2);
26483    unsafe extern "unadjusted" {
26484        #[cfg_attr(
26485            any(target_arch = "aarch64", target_arch = "arm64ec"),
26486            link_name = "llvm.aarch64.neon.ld4lane.v4i32.p0"
26487        )]
26488        fn _vld4q_lane_s32(
26489            a: int32x4_t,
26490            b: int32x4_t,
26491            c: int32x4_t,
26492            d: int32x4_t,
26493            n: i64,
26494            ptr: *const i8,
26495        ) -> int32x4x4_t;
26496    }
26497    _vld4q_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26498}
26499#[doc = "Load multiple 4-element structures to four registers"]
26500#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"]
26501#[doc = "## Safety"]
26502#[doc = "  * Neon instrinsic unsafe"]
26503#[inline]
26504#[target_feature(enable = "neon,v7")]
26505#[cfg(target_arch = "arm")]
26506#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26507#[rustc_legacy_const_generics(2)]
26508#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26509pub unsafe fn vld4_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x4_t) -> float32x2x4_t {
26510    static_assert_uimm_bits!(LANE, 1);
26511    unsafe extern "unadjusted" {
26512        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v2f32.p0")]
26513        fn _vld4_lane_f32(
26514            ptr: *const i8,
26515            a: float32x2_t,
26516            b: float32x2_t,
26517            c: float32x2_t,
26518            d: float32x2_t,
26519            n: i32,
26520            size: i32,
26521        ) -> float32x2x4_t;
26522    }
26523    _vld4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
26524}
26525#[doc = "Load multiple 4-element structures to four registers"]
26526#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"]
26527#[doc = "## Safety"]
26528#[doc = "  * Neon instrinsic unsafe"]
26529#[inline]
26530#[target_feature(enable = "neon,v7")]
26531#[cfg(target_arch = "arm")]
26532#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26533#[rustc_legacy_const_generics(2)]
26534#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26535pub unsafe fn vld4q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x4_t) -> float32x4x4_t {
26536    static_assert_uimm_bits!(LANE, 2);
26537    unsafe extern "unadjusted" {
26538        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4f32.p0")]
26539        fn _vld4q_lane_f32(
26540            ptr: *const i8,
26541            a: float32x4_t,
26542            b: float32x4_t,
26543            c: float32x4_t,
26544            d: float32x4_t,
26545            n: i32,
26546            size: i32,
26547        ) -> float32x4x4_t;
26548    }
26549    _vld4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
26550}
26551#[doc = "Load multiple 4-element structures to four registers"]
26552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"]
26553#[doc = "## Safety"]
26554#[doc = "  * Neon instrinsic unsafe"]
26555#[inline]
26556#[target_feature(enable = "neon,v7")]
26557#[cfg(target_arch = "arm")]
26558#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26559#[rustc_legacy_const_generics(2)]
26560#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26561pub unsafe fn vld4_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x4_t) -> int8x8x4_t {
26562    static_assert_uimm_bits!(LANE, 3);
26563    unsafe extern "unadjusted" {
26564        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8i8.p0")]
26565        fn _vld4_lane_s8(
26566            ptr: *const i8,
26567            a: int8x8_t,
26568            b: int8x8_t,
26569            c: int8x8_t,
26570            d: int8x8_t,
26571            n: i32,
26572            size: i32,
26573        ) -> int8x8x4_t;
26574    }
26575    _vld4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1)
26576}
26577#[doc = "Load multiple 4-element structures to four registers"]
26578#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"]
26579#[doc = "## Safety"]
26580#[doc = "  * Neon instrinsic unsafe"]
26581#[inline]
26582#[target_feature(enable = "neon,v7")]
26583#[cfg(target_arch = "arm")]
26584#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26585#[rustc_legacy_const_generics(2)]
26586#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26587pub unsafe fn vld4_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x4_t) -> int16x4x4_t {
26588    static_assert_uimm_bits!(LANE, 2);
26589    unsafe extern "unadjusted" {
26590        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4i16.p0")]
26591        fn _vld4_lane_s16(
26592            ptr: *const i8,
26593            a: int16x4_t,
26594            b: int16x4_t,
26595            c: int16x4_t,
26596            d: int16x4_t,
26597            n: i32,
26598            size: i32,
26599        ) -> int16x4x4_t;
26600    }
26601    _vld4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
26602}
26603#[doc = "Load multiple 4-element structures to four registers"]
26604#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"]
26605#[doc = "## Safety"]
26606#[doc = "  * Neon instrinsic unsafe"]
26607#[inline]
26608#[target_feature(enable = "neon,v7")]
26609#[cfg(target_arch = "arm")]
26610#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26611#[rustc_legacy_const_generics(2)]
26612#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26613pub unsafe fn vld4q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x4_t) -> int16x8x4_t {
26614    static_assert_uimm_bits!(LANE, 3);
26615    unsafe extern "unadjusted" {
26616        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8i16.p0")]
26617        fn _vld4q_lane_s16(
26618            ptr: *const i8,
26619            a: int16x8_t,
26620            b: int16x8_t,
26621            c: int16x8_t,
26622            d: int16x8_t,
26623            n: i32,
26624            size: i32,
26625        ) -> int16x8x4_t;
26626    }
26627    _vld4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
26628}
26629#[doc = "Load multiple 4-element structures to four registers"]
26630#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"]
26631#[doc = "## Safety"]
26632#[doc = "  * Neon instrinsic unsafe"]
26633#[inline]
26634#[target_feature(enable = "neon,v7")]
26635#[cfg(target_arch = "arm")]
26636#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26637#[rustc_legacy_const_generics(2)]
26638#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26639pub unsafe fn vld4_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x4_t) -> int32x2x4_t {
26640    static_assert_uimm_bits!(LANE, 1);
26641    unsafe extern "unadjusted" {
26642        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v2i32.p0")]
26643        fn _vld4_lane_s32(
26644            ptr: *const i8,
26645            a: int32x2_t,
26646            b: int32x2_t,
26647            c: int32x2_t,
26648            d: int32x2_t,
26649            n: i32,
26650            size: i32,
26651        ) -> int32x2x4_t;
26652    }
26653    _vld4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
26654}
26655#[doc = "Load multiple 4-element structures to four registers"]
26656#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"]
26657#[doc = "## Safety"]
26658#[doc = "  * Neon instrinsic unsafe"]
26659#[inline]
26660#[target_feature(enable = "neon,v7")]
26661#[cfg(target_arch = "arm")]
26662#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26663#[rustc_legacy_const_generics(2)]
26664#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26665pub unsafe fn vld4q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x4_t) -> int32x4x4_t {
26666    static_assert_uimm_bits!(LANE, 2);
26667    unsafe extern "unadjusted" {
26668        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4i32.p0")]
26669        fn _vld4q_lane_s32(
26670            ptr: *const i8,
26671            a: int32x4_t,
26672            b: int32x4_t,
26673            c: int32x4_t,
26674            d: int32x4_t,
26675            n: i32,
26676            size: i32,
26677        ) -> int32x4x4_t;
26678    }
26679    _vld4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
26680}
26681#[doc = "Load multiple 4-element structures to four registers"]
26682#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u8)"]
26683#[doc = "## Safety"]
26684#[doc = "  * Neon instrinsic unsafe"]
26685#[inline]
26686#[target_feature(enable = "neon")]
26687#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26688#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26689#[cfg_attr(
26690    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26691    assert_instr(ld4, LANE = 0)
26692)]
26693#[rustc_legacy_const_generics(2)]
26694#[cfg_attr(
26695    not(target_arch = "arm"),
26696    stable(feature = "neon_intrinsics", since = "1.59.0")
26697)]
26698#[cfg_attr(
26699    target_arch = "arm",
26700    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26701)]
26702pub unsafe fn vld4_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x4_t) -> uint8x8x4_t {
26703    static_assert_uimm_bits!(LANE, 3);
26704    transmute(vld4_lane_s8::<LANE>(transmute(a), transmute(b)))
26705}
26706#[doc = "Load multiple 4-element structures to four registers"]
26707#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u16)"]
26708#[doc = "## Safety"]
26709#[doc = "  * Neon instrinsic unsafe"]
26710#[inline]
26711#[target_feature(enable = "neon")]
26712#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26713#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26714#[cfg_attr(
26715    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26716    assert_instr(ld4, LANE = 0)
26717)]
26718#[rustc_legacy_const_generics(2)]
26719#[cfg_attr(
26720    not(target_arch = "arm"),
26721    stable(feature = "neon_intrinsics", since = "1.59.0")
26722)]
26723#[cfg_attr(
26724    target_arch = "arm",
26725    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26726)]
26727pub unsafe fn vld4_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x4_t) -> uint16x4x4_t {
26728    static_assert_uimm_bits!(LANE, 2);
26729    transmute(vld4_lane_s16::<LANE>(transmute(a), transmute(b)))
26730}
26731#[doc = "Load multiple 4-element structures to four registers"]
26732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u16)"]
26733#[doc = "## Safety"]
26734#[doc = "  * Neon instrinsic unsafe"]
26735#[inline]
26736#[target_feature(enable = "neon")]
26737#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26738#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26739#[cfg_attr(
26740    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26741    assert_instr(ld4, LANE = 0)
26742)]
26743#[rustc_legacy_const_generics(2)]
26744#[cfg_attr(
26745    not(target_arch = "arm"),
26746    stable(feature = "neon_intrinsics", since = "1.59.0")
26747)]
26748#[cfg_attr(
26749    target_arch = "arm",
26750    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26751)]
26752pub unsafe fn vld4q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x4_t) -> uint16x8x4_t {
26753    static_assert_uimm_bits!(LANE, 3);
26754    transmute(vld4q_lane_s16::<LANE>(transmute(a), transmute(b)))
26755}
26756#[doc = "Load multiple 4-element structures to four registers"]
26757#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u32)"]
26758#[doc = "## Safety"]
26759#[doc = "  * Neon instrinsic unsafe"]
26760#[inline]
26761#[target_feature(enable = "neon")]
26762#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26763#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26764#[cfg_attr(
26765    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26766    assert_instr(ld4, LANE = 0)
26767)]
26768#[rustc_legacy_const_generics(2)]
26769#[cfg_attr(
26770    not(target_arch = "arm"),
26771    stable(feature = "neon_intrinsics", since = "1.59.0")
26772)]
26773#[cfg_attr(
26774    target_arch = "arm",
26775    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26776)]
26777pub unsafe fn vld4_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x4_t) -> uint32x2x4_t {
26778    static_assert_uimm_bits!(LANE, 1);
26779    transmute(vld4_lane_s32::<LANE>(transmute(a), transmute(b)))
26780}
26781#[doc = "Load multiple 4-element structures to four registers"]
26782#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u32)"]
26783#[doc = "## Safety"]
26784#[doc = "  * Neon instrinsic unsafe"]
26785#[inline]
26786#[target_feature(enable = "neon")]
26787#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26788#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26789#[cfg_attr(
26790    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26791    assert_instr(ld4, LANE = 0)
26792)]
26793#[rustc_legacy_const_generics(2)]
26794#[cfg_attr(
26795    not(target_arch = "arm"),
26796    stable(feature = "neon_intrinsics", since = "1.59.0")
26797)]
26798#[cfg_attr(
26799    target_arch = "arm",
26800    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26801)]
26802pub unsafe fn vld4q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x4_t) -> uint32x4x4_t {
26803    static_assert_uimm_bits!(LANE, 2);
26804    transmute(vld4q_lane_s32::<LANE>(transmute(a), transmute(b)))
26805}
26806#[doc = "Load multiple 4-element structures to four registers"]
26807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p8)"]
26808#[doc = "## Safety"]
26809#[doc = "  * Neon instrinsic unsafe"]
26810#[inline]
26811#[target_feature(enable = "neon")]
26812#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26813#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26814#[cfg_attr(
26815    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26816    assert_instr(ld4, LANE = 0)
26817)]
26818#[rustc_legacy_const_generics(2)]
26819#[cfg_attr(
26820    not(target_arch = "arm"),
26821    stable(feature = "neon_intrinsics", since = "1.59.0")
26822)]
26823#[cfg_attr(
26824    target_arch = "arm",
26825    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26826)]
26827pub unsafe fn vld4_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x4_t) -> poly8x8x4_t {
26828    static_assert_uimm_bits!(LANE, 3);
26829    transmute(vld4_lane_s8::<LANE>(transmute(a), transmute(b)))
26830}
26831#[doc = "Load multiple 4-element structures to four registers"]
26832#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p16)"]
26833#[doc = "## Safety"]
26834#[doc = "  * Neon instrinsic unsafe"]
26835#[inline]
26836#[target_feature(enable = "neon")]
26837#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26838#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26839#[cfg_attr(
26840    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26841    assert_instr(ld4, LANE = 0)
26842)]
26843#[rustc_legacy_const_generics(2)]
26844#[cfg_attr(
26845    not(target_arch = "arm"),
26846    stable(feature = "neon_intrinsics", since = "1.59.0")
26847)]
26848#[cfg_attr(
26849    target_arch = "arm",
26850    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26851)]
26852pub unsafe fn vld4_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x4_t) -> poly16x4x4_t {
26853    static_assert_uimm_bits!(LANE, 2);
26854    transmute(vld4_lane_s16::<LANE>(transmute(a), transmute(b)))
26855}
26856#[doc = "Load multiple 4-element structures to four registers"]
26857#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p16)"]
26858#[doc = "## Safety"]
26859#[doc = "  * Neon instrinsic unsafe"]
26860#[inline]
26861#[target_feature(enable = "neon")]
26862#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26863#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26864#[cfg_attr(
26865    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26866    assert_instr(ld4, LANE = 0)
26867)]
26868#[rustc_legacy_const_generics(2)]
26869#[cfg_attr(
26870    not(target_arch = "arm"),
26871    stable(feature = "neon_intrinsics", since = "1.59.0")
26872)]
26873#[cfg_attr(
26874    target_arch = "arm",
26875    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26876)]
26877pub unsafe fn vld4q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x4_t) -> poly16x8x4_t {
26878    static_assert_uimm_bits!(LANE, 3);
26879    transmute(vld4q_lane_s16::<LANE>(transmute(a), transmute(b)))
26880}
26881#[doc = "Load multiple 4-element structures to four registers"]
26882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p64)"]
26883#[doc = "## Safety"]
26884#[doc = "  * Neon instrinsic unsafe"]
26885#[inline]
26886#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
26887#[target_feature(enable = "neon,aes")]
26888#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
26889#[cfg_attr(
26890    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26891    assert_instr(nop)
26892)]
26893#[cfg_attr(
26894    not(target_arch = "arm"),
26895    stable(feature = "neon_intrinsics", since = "1.59.0")
26896)]
26897#[cfg_attr(
26898    target_arch = "arm",
26899    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26900)]
26901pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t {
26902    transmute(vld4_s64(transmute(a)))
26903}
26904#[doc = "Load multiple 4-element structures to four registers"]
26905#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
26906#[doc = "## Safety"]
26907#[doc = "  * Neon instrinsic unsafe"]
26908#[inline]
26909#[target_feature(enable = "neon")]
26910#[cfg(not(target_arch = "arm"))]
26911#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26912#[cfg_attr(test, assert_instr(nop))]
26913pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
26914    unsafe extern "unadjusted" {
26915        #[cfg_attr(
26916            any(target_arch = "aarch64", target_arch = "arm64ec"),
26917            link_name = "llvm.aarch64.neon.ld4.v1i64.p0"
26918        )]
26919        fn _vld4_s64(ptr: *const int64x1_t) -> int64x1x4_t;
26920    }
26921    _vld4_s64(a as _)
26922}
26923#[doc = "Load multiple 4-element structures to four registers"]
26924#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
26925#[doc = "## Safety"]
26926#[doc = "  * Neon instrinsic unsafe"]
26927#[inline]
26928#[target_feature(enable = "neon,v7")]
26929#[cfg(target_arch = "arm")]
26930#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26931#[cfg_attr(test, assert_instr(nop))]
26932pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
26933    unsafe extern "unadjusted" {
26934        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v1i64.p0")]
26935        fn _vld4_s64(ptr: *const i8, size: i32) -> int64x1x4_t;
26936    }
26937    _vld4_s64(a as *const i8, 8)
26938}
26939#[doc = "Load multiple 4-element structures to four registers"]
26940#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u64)"]
26941#[doc = "## Safety"]
26942#[doc = "  * Neon instrinsic unsafe"]
26943#[inline]
26944#[target_feature(enable = "neon")]
26945#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26946#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
26947#[cfg_attr(
26948    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26949    assert_instr(nop)
26950)]
26951#[cfg_attr(
26952    not(target_arch = "arm"),
26953    stable(feature = "neon_intrinsics", since = "1.59.0")
26954)]
26955#[cfg_attr(
26956    target_arch = "arm",
26957    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26958)]
26959pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t {
26960    transmute(vld4_s64(transmute(a)))
26961}
26962#[doc = "Load multiple 4-element structures to four registers"]
26963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"]
26964#[doc = "## Safety"]
26965#[doc = "  * Neon instrinsic unsafe"]
26966#[inline]
26967#[cfg(target_endian = "little")]
26968#[target_feature(enable = "neon")]
26969#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26970#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
26971#[cfg_attr(
26972    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26973    assert_instr(ld4)
26974)]
26975#[cfg_attr(
26976    not(target_arch = "arm"),
26977    stable(feature = "neon_intrinsics", since = "1.59.0")
26978)]
26979#[cfg_attr(
26980    target_arch = "arm",
26981    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26982)]
26983pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t {
26984    transmute(vld4_s8(transmute(a)))
26985}
26986#[doc = "Load multiple 4-element structures to four registers"]
26987#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"]
26988#[doc = "## Safety"]
26989#[doc = "  * Neon instrinsic unsafe"]
26990#[inline]
26991#[cfg(target_endian = "big")]
26992#[target_feature(enable = "neon")]
26993#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26994#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
26995#[cfg_attr(
26996    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26997    assert_instr(ld4)
26998)]
26999#[cfg_attr(
27000    not(target_arch = "arm"),
27001    stable(feature = "neon_intrinsics", since = "1.59.0")
27002)]
27003#[cfg_attr(
27004    target_arch = "arm",
27005    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27006)]
27007pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t {
27008    let mut ret_val: uint8x8x4_t = transmute(vld4_s8(transmute(a)));
27009    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
27010    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
27011    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
27012    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
27013    ret_val
27014}
27015#[doc = "Load multiple 4-element structures to four registers"]
27016#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"]
27017#[doc = "## Safety"]
27018#[doc = "  * Neon instrinsic unsafe"]
27019#[inline]
27020#[cfg(target_endian = "little")]
27021#[target_feature(enable = "neon")]
27022#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27023#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27024#[cfg_attr(
27025    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27026    assert_instr(ld4)
27027)]
27028#[cfg_attr(
27029    not(target_arch = "arm"),
27030    stable(feature = "neon_intrinsics", since = "1.59.0")
27031)]
27032#[cfg_attr(
27033    target_arch = "arm",
27034    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27035)]
27036pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t {
27037    transmute(vld4q_s8(transmute(a)))
27038}
27039#[doc = "Load multiple 4-element structures to four registers"]
27040#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"]
27041#[doc = "## Safety"]
27042#[doc = "  * Neon instrinsic unsafe"]
27043#[inline]
27044#[cfg(target_endian = "big")]
27045#[target_feature(enable = "neon")]
27046#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27047#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27048#[cfg_attr(
27049    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27050    assert_instr(ld4)
27051)]
27052#[cfg_attr(
27053    not(target_arch = "arm"),
27054    stable(feature = "neon_intrinsics", since = "1.59.0")
27055)]
27056#[cfg_attr(
27057    target_arch = "arm",
27058    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27059)]
27060pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t {
27061    let mut ret_val: uint8x16x4_t = transmute(vld4q_s8(transmute(a)));
27062    ret_val.0 = unsafe {
27063        simd_shuffle!(
27064            ret_val.0,
27065            ret_val.0,
27066            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27067        )
27068    };
27069    ret_val.1 = unsafe {
27070        simd_shuffle!(
27071            ret_val.1,
27072            ret_val.1,
27073            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27074        )
27075    };
27076    ret_val.2 = unsafe {
27077        simd_shuffle!(
27078            ret_val.2,
27079            ret_val.2,
27080            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27081        )
27082    };
27083    ret_val.3 = unsafe {
27084        simd_shuffle!(
27085            ret_val.3,
27086            ret_val.3,
27087            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27088        )
27089    };
27090    ret_val
27091}
27092#[doc = "Load multiple 4-element structures to four registers"]
27093#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"]
27094#[doc = "## Safety"]
27095#[doc = "  * Neon instrinsic unsafe"]
27096#[inline]
27097#[cfg(target_endian = "little")]
27098#[target_feature(enable = "neon")]
27099#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27100#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27101#[cfg_attr(
27102    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27103    assert_instr(ld4)
27104)]
27105#[cfg_attr(
27106    not(target_arch = "arm"),
27107    stable(feature = "neon_intrinsics", since = "1.59.0")
27108)]
27109#[cfg_attr(
27110    target_arch = "arm",
27111    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27112)]
27113pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
27114    transmute(vld4_s16(transmute(a)))
27115}
27116#[doc = "Load multiple 4-element structures to four registers"]
27117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"]
27118#[doc = "## Safety"]
27119#[doc = "  * Neon instrinsic unsafe"]
27120#[inline]
27121#[cfg(target_endian = "big")]
27122#[target_feature(enable = "neon")]
27123#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27124#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27125#[cfg_attr(
27126    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27127    assert_instr(ld4)
27128)]
27129#[cfg_attr(
27130    not(target_arch = "arm"),
27131    stable(feature = "neon_intrinsics", since = "1.59.0")
27132)]
27133#[cfg_attr(
27134    target_arch = "arm",
27135    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27136)]
27137pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
27138    let mut ret_val: uint16x4x4_t = transmute(vld4_s16(transmute(a)));
27139    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
27140    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
27141    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
27142    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
27143    ret_val
27144}
27145#[doc = "Load multiple 4-element structures to four registers"]
27146#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"]
27147#[doc = "## Safety"]
27148#[doc = "  * Neon instrinsic unsafe"]
27149#[inline]
27150#[cfg(target_endian = "little")]
27151#[target_feature(enable = "neon")]
27152#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27153#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27154#[cfg_attr(
27155    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27156    assert_instr(ld4)
27157)]
27158#[cfg_attr(
27159    not(target_arch = "arm"),
27160    stable(feature = "neon_intrinsics", since = "1.59.0")
27161)]
27162#[cfg_attr(
27163    target_arch = "arm",
27164    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27165)]
27166pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
27167    transmute(vld4q_s16(transmute(a)))
27168}
27169#[doc = "Load multiple 4-element structures to four registers"]
27170#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"]
27171#[doc = "## Safety"]
27172#[doc = "  * Neon instrinsic unsafe"]
27173#[inline]
27174#[cfg(target_endian = "big")]
27175#[target_feature(enable = "neon")]
27176#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27177#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27178#[cfg_attr(
27179    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27180    assert_instr(ld4)
27181)]
27182#[cfg_attr(
27183    not(target_arch = "arm"),
27184    stable(feature = "neon_intrinsics", since = "1.59.0")
27185)]
27186#[cfg_attr(
27187    target_arch = "arm",
27188    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27189)]
27190pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
27191    let mut ret_val: uint16x8x4_t = transmute(vld4q_s16(transmute(a)));
27192    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
27193    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
27194    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
27195    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
27196    ret_val
27197}
27198#[doc = "Load multiple 4-element structures to four registers"]
27199#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"]
27200#[doc = "## Safety"]
27201#[doc = "  * Neon instrinsic unsafe"]
27202#[inline]
27203#[cfg(target_endian = "little")]
27204#[target_feature(enable = "neon")]
27205#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27206#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27207#[cfg_attr(
27208    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27209    assert_instr(ld4)
27210)]
27211#[cfg_attr(
27212    not(target_arch = "arm"),
27213    stable(feature = "neon_intrinsics", since = "1.59.0")
27214)]
27215#[cfg_attr(
27216    target_arch = "arm",
27217    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27218)]
27219pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
27220    transmute(vld4_s32(transmute(a)))
27221}
27222#[doc = "Load multiple 4-element structures to four registers"]
27223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"]
27224#[doc = "## Safety"]
27225#[doc = "  * Neon instrinsic unsafe"]
27226#[inline]
27227#[cfg(target_endian = "big")]
27228#[target_feature(enable = "neon")]
27229#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27230#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27231#[cfg_attr(
27232    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27233    assert_instr(ld4)
27234)]
27235#[cfg_attr(
27236    not(target_arch = "arm"),
27237    stable(feature = "neon_intrinsics", since = "1.59.0")
27238)]
27239#[cfg_attr(
27240    target_arch = "arm",
27241    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27242)]
27243pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
27244    let mut ret_val: uint32x2x4_t = transmute(vld4_s32(transmute(a)));
27245    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
27246    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
27247    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
27248    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
27249    ret_val
27250}
27251#[doc = "Load multiple 4-element structures to four registers"]
27252#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"]
27253#[doc = "## Safety"]
27254#[doc = "  * Neon instrinsic unsafe"]
27255#[inline]
27256#[cfg(target_endian = "little")]
27257#[target_feature(enable = "neon")]
27258#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27259#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27260#[cfg_attr(
27261    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27262    assert_instr(ld4)
27263)]
27264#[cfg_attr(
27265    not(target_arch = "arm"),
27266    stable(feature = "neon_intrinsics", since = "1.59.0")
27267)]
27268#[cfg_attr(
27269    target_arch = "arm",
27270    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27271)]
27272pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
27273    transmute(vld4q_s32(transmute(a)))
27274}
27275#[doc = "Load multiple 4-element structures to four registers"]
27276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"]
27277#[doc = "## Safety"]
27278#[doc = "  * Neon instrinsic unsafe"]
27279#[inline]
27280#[cfg(target_endian = "big")]
27281#[target_feature(enable = "neon")]
27282#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27283#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27284#[cfg_attr(
27285    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27286    assert_instr(ld4)
27287)]
27288#[cfg_attr(
27289    not(target_arch = "arm"),
27290    stable(feature = "neon_intrinsics", since = "1.59.0")
27291)]
27292#[cfg_attr(
27293    target_arch = "arm",
27294    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27295)]
27296pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
27297    let mut ret_val: uint32x4x4_t = transmute(vld4q_s32(transmute(a)));
27298    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
27299    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
27300    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
27301    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
27302    ret_val
27303}
27304#[doc = "Load multiple 4-element structures to four registers"]
27305#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"]
27306#[doc = "## Safety"]
27307#[doc = "  * Neon instrinsic unsafe"]
27308#[inline]
27309#[cfg(target_endian = "little")]
27310#[target_feature(enable = "neon")]
27311#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27312#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27313#[cfg_attr(
27314    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27315    assert_instr(ld4)
27316)]
27317#[cfg_attr(
27318    not(target_arch = "arm"),
27319    stable(feature = "neon_intrinsics", since = "1.59.0")
27320)]
27321#[cfg_attr(
27322    target_arch = "arm",
27323    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27324)]
27325pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
27326    transmute(vld4_s8(transmute(a)))
27327}
27328#[doc = "Load multiple 4-element structures to four registers"]
27329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"]
27330#[doc = "## Safety"]
27331#[doc = "  * Neon instrinsic unsafe"]
27332#[inline]
27333#[cfg(target_endian = "big")]
27334#[target_feature(enable = "neon")]
27335#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27336#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27337#[cfg_attr(
27338    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27339    assert_instr(ld4)
27340)]
27341#[cfg_attr(
27342    not(target_arch = "arm"),
27343    stable(feature = "neon_intrinsics", since = "1.59.0")
27344)]
27345#[cfg_attr(
27346    target_arch = "arm",
27347    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27348)]
27349pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
27350    let mut ret_val: poly8x8x4_t = transmute(vld4_s8(transmute(a)));
27351    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
27352    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
27353    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
27354    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
27355    ret_val
27356}
27357#[doc = "Load multiple 4-element structures to four registers"]
27358#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"]
27359#[doc = "## Safety"]
27360#[doc = "  * Neon instrinsic unsafe"]
27361#[inline]
27362#[cfg(target_endian = "little")]
27363#[target_feature(enable = "neon")]
27364#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27365#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27366#[cfg_attr(
27367    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27368    assert_instr(ld4)
27369)]
27370#[cfg_attr(
27371    not(target_arch = "arm"),
27372    stable(feature = "neon_intrinsics", since = "1.59.0")
27373)]
27374#[cfg_attr(
27375    target_arch = "arm",
27376    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27377)]
27378pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
27379    transmute(vld4q_s8(transmute(a)))
27380}
27381#[doc = "Load multiple 4-element structures to four registers"]
27382#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"]
27383#[doc = "## Safety"]
27384#[doc = "  * Neon instrinsic unsafe"]
27385#[inline]
27386#[cfg(target_endian = "big")]
27387#[target_feature(enable = "neon")]
27388#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27389#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27390#[cfg_attr(
27391    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27392    assert_instr(ld4)
27393)]
27394#[cfg_attr(
27395    not(target_arch = "arm"),
27396    stable(feature = "neon_intrinsics", since = "1.59.0")
27397)]
27398#[cfg_attr(
27399    target_arch = "arm",
27400    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27401)]
27402pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
27403    let mut ret_val: poly8x16x4_t = transmute(vld4q_s8(transmute(a)));
27404    ret_val.0 = unsafe {
27405        simd_shuffle!(
27406            ret_val.0,
27407            ret_val.0,
27408            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27409        )
27410    };
27411    ret_val.1 = unsafe {
27412        simd_shuffle!(
27413            ret_val.1,
27414            ret_val.1,
27415            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27416        )
27417    };
27418    ret_val.2 = unsafe {
27419        simd_shuffle!(
27420            ret_val.2,
27421            ret_val.2,
27422            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27423        )
27424    };
27425    ret_val.3 = unsafe {
27426        simd_shuffle!(
27427            ret_val.3,
27428            ret_val.3,
27429            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27430        )
27431    };
27432    ret_val
27433}
27434#[doc = "Load multiple 4-element structures to four registers"]
27435#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"]
27436#[doc = "## Safety"]
27437#[doc = "  * Neon instrinsic unsafe"]
27438#[inline]
27439#[cfg(target_endian = "little")]
27440#[target_feature(enable = "neon")]
27441#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27442#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27443#[cfg_attr(
27444    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27445    assert_instr(ld4)
27446)]
27447#[cfg_attr(
27448    not(target_arch = "arm"),
27449    stable(feature = "neon_intrinsics", since = "1.59.0")
27450)]
27451#[cfg_attr(
27452    target_arch = "arm",
27453    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27454)]
27455pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
27456    transmute(vld4_s16(transmute(a)))
27457}
27458#[doc = "Load multiple 4-element structures to four registers"]
27459#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"]
27460#[doc = "## Safety"]
27461#[doc = "  * Neon instrinsic unsafe"]
27462#[inline]
27463#[cfg(target_endian = "big")]
27464#[target_feature(enable = "neon")]
27465#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27466#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27467#[cfg_attr(
27468    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27469    assert_instr(ld4)
27470)]
27471#[cfg_attr(
27472    not(target_arch = "arm"),
27473    stable(feature = "neon_intrinsics", since = "1.59.0")
27474)]
27475#[cfg_attr(
27476    target_arch = "arm",
27477    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27478)]
27479pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
27480    let mut ret_val: poly16x4x4_t = transmute(vld4_s16(transmute(a)));
27481    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
27482    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
27483    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
27484    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
27485    ret_val
27486}
27487#[doc = "Load multiple 4-element structures to four registers"]
27488#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"]
27489#[doc = "## Safety"]
27490#[doc = "  * Neon instrinsic unsafe"]
27491#[inline]
27492#[cfg(target_endian = "little")]
27493#[target_feature(enable = "neon")]
27494#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27495#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27496#[cfg_attr(
27497    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27498    assert_instr(ld4)
27499)]
27500#[cfg_attr(
27501    not(target_arch = "arm"),
27502    stable(feature = "neon_intrinsics", since = "1.59.0")
27503)]
27504#[cfg_attr(
27505    target_arch = "arm",
27506    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27507)]
27508pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t {
27509    transmute(vld4q_s16(transmute(a)))
27510}
27511#[doc = "Load multiple 4-element structures to four registers"]
27512#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"]
27513#[doc = "## Safety"]
27514#[doc = "  * Neon instrinsic unsafe"]
27515#[inline]
27516#[cfg(target_endian = "big")]
27517#[target_feature(enable = "neon")]
27518#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27519#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27520#[cfg_attr(
27521    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27522    assert_instr(ld4)
27523)]
27524#[cfg_attr(
27525    not(target_arch = "arm"),
27526    stable(feature = "neon_intrinsics", since = "1.59.0")
27527)]
27528#[cfg_attr(
27529    target_arch = "arm",
27530    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27531)]
27532pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t {
27533    let mut ret_val: poly16x8x4_t = transmute(vld4q_s16(transmute(a)));
27534    ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
27535    ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
27536    ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
27537    ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
27538    ret_val
27539}
27540#[doc = "Store SIMD&FP register (immediate offset)"]
27541#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldrq_p128)"]
27542#[doc = "## Safety"]
27543#[doc = "  * Neon instrinsic unsafe"]
27544#[inline]
27545#[target_feature(enable = "neon")]
27546#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27547#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
27548#[cfg_attr(
27549    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27550    assert_instr(nop)
27551)]
27552#[cfg_attr(
27553    not(target_arch = "arm"),
27554    stable(feature = "neon_intrinsics", since = "1.59.0")
27555)]
27556#[cfg_attr(
27557    target_arch = "arm",
27558    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27559)]
27560pub unsafe fn vldrq_p128(a: *const p128) -> p128 {
27561    *a
27562}
27563#[doc = "Maximum (vector)"]
27564#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f16)"]
27565#[inline]
27566#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
27567#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27568#[cfg_attr(
27569    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27570    assert_instr(fmax)
27571)]
27572#[target_feature(enable = "neon,fp16")]
27573#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
27574pub fn vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
27575    unsafe extern "unadjusted" {
27576        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4f16")]
27577        #[cfg_attr(
27578            any(target_arch = "aarch64", target_arch = "arm64ec"),
27579            link_name = "llvm.aarch64.neon.fmax.v4f16"
27580        )]
27581        fn _vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
27582    }
27583    unsafe { _vmax_f16(a, b) }
27584}
27585#[doc = "Maximum (vector)"]
27586#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f16)"]
27587#[inline]
27588#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
27589#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27590#[cfg_attr(
27591    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27592    assert_instr(fmax)
27593)]
27594#[target_feature(enable = "neon,fp16")]
27595#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
27596pub fn vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
27597    unsafe extern "unadjusted" {
27598        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8f16")]
27599        #[cfg_attr(
27600            any(target_arch = "aarch64", target_arch = "arm64ec"),
27601            link_name = "llvm.aarch64.neon.fmax.v8f16"
27602        )]
27603        fn _vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
27604    }
27605    unsafe { _vmaxq_f16(a, b) }
27606}
27607#[doc = "Maximum (vector)"]
27608#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f32)"]
27609#[inline]
27610#[target_feature(enable = "neon")]
27611#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27612#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27613#[cfg_attr(
27614    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27615    assert_instr(fmax)
27616)]
27617#[cfg_attr(
27618    not(target_arch = "arm"),
27619    stable(feature = "neon_intrinsics", since = "1.59.0")
27620)]
27621#[cfg_attr(
27622    target_arch = "arm",
27623    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27624)]
27625pub fn vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
27626    unsafe extern "unadjusted" {
27627        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v2f32")]
27628        #[cfg_attr(
27629            any(target_arch = "aarch64", target_arch = "arm64ec"),
27630            link_name = "llvm.aarch64.neon.fmax.v2f32"
27631        )]
27632        fn _vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
27633    }
27634    unsafe { _vmax_f32(a, b) }
27635}
27636#[doc = "Maximum (vector)"]
27637#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f32)"]
27638#[inline]
27639#[target_feature(enable = "neon")]
27640#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27641#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27642#[cfg_attr(
27643    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27644    assert_instr(fmax)
27645)]
27646#[cfg_attr(
27647    not(target_arch = "arm"),
27648    stable(feature = "neon_intrinsics", since = "1.59.0")
27649)]
27650#[cfg_attr(
27651    target_arch = "arm",
27652    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27653)]
27654pub fn vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
27655    unsafe extern "unadjusted" {
27656        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4f32")]
27657        #[cfg_attr(
27658            any(target_arch = "aarch64", target_arch = "arm64ec"),
27659            link_name = "llvm.aarch64.neon.fmax.v4f32"
27660        )]
27661        fn _vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
27662    }
27663    unsafe { _vmaxq_f32(a, b) }
27664}
27665#[doc = "Maximum (vector)"]
27666#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s8)"]
27667#[inline]
27668#[target_feature(enable = "neon")]
27669#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27670#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27671#[cfg_attr(
27672    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27673    assert_instr(smax)
27674)]
27675#[cfg_attr(
27676    not(target_arch = "arm"),
27677    stable(feature = "neon_intrinsics", since = "1.59.0")
27678)]
27679#[cfg_attr(
27680    target_arch = "arm",
27681    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27682)]
27683pub fn vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
27684    unsafe extern "unadjusted" {
27685        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8i8")]
27686        #[cfg_attr(
27687            any(target_arch = "aarch64", target_arch = "arm64ec"),
27688            link_name = "llvm.aarch64.neon.smax.v8i8"
27689        )]
27690        fn _vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
27691    }
27692    unsafe { _vmax_s8(a, b) }
27693}
27694#[doc = "Maximum (vector)"]
27695#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s8)"]
27696#[inline]
27697#[target_feature(enable = "neon")]
27698#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27699#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27700#[cfg_attr(
27701    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27702    assert_instr(smax)
27703)]
27704#[cfg_attr(
27705    not(target_arch = "arm"),
27706    stable(feature = "neon_intrinsics", since = "1.59.0")
27707)]
27708#[cfg_attr(
27709    target_arch = "arm",
27710    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27711)]
27712pub fn vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
27713    unsafe extern "unadjusted" {
27714        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v16i8")]
27715        #[cfg_attr(
27716            any(target_arch = "aarch64", target_arch = "arm64ec"),
27717            link_name = "llvm.aarch64.neon.smax.v16i8"
27718        )]
27719        fn _vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
27720    }
27721    unsafe { _vmaxq_s8(a, b) }
27722}
27723#[doc = "Maximum (vector)"]
27724#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s16)"]
27725#[inline]
27726#[target_feature(enable = "neon")]
27727#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27728#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27729#[cfg_attr(
27730    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27731    assert_instr(smax)
27732)]
27733#[cfg_attr(
27734    not(target_arch = "arm"),
27735    stable(feature = "neon_intrinsics", since = "1.59.0")
27736)]
27737#[cfg_attr(
27738    target_arch = "arm",
27739    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27740)]
27741pub fn vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
27742    unsafe extern "unadjusted" {
27743        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4i16")]
27744        #[cfg_attr(
27745            any(target_arch = "aarch64", target_arch = "arm64ec"),
27746            link_name = "llvm.aarch64.neon.smax.v4i16"
27747        )]
27748        fn _vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
27749    }
27750    unsafe { _vmax_s16(a, b) }
27751}
27752#[doc = "Maximum (vector)"]
27753#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s16)"]
27754#[inline]
27755#[target_feature(enable = "neon")]
27756#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27757#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27758#[cfg_attr(
27759    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27760    assert_instr(smax)
27761)]
27762#[cfg_attr(
27763    not(target_arch = "arm"),
27764    stable(feature = "neon_intrinsics", since = "1.59.0")
27765)]
27766#[cfg_attr(
27767    target_arch = "arm",
27768    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27769)]
27770pub fn vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
27771    unsafe extern "unadjusted" {
27772        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8i16")]
27773        #[cfg_attr(
27774            any(target_arch = "aarch64", target_arch = "arm64ec"),
27775            link_name = "llvm.aarch64.neon.smax.v8i16"
27776        )]
27777        fn _vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
27778    }
27779    unsafe { _vmaxq_s16(a, b) }
27780}
27781#[doc = "Maximum (vector)"]
27782#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s32)"]
27783#[inline]
27784#[target_feature(enable = "neon")]
27785#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27786#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27787#[cfg_attr(
27788    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27789    assert_instr(smax)
27790)]
27791#[cfg_attr(
27792    not(target_arch = "arm"),
27793    stable(feature = "neon_intrinsics", since = "1.59.0")
27794)]
27795#[cfg_attr(
27796    target_arch = "arm",
27797    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27798)]
27799pub fn vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
27800    unsafe extern "unadjusted" {
27801        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v2i32")]
27802        #[cfg_attr(
27803            any(target_arch = "aarch64", target_arch = "arm64ec"),
27804            link_name = "llvm.aarch64.neon.smax.v2i32"
27805        )]
27806        fn _vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
27807    }
27808    unsafe { _vmax_s32(a, b) }
27809}
27810#[doc = "Maximum (vector)"]
27811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s32)"]
27812#[inline]
27813#[target_feature(enable = "neon")]
27814#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27815#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27816#[cfg_attr(
27817    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27818    assert_instr(smax)
27819)]
27820#[cfg_attr(
27821    not(target_arch = "arm"),
27822    stable(feature = "neon_intrinsics", since = "1.59.0")
27823)]
27824#[cfg_attr(
27825    target_arch = "arm",
27826    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27827)]
27828pub fn vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
27829    unsafe extern "unadjusted" {
27830        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4i32")]
27831        #[cfg_attr(
27832            any(target_arch = "aarch64", target_arch = "arm64ec"),
27833            link_name = "llvm.aarch64.neon.smax.v4i32"
27834        )]
27835        fn _vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
27836    }
27837    unsafe { _vmaxq_s32(a, b) }
27838}
27839#[doc = "Maximum (vector)"]
27840#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u8)"]
27841#[inline]
27842#[target_feature(enable = "neon")]
27843#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27844#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27845#[cfg_attr(
27846    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27847    assert_instr(umax)
27848)]
27849#[cfg_attr(
27850    not(target_arch = "arm"),
27851    stable(feature = "neon_intrinsics", since = "1.59.0")
27852)]
27853#[cfg_attr(
27854    target_arch = "arm",
27855    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27856)]
27857pub fn vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
27858    unsafe extern "unadjusted" {
27859        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v8i8")]
27860        #[cfg_attr(
27861            any(target_arch = "aarch64", target_arch = "arm64ec"),
27862            link_name = "llvm.aarch64.neon.umax.v8i8"
27863        )]
27864        fn _vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
27865    }
27866    unsafe { _vmax_u8(a, b) }
27867}
27868#[doc = "Maximum (vector)"]
27869#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u8)"]
27870#[inline]
27871#[target_feature(enable = "neon")]
27872#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27873#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27874#[cfg_attr(
27875    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27876    assert_instr(umax)
27877)]
27878#[cfg_attr(
27879    not(target_arch = "arm"),
27880    stable(feature = "neon_intrinsics", since = "1.59.0")
27881)]
27882#[cfg_attr(
27883    target_arch = "arm",
27884    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27885)]
27886pub fn vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
27887    unsafe extern "unadjusted" {
27888        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v16i8")]
27889        #[cfg_attr(
27890            any(target_arch = "aarch64", target_arch = "arm64ec"),
27891            link_name = "llvm.aarch64.neon.umax.v16i8"
27892        )]
27893        fn _vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
27894    }
27895    unsafe { _vmaxq_u8(a, b) }
27896}
27897#[doc = "Maximum (vector)"]
27898#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u16)"]
27899#[inline]
27900#[target_feature(enable = "neon")]
27901#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27902#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27903#[cfg_attr(
27904    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27905    assert_instr(umax)
27906)]
27907#[cfg_attr(
27908    not(target_arch = "arm"),
27909    stable(feature = "neon_intrinsics", since = "1.59.0")
27910)]
27911#[cfg_attr(
27912    target_arch = "arm",
27913    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27914)]
27915pub fn vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
27916    unsafe extern "unadjusted" {
27917        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v4i16")]
27918        #[cfg_attr(
27919            any(target_arch = "aarch64", target_arch = "arm64ec"),
27920            link_name = "llvm.aarch64.neon.umax.v4i16"
27921        )]
27922        fn _vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
27923    }
27924    unsafe { _vmax_u16(a, b) }
27925}
27926#[doc = "Maximum (vector)"]
27927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u16)"]
27928#[inline]
27929#[target_feature(enable = "neon")]
27930#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27931#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27932#[cfg_attr(
27933    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27934    assert_instr(umax)
27935)]
27936#[cfg_attr(
27937    not(target_arch = "arm"),
27938    stable(feature = "neon_intrinsics", since = "1.59.0")
27939)]
27940#[cfg_attr(
27941    target_arch = "arm",
27942    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27943)]
27944pub fn vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
27945    unsafe extern "unadjusted" {
27946        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v8i16")]
27947        #[cfg_attr(
27948            any(target_arch = "aarch64", target_arch = "arm64ec"),
27949            link_name = "llvm.aarch64.neon.umax.v8i16"
27950        )]
27951        fn _vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
27952    }
27953    unsafe { _vmaxq_u16(a, b) }
27954}
27955#[doc = "Maximum (vector)"]
27956#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u32)"]
27957#[inline]
27958#[target_feature(enable = "neon")]
27959#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27960#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27961#[cfg_attr(
27962    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27963    assert_instr(umax)
27964)]
27965#[cfg_attr(
27966    not(target_arch = "arm"),
27967    stable(feature = "neon_intrinsics", since = "1.59.0")
27968)]
27969#[cfg_attr(
27970    target_arch = "arm",
27971    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27972)]
27973pub fn vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
27974    unsafe extern "unadjusted" {
27975        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v2i32")]
27976        #[cfg_attr(
27977            any(target_arch = "aarch64", target_arch = "arm64ec"),
27978            link_name = "llvm.aarch64.neon.umax.v2i32"
27979        )]
27980        fn _vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
27981    }
27982    unsafe { _vmax_u32(a, b) }
27983}
27984#[doc = "Maximum (vector)"]
27985#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u32)"]
27986#[inline]
27987#[target_feature(enable = "neon")]
27988#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27989#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27990#[cfg_attr(
27991    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27992    assert_instr(umax)
27993)]
27994#[cfg_attr(
27995    not(target_arch = "arm"),
27996    stable(feature = "neon_intrinsics", since = "1.59.0")
27997)]
27998#[cfg_attr(
27999    target_arch = "arm",
28000    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28001)]
28002pub fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
28003    unsafe extern "unadjusted" {
28004        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v4i32")]
28005        #[cfg_attr(
28006            any(target_arch = "aarch64", target_arch = "arm64ec"),
28007            link_name = "llvm.aarch64.neon.umax.v4i32"
28008        )]
28009        fn _vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
28010    }
28011    unsafe { _vmaxq_u32(a, b) }
28012}
28013#[doc = "Floating-point Maximum Number (vector)"]
28014#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f16)"]
28015#[inline]
28016#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28017#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
28018#[cfg_attr(
28019    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28020    assert_instr(fmaxnm)
28021)]
28022#[target_feature(enable = "neon,fp16")]
28023#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
28024pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
28025    unsafe extern "unadjusted" {
28026        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f16")]
28027        #[cfg_attr(
28028            any(target_arch = "aarch64", target_arch = "arm64ec"),
28029            link_name = "llvm.aarch64.neon.fmaxnm.v4f16"
28030        )]
28031        fn _vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
28032    }
28033    unsafe { _vmaxnm_f16(a, b) }
28034}
28035#[doc = "Floating-point Maximum Number (vector)"]
28036#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f16)"]
28037#[inline]
28038#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28039#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
28040#[cfg_attr(
28041    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28042    assert_instr(fmaxnm)
28043)]
28044#[target_feature(enable = "neon,fp16")]
28045#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
28046pub fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
28047    unsafe extern "unadjusted" {
28048        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v8f16")]
28049        #[cfg_attr(
28050            any(target_arch = "aarch64", target_arch = "arm64ec"),
28051            link_name = "llvm.aarch64.neon.fmaxnm.v8f16"
28052        )]
28053        fn _vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
28054    }
28055    unsafe { _vmaxnmq_f16(a, b) }
28056}
28057#[doc = "Floating-point Maximum Number (vector)"]
28058#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f32)"]
28059#[inline]
28060#[target_feature(enable = "neon")]
28061#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28062#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
28063#[cfg_attr(
28064    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28065    assert_instr(fmaxnm)
28066)]
28067#[cfg_attr(
28068    not(target_arch = "arm"),
28069    stable(feature = "neon_intrinsics", since = "1.59.0")
28070)]
28071#[cfg_attr(
28072    target_arch = "arm",
28073    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28074)]
28075pub fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
28076    unsafe extern "unadjusted" {
28077        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v2f32")]
28078        #[cfg_attr(
28079            any(target_arch = "aarch64", target_arch = "arm64ec"),
28080            link_name = "llvm.aarch64.neon.fmaxnm.v2f32"
28081        )]
28082        fn _vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
28083    }
28084    unsafe { _vmaxnm_f32(a, b) }
28085}
28086#[doc = "Floating-point Maximum Number (vector)"]
28087#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f32)"]
28088#[inline]
28089#[target_feature(enable = "neon")]
28090#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28091#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
28092#[cfg_attr(
28093    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28094    assert_instr(fmaxnm)
28095)]
28096#[cfg_attr(
28097    not(target_arch = "arm"),
28098    stable(feature = "neon_intrinsics", since = "1.59.0")
28099)]
28100#[cfg_attr(
28101    target_arch = "arm",
28102    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28103)]
28104pub fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
28105    unsafe extern "unadjusted" {
28106        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f32")]
28107        #[cfg_attr(
28108            any(target_arch = "aarch64", target_arch = "arm64ec"),
28109            link_name = "llvm.aarch64.neon.fmaxnm.v4f32"
28110        )]
28111        fn _vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
28112    }
28113    unsafe { _vmaxnmq_f32(a, b) }
28114}
28115#[doc = "Minimum (vector)"]
28116#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f16)"]
28117#[inline]
28118#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
28119#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28120#[cfg_attr(
28121    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28122    assert_instr(fmin)
28123)]
28124#[target_feature(enable = "neon,fp16")]
28125#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
28126pub fn vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
28127    unsafe extern "unadjusted" {
28128        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4f16")]
28129        #[cfg_attr(
28130            any(target_arch = "aarch64", target_arch = "arm64ec"),
28131            link_name = "llvm.aarch64.neon.fmin.v4f16"
28132        )]
28133        fn _vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
28134    }
28135    unsafe { _vmin_f16(a, b) }
28136}
28137#[doc = "Minimum (vector)"]
28138#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f16)"]
28139#[inline]
28140#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
28141#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28142#[cfg_attr(
28143    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28144    assert_instr(fmin)
28145)]
28146#[target_feature(enable = "neon,fp16")]
28147#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
28148pub fn vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
28149    unsafe extern "unadjusted" {
28150        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8f16")]
28151        #[cfg_attr(
28152            any(target_arch = "aarch64", target_arch = "arm64ec"),
28153            link_name = "llvm.aarch64.neon.fmin.v8f16"
28154        )]
28155        fn _vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
28156    }
28157    unsafe { _vminq_f16(a, b) }
28158}
28159#[doc = "Minimum (vector)"]
28160#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f32)"]
28161#[inline]
28162#[target_feature(enable = "neon")]
28163#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28164#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28165#[cfg_attr(
28166    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28167    assert_instr(fmin)
28168)]
28169#[cfg_attr(
28170    not(target_arch = "arm"),
28171    stable(feature = "neon_intrinsics", since = "1.59.0")
28172)]
28173#[cfg_attr(
28174    target_arch = "arm",
28175    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28176)]
28177pub fn vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
28178    unsafe extern "unadjusted" {
28179        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v2f32")]
28180        #[cfg_attr(
28181            any(target_arch = "aarch64", target_arch = "arm64ec"),
28182            link_name = "llvm.aarch64.neon.fmin.v2f32"
28183        )]
28184        fn _vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
28185    }
28186    unsafe { _vmin_f32(a, b) }
28187}
28188#[doc = "Minimum (vector)"]
28189#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f32)"]
28190#[inline]
28191#[target_feature(enable = "neon")]
28192#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28193#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28194#[cfg_attr(
28195    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28196    assert_instr(fmin)
28197)]
28198#[cfg_attr(
28199    not(target_arch = "arm"),
28200    stable(feature = "neon_intrinsics", since = "1.59.0")
28201)]
28202#[cfg_attr(
28203    target_arch = "arm",
28204    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28205)]
28206pub fn vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
28207    unsafe extern "unadjusted" {
28208        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4f32")]
28209        #[cfg_attr(
28210            any(target_arch = "aarch64", target_arch = "arm64ec"),
28211            link_name = "llvm.aarch64.neon.fmin.v4f32"
28212        )]
28213        fn _vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
28214    }
28215    unsafe { _vminq_f32(a, b) }
28216}
28217#[doc = "Minimum (vector)"]
28218#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s8)"]
28219#[inline]
28220#[target_feature(enable = "neon")]
28221#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28222#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28223#[cfg_attr(
28224    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28225    assert_instr(smin)
28226)]
28227#[cfg_attr(
28228    not(target_arch = "arm"),
28229    stable(feature = "neon_intrinsics", since = "1.59.0")
28230)]
28231#[cfg_attr(
28232    target_arch = "arm",
28233    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28234)]
28235pub fn vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
28236    unsafe extern "unadjusted" {
28237        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8i8")]
28238        #[cfg_attr(
28239            any(target_arch = "aarch64", target_arch = "arm64ec"),
28240            link_name = "llvm.aarch64.neon.smin.v8i8"
28241        )]
28242        fn _vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
28243    }
28244    unsafe { _vmin_s8(a, b) }
28245}
28246#[doc = "Minimum (vector)"]
28247#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s8)"]
28248#[inline]
28249#[target_feature(enable = "neon")]
28250#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28251#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28252#[cfg_attr(
28253    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28254    assert_instr(smin)
28255)]
28256#[cfg_attr(
28257    not(target_arch = "arm"),
28258    stable(feature = "neon_intrinsics", since = "1.59.0")
28259)]
28260#[cfg_attr(
28261    target_arch = "arm",
28262    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28263)]
28264pub fn vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
28265    unsafe extern "unadjusted" {
28266        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v16i8")]
28267        #[cfg_attr(
28268            any(target_arch = "aarch64", target_arch = "arm64ec"),
28269            link_name = "llvm.aarch64.neon.smin.v16i8"
28270        )]
28271        fn _vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
28272    }
28273    unsafe { _vminq_s8(a, b) }
28274}
28275#[doc = "Minimum (vector)"]
28276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s16)"]
28277#[inline]
28278#[target_feature(enable = "neon")]
28279#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28280#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28281#[cfg_attr(
28282    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28283    assert_instr(smin)
28284)]
28285#[cfg_attr(
28286    not(target_arch = "arm"),
28287    stable(feature = "neon_intrinsics", since = "1.59.0")
28288)]
28289#[cfg_attr(
28290    target_arch = "arm",
28291    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28292)]
28293pub fn vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
28294    unsafe extern "unadjusted" {
28295        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4i16")]
28296        #[cfg_attr(
28297            any(target_arch = "aarch64", target_arch = "arm64ec"),
28298            link_name = "llvm.aarch64.neon.smin.v4i16"
28299        )]
28300        fn _vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
28301    }
28302    unsafe { _vmin_s16(a, b) }
28303}
28304#[doc = "Minimum (vector)"]
28305#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s16)"]
28306#[inline]
28307#[target_feature(enable = "neon")]
28308#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28309#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28310#[cfg_attr(
28311    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28312    assert_instr(smin)
28313)]
28314#[cfg_attr(
28315    not(target_arch = "arm"),
28316    stable(feature = "neon_intrinsics", since = "1.59.0")
28317)]
28318#[cfg_attr(
28319    target_arch = "arm",
28320    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28321)]
28322pub fn vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
28323    unsafe extern "unadjusted" {
28324        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8i16")]
28325        #[cfg_attr(
28326            any(target_arch = "aarch64", target_arch = "arm64ec"),
28327            link_name = "llvm.aarch64.neon.smin.v8i16"
28328        )]
28329        fn _vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
28330    }
28331    unsafe { _vminq_s16(a, b) }
28332}
28333#[doc = "Minimum (vector)"]
28334#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s32)"]
28335#[inline]
28336#[target_feature(enable = "neon")]
28337#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28338#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28339#[cfg_attr(
28340    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28341    assert_instr(smin)
28342)]
28343#[cfg_attr(
28344    not(target_arch = "arm"),
28345    stable(feature = "neon_intrinsics", since = "1.59.0")
28346)]
28347#[cfg_attr(
28348    target_arch = "arm",
28349    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28350)]
28351pub fn vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
28352    unsafe extern "unadjusted" {
28353        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v2i32")]
28354        #[cfg_attr(
28355            any(target_arch = "aarch64", target_arch = "arm64ec"),
28356            link_name = "llvm.aarch64.neon.smin.v2i32"
28357        )]
28358        fn _vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
28359    }
28360    unsafe { _vmin_s32(a, b) }
28361}
28362#[doc = "Minimum (vector)"]
28363#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s32)"]
28364#[inline]
28365#[target_feature(enable = "neon")]
28366#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28367#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28368#[cfg_attr(
28369    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28370    assert_instr(smin)
28371)]
28372#[cfg_attr(
28373    not(target_arch = "arm"),
28374    stable(feature = "neon_intrinsics", since = "1.59.0")
28375)]
28376#[cfg_attr(
28377    target_arch = "arm",
28378    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28379)]
28380pub fn vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
28381    unsafe extern "unadjusted" {
28382        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4i32")]
28383        #[cfg_attr(
28384            any(target_arch = "aarch64", target_arch = "arm64ec"),
28385            link_name = "llvm.aarch64.neon.smin.v4i32"
28386        )]
28387        fn _vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
28388    }
28389    unsafe { _vminq_s32(a, b) }
28390}
28391#[doc = "Minimum (vector)"]
28392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u8)"]
28393#[inline]
28394#[target_feature(enable = "neon")]
28395#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28396#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28397#[cfg_attr(
28398    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28399    assert_instr(umin)
28400)]
28401#[cfg_attr(
28402    not(target_arch = "arm"),
28403    stable(feature = "neon_intrinsics", since = "1.59.0")
28404)]
28405#[cfg_attr(
28406    target_arch = "arm",
28407    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28408)]
28409pub fn vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
28410    unsafe extern "unadjusted" {
28411        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v8i8")]
28412        #[cfg_attr(
28413            any(target_arch = "aarch64", target_arch = "arm64ec"),
28414            link_name = "llvm.aarch64.neon.umin.v8i8"
28415        )]
28416        fn _vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
28417    }
28418    unsafe { _vmin_u8(a, b) }
28419}
28420#[doc = "Minimum (vector)"]
28421#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u8)"]
28422#[inline]
28423#[target_feature(enable = "neon")]
28424#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28425#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28426#[cfg_attr(
28427    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28428    assert_instr(umin)
28429)]
28430#[cfg_attr(
28431    not(target_arch = "arm"),
28432    stable(feature = "neon_intrinsics", since = "1.59.0")
28433)]
28434#[cfg_attr(
28435    target_arch = "arm",
28436    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28437)]
28438pub fn vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
28439    unsafe extern "unadjusted" {
28440        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v16i8")]
28441        #[cfg_attr(
28442            any(target_arch = "aarch64", target_arch = "arm64ec"),
28443            link_name = "llvm.aarch64.neon.umin.v16i8"
28444        )]
28445        fn _vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
28446    }
28447    unsafe { _vminq_u8(a, b) }
28448}
28449#[doc = "Minimum (vector)"]
28450#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u16)"]
28451#[inline]
28452#[target_feature(enable = "neon")]
28453#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28454#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28455#[cfg_attr(
28456    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28457    assert_instr(umin)
28458)]
28459#[cfg_attr(
28460    not(target_arch = "arm"),
28461    stable(feature = "neon_intrinsics", since = "1.59.0")
28462)]
28463#[cfg_attr(
28464    target_arch = "arm",
28465    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28466)]
28467pub fn vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
28468    unsafe extern "unadjusted" {
28469        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v4i16")]
28470        #[cfg_attr(
28471            any(target_arch = "aarch64", target_arch = "arm64ec"),
28472            link_name = "llvm.aarch64.neon.umin.v4i16"
28473        )]
28474        fn _vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
28475    }
28476    unsafe { _vmin_u16(a, b) }
28477}
28478#[doc = "Minimum (vector)"]
28479#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u16)"]
28480#[inline]
28481#[target_feature(enable = "neon")]
28482#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28483#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28484#[cfg_attr(
28485    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28486    assert_instr(umin)
28487)]
28488#[cfg_attr(
28489    not(target_arch = "arm"),
28490    stable(feature = "neon_intrinsics", since = "1.59.0")
28491)]
28492#[cfg_attr(
28493    target_arch = "arm",
28494    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28495)]
28496pub fn vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
28497    unsafe extern "unadjusted" {
28498        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v8i16")]
28499        #[cfg_attr(
28500            any(target_arch = "aarch64", target_arch = "arm64ec"),
28501            link_name = "llvm.aarch64.neon.umin.v8i16"
28502        )]
28503        fn _vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
28504    }
28505    unsafe { _vminq_u16(a, b) }
28506}
28507#[doc = "Minimum (vector)"]
28508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u32)"]
28509#[inline]
28510#[target_feature(enable = "neon")]
28511#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28512#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28513#[cfg_attr(
28514    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28515    assert_instr(umin)
28516)]
28517#[cfg_attr(
28518    not(target_arch = "arm"),
28519    stable(feature = "neon_intrinsics", since = "1.59.0")
28520)]
28521#[cfg_attr(
28522    target_arch = "arm",
28523    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28524)]
28525pub fn vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
28526    unsafe extern "unadjusted" {
28527        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v2i32")]
28528        #[cfg_attr(
28529            any(target_arch = "aarch64", target_arch = "arm64ec"),
28530            link_name = "llvm.aarch64.neon.umin.v2i32"
28531        )]
28532        fn _vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
28533    }
28534    unsafe { _vmin_u32(a, b) }
28535}
28536#[doc = "Minimum (vector)"]
28537#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u32)"]
28538#[inline]
28539#[target_feature(enable = "neon")]
28540#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28541#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28542#[cfg_attr(
28543    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28544    assert_instr(umin)
28545)]
28546#[cfg_attr(
28547    not(target_arch = "arm"),
28548    stable(feature = "neon_intrinsics", since = "1.59.0")
28549)]
28550#[cfg_attr(
28551    target_arch = "arm",
28552    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28553)]
28554pub fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
28555    unsafe extern "unadjusted" {
28556        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v4i32")]
28557        #[cfg_attr(
28558            any(target_arch = "aarch64", target_arch = "arm64ec"),
28559            link_name = "llvm.aarch64.neon.umin.v4i32"
28560        )]
28561        fn _vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
28562    }
28563    unsafe { _vminq_u32(a, b) }
28564}
28565#[doc = "Floating-point Minimum Number (vector)"]
28566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f16)"]
28567#[inline]
28568#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28569#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
28570#[cfg_attr(
28571    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28572    assert_instr(fminnm)
28573)]
28574#[target_feature(enable = "neon,fp16")]
28575#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
28576pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
28577    unsafe extern "unadjusted" {
28578        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f16")]
28579        #[cfg_attr(
28580            any(target_arch = "aarch64", target_arch = "arm64ec"),
28581            link_name = "llvm.aarch64.neon.fminnm.v4f16"
28582        )]
28583        fn _vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
28584    }
28585    unsafe { _vminnm_f16(a, b) }
28586}
28587#[doc = "Floating-point Minimum Number (vector)"]
28588#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f16)"]
28589#[inline]
28590#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28591#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
28592#[cfg_attr(
28593    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28594    assert_instr(fminnm)
28595)]
28596#[target_feature(enable = "neon,fp16")]
28597#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
28598pub fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
28599    unsafe extern "unadjusted" {
28600        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v8f16")]
28601        #[cfg_attr(
28602            any(target_arch = "aarch64", target_arch = "arm64ec"),
28603            link_name = "llvm.aarch64.neon.fminnm.v8f16"
28604        )]
28605        fn _vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
28606    }
28607    unsafe { _vminnmq_f16(a, b) }
28608}
28609#[doc = "Floating-point Minimum Number (vector)"]
28610#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f32)"]
28611#[inline]
28612#[target_feature(enable = "neon")]
28613#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28614#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
28615#[cfg_attr(
28616    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28617    assert_instr(fminnm)
28618)]
28619#[cfg_attr(
28620    not(target_arch = "arm"),
28621    stable(feature = "neon_intrinsics", since = "1.59.0")
28622)]
28623#[cfg_attr(
28624    target_arch = "arm",
28625    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28626)]
28627pub fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
28628    unsafe extern "unadjusted" {
28629        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v2f32")]
28630        #[cfg_attr(
28631            any(target_arch = "aarch64", target_arch = "arm64ec"),
28632            link_name = "llvm.aarch64.neon.fminnm.v2f32"
28633        )]
28634        fn _vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
28635    }
28636    unsafe { _vminnm_f32(a, b) }
28637}
28638#[doc = "Floating-point Minimum Number (vector)"]
28639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f32)"]
28640#[inline]
28641#[target_feature(enable = "neon")]
28642#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28643#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
28644#[cfg_attr(
28645    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28646    assert_instr(fminnm)
28647)]
28648#[cfg_attr(
28649    not(target_arch = "arm"),
28650    stable(feature = "neon_intrinsics", since = "1.59.0")
28651)]
28652#[cfg_attr(
28653    target_arch = "arm",
28654    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28655)]
28656pub fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
28657    unsafe extern "unadjusted" {
28658        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f32")]
28659        #[cfg_attr(
28660            any(target_arch = "aarch64", target_arch = "arm64ec"),
28661            link_name = "llvm.aarch64.neon.fminnm.v4f32"
28662        )]
28663        fn _vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
28664    }
28665    unsafe { _vminnmq_f32(a, b) }
28666}
28667#[doc = "Floating-point multiply-add to accumulator"]
28668#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f32)"]
28669#[inline]
28670#[target_feature(enable = "neon")]
28671#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28672#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
28673#[cfg_attr(
28674    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28675    assert_instr(fmul)
28676)]
28677#[cfg_attr(
28678    not(target_arch = "arm"),
28679    stable(feature = "neon_intrinsics", since = "1.59.0")
28680)]
28681#[cfg_attr(
28682    target_arch = "arm",
28683    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28684)]
28685pub fn vmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
28686    unsafe { simd_add(a, simd_mul(b, c)) }
28687}
28688#[doc = "Floating-point multiply-add to accumulator"]
28689#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f32)"]
28690#[inline]
28691#[target_feature(enable = "neon")]
28692#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28693#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
28694#[cfg_attr(
28695    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28696    assert_instr(fmul)
28697)]
28698#[cfg_attr(
28699    not(target_arch = "arm"),
28700    stable(feature = "neon_intrinsics", since = "1.59.0")
28701)]
28702#[cfg_attr(
28703    target_arch = "arm",
28704    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28705)]
28706pub fn vmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
28707    unsafe { simd_add(a, simd_mul(b, c)) }
28708}
28709#[doc = "Vector multiply accumulate with scalar"]
28710#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_f32)"]
28711#[inline]
28712#[target_feature(enable = "neon")]
28713#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28714#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
28715#[cfg_attr(
28716    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28717    assert_instr(fmul, LANE = 1)
28718)]
28719#[rustc_legacy_const_generics(3)]
28720#[cfg_attr(
28721    not(target_arch = "arm"),
28722    stable(feature = "neon_intrinsics", since = "1.59.0")
28723)]
28724#[cfg_attr(
28725    target_arch = "arm",
28726    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28727)]
28728pub fn vmla_lane_f32<const LANE: i32>(
28729    a: float32x2_t,
28730    b: float32x2_t,
28731    c: float32x2_t,
28732) -> float32x2_t {
28733    static_assert_uimm_bits!(LANE, 1);
28734    unsafe { vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
28735}
28736#[doc = "Vector multiply accumulate with scalar"]
28737#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_f32)"]
28738#[inline]
28739#[target_feature(enable = "neon")]
28740#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28741#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
28742#[cfg_attr(
28743    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28744    assert_instr(fmul, LANE = 1)
28745)]
28746#[rustc_legacy_const_generics(3)]
28747#[cfg_attr(
28748    not(target_arch = "arm"),
28749    stable(feature = "neon_intrinsics", since = "1.59.0")
28750)]
28751#[cfg_attr(
28752    target_arch = "arm",
28753    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28754)]
28755pub fn vmla_laneq_f32<const LANE: i32>(
28756    a: float32x2_t,
28757    b: float32x2_t,
28758    c: float32x4_t,
28759) -> float32x2_t {
28760    static_assert_uimm_bits!(LANE, 2);
28761    unsafe { vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
28762}
28763#[doc = "Vector multiply accumulate with scalar"]
28764#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_f32)"]
28765#[inline]
28766#[target_feature(enable = "neon")]
28767#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28768#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
28769#[cfg_attr(
28770    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28771    assert_instr(fmul, LANE = 1)
28772)]
28773#[rustc_legacy_const_generics(3)]
28774#[cfg_attr(
28775    not(target_arch = "arm"),
28776    stable(feature = "neon_intrinsics", since = "1.59.0")
28777)]
28778#[cfg_attr(
28779    target_arch = "arm",
28780    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28781)]
28782pub fn vmlaq_lane_f32<const LANE: i32>(
28783    a: float32x4_t,
28784    b: float32x4_t,
28785    c: float32x2_t,
28786) -> float32x4_t {
28787    static_assert_uimm_bits!(LANE, 1);
28788    unsafe {
28789        vmlaq_f32(
28790            a,
28791            b,
28792            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28793        )
28794    }
28795}
28796#[doc = "Vector multiply accumulate with scalar"]
28797#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_f32)"]
28798#[inline]
28799#[target_feature(enable = "neon")]
28800#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28801#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
28802#[cfg_attr(
28803    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28804    assert_instr(fmul, LANE = 1)
28805)]
28806#[rustc_legacy_const_generics(3)]
28807#[cfg_attr(
28808    not(target_arch = "arm"),
28809    stable(feature = "neon_intrinsics", since = "1.59.0")
28810)]
28811#[cfg_attr(
28812    target_arch = "arm",
28813    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28814)]
28815pub fn vmlaq_laneq_f32<const LANE: i32>(
28816    a: float32x4_t,
28817    b: float32x4_t,
28818    c: float32x4_t,
28819) -> float32x4_t {
28820    static_assert_uimm_bits!(LANE, 2);
28821    unsafe {
28822        vmlaq_f32(
28823            a,
28824            b,
28825            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28826        )
28827    }
28828}
28829#[doc = "Vector multiply accumulate with scalar"]
28830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s16)"]
28831#[inline]
28832#[target_feature(enable = "neon")]
28833#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28834#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
28835#[cfg_attr(
28836    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28837    assert_instr(mla, LANE = 1)
28838)]
28839#[rustc_legacy_const_generics(3)]
28840#[cfg_attr(
28841    not(target_arch = "arm"),
28842    stable(feature = "neon_intrinsics", since = "1.59.0")
28843)]
28844#[cfg_attr(
28845    target_arch = "arm",
28846    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28847)]
28848pub fn vmla_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
28849    static_assert_uimm_bits!(LANE, 2);
28850    unsafe {
28851        vmla_s16(
28852            a,
28853            b,
28854            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28855        )
28856    }
28857}
28858#[doc = "Vector multiply accumulate with scalar"]
28859#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u16)"]
28860#[inline]
28861#[target_feature(enable = "neon")]
28862#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28863#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
28864#[cfg_attr(
28865    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28866    assert_instr(mla, LANE = 1)
28867)]
28868#[rustc_legacy_const_generics(3)]
28869#[cfg_attr(
28870    not(target_arch = "arm"),
28871    stable(feature = "neon_intrinsics", since = "1.59.0")
28872)]
28873#[cfg_attr(
28874    target_arch = "arm",
28875    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28876)]
28877pub fn vmla_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
28878    static_assert_uimm_bits!(LANE, 2);
28879    unsafe {
28880        vmla_u16(
28881            a,
28882            b,
28883            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28884        )
28885    }
28886}
28887#[doc = "Vector multiply accumulate with scalar"]
28888#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s16)"]
28889#[inline]
28890#[target_feature(enable = "neon")]
28891#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28892#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
28893#[cfg_attr(
28894    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28895    assert_instr(mla, LANE = 1)
28896)]
28897#[rustc_legacy_const_generics(3)]
28898#[cfg_attr(
28899    not(target_arch = "arm"),
28900    stable(feature = "neon_intrinsics", since = "1.59.0")
28901)]
28902#[cfg_attr(
28903    target_arch = "arm",
28904    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28905)]
28906pub fn vmla_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t {
28907    static_assert_uimm_bits!(LANE, 3);
28908    unsafe {
28909        vmla_s16(
28910            a,
28911            b,
28912            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28913        )
28914    }
28915}
28916#[doc = "Vector multiply accumulate with scalar"]
28917#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u16)"]
28918#[inline]
28919#[target_feature(enable = "neon")]
28920#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28921#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
28922#[cfg_attr(
28923    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28924    assert_instr(mla, LANE = 1)
28925)]
28926#[rustc_legacy_const_generics(3)]
28927#[cfg_attr(
28928    not(target_arch = "arm"),
28929    stable(feature = "neon_intrinsics", since = "1.59.0")
28930)]
28931#[cfg_attr(
28932    target_arch = "arm",
28933    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28934)]
28935pub fn vmla_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x8_t) -> uint16x4_t {
28936    static_assert_uimm_bits!(LANE, 3);
28937    unsafe {
28938        vmla_u16(
28939            a,
28940            b,
28941            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28942        )
28943    }
28944}
28945#[doc = "Vector multiply accumulate with scalar"]
28946#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s16)"]
28947#[inline]
28948#[target_feature(enable = "neon")]
28949#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28950#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
28951#[cfg_attr(
28952    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28953    assert_instr(mla, LANE = 1)
28954)]
28955#[rustc_legacy_const_generics(3)]
28956#[cfg_attr(
28957    not(target_arch = "arm"),
28958    stable(feature = "neon_intrinsics", since = "1.59.0")
28959)]
28960#[cfg_attr(
28961    target_arch = "arm",
28962    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28963)]
28964pub fn vmlaq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t {
28965    static_assert_uimm_bits!(LANE, 2);
28966    unsafe {
28967        vmlaq_s16(
28968            a,
28969            b,
28970            simd_shuffle!(
28971                c,
28972                c,
28973                [
28974                    LANE as u32,
28975                    LANE as u32,
28976                    LANE as u32,
28977                    LANE as u32,
28978                    LANE as u32,
28979                    LANE as u32,
28980                    LANE as u32,
28981                    LANE as u32
28982                ]
28983            ),
28984        )
28985    }
28986}
28987#[doc = "Vector multiply accumulate with scalar"]
28988#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u16)"]
28989#[inline]
28990#[target_feature(enable = "neon")]
28991#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28992#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
28993#[cfg_attr(
28994    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28995    assert_instr(mla, LANE = 1)
28996)]
28997#[rustc_legacy_const_generics(3)]
28998#[cfg_attr(
28999    not(target_arch = "arm"),
29000    stable(feature = "neon_intrinsics", since = "1.59.0")
29001)]
29002#[cfg_attr(
29003    target_arch = "arm",
29004    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29005)]
29006pub fn vmlaq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t {
29007    static_assert_uimm_bits!(LANE, 2);
29008    unsafe {
29009        vmlaq_u16(
29010            a,
29011            b,
29012            simd_shuffle!(
29013                c,
29014                c,
29015                [
29016                    LANE as u32,
29017                    LANE as u32,
29018                    LANE as u32,
29019                    LANE as u32,
29020                    LANE as u32,
29021                    LANE as u32,
29022                    LANE as u32,
29023                    LANE as u32
29024                ]
29025            ),
29026        )
29027    }
29028}
29029#[doc = "Vector multiply accumulate with scalar"]
29030#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s16)"]
29031#[inline]
29032#[target_feature(enable = "neon")]
29033#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29034#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
29035#[cfg_attr(
29036    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29037    assert_instr(mla, LANE = 1)
29038)]
29039#[rustc_legacy_const_generics(3)]
29040#[cfg_attr(
29041    not(target_arch = "arm"),
29042    stable(feature = "neon_intrinsics", since = "1.59.0")
29043)]
29044#[cfg_attr(
29045    target_arch = "arm",
29046    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29047)]
29048pub fn vmlaq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
29049    static_assert_uimm_bits!(LANE, 3);
29050    unsafe {
29051        vmlaq_s16(
29052            a,
29053            b,
29054            simd_shuffle!(
29055                c,
29056                c,
29057                [
29058                    LANE as u32,
29059                    LANE as u32,
29060                    LANE as u32,
29061                    LANE as u32,
29062                    LANE as u32,
29063                    LANE as u32,
29064                    LANE as u32,
29065                    LANE as u32
29066                ]
29067            ),
29068        )
29069    }
29070}
29071#[doc = "Vector multiply accumulate with scalar"]
29072#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u16)"]
29073#[inline]
29074#[target_feature(enable = "neon")]
29075#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29076#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
29077#[cfg_attr(
29078    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29079    assert_instr(mla, LANE = 1)
29080)]
29081#[rustc_legacy_const_generics(3)]
29082#[cfg_attr(
29083    not(target_arch = "arm"),
29084    stable(feature = "neon_intrinsics", since = "1.59.0")
29085)]
29086#[cfg_attr(
29087    target_arch = "arm",
29088    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29089)]
29090pub fn vmlaq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
29091    static_assert_uimm_bits!(LANE, 3);
29092    unsafe {
29093        vmlaq_u16(
29094            a,
29095            b,
29096            simd_shuffle!(
29097                c,
29098                c,
29099                [
29100                    LANE as u32,
29101                    LANE as u32,
29102                    LANE as u32,
29103                    LANE as u32,
29104                    LANE as u32,
29105                    LANE as u32,
29106                    LANE as u32,
29107                    LANE as u32
29108                ]
29109            ),
29110        )
29111    }
29112}
29113#[doc = "Vector multiply accumulate with scalar"]
29114#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s32)"]
29115#[inline]
29116#[target_feature(enable = "neon")]
29117#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29118#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29119#[cfg_attr(
29120    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29121    assert_instr(mla, LANE = 1)
29122)]
29123#[rustc_legacy_const_generics(3)]
29124#[cfg_attr(
29125    not(target_arch = "arm"),
29126    stable(feature = "neon_intrinsics", since = "1.59.0")
29127)]
29128#[cfg_attr(
29129    target_arch = "arm",
29130    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29131)]
29132pub fn vmla_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
29133    static_assert_uimm_bits!(LANE, 1);
29134    unsafe { vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29135}
29136#[doc = "Vector multiply accumulate with scalar"]
29137#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u32)"]
29138#[inline]
29139#[target_feature(enable = "neon")]
29140#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29141#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29142#[cfg_attr(
29143    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29144    assert_instr(mla, LANE = 1)
29145)]
29146#[rustc_legacy_const_generics(3)]
29147#[cfg_attr(
29148    not(target_arch = "arm"),
29149    stable(feature = "neon_intrinsics", since = "1.59.0")
29150)]
29151#[cfg_attr(
29152    target_arch = "arm",
29153    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29154)]
29155pub fn vmla_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
29156    static_assert_uimm_bits!(LANE, 1);
29157    unsafe { vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29158}
29159#[doc = "Vector multiply accumulate with scalar"]
29160#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s32)"]
29161#[inline]
29162#[target_feature(enable = "neon")]
29163#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29164#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29165#[cfg_attr(
29166    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29167    assert_instr(mla, LANE = 1)
29168)]
29169#[rustc_legacy_const_generics(3)]
29170#[cfg_attr(
29171    not(target_arch = "arm"),
29172    stable(feature = "neon_intrinsics", since = "1.59.0")
29173)]
29174#[cfg_attr(
29175    target_arch = "arm",
29176    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29177)]
29178pub fn vmla_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t {
29179    static_assert_uimm_bits!(LANE, 2);
29180    unsafe { vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29181}
29182#[doc = "Vector multiply accumulate with scalar"]
29183#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u32)"]
29184#[inline]
29185#[target_feature(enable = "neon")]
29186#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29187#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29188#[cfg_attr(
29189    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29190    assert_instr(mla, LANE = 1)
29191)]
29192#[rustc_legacy_const_generics(3)]
29193#[cfg_attr(
29194    not(target_arch = "arm"),
29195    stable(feature = "neon_intrinsics", since = "1.59.0")
29196)]
29197#[cfg_attr(
29198    target_arch = "arm",
29199    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29200)]
29201pub fn vmla_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t {
29202    static_assert_uimm_bits!(LANE, 2);
29203    unsafe { vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29204}
29205#[doc = "Vector multiply accumulate with scalar"]
29206#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s32)"]
29207#[inline]
29208#[target_feature(enable = "neon")]
29209#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29210#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29211#[cfg_attr(
29212    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29213    assert_instr(mla, LANE = 1)
29214)]
29215#[rustc_legacy_const_generics(3)]
29216#[cfg_attr(
29217    not(target_arch = "arm"),
29218    stable(feature = "neon_intrinsics", since = "1.59.0")
29219)]
29220#[cfg_attr(
29221    target_arch = "arm",
29222    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29223)]
29224pub fn vmlaq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t {
29225    static_assert_uimm_bits!(LANE, 1);
29226    unsafe {
29227        vmlaq_s32(
29228            a,
29229            b,
29230            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29231        )
29232    }
29233}
29234#[doc = "Vector multiply accumulate with scalar"]
29235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u32)"]
29236#[inline]
29237#[target_feature(enable = "neon")]
29238#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29239#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29240#[cfg_attr(
29241    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29242    assert_instr(mla, LANE = 1)
29243)]
29244#[rustc_legacy_const_generics(3)]
29245#[cfg_attr(
29246    not(target_arch = "arm"),
29247    stable(feature = "neon_intrinsics", since = "1.59.0")
29248)]
29249#[cfg_attr(
29250    target_arch = "arm",
29251    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29252)]
29253pub fn vmlaq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t {
29254    static_assert_uimm_bits!(LANE, 1);
29255    unsafe {
29256        vmlaq_u32(
29257            a,
29258            b,
29259            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29260        )
29261    }
29262}
29263#[doc = "Vector multiply accumulate with scalar"]
29264#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s32)"]
29265#[inline]
29266#[target_feature(enable = "neon")]
29267#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29268#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29269#[cfg_attr(
29270    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29271    assert_instr(mla, LANE = 1)
29272)]
29273#[rustc_legacy_const_generics(3)]
29274#[cfg_attr(
29275    not(target_arch = "arm"),
29276    stable(feature = "neon_intrinsics", since = "1.59.0")
29277)]
29278#[cfg_attr(
29279    target_arch = "arm",
29280    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29281)]
29282pub fn vmlaq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
29283    static_assert_uimm_bits!(LANE, 2);
29284    unsafe {
29285        vmlaq_s32(
29286            a,
29287            b,
29288            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29289        )
29290    }
29291}
29292#[doc = "Vector multiply accumulate with scalar"]
29293#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u32)"]
29294#[inline]
29295#[target_feature(enable = "neon")]
29296#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29297#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29298#[cfg_attr(
29299    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29300    assert_instr(mla, LANE = 1)
29301)]
29302#[rustc_legacy_const_generics(3)]
29303#[cfg_attr(
29304    not(target_arch = "arm"),
29305    stable(feature = "neon_intrinsics", since = "1.59.0")
29306)]
29307#[cfg_attr(
29308    target_arch = "arm",
29309    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29310)]
29311pub fn vmlaq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
29312    static_assert_uimm_bits!(LANE, 2);
29313    unsafe {
29314        vmlaq_u32(
29315            a,
29316            b,
29317            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29318        )
29319    }
29320}
29321#[doc = "Vector multiply accumulate with scalar"]
29322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_f32)"]
29323#[inline]
29324#[target_feature(enable = "neon")]
29325#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29326#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
29327#[cfg_attr(
29328    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29329    assert_instr(fmul)
29330)]
29331#[cfg_attr(
29332    not(target_arch = "arm"),
29333    stable(feature = "neon_intrinsics", since = "1.59.0")
29334)]
29335#[cfg_attr(
29336    target_arch = "arm",
29337    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29338)]
29339pub fn vmla_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
29340    vmla_f32(a, b, vdup_n_f32(c))
29341}
29342#[doc = "Vector multiply accumulate with scalar"]
29343#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_f32)"]
29344#[inline]
29345#[target_feature(enable = "neon")]
29346#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29347#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
29348#[cfg_attr(
29349    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29350    assert_instr(fmul)
29351)]
29352#[cfg_attr(
29353    not(target_arch = "arm"),
29354    stable(feature = "neon_intrinsics", since = "1.59.0")
29355)]
29356#[cfg_attr(
29357    target_arch = "arm",
29358    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29359)]
29360pub fn vmlaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
29361    vmlaq_f32(a, b, vdupq_n_f32(c))
29362}
29363#[doc = "Vector multiply accumulate with scalar"]
29364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s16)"]
29365#[inline]
29366#[target_feature(enable = "neon")]
29367#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29368#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29369#[cfg_attr(
29370    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29371    assert_instr(mla)
29372)]
29373#[cfg_attr(
29374    not(target_arch = "arm"),
29375    stable(feature = "neon_intrinsics", since = "1.59.0")
29376)]
29377#[cfg_attr(
29378    target_arch = "arm",
29379    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29380)]
29381pub fn vmla_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t {
29382    vmla_s16(a, b, vdup_n_s16(c))
29383}
29384#[doc = "Vector multiply accumulate with scalar"]
29385#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s16)"]
29386#[inline]
29387#[target_feature(enable = "neon")]
29388#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29389#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29390#[cfg_attr(
29391    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29392    assert_instr(mla)
29393)]
29394#[cfg_attr(
29395    not(target_arch = "arm"),
29396    stable(feature = "neon_intrinsics", since = "1.59.0")
29397)]
29398#[cfg_attr(
29399    target_arch = "arm",
29400    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29401)]
29402pub fn vmlaq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t {
29403    vmlaq_s16(a, b, vdupq_n_s16(c))
29404}
29405#[doc = "Vector multiply accumulate with scalar"]
29406#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u16)"]
29407#[inline]
29408#[target_feature(enable = "neon")]
29409#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29410#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29411#[cfg_attr(
29412    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29413    assert_instr(mla)
29414)]
29415#[cfg_attr(
29416    not(target_arch = "arm"),
29417    stable(feature = "neon_intrinsics", since = "1.59.0")
29418)]
29419#[cfg_attr(
29420    target_arch = "arm",
29421    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29422)]
29423pub fn vmla_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t {
29424    vmla_u16(a, b, vdup_n_u16(c))
29425}
29426#[doc = "Vector multiply accumulate with scalar"]
29427#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u16)"]
29428#[inline]
29429#[target_feature(enable = "neon")]
29430#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29431#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29432#[cfg_attr(
29433    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29434    assert_instr(mla)
29435)]
29436#[cfg_attr(
29437    not(target_arch = "arm"),
29438    stable(feature = "neon_intrinsics", since = "1.59.0")
29439)]
29440#[cfg_attr(
29441    target_arch = "arm",
29442    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29443)]
29444pub fn vmlaq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t {
29445    vmlaq_u16(a, b, vdupq_n_u16(c))
29446}
29447#[doc = "Vector multiply accumulate with scalar"]
29448#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s32)"]
29449#[inline]
29450#[target_feature(enable = "neon")]
29451#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29452#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29453#[cfg_attr(
29454    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29455    assert_instr(mla)
29456)]
29457#[cfg_attr(
29458    not(target_arch = "arm"),
29459    stable(feature = "neon_intrinsics", since = "1.59.0")
29460)]
29461#[cfg_attr(
29462    target_arch = "arm",
29463    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29464)]
29465pub fn vmla_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t {
29466    vmla_s32(a, b, vdup_n_s32(c))
29467}
29468#[doc = "Vector multiply accumulate with scalar"]
29469#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s32)"]
29470#[inline]
29471#[target_feature(enable = "neon")]
29472#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29473#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29474#[cfg_attr(
29475    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29476    assert_instr(mla)
29477)]
29478#[cfg_attr(
29479    not(target_arch = "arm"),
29480    stable(feature = "neon_intrinsics", since = "1.59.0")
29481)]
29482#[cfg_attr(
29483    target_arch = "arm",
29484    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29485)]
29486pub fn vmlaq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t {
29487    vmlaq_s32(a, b, vdupq_n_s32(c))
29488}
29489#[doc = "Vector multiply accumulate with scalar"]
29490#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u32)"]
29491#[inline]
29492#[target_feature(enable = "neon")]
29493#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29494#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29495#[cfg_attr(
29496    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29497    assert_instr(mla)
29498)]
29499#[cfg_attr(
29500    not(target_arch = "arm"),
29501    stable(feature = "neon_intrinsics", since = "1.59.0")
29502)]
29503#[cfg_attr(
29504    target_arch = "arm",
29505    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29506)]
29507pub fn vmla_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t {
29508    vmla_u32(a, b, vdup_n_u32(c))
29509}
29510#[doc = "Vector multiply accumulate with scalar"]
29511#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u32)"]
29512#[inline]
29513#[target_feature(enable = "neon")]
29514#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29515#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29516#[cfg_attr(
29517    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29518    assert_instr(mla)
29519)]
29520#[cfg_attr(
29521    not(target_arch = "arm"),
29522    stable(feature = "neon_intrinsics", since = "1.59.0")
29523)]
29524#[cfg_attr(
29525    target_arch = "arm",
29526    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29527)]
29528pub fn vmlaq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t {
29529    vmlaq_u32(a, b, vdupq_n_u32(c))
29530}
29531#[doc = "Multiply-add to accumulator"]
29532#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s8)"]
29533#[inline]
29534#[target_feature(enable = "neon")]
29535#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29536#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
29537#[cfg_attr(
29538    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29539    assert_instr(mla)
29540)]
29541#[cfg_attr(
29542    not(target_arch = "arm"),
29543    stable(feature = "neon_intrinsics", since = "1.59.0")
29544)]
29545#[cfg_attr(
29546    target_arch = "arm",
29547    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29548)]
29549pub fn vmla_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
29550    unsafe { simd_add(a, simd_mul(b, c)) }
29551}
29552#[doc = "Multiply-add to accumulator"]
29553#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s8)"]
29554#[inline]
29555#[target_feature(enable = "neon")]
29556#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29557#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
29558#[cfg_attr(
29559    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29560    assert_instr(mla)
29561)]
29562#[cfg_attr(
29563    not(target_arch = "arm"),
29564    stable(feature = "neon_intrinsics", since = "1.59.0")
29565)]
29566#[cfg_attr(
29567    target_arch = "arm",
29568    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29569)]
29570pub fn vmlaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
29571    unsafe { simd_add(a, simd_mul(b, c)) }
29572}
29573#[doc = "Multiply-add to accumulator"]
29574#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s16)"]
29575#[inline]
29576#[target_feature(enable = "neon")]
29577#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29578#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29579#[cfg_attr(
29580    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29581    assert_instr(mla)
29582)]
29583#[cfg_attr(
29584    not(target_arch = "arm"),
29585    stable(feature = "neon_intrinsics", since = "1.59.0")
29586)]
29587#[cfg_attr(
29588    target_arch = "arm",
29589    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29590)]
29591pub fn vmla_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
29592    unsafe { simd_add(a, simd_mul(b, c)) }
29593}
29594#[doc = "Multiply-add to accumulator"]
29595#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s16)"]
29596#[inline]
29597#[target_feature(enable = "neon")]
29598#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29599#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29600#[cfg_attr(
29601    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29602    assert_instr(mla)
29603)]
29604#[cfg_attr(
29605    not(target_arch = "arm"),
29606    stable(feature = "neon_intrinsics", since = "1.59.0")
29607)]
29608#[cfg_attr(
29609    target_arch = "arm",
29610    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29611)]
29612pub fn vmlaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
29613    unsafe { simd_add(a, simd_mul(b, c)) }
29614}
29615#[doc = "Multiply-add to accumulator"]
29616#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s32)"]
29617#[inline]
29618#[target_feature(enable = "neon")]
29619#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29620#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29621#[cfg_attr(
29622    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29623    assert_instr(mla)
29624)]
29625#[cfg_attr(
29626    not(target_arch = "arm"),
29627    stable(feature = "neon_intrinsics", since = "1.59.0")
29628)]
29629#[cfg_attr(
29630    target_arch = "arm",
29631    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29632)]
29633pub fn vmla_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
29634    unsafe { simd_add(a, simd_mul(b, c)) }
29635}
29636#[doc = "Multiply-add to accumulator"]
29637#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s32)"]
29638#[inline]
29639#[target_feature(enable = "neon")]
29640#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29641#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29642#[cfg_attr(
29643    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29644    assert_instr(mla)
29645)]
29646#[cfg_attr(
29647    not(target_arch = "arm"),
29648    stable(feature = "neon_intrinsics", since = "1.59.0")
29649)]
29650#[cfg_attr(
29651    target_arch = "arm",
29652    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29653)]
29654pub fn vmlaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
29655    unsafe { simd_add(a, simd_mul(b, c)) }
29656}
29657#[doc = "Multiply-add to accumulator"]
29658#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u8)"]
29659#[inline]
29660#[target_feature(enable = "neon")]
29661#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29662#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
29663#[cfg_attr(
29664    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29665    assert_instr(mla)
29666)]
29667#[cfg_attr(
29668    not(target_arch = "arm"),
29669    stable(feature = "neon_intrinsics", since = "1.59.0")
29670)]
29671#[cfg_attr(
29672    target_arch = "arm",
29673    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29674)]
29675pub fn vmla_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
29676    unsafe { simd_add(a, simd_mul(b, c)) }
29677}
29678#[doc = "Multiply-add to accumulator"]
29679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u8)"]
29680#[inline]
29681#[target_feature(enable = "neon")]
29682#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29683#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
29684#[cfg_attr(
29685    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29686    assert_instr(mla)
29687)]
29688#[cfg_attr(
29689    not(target_arch = "arm"),
29690    stable(feature = "neon_intrinsics", since = "1.59.0")
29691)]
29692#[cfg_attr(
29693    target_arch = "arm",
29694    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29695)]
29696pub fn vmlaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
29697    unsafe { simd_add(a, simd_mul(b, c)) }
29698}
29699#[doc = "Multiply-add to accumulator"]
29700#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u16)"]
29701#[inline]
29702#[target_feature(enable = "neon")]
29703#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29704#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29705#[cfg_attr(
29706    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29707    assert_instr(mla)
29708)]
29709#[cfg_attr(
29710    not(target_arch = "arm"),
29711    stable(feature = "neon_intrinsics", since = "1.59.0")
29712)]
29713#[cfg_attr(
29714    target_arch = "arm",
29715    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29716)]
29717pub fn vmla_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
29718    unsafe { simd_add(a, simd_mul(b, c)) }
29719}
29720#[doc = "Multiply-add to accumulator"]
29721#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u16)"]
29722#[inline]
29723#[target_feature(enable = "neon")]
29724#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29725#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29726#[cfg_attr(
29727    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29728    assert_instr(mla)
29729)]
29730#[cfg_attr(
29731    not(target_arch = "arm"),
29732    stable(feature = "neon_intrinsics", since = "1.59.0")
29733)]
29734#[cfg_attr(
29735    target_arch = "arm",
29736    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29737)]
29738pub fn vmlaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
29739    unsafe { simd_add(a, simd_mul(b, c)) }
29740}
29741#[doc = "Multiply-add to accumulator"]
29742#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u32)"]
29743#[inline]
29744#[target_feature(enable = "neon")]
29745#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29746#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29747#[cfg_attr(
29748    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29749    assert_instr(mla)
29750)]
29751#[cfg_attr(
29752    not(target_arch = "arm"),
29753    stable(feature = "neon_intrinsics", since = "1.59.0")
29754)]
29755#[cfg_attr(
29756    target_arch = "arm",
29757    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29758)]
29759pub fn vmla_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
29760    unsafe { simd_add(a, simd_mul(b, c)) }
29761}
29762#[doc = "Multiply-add to accumulator"]
29763#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u32)"]
29764#[inline]
29765#[target_feature(enable = "neon")]
29766#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29767#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29768#[cfg_attr(
29769    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29770    assert_instr(mla)
29771)]
29772#[cfg_attr(
29773    not(target_arch = "arm"),
29774    stable(feature = "neon_intrinsics", since = "1.59.0")
29775)]
29776#[cfg_attr(
29777    target_arch = "arm",
29778    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29779)]
29780pub fn vmlaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
29781    unsafe { simd_add(a, simd_mul(b, c)) }
29782}
29783#[doc = "Vector widening multiply accumulate with scalar"]
29784#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s16)"]
29785#[inline]
29786#[target_feature(enable = "neon")]
29787#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29788#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))]
29789#[cfg_attr(
29790    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29791    assert_instr(smlal, LANE = 1)
29792)]
29793#[rustc_legacy_const_generics(3)]
29794#[cfg_attr(
29795    not(target_arch = "arm"),
29796    stable(feature = "neon_intrinsics", since = "1.59.0")
29797)]
29798#[cfg_attr(
29799    target_arch = "arm",
29800    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29801)]
29802pub fn vmlal_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
29803    static_assert_uimm_bits!(LANE, 2);
29804    unsafe {
29805        vmlal_s16(
29806            a,
29807            b,
29808            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29809        )
29810    }
29811}
29812#[doc = "Vector widening multiply accumulate with scalar"]
29813#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s16)"]
29814#[inline]
29815#[target_feature(enable = "neon")]
29816#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29817#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))]
29818#[cfg_attr(
29819    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29820    assert_instr(smlal, LANE = 1)
29821)]
29822#[rustc_legacy_const_generics(3)]
29823#[cfg_attr(
29824    not(target_arch = "arm"),
29825    stable(feature = "neon_intrinsics", since = "1.59.0")
29826)]
29827#[cfg_attr(
29828    target_arch = "arm",
29829    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29830)]
29831pub fn vmlal_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t {
29832    static_assert_uimm_bits!(LANE, 3);
29833    unsafe {
29834        vmlal_s16(
29835            a,
29836            b,
29837            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29838        )
29839    }
29840}
29841#[doc = "Vector widening multiply accumulate with scalar"]
29842#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s32)"]
29843#[inline]
29844#[target_feature(enable = "neon")]
29845#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29846#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))]
29847#[cfg_attr(
29848    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29849    assert_instr(smlal, LANE = 1)
29850)]
29851#[rustc_legacy_const_generics(3)]
29852#[cfg_attr(
29853    not(target_arch = "arm"),
29854    stable(feature = "neon_intrinsics", since = "1.59.0")
29855)]
29856#[cfg_attr(
29857    target_arch = "arm",
29858    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29859)]
29860pub fn vmlal_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
29861    static_assert_uimm_bits!(LANE, 1);
29862    unsafe { vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29863}
29864#[doc = "Vector widening multiply accumulate with scalar"]
29865#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s32)"]
29866#[inline]
29867#[target_feature(enable = "neon")]
29868#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29869#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))]
29870#[cfg_attr(
29871    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29872    assert_instr(smlal, LANE = 1)
29873)]
29874#[rustc_legacy_const_generics(3)]
29875#[cfg_attr(
29876    not(target_arch = "arm"),
29877    stable(feature = "neon_intrinsics", since = "1.59.0")
29878)]
29879#[cfg_attr(
29880    target_arch = "arm",
29881    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29882)]
29883pub fn vmlal_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t {
29884    static_assert_uimm_bits!(LANE, 2);
29885    unsafe { vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29886}
29887#[doc = "Vector widening multiply accumulate with scalar"]
29888#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u16)"]
29889#[inline]
29890#[target_feature(enable = "neon")]
29891#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29892#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))]
29893#[cfg_attr(
29894    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29895    assert_instr(umlal, LANE = 1)
29896)]
29897#[rustc_legacy_const_generics(3)]
29898#[cfg_attr(
29899    not(target_arch = "arm"),
29900    stable(feature = "neon_intrinsics", since = "1.59.0")
29901)]
29902#[cfg_attr(
29903    target_arch = "arm",
29904    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29905)]
29906pub fn vmlal_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
29907    static_assert_uimm_bits!(LANE, 2);
29908    unsafe {
29909        vmlal_u16(
29910            a,
29911            b,
29912            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29913        )
29914    }
29915}
29916#[doc = "Vector widening multiply accumulate with scalar"]
29917#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u16)"]
29918#[inline]
29919#[target_feature(enable = "neon")]
29920#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29921#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))]
29922#[cfg_attr(
29923    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29924    assert_instr(umlal, LANE = 1)
29925)]
29926#[rustc_legacy_const_generics(3)]
29927#[cfg_attr(
29928    not(target_arch = "arm"),
29929    stable(feature = "neon_intrinsics", since = "1.59.0")
29930)]
29931#[cfg_attr(
29932    target_arch = "arm",
29933    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29934)]
29935pub fn vmlal_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x8_t) -> uint32x4_t {
29936    static_assert_uimm_bits!(LANE, 3);
29937    unsafe {
29938        vmlal_u16(
29939            a,
29940            b,
29941            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29942        )
29943    }
29944}
29945#[doc = "Vector widening multiply accumulate with scalar"]
29946#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u32)"]
29947#[inline]
29948#[target_feature(enable = "neon")]
29949#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29950#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))]
29951#[cfg_attr(
29952    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29953    assert_instr(umlal, LANE = 1)
29954)]
29955#[rustc_legacy_const_generics(3)]
29956#[cfg_attr(
29957    not(target_arch = "arm"),
29958    stable(feature = "neon_intrinsics", since = "1.59.0")
29959)]
29960#[cfg_attr(
29961    target_arch = "arm",
29962    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29963)]
29964pub fn vmlal_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
29965    static_assert_uimm_bits!(LANE, 1);
29966    unsafe { vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29967}
29968#[doc = "Vector widening multiply accumulate with scalar"]
29969#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u32)"]
29970#[inline]
29971#[target_feature(enable = "neon")]
29972#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29973#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))]
29974#[cfg_attr(
29975    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29976    assert_instr(umlal, LANE = 1)
29977)]
29978#[rustc_legacy_const_generics(3)]
29979#[cfg_attr(
29980    not(target_arch = "arm"),
29981    stable(feature = "neon_intrinsics", since = "1.59.0")
29982)]
29983#[cfg_attr(
29984    target_arch = "arm",
29985    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29986)]
29987pub fn vmlal_laneq_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x4_t) -> uint64x2_t {
29988    static_assert_uimm_bits!(LANE, 2);
29989    unsafe { vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29990}
29991#[doc = "Vector widening multiply accumulate with scalar"]
29992#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s16)"]
29993#[inline]
29994#[target_feature(enable = "neon")]
29995#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29996#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))]
29997#[cfg_attr(
29998    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29999    assert_instr(smlal)
30000)]
30001#[cfg_attr(
30002    not(target_arch = "arm"),
30003    stable(feature = "neon_intrinsics", since = "1.59.0")
30004)]
30005#[cfg_attr(
30006    target_arch = "arm",
30007    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30008)]
30009pub fn vmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
30010    vmlal_s16(a, b, vdup_n_s16(c))
30011}
30012#[doc = "Vector widening multiply accumulate with scalar"]
30013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s32)"]
30014#[inline]
30015#[target_feature(enable = "neon")]
30016#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30017#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))]
30018#[cfg_attr(
30019    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30020    assert_instr(smlal)
30021)]
30022#[cfg_attr(
30023    not(target_arch = "arm"),
30024    stable(feature = "neon_intrinsics", since = "1.59.0")
30025)]
30026#[cfg_attr(
30027    target_arch = "arm",
30028    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30029)]
30030pub fn vmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
30031    vmlal_s32(a, b, vdup_n_s32(c))
30032}
30033#[doc = "Vector widening multiply accumulate with scalar"]
30034#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u16)"]
30035#[inline]
30036#[target_feature(enable = "neon")]
30037#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30038#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))]
30039#[cfg_attr(
30040    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30041    assert_instr(umlal)
30042)]
30043#[cfg_attr(
30044    not(target_arch = "arm"),
30045    stable(feature = "neon_intrinsics", since = "1.59.0")
30046)]
30047#[cfg_attr(
30048    target_arch = "arm",
30049    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30050)]
30051pub fn vmlal_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t {
30052    vmlal_u16(a, b, vdup_n_u16(c))
30053}
30054#[doc = "Vector widening multiply accumulate with scalar"]
30055#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u32)"]
30056#[inline]
30057#[target_feature(enable = "neon")]
30058#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30059#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))]
30060#[cfg_attr(
30061    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30062    assert_instr(umlal)
30063)]
30064#[cfg_attr(
30065    not(target_arch = "arm"),
30066    stable(feature = "neon_intrinsics", since = "1.59.0")
30067)]
30068#[cfg_attr(
30069    target_arch = "arm",
30070    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30071)]
30072pub fn vmlal_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t {
30073    vmlal_u32(a, b, vdup_n_u32(c))
30074}
30075#[doc = "Signed multiply-add long"]
30076#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s8)"]
30077#[inline]
30078#[target_feature(enable = "neon")]
30079#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30080#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s8"))]
30081#[cfg_attr(
30082    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30083    assert_instr(smlal)
30084)]
30085#[cfg_attr(
30086    not(target_arch = "arm"),
30087    stable(feature = "neon_intrinsics", since = "1.59.0")
30088)]
30089#[cfg_attr(
30090    target_arch = "arm",
30091    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30092)]
30093pub fn vmlal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
30094    unsafe { simd_add(a, vmull_s8(b, c)) }
30095}
30096#[doc = "Signed multiply-add long"]
30097#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s16)"]
30098#[inline]
30099#[target_feature(enable = "neon")]
30100#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30101#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))]
30102#[cfg_attr(
30103    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30104    assert_instr(smlal)
30105)]
30106#[cfg_attr(
30107    not(target_arch = "arm"),
30108    stable(feature = "neon_intrinsics", since = "1.59.0")
30109)]
30110#[cfg_attr(
30111    target_arch = "arm",
30112    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30113)]
30114pub fn vmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
30115    unsafe { simd_add(a, vmull_s16(b, c)) }
30116}
30117#[doc = "Signed multiply-add long"]
30118#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s32)"]
30119#[inline]
30120#[target_feature(enable = "neon")]
30121#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30122#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))]
30123#[cfg_attr(
30124    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30125    assert_instr(smlal)
30126)]
30127#[cfg_attr(
30128    not(target_arch = "arm"),
30129    stable(feature = "neon_intrinsics", since = "1.59.0")
30130)]
30131#[cfg_attr(
30132    target_arch = "arm",
30133    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30134)]
30135pub fn vmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
30136    unsafe { simd_add(a, vmull_s32(b, c)) }
30137}
30138#[doc = "Unsigned multiply-add long"]
30139#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u8)"]
30140#[inline]
30141#[target_feature(enable = "neon")]
30142#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30143#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u8"))]
30144#[cfg_attr(
30145    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30146    assert_instr(umlal)
30147)]
30148#[cfg_attr(
30149    not(target_arch = "arm"),
30150    stable(feature = "neon_intrinsics", since = "1.59.0")
30151)]
30152#[cfg_attr(
30153    target_arch = "arm",
30154    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30155)]
30156pub fn vmlal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
30157    unsafe { simd_add(a, vmull_u8(b, c)) }
30158}
30159#[doc = "Unsigned multiply-add long"]
30160#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u16)"]
30161#[inline]
30162#[target_feature(enable = "neon")]
30163#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30164#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))]
30165#[cfg_attr(
30166    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30167    assert_instr(umlal)
30168)]
30169#[cfg_attr(
30170    not(target_arch = "arm"),
30171    stable(feature = "neon_intrinsics", since = "1.59.0")
30172)]
30173#[cfg_attr(
30174    target_arch = "arm",
30175    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30176)]
30177pub fn vmlal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
30178    unsafe { simd_add(a, vmull_u16(b, c)) }
30179}
30180#[doc = "Unsigned multiply-add long"]
30181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u32)"]
30182#[inline]
30183#[target_feature(enable = "neon")]
30184#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30185#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))]
30186#[cfg_attr(
30187    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30188    assert_instr(umlal)
30189)]
30190#[cfg_attr(
30191    not(target_arch = "arm"),
30192    stable(feature = "neon_intrinsics", since = "1.59.0")
30193)]
30194#[cfg_attr(
30195    target_arch = "arm",
30196    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30197)]
30198pub fn vmlal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
30199    unsafe { simd_add(a, vmull_u32(b, c)) }
30200}
30201#[doc = "Floating-point multiply-subtract from accumulator"]
30202#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f32)"]
30203#[inline]
30204#[target_feature(enable = "neon")]
30205#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30206#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
30207#[cfg_attr(
30208    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30209    assert_instr(fmul)
30210)]
30211#[cfg_attr(
30212    not(target_arch = "arm"),
30213    stable(feature = "neon_intrinsics", since = "1.59.0")
30214)]
30215#[cfg_attr(
30216    target_arch = "arm",
30217    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30218)]
30219pub fn vmls_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
30220    unsafe { simd_sub(a, simd_mul(b, c)) }
30221}
30222#[doc = "Floating-point multiply-subtract from accumulator"]
30223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f32)"]
30224#[inline]
30225#[target_feature(enable = "neon")]
30226#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30227#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
30228#[cfg_attr(
30229    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30230    assert_instr(fmul)
30231)]
30232#[cfg_attr(
30233    not(target_arch = "arm"),
30234    stable(feature = "neon_intrinsics", since = "1.59.0")
30235)]
30236#[cfg_attr(
30237    target_arch = "arm",
30238    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30239)]
30240pub fn vmlsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
30241    unsafe { simd_sub(a, simd_mul(b, c)) }
30242}
30243#[doc = "Vector multiply subtract with scalar"]
30244#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_f32)"]
30245#[inline]
30246#[target_feature(enable = "neon")]
30247#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30248#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
30249#[cfg_attr(
30250    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30251    assert_instr(fmul, LANE = 1)
30252)]
30253#[rustc_legacy_const_generics(3)]
30254#[cfg_attr(
30255    not(target_arch = "arm"),
30256    stable(feature = "neon_intrinsics", since = "1.59.0")
30257)]
30258#[cfg_attr(
30259    target_arch = "arm",
30260    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30261)]
30262pub fn vmls_lane_f32<const LANE: i32>(
30263    a: float32x2_t,
30264    b: float32x2_t,
30265    c: float32x2_t,
30266) -> float32x2_t {
30267    static_assert_uimm_bits!(LANE, 1);
30268    unsafe { vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30269}
30270#[doc = "Vector multiply subtract with scalar"]
30271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_f32)"]
30272#[inline]
30273#[target_feature(enable = "neon")]
30274#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30275#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
30276#[cfg_attr(
30277    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30278    assert_instr(fmul, LANE = 1)
30279)]
30280#[rustc_legacy_const_generics(3)]
30281#[cfg_attr(
30282    not(target_arch = "arm"),
30283    stable(feature = "neon_intrinsics", since = "1.59.0")
30284)]
30285#[cfg_attr(
30286    target_arch = "arm",
30287    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30288)]
30289pub fn vmls_laneq_f32<const LANE: i32>(
30290    a: float32x2_t,
30291    b: float32x2_t,
30292    c: float32x4_t,
30293) -> float32x2_t {
30294    static_assert_uimm_bits!(LANE, 2);
30295    unsafe { vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30296}
30297#[doc = "Vector multiply subtract with scalar"]
30298#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_f32)"]
30299#[inline]
30300#[target_feature(enable = "neon")]
30301#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30302#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
30303#[cfg_attr(
30304    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30305    assert_instr(fmul, LANE = 1)
30306)]
30307#[rustc_legacy_const_generics(3)]
30308#[cfg_attr(
30309    not(target_arch = "arm"),
30310    stable(feature = "neon_intrinsics", since = "1.59.0")
30311)]
30312#[cfg_attr(
30313    target_arch = "arm",
30314    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30315)]
30316pub fn vmlsq_lane_f32<const LANE: i32>(
30317    a: float32x4_t,
30318    b: float32x4_t,
30319    c: float32x2_t,
30320) -> float32x4_t {
30321    static_assert_uimm_bits!(LANE, 1);
30322    unsafe {
30323        vmlsq_f32(
30324            a,
30325            b,
30326            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30327        )
30328    }
30329}
30330#[doc = "Vector multiply subtract with scalar"]
30331#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_f32)"]
30332#[inline]
30333#[target_feature(enable = "neon")]
30334#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30335#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
30336#[cfg_attr(
30337    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30338    assert_instr(fmul, LANE = 1)
30339)]
30340#[rustc_legacy_const_generics(3)]
30341#[cfg_attr(
30342    not(target_arch = "arm"),
30343    stable(feature = "neon_intrinsics", since = "1.59.0")
30344)]
30345#[cfg_attr(
30346    target_arch = "arm",
30347    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30348)]
30349pub fn vmlsq_laneq_f32<const LANE: i32>(
30350    a: float32x4_t,
30351    b: float32x4_t,
30352    c: float32x4_t,
30353) -> float32x4_t {
30354    static_assert_uimm_bits!(LANE, 2);
30355    unsafe {
30356        vmlsq_f32(
30357            a,
30358            b,
30359            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30360        )
30361    }
30362}
30363#[doc = "Vector multiply subtract with scalar"]
30364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s16)"]
30365#[inline]
30366#[target_feature(enable = "neon")]
30367#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30368#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30369#[cfg_attr(
30370    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30371    assert_instr(mls, LANE = 1)
30372)]
30373#[rustc_legacy_const_generics(3)]
30374#[cfg_attr(
30375    not(target_arch = "arm"),
30376    stable(feature = "neon_intrinsics", since = "1.59.0")
30377)]
30378#[cfg_attr(
30379    target_arch = "arm",
30380    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30381)]
30382pub fn vmls_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
30383    static_assert_uimm_bits!(LANE, 2);
30384    unsafe {
30385        vmls_s16(
30386            a,
30387            b,
30388            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30389        )
30390    }
30391}
30392#[doc = "Vector multiply subtract with scalar"]
30393#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u16)"]
30394#[inline]
30395#[target_feature(enable = "neon")]
30396#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30397#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30398#[cfg_attr(
30399    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30400    assert_instr(mls, LANE = 1)
30401)]
30402#[rustc_legacy_const_generics(3)]
30403#[cfg_attr(
30404    not(target_arch = "arm"),
30405    stable(feature = "neon_intrinsics", since = "1.59.0")
30406)]
30407#[cfg_attr(
30408    target_arch = "arm",
30409    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30410)]
30411pub fn vmls_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
30412    static_assert_uimm_bits!(LANE, 2);
30413    unsafe {
30414        vmls_u16(
30415            a,
30416            b,
30417            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30418        )
30419    }
30420}
30421#[doc = "Vector multiply subtract with scalar"]
30422#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s16)"]
30423#[inline]
30424#[target_feature(enable = "neon")]
30425#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30426#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30427#[cfg_attr(
30428    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30429    assert_instr(mls, LANE = 1)
30430)]
30431#[rustc_legacy_const_generics(3)]
30432#[cfg_attr(
30433    not(target_arch = "arm"),
30434    stable(feature = "neon_intrinsics", since = "1.59.0")
30435)]
30436#[cfg_attr(
30437    target_arch = "arm",
30438    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30439)]
30440pub fn vmls_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t {
30441    static_assert_uimm_bits!(LANE, 3);
30442    unsafe {
30443        vmls_s16(
30444            a,
30445            b,
30446            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30447        )
30448    }
30449}
30450#[doc = "Vector multiply subtract with scalar"]
30451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u16)"]
30452#[inline]
30453#[target_feature(enable = "neon")]
30454#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30455#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30456#[cfg_attr(
30457    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30458    assert_instr(mls, LANE = 1)
30459)]
30460#[rustc_legacy_const_generics(3)]
30461#[cfg_attr(
30462    not(target_arch = "arm"),
30463    stable(feature = "neon_intrinsics", since = "1.59.0")
30464)]
30465#[cfg_attr(
30466    target_arch = "arm",
30467    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30468)]
30469pub fn vmls_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x8_t) -> uint16x4_t {
30470    static_assert_uimm_bits!(LANE, 3);
30471    unsafe {
30472        vmls_u16(
30473            a,
30474            b,
30475            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30476        )
30477    }
30478}
30479#[doc = "Vector multiply subtract with scalar"]
30480#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s16)"]
30481#[inline]
30482#[target_feature(enable = "neon")]
30483#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30484#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30485#[cfg_attr(
30486    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30487    assert_instr(mls, LANE = 1)
30488)]
30489#[rustc_legacy_const_generics(3)]
30490#[cfg_attr(
30491    not(target_arch = "arm"),
30492    stable(feature = "neon_intrinsics", since = "1.59.0")
30493)]
30494#[cfg_attr(
30495    target_arch = "arm",
30496    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30497)]
30498pub fn vmlsq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t {
30499    static_assert_uimm_bits!(LANE, 2);
30500    unsafe {
30501        vmlsq_s16(
30502            a,
30503            b,
30504            simd_shuffle!(
30505                c,
30506                c,
30507                [
30508                    LANE as u32,
30509                    LANE as u32,
30510                    LANE as u32,
30511                    LANE as u32,
30512                    LANE as u32,
30513                    LANE as u32,
30514                    LANE as u32,
30515                    LANE as u32
30516                ]
30517            ),
30518        )
30519    }
30520}
30521#[doc = "Vector multiply subtract with scalar"]
30522#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u16)"]
30523#[inline]
30524#[target_feature(enable = "neon")]
30525#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30526#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30527#[cfg_attr(
30528    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30529    assert_instr(mls, LANE = 1)
30530)]
30531#[rustc_legacy_const_generics(3)]
30532#[cfg_attr(
30533    not(target_arch = "arm"),
30534    stable(feature = "neon_intrinsics", since = "1.59.0")
30535)]
30536#[cfg_attr(
30537    target_arch = "arm",
30538    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30539)]
30540pub fn vmlsq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t {
30541    static_assert_uimm_bits!(LANE, 2);
30542    unsafe {
30543        vmlsq_u16(
30544            a,
30545            b,
30546            simd_shuffle!(
30547                c,
30548                c,
30549                [
30550                    LANE as u32,
30551                    LANE as u32,
30552                    LANE as u32,
30553                    LANE as u32,
30554                    LANE as u32,
30555                    LANE as u32,
30556                    LANE as u32,
30557                    LANE as u32
30558                ]
30559            ),
30560        )
30561    }
30562}
30563#[doc = "Vector multiply subtract with scalar"]
30564#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s16)"]
30565#[inline]
30566#[target_feature(enable = "neon")]
30567#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30568#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30569#[cfg_attr(
30570    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30571    assert_instr(mls, LANE = 1)
30572)]
30573#[rustc_legacy_const_generics(3)]
30574#[cfg_attr(
30575    not(target_arch = "arm"),
30576    stable(feature = "neon_intrinsics", since = "1.59.0")
30577)]
30578#[cfg_attr(
30579    target_arch = "arm",
30580    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30581)]
30582pub fn vmlsq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
30583    static_assert_uimm_bits!(LANE, 3);
30584    unsafe {
30585        vmlsq_s16(
30586            a,
30587            b,
30588            simd_shuffle!(
30589                c,
30590                c,
30591                [
30592                    LANE as u32,
30593                    LANE as u32,
30594                    LANE as u32,
30595                    LANE as u32,
30596                    LANE as u32,
30597                    LANE as u32,
30598                    LANE as u32,
30599                    LANE as u32
30600                ]
30601            ),
30602        )
30603    }
30604}
30605#[doc = "Vector multiply subtract with scalar"]
30606#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u16)"]
30607#[inline]
30608#[target_feature(enable = "neon")]
30609#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30610#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30611#[cfg_attr(
30612    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30613    assert_instr(mls, LANE = 1)
30614)]
30615#[rustc_legacy_const_generics(3)]
30616#[cfg_attr(
30617    not(target_arch = "arm"),
30618    stable(feature = "neon_intrinsics", since = "1.59.0")
30619)]
30620#[cfg_attr(
30621    target_arch = "arm",
30622    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30623)]
30624pub fn vmlsq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
30625    static_assert_uimm_bits!(LANE, 3);
30626    unsafe {
30627        vmlsq_u16(
30628            a,
30629            b,
30630            simd_shuffle!(
30631                c,
30632                c,
30633                [
30634                    LANE as u32,
30635                    LANE as u32,
30636                    LANE as u32,
30637                    LANE as u32,
30638                    LANE as u32,
30639                    LANE as u32,
30640                    LANE as u32,
30641                    LANE as u32
30642                ]
30643            ),
30644        )
30645    }
30646}
30647#[doc = "Vector multiply subtract with scalar"]
30648#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s32)"]
30649#[inline]
30650#[target_feature(enable = "neon")]
30651#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30652#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30653#[cfg_attr(
30654    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30655    assert_instr(mls, LANE = 1)
30656)]
30657#[rustc_legacy_const_generics(3)]
30658#[cfg_attr(
30659    not(target_arch = "arm"),
30660    stable(feature = "neon_intrinsics", since = "1.59.0")
30661)]
30662#[cfg_attr(
30663    target_arch = "arm",
30664    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30665)]
30666pub fn vmls_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
30667    static_assert_uimm_bits!(LANE, 1);
30668    unsafe { vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30669}
30670#[doc = "Vector multiply subtract with scalar"]
30671#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u32)"]
30672#[inline]
30673#[target_feature(enable = "neon")]
30674#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30675#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30676#[cfg_attr(
30677    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30678    assert_instr(mls, LANE = 1)
30679)]
30680#[rustc_legacy_const_generics(3)]
30681#[cfg_attr(
30682    not(target_arch = "arm"),
30683    stable(feature = "neon_intrinsics", since = "1.59.0")
30684)]
30685#[cfg_attr(
30686    target_arch = "arm",
30687    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30688)]
30689pub fn vmls_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
30690    static_assert_uimm_bits!(LANE, 1);
30691    unsafe { vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30692}
30693#[doc = "Vector multiply subtract with scalar"]
30694#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s32)"]
30695#[inline]
30696#[target_feature(enable = "neon")]
30697#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30698#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30699#[cfg_attr(
30700    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30701    assert_instr(mls, LANE = 1)
30702)]
30703#[rustc_legacy_const_generics(3)]
30704#[cfg_attr(
30705    not(target_arch = "arm"),
30706    stable(feature = "neon_intrinsics", since = "1.59.0")
30707)]
30708#[cfg_attr(
30709    target_arch = "arm",
30710    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30711)]
30712pub fn vmls_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t {
30713    static_assert_uimm_bits!(LANE, 2);
30714    unsafe { vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30715}
30716#[doc = "Vector multiply subtract with scalar"]
30717#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u32)"]
30718#[inline]
30719#[target_feature(enable = "neon")]
30720#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30721#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30722#[cfg_attr(
30723    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30724    assert_instr(mls, LANE = 1)
30725)]
30726#[rustc_legacy_const_generics(3)]
30727#[cfg_attr(
30728    not(target_arch = "arm"),
30729    stable(feature = "neon_intrinsics", since = "1.59.0")
30730)]
30731#[cfg_attr(
30732    target_arch = "arm",
30733    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30734)]
30735pub fn vmls_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t {
30736    static_assert_uimm_bits!(LANE, 2);
30737    unsafe { vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30738}
30739#[doc = "Vector multiply subtract with scalar"]
30740#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s32)"]
30741#[inline]
30742#[target_feature(enable = "neon")]
30743#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30744#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30745#[cfg_attr(
30746    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30747    assert_instr(mls, LANE = 1)
30748)]
30749#[rustc_legacy_const_generics(3)]
30750#[cfg_attr(
30751    not(target_arch = "arm"),
30752    stable(feature = "neon_intrinsics", since = "1.59.0")
30753)]
30754#[cfg_attr(
30755    target_arch = "arm",
30756    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30757)]
30758pub fn vmlsq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t {
30759    static_assert_uimm_bits!(LANE, 1);
30760    unsafe {
30761        vmlsq_s32(
30762            a,
30763            b,
30764            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30765        )
30766    }
30767}
30768#[doc = "Vector multiply subtract with scalar"]
30769#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u32)"]
30770#[inline]
30771#[target_feature(enable = "neon")]
30772#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30773#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30774#[cfg_attr(
30775    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30776    assert_instr(mls, LANE = 1)
30777)]
30778#[rustc_legacy_const_generics(3)]
30779#[cfg_attr(
30780    not(target_arch = "arm"),
30781    stable(feature = "neon_intrinsics", since = "1.59.0")
30782)]
30783#[cfg_attr(
30784    target_arch = "arm",
30785    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30786)]
30787pub fn vmlsq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t {
30788    static_assert_uimm_bits!(LANE, 1);
30789    unsafe {
30790        vmlsq_u32(
30791            a,
30792            b,
30793            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30794        )
30795    }
30796}
30797#[doc = "Vector multiply subtract with scalar"]
30798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s32)"]
30799#[inline]
30800#[target_feature(enable = "neon")]
30801#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30802#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30803#[cfg_attr(
30804    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30805    assert_instr(mls, LANE = 1)
30806)]
30807#[rustc_legacy_const_generics(3)]
30808#[cfg_attr(
30809    not(target_arch = "arm"),
30810    stable(feature = "neon_intrinsics", since = "1.59.0")
30811)]
30812#[cfg_attr(
30813    target_arch = "arm",
30814    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30815)]
30816pub fn vmlsq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
30817    static_assert_uimm_bits!(LANE, 2);
30818    unsafe {
30819        vmlsq_s32(
30820            a,
30821            b,
30822            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30823        )
30824    }
30825}
30826#[doc = "Vector multiply subtract with scalar"]
30827#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u32)"]
30828#[inline]
30829#[target_feature(enable = "neon")]
30830#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30831#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30832#[cfg_attr(
30833    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30834    assert_instr(mls, LANE = 1)
30835)]
30836#[rustc_legacy_const_generics(3)]
30837#[cfg_attr(
30838    not(target_arch = "arm"),
30839    stable(feature = "neon_intrinsics", since = "1.59.0")
30840)]
30841#[cfg_attr(
30842    target_arch = "arm",
30843    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30844)]
30845pub fn vmlsq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
30846    static_assert_uimm_bits!(LANE, 2);
30847    unsafe {
30848        vmlsq_u32(
30849            a,
30850            b,
30851            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30852        )
30853    }
30854}
30855#[doc = "Vector multiply subtract with scalar"]
30856#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_f32)"]
30857#[inline]
30858#[target_feature(enable = "neon")]
30859#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30860#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
30861#[cfg_attr(
30862    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30863    assert_instr(fmul)
30864)]
30865#[cfg_attr(
30866    not(target_arch = "arm"),
30867    stable(feature = "neon_intrinsics", since = "1.59.0")
30868)]
30869#[cfg_attr(
30870    target_arch = "arm",
30871    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30872)]
30873pub fn vmls_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
30874    vmls_f32(a, b, vdup_n_f32(c))
30875}
30876#[doc = "Vector multiply subtract with scalar"]
30877#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_f32)"]
30878#[inline]
30879#[target_feature(enable = "neon")]
30880#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30881#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
30882#[cfg_attr(
30883    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30884    assert_instr(fmul)
30885)]
30886#[cfg_attr(
30887    not(target_arch = "arm"),
30888    stable(feature = "neon_intrinsics", since = "1.59.0")
30889)]
30890#[cfg_attr(
30891    target_arch = "arm",
30892    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30893)]
30894pub fn vmlsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
30895    vmlsq_f32(a, b, vdupq_n_f32(c))
30896}
30897#[doc = "Vector multiply subtract with scalar"]
30898#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s16)"]
30899#[inline]
30900#[target_feature(enable = "neon")]
30901#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30902#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
30903#[cfg_attr(
30904    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30905    assert_instr(mls)
30906)]
30907#[cfg_attr(
30908    not(target_arch = "arm"),
30909    stable(feature = "neon_intrinsics", since = "1.59.0")
30910)]
30911#[cfg_attr(
30912    target_arch = "arm",
30913    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30914)]
30915pub fn vmls_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t {
30916    vmls_s16(a, b, vdup_n_s16(c))
30917}
30918#[doc = "Vector multiply subtract with scalar"]
30919#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s16)"]
30920#[inline]
30921#[target_feature(enable = "neon")]
30922#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30923#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
30924#[cfg_attr(
30925    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30926    assert_instr(mls)
30927)]
30928#[cfg_attr(
30929    not(target_arch = "arm"),
30930    stable(feature = "neon_intrinsics", since = "1.59.0")
30931)]
30932#[cfg_attr(
30933    target_arch = "arm",
30934    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30935)]
30936pub fn vmlsq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t {
30937    vmlsq_s16(a, b, vdupq_n_s16(c))
30938}
30939#[doc = "Vector multiply subtract with scalar"]
30940#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u16)"]
30941#[inline]
30942#[target_feature(enable = "neon")]
30943#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30944#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
30945#[cfg_attr(
30946    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30947    assert_instr(mls)
30948)]
30949#[cfg_attr(
30950    not(target_arch = "arm"),
30951    stable(feature = "neon_intrinsics", since = "1.59.0")
30952)]
30953#[cfg_attr(
30954    target_arch = "arm",
30955    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30956)]
30957pub fn vmls_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t {
30958    vmls_u16(a, b, vdup_n_u16(c))
30959}
30960#[doc = "Vector multiply subtract with scalar"]
30961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u16)"]
30962#[inline]
30963#[target_feature(enable = "neon")]
30964#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30965#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
30966#[cfg_attr(
30967    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30968    assert_instr(mls)
30969)]
30970#[cfg_attr(
30971    not(target_arch = "arm"),
30972    stable(feature = "neon_intrinsics", since = "1.59.0")
30973)]
30974#[cfg_attr(
30975    target_arch = "arm",
30976    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30977)]
30978pub fn vmlsq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t {
30979    vmlsq_u16(a, b, vdupq_n_u16(c))
30980}
30981#[doc = "Vector multiply subtract with scalar"]
30982#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s32)"]
30983#[inline]
30984#[target_feature(enable = "neon")]
30985#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30986#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
30987#[cfg_attr(
30988    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30989    assert_instr(mls)
30990)]
30991#[cfg_attr(
30992    not(target_arch = "arm"),
30993    stable(feature = "neon_intrinsics", since = "1.59.0")
30994)]
30995#[cfg_attr(
30996    target_arch = "arm",
30997    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30998)]
30999pub fn vmls_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t {
31000    vmls_s32(a, b, vdup_n_s32(c))
31001}
31002#[doc = "Vector multiply subtract with scalar"]
31003#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s32)"]
31004#[inline]
31005#[target_feature(enable = "neon")]
31006#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31007#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31008#[cfg_attr(
31009    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31010    assert_instr(mls)
31011)]
31012#[cfg_attr(
31013    not(target_arch = "arm"),
31014    stable(feature = "neon_intrinsics", since = "1.59.0")
31015)]
31016#[cfg_attr(
31017    target_arch = "arm",
31018    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31019)]
31020pub fn vmlsq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t {
31021    vmlsq_s32(a, b, vdupq_n_s32(c))
31022}
31023#[doc = "Vector multiply subtract with scalar"]
31024#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u32)"]
31025#[inline]
31026#[target_feature(enable = "neon")]
31027#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31028#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31029#[cfg_attr(
31030    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31031    assert_instr(mls)
31032)]
31033#[cfg_attr(
31034    not(target_arch = "arm"),
31035    stable(feature = "neon_intrinsics", since = "1.59.0")
31036)]
31037#[cfg_attr(
31038    target_arch = "arm",
31039    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31040)]
31041pub fn vmls_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t {
31042    vmls_u32(a, b, vdup_n_u32(c))
31043}
31044#[doc = "Vector multiply subtract with scalar"]
31045#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u32)"]
31046#[inline]
31047#[target_feature(enable = "neon")]
31048#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31049#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31050#[cfg_attr(
31051    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31052    assert_instr(mls)
31053)]
31054#[cfg_attr(
31055    not(target_arch = "arm"),
31056    stable(feature = "neon_intrinsics", since = "1.59.0")
31057)]
31058#[cfg_attr(
31059    target_arch = "arm",
31060    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31061)]
31062pub fn vmlsq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t {
31063    vmlsq_u32(a, b, vdupq_n_u32(c))
31064}
31065#[doc = "Multiply-subtract from accumulator"]
31066#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s8)"]
31067#[inline]
31068#[target_feature(enable = "neon")]
31069#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31070#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
31071#[cfg_attr(
31072    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31073    assert_instr(mls)
31074)]
31075#[cfg_attr(
31076    not(target_arch = "arm"),
31077    stable(feature = "neon_intrinsics", since = "1.59.0")
31078)]
31079#[cfg_attr(
31080    target_arch = "arm",
31081    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31082)]
31083pub fn vmls_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
31084    unsafe { simd_sub(a, simd_mul(b, c)) }
31085}
31086#[doc = "Multiply-subtract from accumulator"]
31087#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s8)"]
31088#[inline]
31089#[target_feature(enable = "neon")]
31090#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31091#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
31092#[cfg_attr(
31093    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31094    assert_instr(mls)
31095)]
31096#[cfg_attr(
31097    not(target_arch = "arm"),
31098    stable(feature = "neon_intrinsics", since = "1.59.0")
31099)]
31100#[cfg_attr(
31101    target_arch = "arm",
31102    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31103)]
31104pub fn vmlsq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
31105    unsafe { simd_sub(a, simd_mul(b, c)) }
31106}
31107#[doc = "Multiply-subtract from accumulator"]
31108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s16)"]
31109#[inline]
31110#[target_feature(enable = "neon")]
31111#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31112#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
31113#[cfg_attr(
31114    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31115    assert_instr(mls)
31116)]
31117#[cfg_attr(
31118    not(target_arch = "arm"),
31119    stable(feature = "neon_intrinsics", since = "1.59.0")
31120)]
31121#[cfg_attr(
31122    target_arch = "arm",
31123    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31124)]
31125pub fn vmls_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
31126    unsafe { simd_sub(a, simd_mul(b, c)) }
31127}
31128#[doc = "Multiply-subtract from accumulator"]
31129#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s16)"]
31130#[inline]
31131#[target_feature(enable = "neon")]
31132#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31133#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
31134#[cfg_attr(
31135    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31136    assert_instr(mls)
31137)]
31138#[cfg_attr(
31139    not(target_arch = "arm"),
31140    stable(feature = "neon_intrinsics", since = "1.59.0")
31141)]
31142#[cfg_attr(
31143    target_arch = "arm",
31144    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31145)]
31146pub fn vmlsq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
31147    unsafe { simd_sub(a, simd_mul(b, c)) }
31148}
31149#[doc = "Multiply-subtract from accumulator"]
31150#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s32)"]
31151#[inline]
31152#[target_feature(enable = "neon")]
31153#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31154#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31155#[cfg_attr(
31156    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31157    assert_instr(mls)
31158)]
31159#[cfg_attr(
31160    not(target_arch = "arm"),
31161    stable(feature = "neon_intrinsics", since = "1.59.0")
31162)]
31163#[cfg_attr(
31164    target_arch = "arm",
31165    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31166)]
31167pub fn vmls_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
31168    unsafe { simd_sub(a, simd_mul(b, c)) }
31169}
31170#[doc = "Multiply-subtract from accumulator"]
31171#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s32)"]
31172#[inline]
31173#[target_feature(enable = "neon")]
31174#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31175#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31176#[cfg_attr(
31177    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31178    assert_instr(mls)
31179)]
31180#[cfg_attr(
31181    not(target_arch = "arm"),
31182    stable(feature = "neon_intrinsics", since = "1.59.0")
31183)]
31184#[cfg_attr(
31185    target_arch = "arm",
31186    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31187)]
31188pub fn vmlsq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
31189    unsafe { simd_sub(a, simd_mul(b, c)) }
31190}
31191#[doc = "Multiply-subtract from accumulator"]
31192#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u8)"]
31193#[inline]
31194#[target_feature(enable = "neon")]
31195#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31196#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
31197#[cfg_attr(
31198    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31199    assert_instr(mls)
31200)]
31201#[cfg_attr(
31202    not(target_arch = "arm"),
31203    stable(feature = "neon_intrinsics", since = "1.59.0")
31204)]
31205#[cfg_attr(
31206    target_arch = "arm",
31207    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31208)]
31209pub fn vmls_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
31210    unsafe { simd_sub(a, simd_mul(b, c)) }
31211}
31212#[doc = "Multiply-subtract from accumulator"]
31213#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u8)"]
31214#[inline]
31215#[target_feature(enable = "neon")]
31216#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31217#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
31218#[cfg_attr(
31219    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31220    assert_instr(mls)
31221)]
31222#[cfg_attr(
31223    not(target_arch = "arm"),
31224    stable(feature = "neon_intrinsics", since = "1.59.0")
31225)]
31226#[cfg_attr(
31227    target_arch = "arm",
31228    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31229)]
31230pub fn vmlsq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
31231    unsafe { simd_sub(a, simd_mul(b, c)) }
31232}
31233#[doc = "Multiply-subtract from accumulator"]
31234#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u16)"]
31235#[inline]
31236#[target_feature(enable = "neon")]
31237#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31238#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
31239#[cfg_attr(
31240    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31241    assert_instr(mls)
31242)]
31243#[cfg_attr(
31244    not(target_arch = "arm"),
31245    stable(feature = "neon_intrinsics", since = "1.59.0")
31246)]
31247#[cfg_attr(
31248    target_arch = "arm",
31249    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31250)]
31251pub fn vmls_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
31252    unsafe { simd_sub(a, simd_mul(b, c)) }
31253}
31254#[doc = "Multiply-subtract from accumulator"]
31255#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u16)"]
31256#[inline]
31257#[target_feature(enable = "neon")]
31258#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31259#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
31260#[cfg_attr(
31261    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31262    assert_instr(mls)
31263)]
31264#[cfg_attr(
31265    not(target_arch = "arm"),
31266    stable(feature = "neon_intrinsics", since = "1.59.0")
31267)]
31268#[cfg_attr(
31269    target_arch = "arm",
31270    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31271)]
31272pub fn vmlsq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
31273    unsafe { simd_sub(a, simd_mul(b, c)) }
31274}
31275#[doc = "Multiply-subtract from accumulator"]
31276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u32)"]
31277#[inline]
31278#[target_feature(enable = "neon")]
31279#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31280#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31281#[cfg_attr(
31282    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31283    assert_instr(mls)
31284)]
31285#[cfg_attr(
31286    not(target_arch = "arm"),
31287    stable(feature = "neon_intrinsics", since = "1.59.0")
31288)]
31289#[cfg_attr(
31290    target_arch = "arm",
31291    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31292)]
31293pub fn vmls_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
31294    unsafe { simd_sub(a, simd_mul(b, c)) }
31295}
31296#[doc = "Multiply-subtract from accumulator"]
31297#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u32)"]
31298#[inline]
31299#[target_feature(enable = "neon")]
31300#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31301#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31302#[cfg_attr(
31303    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31304    assert_instr(mls)
31305)]
31306#[cfg_attr(
31307    not(target_arch = "arm"),
31308    stable(feature = "neon_intrinsics", since = "1.59.0")
31309)]
31310#[cfg_attr(
31311    target_arch = "arm",
31312    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31313)]
31314pub fn vmlsq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
31315    unsafe { simd_sub(a, simd_mul(b, c)) }
31316}
31317#[doc = "Vector widening multiply subtract with scalar"]
31318#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s16)"]
31319#[inline]
31320#[target_feature(enable = "neon")]
31321#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31322#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))]
31323#[cfg_attr(
31324    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31325    assert_instr(smlsl, LANE = 1)
31326)]
31327#[rustc_legacy_const_generics(3)]
31328#[cfg_attr(
31329    not(target_arch = "arm"),
31330    stable(feature = "neon_intrinsics", since = "1.59.0")
31331)]
31332#[cfg_attr(
31333    target_arch = "arm",
31334    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31335)]
31336pub fn vmlsl_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
31337    static_assert_uimm_bits!(LANE, 2);
31338    unsafe {
31339        vmlsl_s16(
31340            a,
31341            b,
31342            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
31343        )
31344    }
31345}
31346#[doc = "Vector widening multiply subtract with scalar"]
31347#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s16)"]
31348#[inline]
31349#[target_feature(enable = "neon")]
31350#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31351#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))]
31352#[cfg_attr(
31353    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31354    assert_instr(smlsl, LANE = 1)
31355)]
31356#[rustc_legacy_const_generics(3)]
31357#[cfg_attr(
31358    not(target_arch = "arm"),
31359    stable(feature = "neon_intrinsics", since = "1.59.0")
31360)]
31361#[cfg_attr(
31362    target_arch = "arm",
31363    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31364)]
31365pub fn vmlsl_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t {
31366    static_assert_uimm_bits!(LANE, 3);
31367    unsafe {
31368        vmlsl_s16(
31369            a,
31370            b,
31371            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
31372        )
31373    }
31374}
31375#[doc = "Vector widening multiply subtract with scalar"]
31376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s32)"]
31377#[inline]
31378#[target_feature(enable = "neon")]
31379#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31380#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))]
31381#[cfg_attr(
31382    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31383    assert_instr(smlsl, LANE = 1)
31384)]
31385#[rustc_legacy_const_generics(3)]
31386#[cfg_attr(
31387    not(target_arch = "arm"),
31388    stable(feature = "neon_intrinsics", since = "1.59.0")
31389)]
31390#[cfg_attr(
31391    target_arch = "arm",
31392    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31393)]
31394pub fn vmlsl_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
31395    static_assert_uimm_bits!(LANE, 1);
31396    unsafe { vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
31397}
31398#[doc = "Vector widening multiply subtract with scalar"]
31399#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s32)"]
31400#[inline]
31401#[target_feature(enable = "neon")]
31402#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31403#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))]
31404#[cfg_attr(
31405    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31406    assert_instr(smlsl, LANE = 1)
31407)]
31408#[rustc_legacy_const_generics(3)]
31409#[cfg_attr(
31410    not(target_arch = "arm"),
31411    stable(feature = "neon_intrinsics", since = "1.59.0")
31412)]
31413#[cfg_attr(
31414    target_arch = "arm",
31415    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31416)]
31417pub fn vmlsl_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t {
31418    static_assert_uimm_bits!(LANE, 2);
31419    unsafe { vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
31420}
31421#[doc = "Vector widening multiply subtract with scalar"]
31422#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u16)"]
31423#[inline]
31424#[target_feature(enable = "neon")]
31425#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31426#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))]
31427#[cfg_attr(
31428    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31429    assert_instr(umlsl, LANE = 1)
31430)]
31431#[rustc_legacy_const_generics(3)]
31432#[cfg_attr(
31433    not(target_arch = "arm"),
31434    stable(feature = "neon_intrinsics", since = "1.59.0")
31435)]
31436#[cfg_attr(
31437    target_arch = "arm",
31438    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31439)]
31440pub fn vmlsl_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
31441    static_assert_uimm_bits!(LANE, 2);
31442    unsafe {
31443        vmlsl_u16(
31444            a,
31445            b,
31446            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
31447        )
31448    }
31449}
31450#[doc = "Vector widening multiply subtract with scalar"]
31451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u16)"]
31452#[inline]
31453#[target_feature(enable = "neon")]
31454#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31455#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))]
31456#[cfg_attr(
31457    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31458    assert_instr(umlsl, LANE = 1)
31459)]
31460#[rustc_legacy_const_generics(3)]
31461#[cfg_attr(
31462    not(target_arch = "arm"),
31463    stable(feature = "neon_intrinsics", since = "1.59.0")
31464)]
31465#[cfg_attr(
31466    target_arch = "arm",
31467    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31468)]
31469pub fn vmlsl_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x8_t) -> uint32x4_t {
31470    static_assert_uimm_bits!(LANE, 3);
31471    unsafe {
31472        vmlsl_u16(
31473            a,
31474            b,
31475            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
31476        )
31477    }
31478}
31479#[doc = "Vector widening multiply subtract with scalar"]
31480#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u32)"]
31481#[inline]
31482#[target_feature(enable = "neon")]
31483#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31484#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))]
31485#[cfg_attr(
31486    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31487    assert_instr(umlsl, LANE = 1)
31488)]
31489#[rustc_legacy_const_generics(3)]
31490#[cfg_attr(
31491    not(target_arch = "arm"),
31492    stable(feature = "neon_intrinsics", since = "1.59.0")
31493)]
31494#[cfg_attr(
31495    target_arch = "arm",
31496    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31497)]
31498pub fn vmlsl_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
31499    static_assert_uimm_bits!(LANE, 1);
31500    unsafe { vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
31501}
31502#[doc = "Vector widening multiply subtract with scalar"]
31503#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u32)"]
31504#[inline]
31505#[target_feature(enable = "neon")]
31506#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31507#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))]
31508#[cfg_attr(
31509    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31510    assert_instr(umlsl, LANE = 1)
31511)]
31512#[rustc_legacy_const_generics(3)]
31513#[cfg_attr(
31514    not(target_arch = "arm"),
31515    stable(feature = "neon_intrinsics", since = "1.59.0")
31516)]
31517#[cfg_attr(
31518    target_arch = "arm",
31519    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31520)]
31521pub fn vmlsl_laneq_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x4_t) -> uint64x2_t {
31522    static_assert_uimm_bits!(LANE, 2);
31523    unsafe { vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
31524}
31525#[doc = "Vector widening multiply subtract with scalar"]
31526#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s16)"]
31527#[inline]
31528#[target_feature(enable = "neon")]
31529#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31530#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))]
31531#[cfg_attr(
31532    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31533    assert_instr(smlsl)
31534)]
31535#[cfg_attr(
31536    not(target_arch = "arm"),
31537    stable(feature = "neon_intrinsics", since = "1.59.0")
31538)]
31539#[cfg_attr(
31540    target_arch = "arm",
31541    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31542)]
31543pub fn vmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
31544    vmlsl_s16(a, b, vdup_n_s16(c))
31545}
31546#[doc = "Vector widening multiply subtract with scalar"]
31547#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s32)"]
31548#[inline]
31549#[target_feature(enable = "neon")]
31550#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31551#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))]
31552#[cfg_attr(
31553    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31554    assert_instr(smlsl)
31555)]
31556#[cfg_attr(
31557    not(target_arch = "arm"),
31558    stable(feature = "neon_intrinsics", since = "1.59.0")
31559)]
31560#[cfg_attr(
31561    target_arch = "arm",
31562    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31563)]
31564pub fn vmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
31565    vmlsl_s32(a, b, vdup_n_s32(c))
31566}
31567#[doc = "Vector widening multiply subtract with scalar"]
31568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u16)"]
31569#[inline]
31570#[target_feature(enable = "neon")]
31571#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31572#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))]
31573#[cfg_attr(
31574    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31575    assert_instr(umlsl)
31576)]
31577#[cfg_attr(
31578    not(target_arch = "arm"),
31579    stable(feature = "neon_intrinsics", since = "1.59.0")
31580)]
31581#[cfg_attr(
31582    target_arch = "arm",
31583    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31584)]
31585pub fn vmlsl_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t {
31586    vmlsl_u16(a, b, vdup_n_u16(c))
31587}
31588#[doc = "Vector widening multiply subtract with scalar"]
31589#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u32)"]
31590#[inline]
31591#[target_feature(enable = "neon")]
31592#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31593#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))]
31594#[cfg_attr(
31595    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31596    assert_instr(umlsl)
31597)]
31598#[cfg_attr(
31599    not(target_arch = "arm"),
31600    stable(feature = "neon_intrinsics", since = "1.59.0")
31601)]
31602#[cfg_attr(
31603    target_arch = "arm",
31604    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31605)]
31606pub fn vmlsl_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t {
31607    vmlsl_u32(a, b, vdup_n_u32(c))
31608}
31609#[doc = "Signed multiply-subtract long"]
31610#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s8)"]
31611#[inline]
31612#[target_feature(enable = "neon")]
31613#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31614#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s8"))]
31615#[cfg_attr(
31616    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31617    assert_instr(smlsl)
31618)]
31619#[cfg_attr(
31620    not(target_arch = "arm"),
31621    stable(feature = "neon_intrinsics", since = "1.59.0")
31622)]
31623#[cfg_attr(
31624    target_arch = "arm",
31625    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31626)]
31627pub fn vmlsl_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
31628    unsafe { simd_sub(a, vmull_s8(b, c)) }
31629}
31630#[doc = "Signed multiply-subtract long"]
31631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s16)"]
31632#[inline]
31633#[target_feature(enable = "neon")]
31634#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31635#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))]
31636#[cfg_attr(
31637    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31638    assert_instr(smlsl)
31639)]
31640#[cfg_attr(
31641    not(target_arch = "arm"),
31642    stable(feature = "neon_intrinsics", since = "1.59.0")
31643)]
31644#[cfg_attr(
31645    target_arch = "arm",
31646    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31647)]
31648pub fn vmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
31649    unsafe { simd_sub(a, vmull_s16(b, c)) }
31650}
31651#[doc = "Signed multiply-subtract long"]
31652#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s32)"]
31653#[inline]
31654#[target_feature(enable = "neon")]
31655#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31656#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))]
31657#[cfg_attr(
31658    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31659    assert_instr(smlsl)
31660)]
31661#[cfg_attr(
31662    not(target_arch = "arm"),
31663    stable(feature = "neon_intrinsics", since = "1.59.0")
31664)]
31665#[cfg_attr(
31666    target_arch = "arm",
31667    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31668)]
31669pub fn vmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
31670    unsafe { simd_sub(a, vmull_s32(b, c)) }
31671}
31672#[doc = "Unsigned multiply-subtract long"]
31673#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u8)"]
31674#[inline]
31675#[target_feature(enable = "neon")]
31676#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31677#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u8"))]
31678#[cfg_attr(
31679    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31680    assert_instr(umlsl)
31681)]
31682#[cfg_attr(
31683    not(target_arch = "arm"),
31684    stable(feature = "neon_intrinsics", since = "1.59.0")
31685)]
31686#[cfg_attr(
31687    target_arch = "arm",
31688    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31689)]
31690pub fn vmlsl_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
31691    unsafe { simd_sub(a, vmull_u8(b, c)) }
31692}
31693#[doc = "Unsigned multiply-subtract long"]
31694#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u16)"]
31695#[inline]
31696#[target_feature(enable = "neon")]
31697#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31698#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))]
31699#[cfg_attr(
31700    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31701    assert_instr(umlsl)
31702)]
31703#[cfg_attr(
31704    not(target_arch = "arm"),
31705    stable(feature = "neon_intrinsics", since = "1.59.0")
31706)]
31707#[cfg_attr(
31708    target_arch = "arm",
31709    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31710)]
31711pub fn vmlsl_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
31712    unsafe { simd_sub(a, vmull_u16(b, c)) }
31713}
31714#[doc = "Unsigned multiply-subtract long"]
31715#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u32)"]
31716#[inline]
31717#[target_feature(enable = "neon")]
31718#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31719#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))]
31720#[cfg_attr(
31721    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31722    assert_instr(umlsl)
31723)]
31724#[cfg_attr(
31725    not(target_arch = "arm"),
31726    stable(feature = "neon_intrinsics", since = "1.59.0")
31727)]
31728#[cfg_attr(
31729    target_arch = "arm",
31730    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31731)]
31732pub fn vmlsl_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
31733    unsafe { simd_sub(a, vmull_u32(b, c)) }
31734}
31735#[doc = "8-bit integer matrix multiply-accumulate"]
31736#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_s32)"]
31737#[inline]
31738#[target_feature(enable = "neon,i8mm")]
31739#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
31740#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
31741#[cfg_attr(
31742    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31743    assert_instr(smmla)
31744)]
31745#[cfg_attr(
31746    not(target_arch = "arm"),
31747    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
31748)]
31749#[cfg_attr(
31750    target_arch = "arm",
31751    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31752)]
31753pub fn vmmlaq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
31754    unsafe extern "unadjusted" {
31755        #[cfg_attr(
31756            any(target_arch = "aarch64", target_arch = "arm64ec"),
31757            link_name = "llvm.aarch64.neon.smmla.v4i32.v16i8"
31758        )]
31759        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.smmla.v4i32.v16i8")]
31760        fn _vmmlaq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t;
31761    }
31762    unsafe { _vmmlaq_s32(a, b, c) }
31763}
31764#[doc = "8-bit integer matrix multiply-accumulate"]
31765#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_u32)"]
31766#[inline]
31767#[target_feature(enable = "neon,i8mm")]
31768#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
31769#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
31770#[cfg_attr(
31771    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31772    assert_instr(ummla)
31773)]
31774#[cfg_attr(
31775    not(target_arch = "arm"),
31776    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
31777)]
31778#[cfg_attr(
31779    target_arch = "arm",
31780    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31781)]
31782pub fn vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
31783    unsafe extern "unadjusted" {
31784        #[cfg_attr(
31785            any(target_arch = "aarch64", target_arch = "arm64ec"),
31786            link_name = "llvm.aarch64.neon.ummla.v4i32.v16i8"
31787        )]
31788        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.ummla.v4i32.v16i8")]
31789        fn _vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t;
31790    }
31791    unsafe { _vmmlaq_u32(a, b, c) }
31792}
31793#[doc = "Duplicate element to vector"]
31794#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f16)"]
31795#[inline]
31796#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31797#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
31798#[cfg_attr(
31799    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31800    assert_instr(dup)
31801)]
31802#[target_feature(enable = "neon,fp16")]
31803#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
31804pub fn vmov_n_f16(a: f16) -> float16x4_t {
31805    vdup_n_f16(a)
31806}
31807#[doc = "Duplicate element to vector"]
31808#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f16)"]
31809#[inline]
31810#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31811#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
31812#[cfg_attr(
31813    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31814    assert_instr(dup)
31815)]
31816#[target_feature(enable = "neon,fp16")]
31817#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
31818pub fn vmovq_n_f16(a: f16) -> float16x8_t {
31819    vdupq_n_f16(a)
31820}
31821#[doc = "Duplicate vector element to vector or scalar"]
31822#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f32)"]
31823#[inline]
31824#[target_feature(enable = "neon")]
31825#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31826#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
31827#[cfg_attr(
31828    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31829    assert_instr(dup)
31830)]
31831#[cfg_attr(
31832    not(target_arch = "arm"),
31833    stable(feature = "neon_intrinsics", since = "1.59.0")
31834)]
31835#[cfg_attr(
31836    target_arch = "arm",
31837    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31838)]
31839pub fn vmov_n_f32(value: f32) -> float32x2_t {
31840    vdup_n_f32(value)
31841}
31842#[doc = "Duplicate vector element to vector or scalar"]
31843#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p16)"]
31844#[inline]
31845#[target_feature(enable = "neon")]
31846#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31847#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
31848#[cfg_attr(
31849    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31850    assert_instr(dup)
31851)]
31852#[cfg_attr(
31853    not(target_arch = "arm"),
31854    stable(feature = "neon_intrinsics", since = "1.59.0")
31855)]
31856#[cfg_attr(
31857    target_arch = "arm",
31858    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31859)]
31860pub fn vmov_n_p16(value: p16) -> poly16x4_t {
31861    vdup_n_p16(value)
31862}
31863#[doc = "Duplicate vector element to vector or scalar"]
31864#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p8)"]
31865#[inline]
31866#[target_feature(enable = "neon")]
31867#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31868#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
31869#[cfg_attr(
31870    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31871    assert_instr(dup)
31872)]
31873#[cfg_attr(
31874    not(target_arch = "arm"),
31875    stable(feature = "neon_intrinsics", since = "1.59.0")
31876)]
31877#[cfg_attr(
31878    target_arch = "arm",
31879    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31880)]
31881pub fn vmov_n_p8(value: p8) -> poly8x8_t {
31882    vdup_n_p8(value)
31883}
31884#[doc = "Duplicate vector element to vector or scalar"]
31885#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s16)"]
31886#[inline]
31887#[target_feature(enable = "neon")]
31888#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31889#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
31890#[cfg_attr(
31891    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31892    assert_instr(dup)
31893)]
31894#[cfg_attr(
31895    not(target_arch = "arm"),
31896    stable(feature = "neon_intrinsics", since = "1.59.0")
31897)]
31898#[cfg_attr(
31899    target_arch = "arm",
31900    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31901)]
31902pub fn vmov_n_s16(value: i16) -> int16x4_t {
31903    vdup_n_s16(value)
31904}
31905#[doc = "Duplicate vector element to vector or scalar"]
31906#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s32)"]
31907#[inline]
31908#[target_feature(enable = "neon")]
31909#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31910#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
31911#[cfg_attr(
31912    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31913    assert_instr(dup)
31914)]
31915#[cfg_attr(
31916    not(target_arch = "arm"),
31917    stable(feature = "neon_intrinsics", since = "1.59.0")
31918)]
31919#[cfg_attr(
31920    target_arch = "arm",
31921    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31922)]
31923pub fn vmov_n_s32(value: i32) -> int32x2_t {
31924    vdup_n_s32(value)
31925}
31926#[doc = "Duplicate vector element to vector or scalar"]
31927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s64)"]
31928#[inline]
31929#[target_feature(enable = "neon")]
31930#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31931#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
31932#[cfg_attr(
31933    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31934    assert_instr(fmov)
31935)]
31936#[cfg_attr(
31937    not(target_arch = "arm"),
31938    stable(feature = "neon_intrinsics", since = "1.59.0")
31939)]
31940#[cfg_attr(
31941    target_arch = "arm",
31942    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31943)]
31944pub fn vmov_n_s64(value: i64) -> int64x1_t {
31945    vdup_n_s64(value)
31946}
31947#[doc = "Duplicate vector element to vector or scalar"]
31948#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s8)"]
31949#[inline]
31950#[target_feature(enable = "neon")]
31951#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31952#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
31953#[cfg_attr(
31954    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31955    assert_instr(dup)
31956)]
31957#[cfg_attr(
31958    not(target_arch = "arm"),
31959    stable(feature = "neon_intrinsics", since = "1.59.0")
31960)]
31961#[cfg_attr(
31962    target_arch = "arm",
31963    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31964)]
31965pub fn vmov_n_s8(value: i8) -> int8x8_t {
31966    vdup_n_s8(value)
31967}
31968#[doc = "Duplicate vector element to vector or scalar"]
31969#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u16)"]
31970#[inline]
31971#[target_feature(enable = "neon")]
31972#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31973#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
31974#[cfg_attr(
31975    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31976    assert_instr(dup)
31977)]
31978#[cfg_attr(
31979    not(target_arch = "arm"),
31980    stable(feature = "neon_intrinsics", since = "1.59.0")
31981)]
31982#[cfg_attr(
31983    target_arch = "arm",
31984    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31985)]
31986pub fn vmov_n_u16(value: u16) -> uint16x4_t {
31987    vdup_n_u16(value)
31988}
31989#[doc = "Duplicate vector element to vector or scalar"]
31990#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u32)"]
31991#[inline]
31992#[target_feature(enable = "neon")]
31993#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31994#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
31995#[cfg_attr(
31996    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31997    assert_instr(dup)
31998)]
31999#[cfg_attr(
32000    not(target_arch = "arm"),
32001    stable(feature = "neon_intrinsics", since = "1.59.0")
32002)]
32003#[cfg_attr(
32004    target_arch = "arm",
32005    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32006)]
32007pub fn vmov_n_u32(value: u32) -> uint32x2_t {
32008    vdup_n_u32(value)
32009}
32010#[doc = "Duplicate vector element to vector or scalar"]
32011#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u64)"]
32012#[inline]
32013#[target_feature(enable = "neon")]
32014#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32015#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
32016#[cfg_attr(
32017    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32018    assert_instr(fmov)
32019)]
32020#[cfg_attr(
32021    not(target_arch = "arm"),
32022    stable(feature = "neon_intrinsics", since = "1.59.0")
32023)]
32024#[cfg_attr(
32025    target_arch = "arm",
32026    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32027)]
32028pub fn vmov_n_u64(value: u64) -> uint64x1_t {
32029    vdup_n_u64(value)
32030}
32031#[doc = "Duplicate vector element to vector or scalar"]
32032#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u8)"]
32033#[inline]
32034#[target_feature(enable = "neon")]
32035#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32036#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
32037#[cfg_attr(
32038    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32039    assert_instr(dup)
32040)]
32041#[cfg_attr(
32042    not(target_arch = "arm"),
32043    stable(feature = "neon_intrinsics", since = "1.59.0")
32044)]
32045#[cfg_attr(
32046    target_arch = "arm",
32047    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32048)]
32049pub fn vmov_n_u8(value: u8) -> uint8x8_t {
32050    vdup_n_u8(value)
32051}
32052#[doc = "Duplicate vector element to vector or scalar"]
32053#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f32)"]
32054#[inline]
32055#[target_feature(enable = "neon")]
32056#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32057#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
32058#[cfg_attr(
32059    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32060    assert_instr(dup)
32061)]
32062#[cfg_attr(
32063    not(target_arch = "arm"),
32064    stable(feature = "neon_intrinsics", since = "1.59.0")
32065)]
32066#[cfg_attr(
32067    target_arch = "arm",
32068    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32069)]
32070pub fn vmovq_n_f32(value: f32) -> float32x4_t {
32071    vdupq_n_f32(value)
32072}
32073#[doc = "Duplicate vector element to vector or scalar"]
32074#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p16)"]
32075#[inline]
32076#[target_feature(enable = "neon")]
32077#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32078#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
32079#[cfg_attr(
32080    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32081    assert_instr(dup)
32082)]
32083#[cfg_attr(
32084    not(target_arch = "arm"),
32085    stable(feature = "neon_intrinsics", since = "1.59.0")
32086)]
32087#[cfg_attr(
32088    target_arch = "arm",
32089    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32090)]
32091pub fn vmovq_n_p16(value: p16) -> poly16x8_t {
32092    vdupq_n_p16(value)
32093}
32094#[doc = "Duplicate vector element to vector or scalar"]
32095#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p8)"]
32096#[inline]
32097#[target_feature(enable = "neon")]
32098#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32099#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
32100#[cfg_attr(
32101    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32102    assert_instr(dup)
32103)]
32104#[cfg_attr(
32105    not(target_arch = "arm"),
32106    stable(feature = "neon_intrinsics", since = "1.59.0")
32107)]
32108#[cfg_attr(
32109    target_arch = "arm",
32110    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32111)]
32112pub fn vmovq_n_p8(value: p8) -> poly8x16_t {
32113    vdupq_n_p8(value)
32114}
32115#[doc = "Duplicate vector element to vector or scalar"]
32116#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s16)"]
32117#[inline]
32118#[target_feature(enable = "neon")]
32119#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32120#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
32121#[cfg_attr(
32122    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32123    assert_instr(dup)
32124)]
32125#[cfg_attr(
32126    not(target_arch = "arm"),
32127    stable(feature = "neon_intrinsics", since = "1.59.0")
32128)]
32129#[cfg_attr(
32130    target_arch = "arm",
32131    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32132)]
32133pub fn vmovq_n_s16(value: i16) -> int16x8_t {
32134    vdupq_n_s16(value)
32135}
32136#[doc = "Duplicate vector element to vector or scalar"]
32137#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s32)"]
32138#[inline]
32139#[target_feature(enable = "neon")]
32140#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32141#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
32142#[cfg_attr(
32143    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32144    assert_instr(dup)
32145)]
32146#[cfg_attr(
32147    not(target_arch = "arm"),
32148    stable(feature = "neon_intrinsics", since = "1.59.0")
32149)]
32150#[cfg_attr(
32151    target_arch = "arm",
32152    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32153)]
32154pub fn vmovq_n_s32(value: i32) -> int32x4_t {
32155    vdupq_n_s32(value)
32156}
32157#[doc = "Duplicate vector element to vector or scalar"]
32158#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s64)"]
32159#[inline]
32160#[target_feature(enable = "neon")]
32161#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32162#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
32163#[cfg_attr(
32164    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32165    assert_instr(dup)
32166)]
32167#[cfg_attr(
32168    not(target_arch = "arm"),
32169    stable(feature = "neon_intrinsics", since = "1.59.0")
32170)]
32171#[cfg_attr(
32172    target_arch = "arm",
32173    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32174)]
32175pub fn vmovq_n_s64(value: i64) -> int64x2_t {
32176    vdupq_n_s64(value)
32177}
32178#[doc = "Duplicate vector element to vector or scalar"]
32179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s8)"]
32180#[inline]
32181#[target_feature(enable = "neon")]
32182#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32183#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
32184#[cfg_attr(
32185    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32186    assert_instr(dup)
32187)]
32188#[cfg_attr(
32189    not(target_arch = "arm"),
32190    stable(feature = "neon_intrinsics", since = "1.59.0")
32191)]
32192#[cfg_attr(
32193    target_arch = "arm",
32194    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32195)]
32196pub fn vmovq_n_s8(value: i8) -> int8x16_t {
32197    vdupq_n_s8(value)
32198}
32199#[doc = "Duplicate vector element to vector or scalar"]
32200#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u16)"]
32201#[inline]
32202#[target_feature(enable = "neon")]
32203#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32204#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
32205#[cfg_attr(
32206    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32207    assert_instr(dup)
32208)]
32209#[cfg_attr(
32210    not(target_arch = "arm"),
32211    stable(feature = "neon_intrinsics", since = "1.59.0")
32212)]
32213#[cfg_attr(
32214    target_arch = "arm",
32215    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32216)]
32217pub fn vmovq_n_u16(value: u16) -> uint16x8_t {
32218    vdupq_n_u16(value)
32219}
32220#[doc = "Duplicate vector element to vector or scalar"]
32221#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u32)"]
32222#[inline]
32223#[target_feature(enable = "neon")]
32224#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32225#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
32226#[cfg_attr(
32227    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32228    assert_instr(dup)
32229)]
32230#[cfg_attr(
32231    not(target_arch = "arm"),
32232    stable(feature = "neon_intrinsics", since = "1.59.0")
32233)]
32234#[cfg_attr(
32235    target_arch = "arm",
32236    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32237)]
32238pub fn vmovq_n_u32(value: u32) -> uint32x4_t {
32239    vdupq_n_u32(value)
32240}
32241#[doc = "Duplicate vector element to vector or scalar"]
32242#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u64)"]
32243#[inline]
32244#[target_feature(enable = "neon")]
32245#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32246#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
32247#[cfg_attr(
32248    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32249    assert_instr(dup)
32250)]
32251#[cfg_attr(
32252    not(target_arch = "arm"),
32253    stable(feature = "neon_intrinsics", since = "1.59.0")
32254)]
32255#[cfg_attr(
32256    target_arch = "arm",
32257    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32258)]
32259pub fn vmovq_n_u64(value: u64) -> uint64x2_t {
32260    vdupq_n_u64(value)
32261}
32262#[doc = "Duplicate vector element to vector or scalar"]
32263#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u8)"]
32264#[inline]
32265#[target_feature(enable = "neon")]
32266#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32267#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
32268#[cfg_attr(
32269    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32270    assert_instr(dup)
32271)]
32272#[cfg_attr(
32273    not(target_arch = "arm"),
32274    stable(feature = "neon_intrinsics", since = "1.59.0")
32275)]
32276#[cfg_attr(
32277    target_arch = "arm",
32278    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32279)]
32280pub fn vmovq_n_u8(value: u8) -> uint8x16_t {
32281    vdupq_n_u8(value)
32282}
32283#[doc = "Vector long move."]
32284#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s16)"]
32285#[inline]
32286#[target_feature(enable = "neon")]
32287#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32288#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32289#[cfg_attr(
32290    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32291    assert_instr(sxtl)
32292)]
32293#[cfg_attr(
32294    not(target_arch = "arm"),
32295    stable(feature = "neon_intrinsics", since = "1.59.0")
32296)]
32297#[cfg_attr(
32298    target_arch = "arm",
32299    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32300)]
32301pub fn vmovl_s16(a: int16x4_t) -> int32x4_t {
32302    unsafe { simd_cast(a) }
32303}
32304#[doc = "Vector long move."]
32305#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s32)"]
32306#[inline]
32307#[target_feature(enable = "neon")]
32308#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32309#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32310#[cfg_attr(
32311    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32312    assert_instr(sxtl)
32313)]
32314#[cfg_attr(
32315    not(target_arch = "arm"),
32316    stable(feature = "neon_intrinsics", since = "1.59.0")
32317)]
32318#[cfg_attr(
32319    target_arch = "arm",
32320    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32321)]
32322pub fn vmovl_s32(a: int32x2_t) -> int64x2_t {
32323    unsafe { simd_cast(a) }
32324}
32325#[doc = "Vector long move."]
32326#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s8)"]
32327#[inline]
32328#[target_feature(enable = "neon")]
32329#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32330#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32331#[cfg_attr(
32332    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32333    assert_instr(sxtl)
32334)]
32335#[cfg_attr(
32336    not(target_arch = "arm"),
32337    stable(feature = "neon_intrinsics", since = "1.59.0")
32338)]
32339#[cfg_attr(
32340    target_arch = "arm",
32341    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32342)]
32343pub fn vmovl_s8(a: int8x8_t) -> int16x8_t {
32344    unsafe { simd_cast(a) }
32345}
32346#[doc = "Vector long move."]
32347#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u16)"]
32348#[inline]
32349#[target_feature(enable = "neon")]
32350#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32351#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32352#[cfg_attr(
32353    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32354    assert_instr(uxtl)
32355)]
32356#[cfg_attr(
32357    not(target_arch = "arm"),
32358    stable(feature = "neon_intrinsics", since = "1.59.0")
32359)]
32360#[cfg_attr(
32361    target_arch = "arm",
32362    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32363)]
32364pub fn vmovl_u16(a: uint16x4_t) -> uint32x4_t {
32365    unsafe { simd_cast(a) }
32366}
32367#[doc = "Vector long move."]
32368#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u32)"]
32369#[inline]
32370#[target_feature(enable = "neon")]
32371#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32372#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32373#[cfg_attr(
32374    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32375    assert_instr(uxtl)
32376)]
32377#[cfg_attr(
32378    not(target_arch = "arm"),
32379    stable(feature = "neon_intrinsics", since = "1.59.0")
32380)]
32381#[cfg_attr(
32382    target_arch = "arm",
32383    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32384)]
32385pub fn vmovl_u32(a: uint32x2_t) -> uint64x2_t {
32386    unsafe { simd_cast(a) }
32387}
32388#[doc = "Vector long move."]
32389#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u8)"]
32390#[inline]
32391#[target_feature(enable = "neon")]
32392#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32393#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32394#[cfg_attr(
32395    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32396    assert_instr(uxtl)
32397)]
32398#[cfg_attr(
32399    not(target_arch = "arm"),
32400    stable(feature = "neon_intrinsics", since = "1.59.0")
32401)]
32402#[cfg_attr(
32403    target_arch = "arm",
32404    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32405)]
32406pub fn vmovl_u8(a: uint8x8_t) -> uint16x8_t {
32407    unsafe { simd_cast(a) }
32408}
32409#[doc = "Vector narrow integer."]
32410#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s16)"]
32411#[inline]
32412#[target_feature(enable = "neon")]
32413#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32414#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32415#[cfg_attr(
32416    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32417    assert_instr(xtn)
32418)]
32419#[cfg_attr(
32420    not(target_arch = "arm"),
32421    stable(feature = "neon_intrinsics", since = "1.59.0")
32422)]
32423#[cfg_attr(
32424    target_arch = "arm",
32425    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32426)]
32427pub fn vmovn_s16(a: int16x8_t) -> int8x8_t {
32428    unsafe { simd_cast(a) }
32429}
32430#[doc = "Vector narrow integer."]
32431#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s32)"]
32432#[inline]
32433#[target_feature(enable = "neon")]
32434#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32435#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32436#[cfg_attr(
32437    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32438    assert_instr(xtn)
32439)]
32440#[cfg_attr(
32441    not(target_arch = "arm"),
32442    stable(feature = "neon_intrinsics", since = "1.59.0")
32443)]
32444#[cfg_attr(
32445    target_arch = "arm",
32446    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32447)]
32448pub fn vmovn_s32(a: int32x4_t) -> int16x4_t {
32449    unsafe { simd_cast(a) }
32450}
32451#[doc = "Vector narrow integer."]
32452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s64)"]
32453#[inline]
32454#[target_feature(enable = "neon")]
32455#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32456#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32457#[cfg_attr(
32458    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32459    assert_instr(xtn)
32460)]
32461#[cfg_attr(
32462    not(target_arch = "arm"),
32463    stable(feature = "neon_intrinsics", since = "1.59.0")
32464)]
32465#[cfg_attr(
32466    target_arch = "arm",
32467    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32468)]
32469pub fn vmovn_s64(a: int64x2_t) -> int32x2_t {
32470    unsafe { simd_cast(a) }
32471}
32472#[doc = "Vector narrow integer."]
32473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u16)"]
32474#[inline]
32475#[target_feature(enable = "neon")]
32476#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32477#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32478#[cfg_attr(
32479    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32480    assert_instr(xtn)
32481)]
32482#[cfg_attr(
32483    not(target_arch = "arm"),
32484    stable(feature = "neon_intrinsics", since = "1.59.0")
32485)]
32486#[cfg_attr(
32487    target_arch = "arm",
32488    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32489)]
32490pub fn vmovn_u16(a: uint16x8_t) -> uint8x8_t {
32491    unsafe { simd_cast(a) }
32492}
32493#[doc = "Vector narrow integer."]
32494#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u32)"]
32495#[inline]
32496#[target_feature(enable = "neon")]
32497#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32498#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32499#[cfg_attr(
32500    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32501    assert_instr(xtn)
32502)]
32503#[cfg_attr(
32504    not(target_arch = "arm"),
32505    stable(feature = "neon_intrinsics", since = "1.59.0")
32506)]
32507#[cfg_attr(
32508    target_arch = "arm",
32509    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32510)]
32511pub fn vmovn_u32(a: uint32x4_t) -> uint16x4_t {
32512    unsafe { simd_cast(a) }
32513}
32514#[doc = "Vector narrow integer."]
32515#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u64)"]
32516#[inline]
32517#[target_feature(enable = "neon")]
32518#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32519#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32520#[cfg_attr(
32521    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32522    assert_instr(xtn)
32523)]
32524#[cfg_attr(
32525    not(target_arch = "arm"),
32526    stable(feature = "neon_intrinsics", since = "1.59.0")
32527)]
32528#[cfg_attr(
32529    target_arch = "arm",
32530    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32531)]
32532pub fn vmovn_u64(a: uint64x2_t) -> uint32x2_t {
32533    unsafe { simd_cast(a) }
32534}
32535#[doc = "Multiply"]
32536#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f16)"]
32537#[inline]
32538#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
32539#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))]
32540#[cfg_attr(
32541    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32542    assert_instr(fmul)
32543)]
32544#[target_feature(enable = "neon,fp16")]
32545#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
32546pub fn vmul_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
32547    unsafe { simd_mul(a, b) }
32548}
32549#[doc = "Multiply"]
32550#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f16)"]
32551#[inline]
32552#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
32553#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))]
32554#[cfg_attr(
32555    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32556    assert_instr(fmul)
32557)]
32558#[target_feature(enable = "neon,fp16")]
32559#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
32560pub fn vmulq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
32561    unsafe { simd_mul(a, b) }
32562}
32563#[doc = "Multiply"]
32564#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f32)"]
32565#[inline]
32566#[target_feature(enable = "neon")]
32567#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32568#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))]
32569#[cfg_attr(
32570    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32571    assert_instr(fmul)
32572)]
32573#[cfg_attr(
32574    not(target_arch = "arm"),
32575    stable(feature = "neon_intrinsics", since = "1.59.0")
32576)]
32577#[cfg_attr(
32578    target_arch = "arm",
32579    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32580)]
32581pub fn vmul_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
32582    unsafe { simd_mul(a, b) }
32583}
32584#[doc = "Multiply"]
32585#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f32)"]
32586#[inline]
32587#[target_feature(enable = "neon")]
32588#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32589#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))]
32590#[cfg_attr(
32591    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32592    assert_instr(fmul)
32593)]
32594#[cfg_attr(
32595    not(target_arch = "arm"),
32596    stable(feature = "neon_intrinsics", since = "1.59.0")
32597)]
32598#[cfg_attr(
32599    target_arch = "arm",
32600    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32601)]
32602pub fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
32603    unsafe { simd_mul(a, b) }
32604}
32605#[doc = "Multiply"]
32606#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f16)"]
32607#[inline]
32608#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
32609#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32610#[cfg_attr(
32611    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32612    assert_instr(fmul, LANE = 1)
32613)]
32614#[rustc_legacy_const_generics(2)]
32615#[target_feature(enable = "neon,fp16")]
32616#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
32617pub fn vmul_lane_f16<const LANE: i32>(a: float16x4_t, v: float16x4_t) -> float16x4_t {
32618    static_assert_uimm_bits!(LANE, 2);
32619    unsafe {
32620        simd_mul(
32621            a,
32622            simd_shuffle!(v, v, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32623        )
32624    }
32625}
32626#[doc = "Multiply"]
32627#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f16)"]
32628#[inline]
32629#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
32630#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32631#[cfg_attr(
32632    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32633    assert_instr(fmul, LANE = 1)
32634)]
32635#[rustc_legacy_const_generics(2)]
32636#[target_feature(enable = "neon,fp16")]
32637#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
32638pub fn vmulq_lane_f16<const LANE: i32>(a: float16x8_t, v: float16x4_t) -> float16x8_t {
32639    static_assert_uimm_bits!(LANE, 2);
32640    unsafe {
32641        simd_mul(
32642            a,
32643            simd_shuffle!(
32644                v,
32645                v,
32646                [
32647                    LANE as u32,
32648                    LANE as u32,
32649                    LANE as u32,
32650                    LANE as u32,
32651                    LANE as u32,
32652                    LANE as u32,
32653                    LANE as u32,
32654                    LANE as u32
32655                ]
32656            ),
32657        )
32658    }
32659}
32660#[doc = "Floating-point multiply"]
32661#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f32)"]
32662#[inline]
32663#[target_feature(enable = "neon")]
32664#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32665#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
32666#[cfg_attr(
32667    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32668    assert_instr(fmul, LANE = 0)
32669)]
32670#[rustc_legacy_const_generics(2)]
32671#[cfg_attr(
32672    not(target_arch = "arm"),
32673    stable(feature = "neon_intrinsics", since = "1.59.0")
32674)]
32675#[cfg_attr(
32676    target_arch = "arm",
32677    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32678)]
32679pub fn vmul_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t {
32680    static_assert_uimm_bits!(LANE, 1);
32681    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
32682}
32683#[doc = "Floating-point multiply"]
32684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f32)"]
32685#[inline]
32686#[target_feature(enable = "neon")]
32687#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32688#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
32689#[cfg_attr(
32690    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32691    assert_instr(fmul, LANE = 0)
32692)]
32693#[rustc_legacy_const_generics(2)]
32694#[cfg_attr(
32695    not(target_arch = "arm"),
32696    stable(feature = "neon_intrinsics", since = "1.59.0")
32697)]
32698#[cfg_attr(
32699    target_arch = "arm",
32700    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32701)]
32702pub fn vmul_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x4_t) -> float32x2_t {
32703    static_assert_uimm_bits!(LANE, 2);
32704    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
32705}
32706#[doc = "Floating-point multiply"]
32707#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f32)"]
32708#[inline]
32709#[target_feature(enable = "neon")]
32710#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32711#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
32712#[cfg_attr(
32713    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32714    assert_instr(fmul, LANE = 0)
32715)]
32716#[rustc_legacy_const_generics(2)]
32717#[cfg_attr(
32718    not(target_arch = "arm"),
32719    stable(feature = "neon_intrinsics", since = "1.59.0")
32720)]
32721#[cfg_attr(
32722    target_arch = "arm",
32723    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32724)]
32725pub fn vmulq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x2_t) -> float32x4_t {
32726    static_assert_uimm_bits!(LANE, 1);
32727    unsafe {
32728        simd_mul(
32729            a,
32730            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32731        )
32732    }
32733}
32734#[doc = "Floating-point multiply"]
32735#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f32)"]
32736#[inline]
32737#[target_feature(enable = "neon")]
32738#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32739#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
32740#[cfg_attr(
32741    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32742    assert_instr(fmul, LANE = 0)
32743)]
32744#[rustc_legacy_const_generics(2)]
32745#[cfg_attr(
32746    not(target_arch = "arm"),
32747    stable(feature = "neon_intrinsics", since = "1.59.0")
32748)]
32749#[cfg_attr(
32750    target_arch = "arm",
32751    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32752)]
32753pub fn vmulq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t {
32754    static_assert_uimm_bits!(LANE, 2);
32755    unsafe {
32756        simd_mul(
32757            a,
32758            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32759        )
32760    }
32761}
32762#[doc = "Multiply"]
32763#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s16)"]
32764#[inline]
32765#[target_feature(enable = "neon")]
32766#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32767#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32768#[cfg_attr(
32769    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32770    assert_instr(mul, LANE = 1)
32771)]
32772#[rustc_legacy_const_generics(2)]
32773#[cfg_attr(
32774    not(target_arch = "arm"),
32775    stable(feature = "neon_intrinsics", since = "1.59.0")
32776)]
32777#[cfg_attr(
32778    target_arch = "arm",
32779    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32780)]
32781pub fn vmul_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
32782    static_assert_uimm_bits!(LANE, 2);
32783    unsafe {
32784        simd_mul(
32785            a,
32786            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32787        )
32788    }
32789}
32790#[doc = "Multiply"]
32791#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s16)"]
32792#[inline]
32793#[target_feature(enable = "neon")]
32794#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32795#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32796#[cfg_attr(
32797    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32798    assert_instr(mul, LANE = 1)
32799)]
32800#[rustc_legacy_const_generics(2)]
32801#[cfg_attr(
32802    not(target_arch = "arm"),
32803    stable(feature = "neon_intrinsics", since = "1.59.0")
32804)]
32805#[cfg_attr(
32806    target_arch = "arm",
32807    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32808)]
32809pub fn vmulq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x8_t {
32810    static_assert_uimm_bits!(LANE, 2);
32811    unsafe {
32812        simd_mul(
32813            a,
32814            simd_shuffle!(
32815                b,
32816                b,
32817                [
32818                    LANE as u32,
32819                    LANE as u32,
32820                    LANE as u32,
32821                    LANE as u32,
32822                    LANE as u32,
32823                    LANE as u32,
32824                    LANE as u32,
32825                    LANE as u32
32826                ]
32827            ),
32828        )
32829    }
32830}
32831#[doc = "Multiply"]
32832#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s32)"]
32833#[inline]
32834#[target_feature(enable = "neon")]
32835#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32836#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32837#[cfg_attr(
32838    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32839    assert_instr(mul, LANE = 1)
32840)]
32841#[rustc_legacy_const_generics(2)]
32842#[cfg_attr(
32843    not(target_arch = "arm"),
32844    stable(feature = "neon_intrinsics", since = "1.59.0")
32845)]
32846#[cfg_attr(
32847    target_arch = "arm",
32848    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32849)]
32850pub fn vmul_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
32851    static_assert_uimm_bits!(LANE, 1);
32852    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
32853}
32854#[doc = "Multiply"]
32855#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s32)"]
32856#[inline]
32857#[target_feature(enable = "neon")]
32858#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32859#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32860#[cfg_attr(
32861    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32862    assert_instr(mul, LANE = 1)
32863)]
32864#[rustc_legacy_const_generics(2)]
32865#[cfg_attr(
32866    not(target_arch = "arm"),
32867    stable(feature = "neon_intrinsics", since = "1.59.0")
32868)]
32869#[cfg_attr(
32870    target_arch = "arm",
32871    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32872)]
32873pub fn vmulq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x4_t {
32874    static_assert_uimm_bits!(LANE, 1);
32875    unsafe {
32876        simd_mul(
32877            a,
32878            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32879        )
32880    }
32881}
32882#[doc = "Multiply"]
32883#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u16)"]
32884#[inline]
32885#[target_feature(enable = "neon")]
32886#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32887#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32888#[cfg_attr(
32889    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32890    assert_instr(mul, LANE = 1)
32891)]
32892#[rustc_legacy_const_generics(2)]
32893#[cfg_attr(
32894    not(target_arch = "arm"),
32895    stable(feature = "neon_intrinsics", since = "1.59.0")
32896)]
32897#[cfg_attr(
32898    target_arch = "arm",
32899    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32900)]
32901pub fn vmul_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
32902    static_assert_uimm_bits!(LANE, 2);
32903    unsafe {
32904        simd_mul(
32905            a,
32906            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32907        )
32908    }
32909}
32910#[doc = "Multiply"]
32911#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u16)"]
32912#[inline]
32913#[target_feature(enable = "neon")]
32914#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32915#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32916#[cfg_attr(
32917    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32918    assert_instr(mul, LANE = 1)
32919)]
32920#[rustc_legacy_const_generics(2)]
32921#[cfg_attr(
32922    not(target_arch = "arm"),
32923    stable(feature = "neon_intrinsics", since = "1.59.0")
32924)]
32925#[cfg_attr(
32926    target_arch = "arm",
32927    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32928)]
32929pub fn vmulq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uint16x8_t {
32930    static_assert_uimm_bits!(LANE, 2);
32931    unsafe {
32932        simd_mul(
32933            a,
32934            simd_shuffle!(
32935                b,
32936                b,
32937                [
32938                    LANE as u32,
32939                    LANE as u32,
32940                    LANE as u32,
32941                    LANE as u32,
32942                    LANE as u32,
32943                    LANE as u32,
32944                    LANE as u32,
32945                    LANE as u32
32946                ]
32947            ),
32948        )
32949    }
32950}
32951#[doc = "Multiply"]
32952#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u32)"]
32953#[inline]
32954#[target_feature(enable = "neon")]
32955#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32956#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32957#[cfg_attr(
32958    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32959    assert_instr(mul, LANE = 1)
32960)]
32961#[rustc_legacy_const_generics(2)]
32962#[cfg_attr(
32963    not(target_arch = "arm"),
32964    stable(feature = "neon_intrinsics", since = "1.59.0")
32965)]
32966#[cfg_attr(
32967    target_arch = "arm",
32968    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32969)]
32970pub fn vmul_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
32971    static_assert_uimm_bits!(LANE, 1);
32972    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
32973}
32974#[doc = "Multiply"]
32975#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u32)"]
32976#[inline]
32977#[target_feature(enable = "neon")]
32978#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32979#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32980#[cfg_attr(
32981    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32982    assert_instr(mul, LANE = 1)
32983)]
32984#[rustc_legacy_const_generics(2)]
32985#[cfg_attr(
32986    not(target_arch = "arm"),
32987    stable(feature = "neon_intrinsics", since = "1.59.0")
32988)]
32989#[cfg_attr(
32990    target_arch = "arm",
32991    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32992)]
32993pub fn vmulq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uint32x4_t {
32994    static_assert_uimm_bits!(LANE, 1);
32995    unsafe {
32996        simd_mul(
32997            a,
32998            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32999        )
33000    }
33001}
33002#[doc = "Multiply"]
33003#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s16)"]
33004#[inline]
33005#[target_feature(enable = "neon")]
33006#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33007#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33008#[cfg_attr(
33009    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33010    assert_instr(mul, LANE = 1)
33011)]
33012#[rustc_legacy_const_generics(2)]
33013#[cfg_attr(
33014    not(target_arch = "arm"),
33015    stable(feature = "neon_intrinsics", since = "1.59.0")
33016)]
33017#[cfg_attr(
33018    target_arch = "arm",
33019    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33020)]
33021pub fn vmul_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t {
33022    static_assert_uimm_bits!(LANE, 3);
33023    unsafe {
33024        simd_mul(
33025            a,
33026            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33027        )
33028    }
33029}
33030#[doc = "Multiply"]
33031#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s16)"]
33032#[inline]
33033#[target_feature(enable = "neon")]
33034#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33035#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33036#[cfg_attr(
33037    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33038    assert_instr(mul, LANE = 1)
33039)]
33040#[rustc_legacy_const_generics(2)]
33041#[cfg_attr(
33042    not(target_arch = "arm"),
33043    stable(feature = "neon_intrinsics", since = "1.59.0")
33044)]
33045#[cfg_attr(
33046    target_arch = "arm",
33047    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33048)]
33049pub fn vmulq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
33050    static_assert_uimm_bits!(LANE, 3);
33051    unsafe {
33052        simd_mul(
33053            a,
33054            simd_shuffle!(
33055                b,
33056                b,
33057                [
33058                    LANE as u32,
33059                    LANE as u32,
33060                    LANE as u32,
33061                    LANE as u32,
33062                    LANE as u32,
33063                    LANE as u32,
33064                    LANE as u32,
33065                    LANE as u32
33066                ]
33067            ),
33068        )
33069    }
33070}
33071#[doc = "Multiply"]
33072#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s32)"]
33073#[inline]
33074#[target_feature(enable = "neon")]
33075#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33076#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33077#[cfg_attr(
33078    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33079    assert_instr(mul, LANE = 1)
33080)]
33081#[rustc_legacy_const_generics(2)]
33082#[cfg_attr(
33083    not(target_arch = "arm"),
33084    stable(feature = "neon_intrinsics", since = "1.59.0")
33085)]
33086#[cfg_attr(
33087    target_arch = "arm",
33088    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33089)]
33090pub fn vmul_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t {
33091    static_assert_uimm_bits!(LANE, 2);
33092    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
33093}
33094#[doc = "Multiply"]
33095#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s32)"]
33096#[inline]
33097#[target_feature(enable = "neon")]
33098#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33099#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33100#[cfg_attr(
33101    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33102    assert_instr(mul, LANE = 1)
33103)]
33104#[rustc_legacy_const_generics(2)]
33105#[cfg_attr(
33106    not(target_arch = "arm"),
33107    stable(feature = "neon_intrinsics", since = "1.59.0")
33108)]
33109#[cfg_attr(
33110    target_arch = "arm",
33111    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33112)]
33113pub fn vmulq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
33114    static_assert_uimm_bits!(LANE, 2);
33115    unsafe {
33116        simd_mul(
33117            a,
33118            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33119        )
33120    }
33121}
33122#[doc = "Multiply"]
33123#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u16)"]
33124#[inline]
33125#[target_feature(enable = "neon")]
33126#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33127#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33128#[cfg_attr(
33129    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33130    assert_instr(mul, LANE = 1)
33131)]
33132#[rustc_legacy_const_generics(2)]
33133#[cfg_attr(
33134    not(target_arch = "arm"),
33135    stable(feature = "neon_intrinsics", since = "1.59.0")
33136)]
33137#[cfg_attr(
33138    target_arch = "arm",
33139    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33140)]
33141pub fn vmul_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x8_t) -> uint16x4_t {
33142    static_assert_uimm_bits!(LANE, 3);
33143    unsafe {
33144        simd_mul(
33145            a,
33146            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33147        )
33148    }
33149}
33150#[doc = "Multiply"]
33151#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u16)"]
33152#[inline]
33153#[target_feature(enable = "neon")]
33154#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33155#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33156#[cfg_attr(
33157    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33158    assert_instr(mul, LANE = 1)
33159)]
33160#[rustc_legacy_const_generics(2)]
33161#[cfg_attr(
33162    not(target_arch = "arm"),
33163    stable(feature = "neon_intrinsics", since = "1.59.0")
33164)]
33165#[cfg_attr(
33166    target_arch = "arm",
33167    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33168)]
33169pub fn vmulq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
33170    static_assert_uimm_bits!(LANE, 3);
33171    unsafe {
33172        simd_mul(
33173            a,
33174            simd_shuffle!(
33175                b,
33176                b,
33177                [
33178                    LANE as u32,
33179                    LANE as u32,
33180                    LANE as u32,
33181                    LANE as u32,
33182                    LANE as u32,
33183                    LANE as u32,
33184                    LANE as u32,
33185                    LANE as u32
33186                ]
33187            ),
33188        )
33189    }
33190}
33191#[doc = "Multiply"]
33192#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u32)"]
33193#[inline]
33194#[target_feature(enable = "neon")]
33195#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33196#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33197#[cfg_attr(
33198    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33199    assert_instr(mul, LANE = 1)
33200)]
33201#[rustc_legacy_const_generics(2)]
33202#[cfg_attr(
33203    not(target_arch = "arm"),
33204    stable(feature = "neon_intrinsics", since = "1.59.0")
33205)]
33206#[cfg_attr(
33207    target_arch = "arm",
33208    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33209)]
33210pub fn vmul_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x4_t) -> uint32x2_t {
33211    static_assert_uimm_bits!(LANE, 2);
33212    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
33213}
33214#[doc = "Multiply"]
33215#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u32)"]
33216#[inline]
33217#[target_feature(enable = "neon")]
33218#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33219#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33220#[cfg_attr(
33221    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33222    assert_instr(mul, LANE = 1)
33223)]
33224#[rustc_legacy_const_generics(2)]
33225#[cfg_attr(
33226    not(target_arch = "arm"),
33227    stable(feature = "neon_intrinsics", since = "1.59.0")
33228)]
33229#[cfg_attr(
33230    target_arch = "arm",
33231    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33232)]
33233pub fn vmulq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
33234    static_assert_uimm_bits!(LANE, 2);
33235    unsafe {
33236        simd_mul(
33237            a,
33238            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33239        )
33240    }
33241}
33242#[doc = "Vector multiply by scalar"]
33243#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f16)"]
33244#[inline]
33245#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
33246#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33247#[cfg_attr(
33248    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33249    assert_instr(fmul)
33250)]
33251#[target_feature(enable = "neon,fp16")]
33252#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
33253pub fn vmul_n_f16(a: float16x4_t, b: f16) -> float16x4_t {
33254    unsafe { simd_mul(a, vdup_n_f16(b)) }
33255}
33256#[doc = "Vector multiply by scalar"]
33257#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f16)"]
33258#[inline]
33259#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
33260#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33261#[cfg_attr(
33262    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33263    assert_instr(fmul)
33264)]
33265#[target_feature(enable = "neon,fp16")]
33266#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
33267pub fn vmulq_n_f16(a: float16x8_t, b: f16) -> float16x8_t {
33268    unsafe { simd_mul(a, vdupq_n_f16(b)) }
33269}
33270#[doc = "Vector multiply by scalar"]
33271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f32)"]
33272#[inline]
33273#[target_feature(enable = "neon")]
33274#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33275#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33276#[cfg_attr(
33277    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33278    assert_instr(fmul)
33279)]
33280#[cfg_attr(
33281    not(target_arch = "arm"),
33282    stable(feature = "neon_intrinsics", since = "1.59.0")
33283)]
33284#[cfg_attr(
33285    target_arch = "arm",
33286    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33287)]
33288pub fn vmul_n_f32(a: float32x2_t, b: f32) -> float32x2_t {
33289    unsafe { simd_mul(a, vdup_n_f32(b)) }
33290}
33291#[doc = "Vector multiply by scalar"]
33292#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f32)"]
33293#[inline]
33294#[target_feature(enable = "neon")]
33295#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33296#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33297#[cfg_attr(
33298    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33299    assert_instr(fmul)
33300)]
33301#[cfg_attr(
33302    not(target_arch = "arm"),
33303    stable(feature = "neon_intrinsics", since = "1.59.0")
33304)]
33305#[cfg_attr(
33306    target_arch = "arm",
33307    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33308)]
33309pub fn vmulq_n_f32(a: float32x4_t, b: f32) -> float32x4_t {
33310    unsafe { simd_mul(a, vdupq_n_f32(b)) }
33311}
33312#[doc = "Vector multiply by scalar"]
33313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s16)"]
33314#[inline]
33315#[target_feature(enable = "neon")]
33316#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33317#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33318#[cfg_attr(
33319    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33320    assert_instr(mul)
33321)]
33322#[cfg_attr(
33323    not(target_arch = "arm"),
33324    stable(feature = "neon_intrinsics", since = "1.59.0")
33325)]
33326#[cfg_attr(
33327    target_arch = "arm",
33328    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33329)]
33330pub fn vmul_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
33331    unsafe { simd_mul(a, vdup_n_s16(b)) }
33332}
33333#[doc = "Vector multiply by scalar"]
33334#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s16)"]
33335#[inline]
33336#[target_feature(enable = "neon")]
33337#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33338#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33339#[cfg_attr(
33340    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33341    assert_instr(mul)
33342)]
33343#[cfg_attr(
33344    not(target_arch = "arm"),
33345    stable(feature = "neon_intrinsics", since = "1.59.0")
33346)]
33347#[cfg_attr(
33348    target_arch = "arm",
33349    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33350)]
33351pub fn vmulq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
33352    unsafe { simd_mul(a, vdupq_n_s16(b)) }
33353}
33354#[doc = "Vector multiply by scalar"]
33355#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s32)"]
33356#[inline]
33357#[target_feature(enable = "neon")]
33358#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33359#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33360#[cfg_attr(
33361    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33362    assert_instr(mul)
33363)]
33364#[cfg_attr(
33365    not(target_arch = "arm"),
33366    stable(feature = "neon_intrinsics", since = "1.59.0")
33367)]
33368#[cfg_attr(
33369    target_arch = "arm",
33370    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33371)]
33372pub fn vmul_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
33373    unsafe { simd_mul(a, vdup_n_s32(b)) }
33374}
33375#[doc = "Vector multiply by scalar"]
33376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s32)"]
33377#[inline]
33378#[target_feature(enable = "neon")]
33379#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33380#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33381#[cfg_attr(
33382    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33383    assert_instr(mul)
33384)]
33385#[cfg_attr(
33386    not(target_arch = "arm"),
33387    stable(feature = "neon_intrinsics", since = "1.59.0")
33388)]
33389#[cfg_attr(
33390    target_arch = "arm",
33391    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33392)]
33393pub fn vmulq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
33394    unsafe { simd_mul(a, vdupq_n_s32(b)) }
33395}
33396#[doc = "Vector multiply by scalar"]
33397#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u16)"]
33398#[inline]
33399#[target_feature(enable = "neon")]
33400#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33401#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33402#[cfg_attr(
33403    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33404    assert_instr(mul)
33405)]
33406#[cfg_attr(
33407    not(target_arch = "arm"),
33408    stable(feature = "neon_intrinsics", since = "1.59.0")
33409)]
33410#[cfg_attr(
33411    target_arch = "arm",
33412    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33413)]
33414pub fn vmul_n_u16(a: uint16x4_t, b: u16) -> uint16x4_t {
33415    unsafe { simd_mul(a, vdup_n_u16(b)) }
33416}
33417#[doc = "Vector multiply by scalar"]
33418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u16)"]
33419#[inline]
33420#[target_feature(enable = "neon")]
33421#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33422#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33423#[cfg_attr(
33424    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33425    assert_instr(mul)
33426)]
33427#[cfg_attr(
33428    not(target_arch = "arm"),
33429    stable(feature = "neon_intrinsics", since = "1.59.0")
33430)]
33431#[cfg_attr(
33432    target_arch = "arm",
33433    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33434)]
33435pub fn vmulq_n_u16(a: uint16x8_t, b: u16) -> uint16x8_t {
33436    unsafe { simd_mul(a, vdupq_n_u16(b)) }
33437}
33438#[doc = "Vector multiply by scalar"]
33439#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u32)"]
33440#[inline]
33441#[target_feature(enable = "neon")]
33442#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33443#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33444#[cfg_attr(
33445    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33446    assert_instr(mul)
33447)]
33448#[cfg_attr(
33449    not(target_arch = "arm"),
33450    stable(feature = "neon_intrinsics", since = "1.59.0")
33451)]
33452#[cfg_attr(
33453    target_arch = "arm",
33454    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33455)]
33456pub fn vmul_n_u32(a: uint32x2_t, b: u32) -> uint32x2_t {
33457    unsafe { simd_mul(a, vdup_n_u32(b)) }
33458}
33459#[doc = "Vector multiply by scalar"]
33460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u32)"]
33461#[inline]
33462#[target_feature(enable = "neon")]
33463#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33464#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33465#[cfg_attr(
33466    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33467    assert_instr(mul)
33468)]
33469#[cfg_attr(
33470    not(target_arch = "arm"),
33471    stable(feature = "neon_intrinsics", since = "1.59.0")
33472)]
33473#[cfg_attr(
33474    target_arch = "arm",
33475    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33476)]
33477pub fn vmulq_n_u32(a: uint32x4_t, b: u32) -> uint32x4_t {
33478    unsafe { simd_mul(a, vdupq_n_u32(b)) }
33479}
33480#[doc = "Polynomial multiply"]
33481#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_p8)"]
33482#[inline]
33483#[target_feature(enable = "neon")]
33484#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33485#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33486#[cfg_attr(
33487    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33488    assert_instr(pmul)
33489)]
33490#[cfg_attr(
33491    not(target_arch = "arm"),
33492    stable(feature = "neon_intrinsics", since = "1.59.0")
33493)]
33494#[cfg_attr(
33495    target_arch = "arm",
33496    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33497)]
33498pub fn vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
33499    unsafe extern "unadjusted" {
33500        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulp.v8i8")]
33501        #[cfg_attr(
33502            any(target_arch = "aarch64", target_arch = "arm64ec"),
33503            link_name = "llvm.aarch64.neon.pmul.v8i8"
33504        )]
33505        fn _vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t;
33506    }
33507    unsafe { _vmul_p8(a, b) }
33508}
33509#[doc = "Polynomial multiply"]
33510#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_p8)"]
33511#[inline]
33512#[target_feature(enable = "neon")]
33513#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33514#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33515#[cfg_attr(
33516    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33517    assert_instr(pmul)
33518)]
33519#[cfg_attr(
33520    not(target_arch = "arm"),
33521    stable(feature = "neon_intrinsics", since = "1.59.0")
33522)]
33523#[cfg_attr(
33524    target_arch = "arm",
33525    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33526)]
33527pub fn vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
33528    unsafe extern "unadjusted" {
33529        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulp.v16i8")]
33530        #[cfg_attr(
33531            any(target_arch = "aarch64", target_arch = "arm64ec"),
33532            link_name = "llvm.aarch64.neon.pmul.v16i8"
33533        )]
33534        fn _vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t;
33535    }
33536    unsafe { _vmulq_p8(a, b) }
33537}
33538#[doc = "Multiply"]
33539#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s16)"]
33540#[inline]
33541#[target_feature(enable = "neon")]
33542#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33543#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
33544#[cfg_attr(
33545    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33546    assert_instr(mul)
33547)]
33548#[cfg_attr(
33549    not(target_arch = "arm"),
33550    stable(feature = "neon_intrinsics", since = "1.59.0")
33551)]
33552#[cfg_attr(
33553    target_arch = "arm",
33554    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33555)]
33556pub fn vmul_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
33557    unsafe { simd_mul(a, b) }
33558}
33559#[doc = "Multiply"]
33560#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s16)"]
33561#[inline]
33562#[target_feature(enable = "neon")]
33563#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33564#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
33565#[cfg_attr(
33566    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33567    assert_instr(mul)
33568)]
33569#[cfg_attr(
33570    not(target_arch = "arm"),
33571    stable(feature = "neon_intrinsics", since = "1.59.0")
33572)]
33573#[cfg_attr(
33574    target_arch = "arm",
33575    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33576)]
33577pub fn vmulq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
33578    unsafe { simd_mul(a, b) }
33579}
33580#[doc = "Multiply"]
33581#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u16)"]
33582#[inline]
33583#[target_feature(enable = "neon")]
33584#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33585#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
33586#[cfg_attr(
33587    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33588    assert_instr(mul)
33589)]
33590#[cfg_attr(
33591    not(target_arch = "arm"),
33592    stable(feature = "neon_intrinsics", since = "1.59.0")
33593)]
33594#[cfg_attr(
33595    target_arch = "arm",
33596    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33597)]
33598pub fn vmul_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
33599    unsafe { simd_mul(a, b) }
33600}
33601#[doc = "Multiply"]
33602#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u16)"]
33603#[inline]
33604#[target_feature(enable = "neon")]
33605#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33606#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
33607#[cfg_attr(
33608    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33609    assert_instr(mul)
33610)]
33611#[cfg_attr(
33612    not(target_arch = "arm"),
33613    stable(feature = "neon_intrinsics", since = "1.59.0")
33614)]
33615#[cfg_attr(
33616    target_arch = "arm",
33617    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33618)]
33619pub fn vmulq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
33620    unsafe { simd_mul(a, b) }
33621}
33622#[doc = "Multiply"]
33623#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s32)"]
33624#[inline]
33625#[target_feature(enable = "neon")]
33626#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33627#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
33628#[cfg_attr(
33629    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33630    assert_instr(mul)
33631)]
33632#[cfg_attr(
33633    not(target_arch = "arm"),
33634    stable(feature = "neon_intrinsics", since = "1.59.0")
33635)]
33636#[cfg_attr(
33637    target_arch = "arm",
33638    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33639)]
33640pub fn vmul_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
33641    unsafe { simd_mul(a, b) }
33642}
33643#[doc = "Multiply"]
33644#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s32)"]
33645#[inline]
33646#[target_feature(enable = "neon")]
33647#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33648#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
33649#[cfg_attr(
33650    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33651    assert_instr(mul)
33652)]
33653#[cfg_attr(
33654    not(target_arch = "arm"),
33655    stable(feature = "neon_intrinsics", since = "1.59.0")
33656)]
33657#[cfg_attr(
33658    target_arch = "arm",
33659    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33660)]
33661pub fn vmulq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
33662    unsafe { simd_mul(a, b) }
33663}
33664#[doc = "Multiply"]
33665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u32)"]
33666#[inline]
33667#[target_feature(enable = "neon")]
33668#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33669#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
33670#[cfg_attr(
33671    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33672    assert_instr(mul)
33673)]
33674#[cfg_attr(
33675    not(target_arch = "arm"),
33676    stable(feature = "neon_intrinsics", since = "1.59.0")
33677)]
33678#[cfg_attr(
33679    target_arch = "arm",
33680    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33681)]
33682pub fn vmul_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
33683    unsafe { simd_mul(a, b) }
33684}
33685#[doc = "Multiply"]
33686#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u32)"]
33687#[inline]
33688#[target_feature(enable = "neon")]
33689#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33690#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
33691#[cfg_attr(
33692    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33693    assert_instr(mul)
33694)]
33695#[cfg_attr(
33696    not(target_arch = "arm"),
33697    stable(feature = "neon_intrinsics", since = "1.59.0")
33698)]
33699#[cfg_attr(
33700    target_arch = "arm",
33701    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33702)]
33703pub fn vmulq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
33704    unsafe { simd_mul(a, b) }
33705}
33706#[doc = "Multiply"]
33707#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s8)"]
33708#[inline]
33709#[target_feature(enable = "neon")]
33710#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33711#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
33712#[cfg_attr(
33713    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33714    assert_instr(mul)
33715)]
33716#[cfg_attr(
33717    not(target_arch = "arm"),
33718    stable(feature = "neon_intrinsics", since = "1.59.0")
33719)]
33720#[cfg_attr(
33721    target_arch = "arm",
33722    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33723)]
33724pub fn vmul_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
33725    unsafe { simd_mul(a, b) }
33726}
33727#[doc = "Multiply"]
33728#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s8)"]
33729#[inline]
33730#[target_feature(enable = "neon")]
33731#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33732#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
33733#[cfg_attr(
33734    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33735    assert_instr(mul)
33736)]
33737#[cfg_attr(
33738    not(target_arch = "arm"),
33739    stable(feature = "neon_intrinsics", since = "1.59.0")
33740)]
33741#[cfg_attr(
33742    target_arch = "arm",
33743    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33744)]
33745pub fn vmulq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
33746    unsafe { simd_mul(a, b) }
33747}
33748#[doc = "Multiply"]
33749#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u8)"]
33750#[inline]
33751#[target_feature(enable = "neon")]
33752#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33753#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
33754#[cfg_attr(
33755    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33756    assert_instr(mul)
33757)]
33758#[cfg_attr(
33759    not(target_arch = "arm"),
33760    stable(feature = "neon_intrinsics", since = "1.59.0")
33761)]
33762#[cfg_attr(
33763    target_arch = "arm",
33764    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33765)]
33766pub fn vmul_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
33767    unsafe { simd_mul(a, b) }
33768}
33769#[doc = "Multiply"]
33770#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u8)"]
33771#[inline]
33772#[target_feature(enable = "neon")]
33773#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33774#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
33775#[cfg_attr(
33776    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33777    assert_instr(mul)
33778)]
33779#[cfg_attr(
33780    not(target_arch = "arm"),
33781    stable(feature = "neon_intrinsics", since = "1.59.0")
33782)]
33783#[cfg_attr(
33784    target_arch = "arm",
33785    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33786)]
33787pub fn vmulq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
33788    unsafe { simd_mul(a, b) }
33789}
33790#[doc = "Vector long multiply by scalar"]
33791#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s16)"]
33792#[inline]
33793#[target_feature(enable = "neon")]
33794#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33795#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33796#[cfg_attr(
33797    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33798    assert_instr(smull, LANE = 1)
33799)]
33800#[rustc_legacy_const_generics(2)]
33801#[cfg_attr(
33802    not(target_arch = "arm"),
33803    stable(feature = "neon_intrinsics", since = "1.59.0")
33804)]
33805#[cfg_attr(
33806    target_arch = "arm",
33807    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33808)]
33809pub fn vmull_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int32x4_t {
33810    static_assert_uimm_bits!(LANE, 2);
33811    unsafe {
33812        vmull_s16(
33813            a,
33814            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33815        )
33816    }
33817}
33818#[doc = "Vector long multiply by scalar"]
33819#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s16)"]
33820#[inline]
33821#[target_feature(enable = "neon")]
33822#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33823#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33824#[cfg_attr(
33825    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33826    assert_instr(smull, LANE = 1)
33827)]
33828#[rustc_legacy_const_generics(2)]
33829#[cfg_attr(
33830    not(target_arch = "arm"),
33831    stable(feature = "neon_intrinsics", since = "1.59.0")
33832)]
33833#[cfg_attr(
33834    target_arch = "arm",
33835    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33836)]
33837pub fn vmull_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int32x4_t {
33838    static_assert_uimm_bits!(LANE, 3);
33839    unsafe {
33840        vmull_s16(
33841            a,
33842            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33843        )
33844    }
33845}
33846#[doc = "Vector long multiply by scalar"]
33847#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s32)"]
33848#[inline]
33849#[target_feature(enable = "neon")]
33850#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33851#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33852#[cfg_attr(
33853    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33854    assert_instr(smull, LANE = 1)
33855)]
33856#[rustc_legacy_const_generics(2)]
33857#[cfg_attr(
33858    not(target_arch = "arm"),
33859    stable(feature = "neon_intrinsics", since = "1.59.0")
33860)]
33861#[cfg_attr(
33862    target_arch = "arm",
33863    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33864)]
33865pub fn vmull_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int64x2_t {
33866    static_assert_uimm_bits!(LANE, 1);
33867    unsafe { vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
33868}
33869#[doc = "Vector long multiply by scalar"]
33870#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s32)"]
33871#[inline]
33872#[target_feature(enable = "neon")]
33873#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33874#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33875#[cfg_attr(
33876    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33877    assert_instr(smull, LANE = 1)
33878)]
33879#[rustc_legacy_const_generics(2)]
33880#[cfg_attr(
33881    not(target_arch = "arm"),
33882    stable(feature = "neon_intrinsics", since = "1.59.0")
33883)]
33884#[cfg_attr(
33885    target_arch = "arm",
33886    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33887)]
33888pub fn vmull_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int64x2_t {
33889    static_assert_uimm_bits!(LANE, 2);
33890    unsafe { vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
33891}
33892#[doc = "Vector long multiply by scalar"]
33893#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u16)"]
33894#[inline]
33895#[target_feature(enable = "neon")]
33896#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33897#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33898#[cfg_attr(
33899    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33900    assert_instr(umull, LANE = 1)
33901)]
33902#[rustc_legacy_const_generics(2)]
33903#[cfg_attr(
33904    not(target_arch = "arm"),
33905    stable(feature = "neon_intrinsics", since = "1.59.0")
33906)]
33907#[cfg_attr(
33908    target_arch = "arm",
33909    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33910)]
33911pub fn vmull_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
33912    static_assert_uimm_bits!(LANE, 2);
33913    unsafe {
33914        vmull_u16(
33915            a,
33916            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33917        )
33918    }
33919}
33920#[doc = "Vector long multiply by scalar"]
33921#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u16)"]
33922#[inline]
33923#[target_feature(enable = "neon")]
33924#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33925#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33926#[cfg_attr(
33927    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33928    assert_instr(umull, LANE = 1)
33929)]
33930#[rustc_legacy_const_generics(2)]
33931#[cfg_attr(
33932    not(target_arch = "arm"),
33933    stable(feature = "neon_intrinsics", since = "1.59.0")
33934)]
33935#[cfg_attr(
33936    target_arch = "arm",
33937    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33938)]
33939pub fn vmull_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x8_t) -> uint32x4_t {
33940    static_assert_uimm_bits!(LANE, 3);
33941    unsafe {
33942        vmull_u16(
33943            a,
33944            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33945        )
33946    }
33947}
33948#[doc = "Vector long multiply by scalar"]
33949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u32)"]
33950#[inline]
33951#[target_feature(enable = "neon")]
33952#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33953#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33954#[cfg_attr(
33955    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33956    assert_instr(umull, LANE = 1)
33957)]
33958#[rustc_legacy_const_generics(2)]
33959#[cfg_attr(
33960    not(target_arch = "arm"),
33961    stable(feature = "neon_intrinsics", since = "1.59.0")
33962)]
33963#[cfg_attr(
33964    target_arch = "arm",
33965    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33966)]
33967pub fn vmull_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
33968    static_assert_uimm_bits!(LANE, 1);
33969    unsafe { vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
33970}
33971#[doc = "Vector long multiply by scalar"]
33972#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u32)"]
33973#[inline]
33974#[target_feature(enable = "neon")]
33975#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33976#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33977#[cfg_attr(
33978    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33979    assert_instr(umull, LANE = 1)
33980)]
33981#[rustc_legacy_const_generics(2)]
33982#[cfg_attr(
33983    not(target_arch = "arm"),
33984    stable(feature = "neon_intrinsics", since = "1.59.0")
33985)]
33986#[cfg_attr(
33987    target_arch = "arm",
33988    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33989)]
33990pub fn vmull_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x4_t) -> uint64x2_t {
33991    static_assert_uimm_bits!(LANE, 2);
33992    unsafe { vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
33993}
33994#[doc = "Vector long multiply with scalar"]
33995#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s16)"]
33996#[inline]
33997#[target_feature(enable = "neon")]
33998#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33999#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
34000#[cfg_attr(
34001    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34002    assert_instr(smull)
34003)]
34004#[cfg_attr(
34005    not(target_arch = "arm"),
34006    stable(feature = "neon_intrinsics", since = "1.59.0")
34007)]
34008#[cfg_attr(
34009    target_arch = "arm",
34010    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34011)]
34012pub fn vmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t {
34013    vmull_s16(a, vdup_n_s16(b))
34014}
34015#[doc = "Vector long multiply with scalar"]
34016#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s32)"]
34017#[inline]
34018#[target_feature(enable = "neon")]
34019#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34020#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
34021#[cfg_attr(
34022    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34023    assert_instr(smull)
34024)]
34025#[cfg_attr(
34026    not(target_arch = "arm"),
34027    stable(feature = "neon_intrinsics", since = "1.59.0")
34028)]
34029#[cfg_attr(
34030    target_arch = "arm",
34031    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34032)]
34033pub fn vmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t {
34034    vmull_s32(a, vdup_n_s32(b))
34035}
34036#[doc = "Vector long multiply with scalar"]
34037#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u16)"]
34038#[inline]
34039#[target_feature(enable = "neon")]
34040#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34041#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
34042#[cfg_attr(
34043    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34044    assert_instr(umull)
34045)]
34046#[cfg_attr(
34047    not(target_arch = "arm"),
34048    stable(feature = "neon_intrinsics", since = "1.59.0")
34049)]
34050#[cfg_attr(
34051    target_arch = "arm",
34052    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34053)]
34054pub fn vmull_n_u16(a: uint16x4_t, b: u16) -> uint32x4_t {
34055    vmull_u16(a, vdup_n_u16(b))
34056}
34057#[doc = "Vector long multiply with scalar"]
34058#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u32)"]
34059#[inline]
34060#[target_feature(enable = "neon")]
34061#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34062#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
34063#[cfg_attr(
34064    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34065    assert_instr(umull)
34066)]
34067#[cfg_attr(
34068    not(target_arch = "arm"),
34069    stable(feature = "neon_intrinsics", since = "1.59.0")
34070)]
34071#[cfg_attr(
34072    target_arch = "arm",
34073    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34074)]
34075pub fn vmull_n_u32(a: uint32x2_t, b: u32) -> uint64x2_t {
34076    vmull_u32(a, vdup_n_u32(b))
34077}
34078#[doc = "Polynomial multiply long"]
34079#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p8)"]
34080#[inline]
34081#[target_feature(enable = "neon")]
34082#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34083#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.p8"))]
34084#[cfg_attr(
34085    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34086    assert_instr(pmull)
34087)]
34088#[cfg_attr(
34089    not(target_arch = "arm"),
34090    stable(feature = "neon_intrinsics", since = "1.59.0")
34091)]
34092#[cfg_attr(
34093    target_arch = "arm",
34094    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34095)]
34096pub fn vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t {
34097    unsafe extern "unadjusted" {
34098        #[cfg_attr(
34099            any(target_arch = "aarch64", target_arch = "arm64ec"),
34100            link_name = "llvm.aarch64.neon.pmull.v8i16"
34101        )]
34102        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullp.v8i16")]
34103        fn _vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t;
34104    }
34105    unsafe { _vmull_p8(a, b) }
34106}
34107#[doc = "Signed multiply long"]
34108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s16)"]
34109#[inline]
34110#[target_feature(enable = "neon")]
34111#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34112#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s16"))]
34113#[cfg_attr(
34114    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34115    assert_instr(smull)
34116)]
34117#[cfg_attr(
34118    not(target_arch = "arm"),
34119    stable(feature = "neon_intrinsics", since = "1.59.0")
34120)]
34121#[cfg_attr(
34122    target_arch = "arm",
34123    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34124)]
34125pub fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
34126    unsafe extern "unadjusted" {
34127        #[cfg_attr(
34128            any(target_arch = "aarch64", target_arch = "arm64ec"),
34129            link_name = "llvm.aarch64.neon.smull.v4i32"
34130        )]
34131        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v4i32")]
34132        fn _vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t;
34133    }
34134    unsafe { _vmull_s16(a, b) }
34135}
34136#[doc = "Signed multiply long"]
34137#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s32)"]
34138#[inline]
34139#[target_feature(enable = "neon")]
34140#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34141#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s32"))]
34142#[cfg_attr(
34143    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34144    assert_instr(smull)
34145)]
34146#[cfg_attr(
34147    not(target_arch = "arm"),
34148    stable(feature = "neon_intrinsics", since = "1.59.0")
34149)]
34150#[cfg_attr(
34151    target_arch = "arm",
34152    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34153)]
34154pub fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
34155    unsafe extern "unadjusted" {
34156        #[cfg_attr(
34157            any(target_arch = "aarch64", target_arch = "arm64ec"),
34158            link_name = "llvm.aarch64.neon.smull.v2i64"
34159        )]
34160        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v2i64")]
34161        fn _vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t;
34162    }
34163    unsafe { _vmull_s32(a, b) }
34164}
34165#[doc = "Signed multiply long"]
34166#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s8)"]
34167#[inline]
34168#[target_feature(enable = "neon")]
34169#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34170#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s8"))]
34171#[cfg_attr(
34172    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34173    assert_instr(smull)
34174)]
34175#[cfg_attr(
34176    not(target_arch = "arm"),
34177    stable(feature = "neon_intrinsics", since = "1.59.0")
34178)]
34179#[cfg_attr(
34180    target_arch = "arm",
34181    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34182)]
34183pub fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
34184    unsafe extern "unadjusted" {
34185        #[cfg_attr(
34186            any(target_arch = "aarch64", target_arch = "arm64ec"),
34187            link_name = "llvm.aarch64.neon.smull.v8i16"
34188        )]
34189        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v8i16")]
34190        fn _vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t;
34191    }
34192    unsafe { _vmull_s8(a, b) }
34193}
34194#[doc = "Unsigned multiply long"]
34195#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u8)"]
34196#[inline]
34197#[target_feature(enable = "neon")]
34198#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34199#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u8"))]
34200#[cfg_attr(
34201    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34202    assert_instr(umull)
34203)]
34204#[cfg_attr(
34205    not(target_arch = "arm"),
34206    stable(feature = "neon_intrinsics", since = "1.59.0")
34207)]
34208#[cfg_attr(
34209    target_arch = "arm",
34210    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34211)]
34212pub fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
34213    unsafe extern "unadjusted" {
34214        #[cfg_attr(
34215            any(target_arch = "aarch64", target_arch = "arm64ec"),
34216            link_name = "llvm.aarch64.neon.umull.v8i16"
34217        )]
34218        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v8i16")]
34219        fn _vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t;
34220    }
34221    unsafe { _vmull_u8(a, b) }
34222}
34223#[doc = "Unsigned multiply long"]
34224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u16)"]
34225#[inline]
34226#[target_feature(enable = "neon")]
34227#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34228#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u16"))]
34229#[cfg_attr(
34230    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34231    assert_instr(umull)
34232)]
34233#[cfg_attr(
34234    not(target_arch = "arm"),
34235    stable(feature = "neon_intrinsics", since = "1.59.0")
34236)]
34237#[cfg_attr(
34238    target_arch = "arm",
34239    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34240)]
34241pub fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
34242    unsafe extern "unadjusted" {
34243        #[cfg_attr(
34244            any(target_arch = "aarch64", target_arch = "arm64ec"),
34245            link_name = "llvm.aarch64.neon.umull.v4i32"
34246        )]
34247        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v4i32")]
34248        fn _vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t;
34249    }
34250    unsafe { _vmull_u16(a, b) }
34251}
34252#[doc = "Unsigned multiply long"]
34253#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u32)"]
34254#[inline]
34255#[target_feature(enable = "neon")]
34256#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34257#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u32"))]
34258#[cfg_attr(
34259    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34260    assert_instr(umull)
34261)]
34262#[cfg_attr(
34263    not(target_arch = "arm"),
34264    stable(feature = "neon_intrinsics", since = "1.59.0")
34265)]
34266#[cfg_attr(
34267    target_arch = "arm",
34268    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34269)]
34270pub fn vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
34271    unsafe extern "unadjusted" {
34272        #[cfg_attr(
34273            any(target_arch = "aarch64", target_arch = "arm64ec"),
34274            link_name = "llvm.aarch64.neon.umull.v2i64"
34275        )]
34276        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v2i64")]
34277        fn _vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t;
34278    }
34279    unsafe { _vmull_u32(a, b) }
34280}
34281#[doc = "Vector bitwise not."]
34282#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_p8)"]
34283#[inline]
34284#[target_feature(enable = "neon")]
34285#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34286#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34287#[cfg_attr(
34288    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34289    assert_instr(mvn)
34290)]
34291#[cfg_attr(
34292    not(target_arch = "arm"),
34293    stable(feature = "neon_intrinsics", since = "1.59.0")
34294)]
34295#[cfg_attr(
34296    target_arch = "arm",
34297    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34298)]
34299pub fn vmvn_p8(a: poly8x8_t) -> poly8x8_t {
34300    let b = poly8x8_t::splat(255);
34301    unsafe { simd_xor(a, b) }
34302}
34303#[doc = "Vector bitwise not."]
34304#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s16)"]
34305#[inline]
34306#[target_feature(enable = "neon")]
34307#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34308#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34309#[cfg_attr(
34310    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34311    assert_instr(mvn)
34312)]
34313#[cfg_attr(
34314    not(target_arch = "arm"),
34315    stable(feature = "neon_intrinsics", since = "1.59.0")
34316)]
34317#[cfg_attr(
34318    target_arch = "arm",
34319    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34320)]
34321pub fn vmvn_s16(a: int16x4_t) -> int16x4_t {
34322    let b = int16x4_t::splat(-1);
34323    unsafe { simd_xor(a, b) }
34324}
34325#[doc = "Vector bitwise not."]
34326#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s32)"]
34327#[inline]
34328#[target_feature(enable = "neon")]
34329#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34330#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34331#[cfg_attr(
34332    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34333    assert_instr(mvn)
34334)]
34335#[cfg_attr(
34336    not(target_arch = "arm"),
34337    stable(feature = "neon_intrinsics", since = "1.59.0")
34338)]
34339#[cfg_attr(
34340    target_arch = "arm",
34341    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34342)]
34343pub fn vmvn_s32(a: int32x2_t) -> int32x2_t {
34344    let b = int32x2_t::splat(-1);
34345    unsafe { simd_xor(a, b) }
34346}
34347#[doc = "Vector bitwise not."]
34348#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s8)"]
34349#[inline]
34350#[target_feature(enable = "neon")]
34351#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34352#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34353#[cfg_attr(
34354    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34355    assert_instr(mvn)
34356)]
34357#[cfg_attr(
34358    not(target_arch = "arm"),
34359    stable(feature = "neon_intrinsics", since = "1.59.0")
34360)]
34361#[cfg_attr(
34362    target_arch = "arm",
34363    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34364)]
34365pub fn vmvn_s8(a: int8x8_t) -> int8x8_t {
34366    let b = int8x8_t::splat(-1);
34367    unsafe { simd_xor(a, b) }
34368}
34369#[doc = "Vector bitwise not."]
34370#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u16)"]
34371#[inline]
34372#[target_feature(enable = "neon")]
34373#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34374#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34375#[cfg_attr(
34376    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34377    assert_instr(mvn)
34378)]
34379#[cfg_attr(
34380    not(target_arch = "arm"),
34381    stable(feature = "neon_intrinsics", since = "1.59.0")
34382)]
34383#[cfg_attr(
34384    target_arch = "arm",
34385    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34386)]
34387pub fn vmvn_u16(a: uint16x4_t) -> uint16x4_t {
34388    let b = uint16x4_t::splat(65_535);
34389    unsafe { simd_xor(a, b) }
34390}
34391#[doc = "Vector bitwise not."]
34392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u32)"]
34393#[inline]
34394#[target_feature(enable = "neon")]
34395#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34396#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34397#[cfg_attr(
34398    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34399    assert_instr(mvn)
34400)]
34401#[cfg_attr(
34402    not(target_arch = "arm"),
34403    stable(feature = "neon_intrinsics", since = "1.59.0")
34404)]
34405#[cfg_attr(
34406    target_arch = "arm",
34407    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34408)]
34409pub fn vmvn_u32(a: uint32x2_t) -> uint32x2_t {
34410    let b = uint32x2_t::splat(4_294_967_295);
34411    unsafe { simd_xor(a, b) }
34412}
34413#[doc = "Vector bitwise not."]
34414#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u8)"]
34415#[inline]
34416#[target_feature(enable = "neon")]
34417#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34418#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34419#[cfg_attr(
34420    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34421    assert_instr(mvn)
34422)]
34423#[cfg_attr(
34424    not(target_arch = "arm"),
34425    stable(feature = "neon_intrinsics", since = "1.59.0")
34426)]
34427#[cfg_attr(
34428    target_arch = "arm",
34429    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34430)]
34431pub fn vmvn_u8(a: uint8x8_t) -> uint8x8_t {
34432    let b = uint8x8_t::splat(255);
34433    unsafe { simd_xor(a, b) }
34434}
34435#[doc = "Vector bitwise not."]
34436#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_p8)"]
34437#[inline]
34438#[target_feature(enable = "neon")]
34439#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34440#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34441#[cfg_attr(
34442    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34443    assert_instr(mvn)
34444)]
34445#[cfg_attr(
34446    not(target_arch = "arm"),
34447    stable(feature = "neon_intrinsics", since = "1.59.0")
34448)]
34449#[cfg_attr(
34450    target_arch = "arm",
34451    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34452)]
34453pub fn vmvnq_p8(a: poly8x16_t) -> poly8x16_t {
34454    let b = poly8x16_t::splat(255);
34455    unsafe { simd_xor(a, b) }
34456}
34457#[doc = "Vector bitwise not."]
34458#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s16)"]
34459#[inline]
34460#[target_feature(enable = "neon")]
34461#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34462#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34463#[cfg_attr(
34464    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34465    assert_instr(mvn)
34466)]
34467#[cfg_attr(
34468    not(target_arch = "arm"),
34469    stable(feature = "neon_intrinsics", since = "1.59.0")
34470)]
34471#[cfg_attr(
34472    target_arch = "arm",
34473    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34474)]
34475pub fn vmvnq_s16(a: int16x8_t) -> int16x8_t {
34476    let b = int16x8_t::splat(-1);
34477    unsafe { simd_xor(a, b) }
34478}
34479#[doc = "Vector bitwise not."]
34480#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s32)"]
34481#[inline]
34482#[target_feature(enable = "neon")]
34483#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34484#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34485#[cfg_attr(
34486    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34487    assert_instr(mvn)
34488)]
34489#[cfg_attr(
34490    not(target_arch = "arm"),
34491    stable(feature = "neon_intrinsics", since = "1.59.0")
34492)]
34493#[cfg_attr(
34494    target_arch = "arm",
34495    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34496)]
34497pub fn vmvnq_s32(a: int32x4_t) -> int32x4_t {
34498    let b = int32x4_t::splat(-1);
34499    unsafe { simd_xor(a, b) }
34500}
34501#[doc = "Vector bitwise not."]
34502#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s8)"]
34503#[inline]
34504#[target_feature(enable = "neon")]
34505#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34506#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34507#[cfg_attr(
34508    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34509    assert_instr(mvn)
34510)]
34511#[cfg_attr(
34512    not(target_arch = "arm"),
34513    stable(feature = "neon_intrinsics", since = "1.59.0")
34514)]
34515#[cfg_attr(
34516    target_arch = "arm",
34517    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34518)]
34519pub fn vmvnq_s8(a: int8x16_t) -> int8x16_t {
34520    let b = int8x16_t::splat(-1);
34521    unsafe { simd_xor(a, b) }
34522}
34523#[doc = "Vector bitwise not."]
34524#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u16)"]
34525#[inline]
34526#[target_feature(enable = "neon")]
34527#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34528#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34529#[cfg_attr(
34530    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34531    assert_instr(mvn)
34532)]
34533#[cfg_attr(
34534    not(target_arch = "arm"),
34535    stable(feature = "neon_intrinsics", since = "1.59.0")
34536)]
34537#[cfg_attr(
34538    target_arch = "arm",
34539    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34540)]
34541pub fn vmvnq_u16(a: uint16x8_t) -> uint16x8_t {
34542    let b = uint16x8_t::splat(65_535);
34543    unsafe { simd_xor(a, b) }
34544}
34545#[doc = "Vector bitwise not."]
34546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u32)"]
34547#[inline]
34548#[target_feature(enable = "neon")]
34549#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34550#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34551#[cfg_attr(
34552    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34553    assert_instr(mvn)
34554)]
34555#[cfg_attr(
34556    not(target_arch = "arm"),
34557    stable(feature = "neon_intrinsics", since = "1.59.0")
34558)]
34559#[cfg_attr(
34560    target_arch = "arm",
34561    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34562)]
34563pub fn vmvnq_u32(a: uint32x4_t) -> uint32x4_t {
34564    let b = uint32x4_t::splat(4_294_967_295);
34565    unsafe { simd_xor(a, b) }
34566}
34567#[doc = "Vector bitwise not."]
34568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u8)"]
34569#[inline]
34570#[target_feature(enable = "neon")]
34571#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34572#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34573#[cfg_attr(
34574    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34575    assert_instr(mvn)
34576)]
34577#[cfg_attr(
34578    not(target_arch = "arm"),
34579    stable(feature = "neon_intrinsics", since = "1.59.0")
34580)]
34581#[cfg_attr(
34582    target_arch = "arm",
34583    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34584)]
34585pub fn vmvnq_u8(a: uint8x16_t) -> uint8x16_t {
34586    let b = uint8x16_t::splat(255);
34587    unsafe { simd_xor(a, b) }
34588}
34589#[doc = "Negate"]
34590#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f16)"]
34591#[inline]
34592#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
34593#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))]
34594#[cfg_attr(
34595    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34596    assert_instr(fneg)
34597)]
34598#[target_feature(enable = "neon,fp16")]
34599#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
34600pub fn vneg_f16(a: float16x4_t) -> float16x4_t {
34601    unsafe { simd_neg(a) }
34602}
34603#[doc = "Negate"]
34604#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f16)"]
34605#[inline]
34606#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
34607#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))]
34608#[cfg_attr(
34609    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34610    assert_instr(fneg)
34611)]
34612#[target_feature(enable = "neon,fp16")]
34613#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
34614pub fn vnegq_f16(a: float16x8_t) -> float16x8_t {
34615    unsafe { simd_neg(a) }
34616}
34617#[doc = "Negate"]
34618#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f32)"]
34619#[inline]
34620#[target_feature(enable = "neon")]
34621#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34622#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))]
34623#[cfg_attr(
34624    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34625    assert_instr(fneg)
34626)]
34627#[cfg_attr(
34628    not(target_arch = "arm"),
34629    stable(feature = "neon_intrinsics", since = "1.59.0")
34630)]
34631#[cfg_attr(
34632    target_arch = "arm",
34633    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34634)]
34635pub fn vneg_f32(a: float32x2_t) -> float32x2_t {
34636    unsafe { simd_neg(a) }
34637}
34638#[doc = "Negate"]
34639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f32)"]
34640#[inline]
34641#[target_feature(enable = "neon")]
34642#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34643#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))]
34644#[cfg_attr(
34645    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34646    assert_instr(fneg)
34647)]
34648#[cfg_attr(
34649    not(target_arch = "arm"),
34650    stable(feature = "neon_intrinsics", since = "1.59.0")
34651)]
34652#[cfg_attr(
34653    target_arch = "arm",
34654    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34655)]
34656pub fn vnegq_f32(a: float32x4_t) -> float32x4_t {
34657    unsafe { simd_neg(a) }
34658}
34659#[doc = "Negate"]
34660#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s8)"]
34661#[inline]
34662#[target_feature(enable = "neon")]
34663#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34664#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))]
34665#[cfg_attr(
34666    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34667    assert_instr(neg)
34668)]
34669#[cfg_attr(
34670    not(target_arch = "arm"),
34671    stable(feature = "neon_intrinsics", since = "1.59.0")
34672)]
34673#[cfg_attr(
34674    target_arch = "arm",
34675    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34676)]
34677pub fn vneg_s8(a: int8x8_t) -> int8x8_t {
34678    unsafe { simd_neg(a) }
34679}
34680#[doc = "Negate"]
34681#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s8)"]
34682#[inline]
34683#[target_feature(enable = "neon")]
34684#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34685#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))]
34686#[cfg_attr(
34687    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34688    assert_instr(neg)
34689)]
34690#[cfg_attr(
34691    not(target_arch = "arm"),
34692    stable(feature = "neon_intrinsics", since = "1.59.0")
34693)]
34694#[cfg_attr(
34695    target_arch = "arm",
34696    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34697)]
34698pub fn vnegq_s8(a: int8x16_t) -> int8x16_t {
34699    unsafe { simd_neg(a) }
34700}
34701#[doc = "Negate"]
34702#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s16)"]
34703#[inline]
34704#[target_feature(enable = "neon")]
34705#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34706#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))]
34707#[cfg_attr(
34708    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34709    assert_instr(neg)
34710)]
34711#[cfg_attr(
34712    not(target_arch = "arm"),
34713    stable(feature = "neon_intrinsics", since = "1.59.0")
34714)]
34715#[cfg_attr(
34716    target_arch = "arm",
34717    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34718)]
34719pub fn vneg_s16(a: int16x4_t) -> int16x4_t {
34720    unsafe { simd_neg(a) }
34721}
34722#[doc = "Negate"]
34723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s16)"]
34724#[inline]
34725#[target_feature(enable = "neon")]
34726#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34727#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))]
34728#[cfg_attr(
34729    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34730    assert_instr(neg)
34731)]
34732#[cfg_attr(
34733    not(target_arch = "arm"),
34734    stable(feature = "neon_intrinsics", since = "1.59.0")
34735)]
34736#[cfg_attr(
34737    target_arch = "arm",
34738    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34739)]
34740pub fn vnegq_s16(a: int16x8_t) -> int16x8_t {
34741    unsafe { simd_neg(a) }
34742}
34743#[doc = "Negate"]
34744#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s32)"]
34745#[inline]
34746#[target_feature(enable = "neon")]
34747#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34748#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))]
34749#[cfg_attr(
34750    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34751    assert_instr(neg)
34752)]
34753#[cfg_attr(
34754    not(target_arch = "arm"),
34755    stable(feature = "neon_intrinsics", since = "1.59.0")
34756)]
34757#[cfg_attr(
34758    target_arch = "arm",
34759    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34760)]
34761pub fn vneg_s32(a: int32x2_t) -> int32x2_t {
34762    unsafe { simd_neg(a) }
34763}
34764#[doc = "Negate"]
34765#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s32)"]
34766#[inline]
34767#[target_feature(enable = "neon")]
34768#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34769#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))]
34770#[cfg_attr(
34771    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34772    assert_instr(neg)
34773)]
34774#[cfg_attr(
34775    not(target_arch = "arm"),
34776    stable(feature = "neon_intrinsics", since = "1.59.0")
34777)]
34778#[cfg_attr(
34779    target_arch = "arm",
34780    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34781)]
34782pub fn vnegq_s32(a: int32x4_t) -> int32x4_t {
34783    unsafe { simd_neg(a) }
34784}
34785#[doc = "Vector bitwise inclusive OR NOT"]
34786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s16)"]
34787#[inline]
34788#[target_feature(enable = "neon")]
34789#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34790#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34791#[cfg_attr(
34792    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34793    assert_instr(orn)
34794)]
34795#[cfg_attr(
34796    not(target_arch = "arm"),
34797    stable(feature = "neon_intrinsics", since = "1.59.0")
34798)]
34799#[cfg_attr(
34800    target_arch = "arm",
34801    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34802)]
34803pub fn vorn_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
34804    let c = int16x4_t::splat(-1);
34805    unsafe { simd_or(simd_xor(b, c), a) }
34806}
34807#[doc = "Vector bitwise inclusive OR NOT"]
34808#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s32)"]
34809#[inline]
34810#[target_feature(enable = "neon")]
34811#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34812#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34813#[cfg_attr(
34814    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34815    assert_instr(orn)
34816)]
34817#[cfg_attr(
34818    not(target_arch = "arm"),
34819    stable(feature = "neon_intrinsics", since = "1.59.0")
34820)]
34821#[cfg_attr(
34822    target_arch = "arm",
34823    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34824)]
34825pub fn vorn_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
34826    let c = int32x2_t::splat(-1);
34827    unsafe { simd_or(simd_xor(b, c), a) }
34828}
34829#[doc = "Vector bitwise inclusive OR NOT"]
34830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s64)"]
34831#[inline]
34832#[target_feature(enable = "neon")]
34833#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34834#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34835#[cfg_attr(
34836    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34837    assert_instr(orn)
34838)]
34839#[cfg_attr(
34840    not(target_arch = "arm"),
34841    stable(feature = "neon_intrinsics", since = "1.59.0")
34842)]
34843#[cfg_attr(
34844    target_arch = "arm",
34845    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34846)]
34847pub fn vorn_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
34848    let c = int64x1_t::splat(-1);
34849    unsafe { simd_or(simd_xor(b, c), a) }
34850}
34851#[doc = "Vector bitwise inclusive OR NOT"]
34852#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s8)"]
34853#[inline]
34854#[target_feature(enable = "neon")]
34855#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34856#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34857#[cfg_attr(
34858    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34859    assert_instr(orn)
34860)]
34861#[cfg_attr(
34862    not(target_arch = "arm"),
34863    stable(feature = "neon_intrinsics", since = "1.59.0")
34864)]
34865#[cfg_attr(
34866    target_arch = "arm",
34867    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34868)]
34869pub fn vorn_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
34870    let c = int8x8_t::splat(-1);
34871    unsafe { simd_or(simd_xor(b, c), a) }
34872}
34873#[doc = "Vector bitwise inclusive OR NOT"]
34874#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s16)"]
34875#[inline]
34876#[target_feature(enable = "neon")]
34877#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34878#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34879#[cfg_attr(
34880    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34881    assert_instr(orn)
34882)]
34883#[cfg_attr(
34884    not(target_arch = "arm"),
34885    stable(feature = "neon_intrinsics", since = "1.59.0")
34886)]
34887#[cfg_attr(
34888    target_arch = "arm",
34889    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34890)]
34891pub fn vornq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
34892    let c = int16x8_t::splat(-1);
34893    unsafe { simd_or(simd_xor(b, c), a) }
34894}
34895#[doc = "Vector bitwise inclusive OR NOT"]
34896#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s32)"]
34897#[inline]
34898#[target_feature(enable = "neon")]
34899#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34900#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34901#[cfg_attr(
34902    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34903    assert_instr(orn)
34904)]
34905#[cfg_attr(
34906    not(target_arch = "arm"),
34907    stable(feature = "neon_intrinsics", since = "1.59.0")
34908)]
34909#[cfg_attr(
34910    target_arch = "arm",
34911    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34912)]
34913pub fn vornq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
34914    let c = int32x4_t::splat(-1);
34915    unsafe { simd_or(simd_xor(b, c), a) }
34916}
34917#[doc = "Vector bitwise inclusive OR NOT"]
34918#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s64)"]
34919#[inline]
34920#[target_feature(enable = "neon")]
34921#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34922#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34923#[cfg_attr(
34924    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34925    assert_instr(orn)
34926)]
34927#[cfg_attr(
34928    not(target_arch = "arm"),
34929    stable(feature = "neon_intrinsics", since = "1.59.0")
34930)]
34931#[cfg_attr(
34932    target_arch = "arm",
34933    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34934)]
34935pub fn vornq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
34936    let c = int64x2_t::splat(-1);
34937    unsafe { simd_or(simd_xor(b, c), a) }
34938}
34939#[doc = "Vector bitwise inclusive OR NOT"]
34940#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s8)"]
34941#[inline]
34942#[target_feature(enable = "neon")]
34943#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34944#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34945#[cfg_attr(
34946    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34947    assert_instr(orn)
34948)]
34949#[cfg_attr(
34950    not(target_arch = "arm"),
34951    stable(feature = "neon_intrinsics", since = "1.59.0")
34952)]
34953#[cfg_attr(
34954    target_arch = "arm",
34955    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34956)]
34957pub fn vornq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
34958    let c = int8x16_t::splat(-1);
34959    unsafe { simd_or(simd_xor(b, c), a) }
34960}
34961#[doc = "Vector bitwise inclusive OR NOT"]
34962#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u16)"]
34963#[inline]
34964#[target_feature(enable = "neon")]
34965#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34966#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34967#[cfg_attr(
34968    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34969    assert_instr(orn)
34970)]
34971#[cfg_attr(
34972    not(target_arch = "arm"),
34973    stable(feature = "neon_intrinsics", since = "1.59.0")
34974)]
34975#[cfg_attr(
34976    target_arch = "arm",
34977    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34978)]
34979pub fn vorn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
34980    let c = int16x4_t::splat(-1);
34981    unsafe { simd_or(simd_xor(b, transmute(c)), a) }
34982}
34983#[doc = "Vector bitwise inclusive OR NOT"]
34984#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u32)"]
34985#[inline]
34986#[target_feature(enable = "neon")]
34987#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34988#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34989#[cfg_attr(
34990    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34991    assert_instr(orn)
34992)]
34993#[cfg_attr(
34994    not(target_arch = "arm"),
34995    stable(feature = "neon_intrinsics", since = "1.59.0")
34996)]
34997#[cfg_attr(
34998    target_arch = "arm",
34999    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35000)]
35001pub fn vorn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
35002    let c = int32x2_t::splat(-1);
35003    unsafe { simd_or(simd_xor(b, transmute(c)), a) }
35004}
35005#[doc = "Vector bitwise inclusive OR NOT"]
35006#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u64)"]
35007#[inline]
35008#[target_feature(enable = "neon")]
35009#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35010#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35011#[cfg_attr(
35012    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35013    assert_instr(orn)
35014)]
35015#[cfg_attr(
35016    not(target_arch = "arm"),
35017    stable(feature = "neon_intrinsics", since = "1.59.0")
35018)]
35019#[cfg_attr(
35020    target_arch = "arm",
35021    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35022)]
35023pub fn vorn_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
35024    let c = int64x1_t::splat(-1);
35025    unsafe { simd_or(simd_xor(b, transmute(c)), a) }
35026}
35027#[doc = "Vector bitwise inclusive OR NOT"]
35028#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u8)"]
35029#[inline]
35030#[target_feature(enable = "neon")]
35031#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35032#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35033#[cfg_attr(
35034    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35035    assert_instr(orn)
35036)]
35037#[cfg_attr(
35038    not(target_arch = "arm"),
35039    stable(feature = "neon_intrinsics", since = "1.59.0")
35040)]
35041#[cfg_attr(
35042    target_arch = "arm",
35043    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35044)]
35045pub fn vorn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
35046    let c = int8x8_t::splat(-1);
35047    unsafe { simd_or(simd_xor(b, transmute(c)), a) }
35048}
35049#[doc = "Vector bitwise inclusive OR NOT"]
35050#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u16)"]
35051#[inline]
35052#[target_feature(enable = "neon")]
35053#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35054#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35055#[cfg_attr(
35056    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35057    assert_instr(orn)
35058)]
35059#[cfg_attr(
35060    not(target_arch = "arm"),
35061    stable(feature = "neon_intrinsics", since = "1.59.0")
35062)]
35063#[cfg_attr(
35064    target_arch = "arm",
35065    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35066)]
35067pub fn vornq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
35068    let c = int16x8_t::splat(-1);
35069    unsafe { simd_or(simd_xor(b, transmute(c)), a) }
35070}
35071#[doc = "Vector bitwise inclusive OR NOT"]
35072#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u32)"]
35073#[inline]
35074#[target_feature(enable = "neon")]
35075#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35076#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35077#[cfg_attr(
35078    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35079    assert_instr(orn)
35080)]
35081#[cfg_attr(
35082    not(target_arch = "arm"),
35083    stable(feature = "neon_intrinsics", since = "1.59.0")
35084)]
35085#[cfg_attr(
35086    target_arch = "arm",
35087    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35088)]
35089pub fn vornq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
35090    let c = int32x4_t::splat(-1);
35091    unsafe { simd_or(simd_xor(b, transmute(c)), a) }
35092}
35093#[doc = "Vector bitwise inclusive OR NOT"]
35094#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u64)"]
35095#[inline]
35096#[target_feature(enable = "neon")]
35097#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35098#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35099#[cfg_attr(
35100    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35101    assert_instr(orn)
35102)]
35103#[cfg_attr(
35104    not(target_arch = "arm"),
35105    stable(feature = "neon_intrinsics", since = "1.59.0")
35106)]
35107#[cfg_attr(
35108    target_arch = "arm",
35109    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35110)]
35111pub fn vornq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
35112    let c = int64x2_t::splat(-1);
35113    unsafe { simd_or(simd_xor(b, transmute(c)), a) }
35114}
35115#[doc = "Vector bitwise inclusive OR NOT"]
35116#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u8)"]
35117#[inline]
35118#[target_feature(enable = "neon")]
35119#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35120#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35121#[cfg_attr(
35122    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35123    assert_instr(orn)
35124)]
35125#[cfg_attr(
35126    not(target_arch = "arm"),
35127    stable(feature = "neon_intrinsics", since = "1.59.0")
35128)]
35129#[cfg_attr(
35130    target_arch = "arm",
35131    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35132)]
35133pub fn vornq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
35134    let c = int8x16_t::splat(-1);
35135    unsafe { simd_or(simd_xor(b, transmute(c)), a) }
35136}
35137#[doc = "Vector bitwise or (immediate, inclusive)"]
35138#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s8)"]
35139#[inline]
35140#[target_feature(enable = "neon")]
35141#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35142#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35143#[cfg_attr(
35144    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35145    assert_instr(orr)
35146)]
35147#[cfg_attr(
35148    not(target_arch = "arm"),
35149    stable(feature = "neon_intrinsics", since = "1.59.0")
35150)]
35151#[cfg_attr(
35152    target_arch = "arm",
35153    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35154)]
35155pub fn vorr_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
35156    unsafe { simd_or(a, b) }
35157}
35158#[doc = "Vector bitwise or (immediate, inclusive)"]
35159#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s8)"]
35160#[inline]
35161#[target_feature(enable = "neon")]
35162#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35163#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35164#[cfg_attr(
35165    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35166    assert_instr(orr)
35167)]
35168#[cfg_attr(
35169    not(target_arch = "arm"),
35170    stable(feature = "neon_intrinsics", since = "1.59.0")
35171)]
35172#[cfg_attr(
35173    target_arch = "arm",
35174    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35175)]
35176pub fn vorrq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
35177    unsafe { simd_or(a, b) }
35178}
35179#[doc = "Vector bitwise or (immediate, inclusive)"]
35180#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s16)"]
35181#[inline]
35182#[target_feature(enable = "neon")]
35183#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35184#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35185#[cfg_attr(
35186    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35187    assert_instr(orr)
35188)]
35189#[cfg_attr(
35190    not(target_arch = "arm"),
35191    stable(feature = "neon_intrinsics", since = "1.59.0")
35192)]
35193#[cfg_attr(
35194    target_arch = "arm",
35195    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35196)]
35197pub fn vorr_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
35198    unsafe { simd_or(a, b) }
35199}
35200#[doc = "Vector bitwise or (immediate, inclusive)"]
35201#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s16)"]
35202#[inline]
35203#[target_feature(enable = "neon")]
35204#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35205#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35206#[cfg_attr(
35207    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35208    assert_instr(orr)
35209)]
35210#[cfg_attr(
35211    not(target_arch = "arm"),
35212    stable(feature = "neon_intrinsics", since = "1.59.0")
35213)]
35214#[cfg_attr(
35215    target_arch = "arm",
35216    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35217)]
35218pub fn vorrq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
35219    unsafe { simd_or(a, b) }
35220}
35221#[doc = "Vector bitwise or (immediate, inclusive)"]
35222#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s32)"]
35223#[inline]
35224#[target_feature(enable = "neon")]
35225#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35226#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35227#[cfg_attr(
35228    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35229    assert_instr(orr)
35230)]
35231#[cfg_attr(
35232    not(target_arch = "arm"),
35233    stable(feature = "neon_intrinsics", since = "1.59.0")
35234)]
35235#[cfg_attr(
35236    target_arch = "arm",
35237    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35238)]
35239pub fn vorr_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
35240    unsafe { simd_or(a, b) }
35241}
35242#[doc = "Vector bitwise or (immediate, inclusive)"]
35243#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s32)"]
35244#[inline]
35245#[target_feature(enable = "neon")]
35246#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35247#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35248#[cfg_attr(
35249    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35250    assert_instr(orr)
35251)]
35252#[cfg_attr(
35253    not(target_arch = "arm"),
35254    stable(feature = "neon_intrinsics", since = "1.59.0")
35255)]
35256#[cfg_attr(
35257    target_arch = "arm",
35258    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35259)]
35260pub fn vorrq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
35261    unsafe { simd_or(a, b) }
35262}
35263#[doc = "Vector bitwise or (immediate, inclusive)"]
35264#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s64)"]
35265#[inline]
35266#[target_feature(enable = "neon")]
35267#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35268#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35269#[cfg_attr(
35270    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35271    assert_instr(orr)
35272)]
35273#[cfg_attr(
35274    not(target_arch = "arm"),
35275    stable(feature = "neon_intrinsics", since = "1.59.0")
35276)]
35277#[cfg_attr(
35278    target_arch = "arm",
35279    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35280)]
35281pub fn vorr_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
35282    unsafe { simd_or(a, b) }
35283}
35284#[doc = "Vector bitwise or (immediate, inclusive)"]
35285#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s64)"]
35286#[inline]
35287#[target_feature(enable = "neon")]
35288#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35289#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35290#[cfg_attr(
35291    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35292    assert_instr(orr)
35293)]
35294#[cfg_attr(
35295    not(target_arch = "arm"),
35296    stable(feature = "neon_intrinsics", since = "1.59.0")
35297)]
35298#[cfg_attr(
35299    target_arch = "arm",
35300    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35301)]
35302pub fn vorrq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
35303    unsafe { simd_or(a, b) }
35304}
35305#[doc = "Vector bitwise or (immediate, inclusive)"]
35306#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u8)"]
35307#[inline]
35308#[target_feature(enable = "neon")]
35309#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35310#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35311#[cfg_attr(
35312    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35313    assert_instr(orr)
35314)]
35315#[cfg_attr(
35316    not(target_arch = "arm"),
35317    stable(feature = "neon_intrinsics", since = "1.59.0")
35318)]
35319#[cfg_attr(
35320    target_arch = "arm",
35321    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35322)]
35323pub fn vorr_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
35324    unsafe { simd_or(a, b) }
35325}
35326#[doc = "Vector bitwise or (immediate, inclusive)"]
35327#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u8)"]
35328#[inline]
35329#[target_feature(enable = "neon")]
35330#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35331#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35332#[cfg_attr(
35333    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35334    assert_instr(orr)
35335)]
35336#[cfg_attr(
35337    not(target_arch = "arm"),
35338    stable(feature = "neon_intrinsics", since = "1.59.0")
35339)]
35340#[cfg_attr(
35341    target_arch = "arm",
35342    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35343)]
35344pub fn vorrq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
35345    unsafe { simd_or(a, b) }
35346}
35347#[doc = "Vector bitwise or (immediate, inclusive)"]
35348#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u16)"]
35349#[inline]
35350#[target_feature(enable = "neon")]
35351#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35352#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35353#[cfg_attr(
35354    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35355    assert_instr(orr)
35356)]
35357#[cfg_attr(
35358    not(target_arch = "arm"),
35359    stable(feature = "neon_intrinsics", since = "1.59.0")
35360)]
35361#[cfg_attr(
35362    target_arch = "arm",
35363    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35364)]
35365pub fn vorr_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
35366    unsafe { simd_or(a, b) }
35367}
35368#[doc = "Vector bitwise or (immediate, inclusive)"]
35369#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u16)"]
35370#[inline]
35371#[target_feature(enable = "neon")]
35372#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35373#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35374#[cfg_attr(
35375    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35376    assert_instr(orr)
35377)]
35378#[cfg_attr(
35379    not(target_arch = "arm"),
35380    stable(feature = "neon_intrinsics", since = "1.59.0")
35381)]
35382#[cfg_attr(
35383    target_arch = "arm",
35384    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35385)]
35386pub fn vorrq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
35387    unsafe { simd_or(a, b) }
35388}
35389#[doc = "Vector bitwise or (immediate, inclusive)"]
35390#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u32)"]
35391#[inline]
35392#[target_feature(enable = "neon")]
35393#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35394#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35395#[cfg_attr(
35396    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35397    assert_instr(orr)
35398)]
35399#[cfg_attr(
35400    not(target_arch = "arm"),
35401    stable(feature = "neon_intrinsics", since = "1.59.0")
35402)]
35403#[cfg_attr(
35404    target_arch = "arm",
35405    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35406)]
35407pub fn vorr_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
35408    unsafe { simd_or(a, b) }
35409}
35410#[doc = "Vector bitwise or (immediate, inclusive)"]
35411#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u32)"]
35412#[inline]
35413#[target_feature(enable = "neon")]
35414#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35415#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35416#[cfg_attr(
35417    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35418    assert_instr(orr)
35419)]
35420#[cfg_attr(
35421    not(target_arch = "arm"),
35422    stable(feature = "neon_intrinsics", since = "1.59.0")
35423)]
35424#[cfg_attr(
35425    target_arch = "arm",
35426    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35427)]
35428pub fn vorrq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
35429    unsafe { simd_or(a, b) }
35430}
35431#[doc = "Vector bitwise or (immediate, inclusive)"]
35432#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u64)"]
35433#[inline]
35434#[target_feature(enable = "neon")]
35435#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35436#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35437#[cfg_attr(
35438    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35439    assert_instr(orr)
35440)]
35441#[cfg_attr(
35442    not(target_arch = "arm"),
35443    stable(feature = "neon_intrinsics", since = "1.59.0")
35444)]
35445#[cfg_attr(
35446    target_arch = "arm",
35447    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35448)]
35449pub fn vorr_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
35450    unsafe { simd_or(a, b) }
35451}
35452#[doc = "Vector bitwise or (immediate, inclusive)"]
35453#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u64)"]
35454#[inline]
35455#[target_feature(enable = "neon")]
35456#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35457#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35458#[cfg_attr(
35459    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35460    assert_instr(orr)
35461)]
35462#[cfg_attr(
35463    not(target_arch = "arm"),
35464    stable(feature = "neon_intrinsics", since = "1.59.0")
35465)]
35466#[cfg_attr(
35467    target_arch = "arm",
35468    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35469)]
35470pub fn vorrq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
35471    unsafe { simd_or(a, b) }
35472}
35473#[doc = "Signed Add and Accumulate Long Pairwise."]
35474#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s8)"]
35475#[inline]
35476#[target_feature(enable = "neon")]
35477#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35478#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
35479#[cfg_attr(
35480    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35481    assert_instr(sadalp)
35482)]
35483#[cfg_attr(
35484    not(target_arch = "arm"),
35485    stable(feature = "neon_intrinsics", since = "1.59.0")
35486)]
35487#[cfg_attr(
35488    target_arch = "arm",
35489    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35490)]
35491pub fn vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t {
35492    let x: int16x4_t;
35493    #[cfg(target_arch = "arm")]
35494    {
35495        x = priv_vpadal_s8(a, b);
35496    }
35497    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35498    unsafe {
35499        x = simd_add(vpaddl_s8(b), a);
35500    };
35501    x
35502}
35503#[doc = "Signed Add and Accumulate Long Pairwise."]
35504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s8)"]
35505#[inline]
35506#[target_feature(enable = "neon")]
35507#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35508#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
35509#[cfg_attr(
35510    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35511    assert_instr(sadalp)
35512)]
35513#[cfg_attr(
35514    not(target_arch = "arm"),
35515    stable(feature = "neon_intrinsics", since = "1.59.0")
35516)]
35517#[cfg_attr(
35518    target_arch = "arm",
35519    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35520)]
35521pub fn vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
35522    let x: int16x8_t;
35523    #[cfg(target_arch = "arm")]
35524    {
35525        x = priv_vpadalq_s8(a, b);
35526    }
35527    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35528    unsafe {
35529        x = simd_add(vpaddlq_s8(b), a);
35530    };
35531    x
35532}
35533#[doc = "Signed Add and Accumulate Long Pairwise."]
35534#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s16)"]
35535#[inline]
35536#[target_feature(enable = "neon")]
35537#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35538#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
35539#[cfg_attr(
35540    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35541    assert_instr(sadalp)
35542)]
35543#[cfg_attr(
35544    not(target_arch = "arm"),
35545    stable(feature = "neon_intrinsics", since = "1.59.0")
35546)]
35547#[cfg_attr(
35548    target_arch = "arm",
35549    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35550)]
35551pub fn vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t {
35552    let x: int32x2_t;
35553    #[cfg(target_arch = "arm")]
35554    {
35555        x = priv_vpadal_s16(a, b);
35556    }
35557    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35558    unsafe {
35559        x = simd_add(vpaddl_s16(b), a);
35560    };
35561    x
35562}
35563#[doc = "Signed Add and Accumulate Long Pairwise."]
35564#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s16)"]
35565#[inline]
35566#[target_feature(enable = "neon")]
35567#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35568#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
35569#[cfg_attr(
35570    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35571    assert_instr(sadalp)
35572)]
35573#[cfg_attr(
35574    not(target_arch = "arm"),
35575    stable(feature = "neon_intrinsics", since = "1.59.0")
35576)]
35577#[cfg_attr(
35578    target_arch = "arm",
35579    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35580)]
35581pub fn vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
35582    let x: int32x4_t;
35583    #[cfg(target_arch = "arm")]
35584    {
35585        x = priv_vpadalq_s16(a, b);
35586    }
35587    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35588    unsafe {
35589        x = simd_add(vpaddlq_s16(b), a);
35590    };
35591    x
35592}
35593#[doc = "Signed Add and Accumulate Long Pairwise."]
35594#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s32)"]
35595#[inline]
35596#[target_feature(enable = "neon")]
35597#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35598#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
35599#[cfg_attr(
35600    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35601    assert_instr(sadalp)
35602)]
35603#[cfg_attr(
35604    not(target_arch = "arm"),
35605    stable(feature = "neon_intrinsics", since = "1.59.0")
35606)]
35607#[cfg_attr(
35608    target_arch = "arm",
35609    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35610)]
35611pub fn vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t {
35612    let x: int64x1_t;
35613    #[cfg(target_arch = "arm")]
35614    {
35615        x = priv_vpadal_s32(a, b);
35616    }
35617    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35618    unsafe {
35619        x = simd_add(vpaddl_s32(b), a);
35620    };
35621    x
35622}
35623#[doc = "Signed Add and Accumulate Long Pairwise."]
35624#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s32)"]
35625#[inline]
35626#[target_feature(enable = "neon")]
35627#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35628#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
35629#[cfg_attr(
35630    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35631    assert_instr(sadalp)
35632)]
35633#[cfg_attr(
35634    not(target_arch = "arm"),
35635    stable(feature = "neon_intrinsics", since = "1.59.0")
35636)]
35637#[cfg_attr(
35638    target_arch = "arm",
35639    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35640)]
35641pub fn vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
35642    let x: int64x2_t;
35643    #[cfg(target_arch = "arm")]
35644    {
35645        x = priv_vpadalq_s32(a, b);
35646    }
35647    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35648    unsafe {
35649        x = simd_add(vpaddlq_s32(b), a);
35650    };
35651    x
35652}
35653#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35654#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u8)"]
35655#[inline]
35656#[target_feature(enable = "neon")]
35657#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35658#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
35659#[cfg_attr(
35660    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35661    assert_instr(uadalp)
35662)]
35663#[cfg_attr(
35664    not(target_arch = "arm"),
35665    stable(feature = "neon_intrinsics", since = "1.59.0")
35666)]
35667#[cfg_attr(
35668    target_arch = "arm",
35669    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35670)]
35671pub fn vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t {
35672    let x: uint16x4_t;
35673    #[cfg(target_arch = "arm")]
35674    {
35675        x = priv_vpadal_u8(a, b);
35676    }
35677    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35678    unsafe {
35679        x = simd_add(vpaddl_u8(b), a);
35680    };
35681    x
35682}
35683#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u8)"]
35685#[inline]
35686#[target_feature(enable = "neon")]
35687#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35688#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
35689#[cfg_attr(
35690    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35691    assert_instr(uadalp)
35692)]
35693#[cfg_attr(
35694    not(target_arch = "arm"),
35695    stable(feature = "neon_intrinsics", since = "1.59.0")
35696)]
35697#[cfg_attr(
35698    target_arch = "arm",
35699    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35700)]
35701pub fn vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
35702    let x: uint16x8_t;
35703    #[cfg(target_arch = "arm")]
35704    {
35705        x = priv_vpadalq_u8(a, b);
35706    }
35707    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35708    unsafe {
35709        x = simd_add(vpaddlq_u8(b), a);
35710    };
35711    x
35712}
35713#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35714#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u16)"]
35715#[inline]
35716#[target_feature(enable = "neon")]
35717#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35718#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
35719#[cfg_attr(
35720    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35721    assert_instr(uadalp)
35722)]
35723#[cfg_attr(
35724    not(target_arch = "arm"),
35725    stable(feature = "neon_intrinsics", since = "1.59.0")
35726)]
35727#[cfg_attr(
35728    target_arch = "arm",
35729    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35730)]
35731pub fn vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t {
35732    let x: uint32x2_t;
35733    #[cfg(target_arch = "arm")]
35734    {
35735        x = priv_vpadal_u16(a, b);
35736    }
35737    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35738    unsafe {
35739        x = simd_add(vpaddl_u16(b), a);
35740    };
35741    x
35742}
35743#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35744#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u16)"]
35745#[inline]
35746#[target_feature(enable = "neon")]
35747#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35748#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
35749#[cfg_attr(
35750    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35751    assert_instr(uadalp)
35752)]
35753#[cfg_attr(
35754    not(target_arch = "arm"),
35755    stable(feature = "neon_intrinsics", since = "1.59.0")
35756)]
35757#[cfg_attr(
35758    target_arch = "arm",
35759    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35760)]
35761pub fn vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
35762    let x: uint32x4_t;
35763    #[cfg(target_arch = "arm")]
35764    {
35765        x = priv_vpadalq_u16(a, b);
35766    }
35767    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35768    unsafe {
35769        x = simd_add(vpaddlq_u16(b), a);
35770    };
35771    x
35772}
35773#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u32)"]
35775#[inline]
35776#[target_feature(enable = "neon")]
35777#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35778#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
35779#[cfg_attr(
35780    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35781    assert_instr(uadalp)
35782)]
35783#[cfg_attr(
35784    not(target_arch = "arm"),
35785    stable(feature = "neon_intrinsics", since = "1.59.0")
35786)]
35787#[cfg_attr(
35788    target_arch = "arm",
35789    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35790)]
35791pub fn vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t {
35792    let x: uint64x1_t;
35793    #[cfg(target_arch = "arm")]
35794    {
35795        x = priv_vpadal_u32(a, b);
35796    }
35797    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35798    unsafe {
35799        x = simd_add(vpaddl_u32(b), a);
35800    };
35801    x
35802}
35803#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35804#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u32)"]
35805#[inline]
35806#[target_feature(enable = "neon")]
35807#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35808#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
35809#[cfg_attr(
35810    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35811    assert_instr(uadalp)
35812)]
35813#[cfg_attr(
35814    not(target_arch = "arm"),
35815    stable(feature = "neon_intrinsics", since = "1.59.0")
35816)]
35817#[cfg_attr(
35818    target_arch = "arm",
35819    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35820)]
35821pub fn vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
35822    let x: uint64x2_t;
35823    #[cfg(target_arch = "arm")]
35824    {
35825        x = priv_vpadalq_u32(a, b);
35826    }
35827    #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35828    unsafe {
35829        x = simd_add(vpaddlq_u32(b), a);
35830    };
35831    x
35832}
35833#[doc = "Floating-point add pairwise"]
35834#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f16)"]
35835#[inline]
35836#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
35837#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35838#[cfg_attr(
35839    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35840    assert_instr(faddp)
35841)]
35842#[target_feature(enable = "neon,fp16")]
35843#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
35844pub fn vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
35845    unsafe extern "unadjusted" {
35846        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v4f16")]
35847        #[cfg_attr(
35848            any(target_arch = "aarch64", target_arch = "arm64ec"),
35849            link_name = "llvm.aarch64.neon.faddp.v4f16"
35850        )]
35851        fn _vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
35852    }
35853    unsafe { _vpadd_f16(a, b) }
35854}
35855#[doc = "Floating-point add pairwise"]
35856#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f32)"]
35857#[inline]
35858#[target_feature(enable = "neon")]
35859#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35860#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35861#[cfg_attr(
35862    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35863    assert_instr(faddp)
35864)]
35865#[cfg_attr(
35866    not(target_arch = "arm"),
35867    stable(feature = "neon_intrinsics", since = "1.59.0")
35868)]
35869#[cfg_attr(
35870    target_arch = "arm",
35871    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35872)]
35873pub fn vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
35874    unsafe extern "unadjusted" {
35875        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2f32")]
35876        #[cfg_attr(
35877            any(target_arch = "aarch64", target_arch = "arm64ec"),
35878            link_name = "llvm.aarch64.neon.faddp.v2f32"
35879        )]
35880        fn _vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
35881    }
35882    unsafe { _vpadd_f32(a, b) }
35883}
35884#[doc = "Add pairwise."]
35885#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s8)"]
35886#[inline]
35887#[target_feature(enable = "neon")]
35888#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35889#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35890#[cfg_attr(
35891    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35892    assert_instr(addp)
35893)]
35894#[cfg_attr(
35895    not(target_arch = "arm"),
35896    stable(feature = "neon_intrinsics", since = "1.59.0")
35897)]
35898#[cfg_attr(
35899    target_arch = "arm",
35900    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35901)]
35902pub fn vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
35903    unsafe extern "unadjusted" {
35904        #[cfg_attr(
35905            any(target_arch = "aarch64", target_arch = "arm64ec"),
35906            link_name = "llvm.aarch64.neon.addp.v8i8"
35907        )]
35908        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v8i8")]
35909        fn _vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
35910    }
35911    unsafe { _vpadd_s8(a, b) }
35912}
35913#[doc = "Add pairwise."]
35914#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s16)"]
35915#[inline]
35916#[target_feature(enable = "neon")]
35917#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35918#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35919#[cfg_attr(
35920    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35921    assert_instr(addp)
35922)]
35923#[cfg_attr(
35924    not(target_arch = "arm"),
35925    stable(feature = "neon_intrinsics", since = "1.59.0")
35926)]
35927#[cfg_attr(
35928    target_arch = "arm",
35929    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35930)]
35931pub fn vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
35932    unsafe extern "unadjusted" {
35933        #[cfg_attr(
35934            any(target_arch = "aarch64", target_arch = "arm64ec"),
35935            link_name = "llvm.aarch64.neon.addp.v4i16"
35936        )]
35937        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v4i16")]
35938        fn _vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
35939    }
35940    unsafe { _vpadd_s16(a, b) }
35941}
35942#[doc = "Add pairwise."]
35943#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s32)"]
35944#[inline]
35945#[target_feature(enable = "neon")]
35946#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35947#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35948#[cfg_attr(
35949    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35950    assert_instr(addp)
35951)]
35952#[cfg_attr(
35953    not(target_arch = "arm"),
35954    stable(feature = "neon_intrinsics", since = "1.59.0")
35955)]
35956#[cfg_attr(
35957    target_arch = "arm",
35958    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35959)]
35960pub fn vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
35961    unsafe extern "unadjusted" {
35962        #[cfg_attr(
35963            any(target_arch = "aarch64", target_arch = "arm64ec"),
35964            link_name = "llvm.aarch64.neon.addp.v2i32"
35965        )]
35966        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2i32")]
35967        fn _vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
35968    }
35969    unsafe { _vpadd_s32(a, b) }
35970}
35971#[doc = "Add pairwise."]
35972#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"]
35973#[inline]
35974#[cfg(target_endian = "little")]
35975#[target_feature(enable = "neon")]
35976#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35977#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35978#[cfg_attr(
35979    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35980    assert_instr(addp)
35981)]
35982#[cfg_attr(
35983    not(target_arch = "arm"),
35984    stable(feature = "neon_intrinsics", since = "1.59.0")
35985)]
35986#[cfg_attr(
35987    target_arch = "arm",
35988    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35989)]
35990pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
35991    unsafe { transmute(vpadd_s8(transmute(a), transmute(b))) }
35992}
35993#[doc = "Add pairwise."]
35994#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"]
35995#[inline]
35996#[cfg(target_endian = "big")]
35997#[target_feature(enable = "neon")]
35998#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35999#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
36000#[cfg_attr(
36001    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36002    assert_instr(addp)
36003)]
36004#[cfg_attr(
36005    not(target_arch = "arm"),
36006    stable(feature = "neon_intrinsics", since = "1.59.0")
36007)]
36008#[cfg_attr(
36009    target_arch = "arm",
36010    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36011)]
36012pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
36013    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
36014    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
36015    unsafe {
36016        let ret_val: uint8x8_t = transmute(vpadd_s8(transmute(a), transmute(b)));
36017        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
36018    }
36019}
36020#[doc = "Add pairwise."]
36021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"]
36022#[inline]
36023#[cfg(target_endian = "little")]
36024#[target_feature(enable = "neon")]
36025#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36026#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
36027#[cfg_attr(
36028    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36029    assert_instr(addp)
36030)]
36031#[cfg_attr(
36032    not(target_arch = "arm"),
36033    stable(feature = "neon_intrinsics", since = "1.59.0")
36034)]
36035#[cfg_attr(
36036    target_arch = "arm",
36037    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36038)]
36039pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
36040    unsafe { transmute(vpadd_s16(transmute(a), transmute(b))) }
36041}
36042#[doc = "Add pairwise."]
36043#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"]
36044#[inline]
36045#[cfg(target_endian = "big")]
36046#[target_feature(enable = "neon")]
36047#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36048#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
36049#[cfg_attr(
36050    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36051    assert_instr(addp)
36052)]
36053#[cfg_attr(
36054    not(target_arch = "arm"),
36055    stable(feature = "neon_intrinsics", since = "1.59.0")
36056)]
36057#[cfg_attr(
36058    target_arch = "arm",
36059    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36060)]
36061pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
36062    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
36063    let b: uint16x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) };
36064    unsafe {
36065        let ret_val: uint16x4_t = transmute(vpadd_s16(transmute(a), transmute(b)));
36066        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
36067    }
36068}
36069#[doc = "Add pairwise."]
36070#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"]
36071#[inline]
36072#[cfg(target_endian = "little")]
36073#[target_feature(enable = "neon")]
36074#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36075#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
36076#[cfg_attr(
36077    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36078    assert_instr(addp)
36079)]
36080#[cfg_attr(
36081    not(target_arch = "arm"),
36082    stable(feature = "neon_intrinsics", since = "1.59.0")
36083)]
36084#[cfg_attr(
36085    target_arch = "arm",
36086    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36087)]
36088pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
36089    unsafe { transmute(vpadd_s32(transmute(a), transmute(b))) }
36090}
36091#[doc = "Add pairwise."]
36092#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"]
36093#[inline]
36094#[cfg(target_endian = "big")]
36095#[target_feature(enable = "neon")]
36096#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36097#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
36098#[cfg_attr(
36099    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36100    assert_instr(addp)
36101)]
36102#[cfg_attr(
36103    not(target_arch = "arm"),
36104    stable(feature = "neon_intrinsics", since = "1.59.0")
36105)]
36106#[cfg_attr(
36107    target_arch = "arm",
36108    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36109)]
36110pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
36111    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
36112    let b: uint32x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) };
36113    unsafe {
36114        let ret_val: uint32x2_t = transmute(vpadd_s32(transmute(a), transmute(b)));
36115        simd_shuffle!(ret_val, ret_val, [1, 0])
36116    }
36117}
36118#[doc = "Signed Add and Accumulate Long Pairwise."]
36119#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s8)"]
36120#[inline]
36121#[target_feature(enable = "neon")]
36122#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36123#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s8"))]
36124#[cfg_attr(
36125    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36126    assert_instr(saddlp)
36127)]
36128#[cfg_attr(
36129    not(target_arch = "arm"),
36130    stable(feature = "neon_intrinsics", since = "1.59.0")
36131)]
36132#[cfg_attr(
36133    target_arch = "arm",
36134    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36135)]
36136pub fn vpaddl_s8(a: int8x8_t) -> int16x4_t {
36137    unsafe extern "unadjusted" {
36138        #[cfg_attr(
36139            any(target_arch = "aarch64", target_arch = "arm64ec"),
36140            link_name = "llvm.aarch64.neon.saddlp.v4i16.v8i8"
36141        )]
36142        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v4i16.v8i8")]
36143        fn _vpaddl_s8(a: int8x8_t) -> int16x4_t;
36144    }
36145    unsafe { _vpaddl_s8(a) }
36146}
36147#[doc = "Signed Add and Accumulate Long Pairwise."]
36148#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s8)"]
36149#[inline]
36150#[target_feature(enable = "neon")]
36151#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36152#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s8"))]
36153#[cfg_attr(
36154    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36155    assert_instr(saddlp)
36156)]
36157#[cfg_attr(
36158    not(target_arch = "arm"),
36159    stable(feature = "neon_intrinsics", since = "1.59.0")
36160)]
36161#[cfg_attr(
36162    target_arch = "arm",
36163    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36164)]
36165pub fn vpaddlq_s8(a: int8x16_t) -> int16x8_t {
36166    unsafe extern "unadjusted" {
36167        #[cfg_attr(
36168            any(target_arch = "aarch64", target_arch = "arm64ec"),
36169            link_name = "llvm.aarch64.neon.saddlp.v8i16.v16i8"
36170        )]
36171        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v8i16.v16i8")]
36172        fn _vpaddlq_s8(a: int8x16_t) -> int16x8_t;
36173    }
36174    unsafe { _vpaddlq_s8(a) }
36175}
36176#[doc = "Signed Add and Accumulate Long Pairwise."]
36177#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s16)"]
36178#[inline]
36179#[target_feature(enable = "neon")]
36180#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36181#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s16"))]
36182#[cfg_attr(
36183    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36184    assert_instr(saddlp)
36185)]
36186#[cfg_attr(
36187    not(target_arch = "arm"),
36188    stable(feature = "neon_intrinsics", since = "1.59.0")
36189)]
36190#[cfg_attr(
36191    target_arch = "arm",
36192    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36193)]
36194pub fn vpaddl_s16(a: int16x4_t) -> int32x2_t {
36195    unsafe extern "unadjusted" {
36196        #[cfg_attr(
36197            any(target_arch = "aarch64", target_arch = "arm64ec"),
36198            link_name = "llvm.aarch64.neon.saddlp.v2i32.v4i16"
36199        )]
36200        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v2i32.v4i16")]
36201        fn _vpaddl_s16(a: int16x4_t) -> int32x2_t;
36202    }
36203    unsafe { _vpaddl_s16(a) }
36204}
36205#[doc = "Signed Add and Accumulate Long Pairwise."]
36206#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s16)"]
36207#[inline]
36208#[target_feature(enable = "neon")]
36209#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36210#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s16"))]
36211#[cfg_attr(
36212    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36213    assert_instr(saddlp)
36214)]
36215#[cfg_attr(
36216    not(target_arch = "arm"),
36217    stable(feature = "neon_intrinsics", since = "1.59.0")
36218)]
36219#[cfg_attr(
36220    target_arch = "arm",
36221    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36222)]
36223pub fn vpaddlq_s16(a: int16x8_t) -> int32x4_t {
36224    unsafe extern "unadjusted" {
36225        #[cfg_attr(
36226            any(target_arch = "aarch64", target_arch = "arm64ec"),
36227            link_name = "llvm.aarch64.neon.saddlp.v4i32.v8i16"
36228        )]
36229        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v4i32.v8i16")]
36230        fn _vpaddlq_s16(a: int16x8_t) -> int32x4_t;
36231    }
36232    unsafe { _vpaddlq_s16(a) }
36233}
36234#[doc = "Signed Add and Accumulate Long Pairwise."]
36235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s32)"]
36236#[inline]
36237#[target_feature(enable = "neon")]
36238#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36239#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s32"))]
36240#[cfg_attr(
36241    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36242    assert_instr(saddlp)
36243)]
36244#[cfg_attr(
36245    not(target_arch = "arm"),
36246    stable(feature = "neon_intrinsics", since = "1.59.0")
36247)]
36248#[cfg_attr(
36249    target_arch = "arm",
36250    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36251)]
36252pub fn vpaddl_s32(a: int32x2_t) -> int64x1_t {
36253    unsafe extern "unadjusted" {
36254        #[cfg_attr(
36255            any(target_arch = "aarch64", target_arch = "arm64ec"),
36256            link_name = "llvm.aarch64.neon.saddlp.v1i64.v2i32"
36257        )]
36258        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v1i64.v2i32")]
36259        fn _vpaddl_s32(a: int32x2_t) -> int64x1_t;
36260    }
36261    unsafe { _vpaddl_s32(a) }
36262}
36263#[doc = "Signed Add and Accumulate Long Pairwise."]
36264#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s32)"]
36265#[inline]
36266#[target_feature(enable = "neon")]
36267#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36268#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s32"))]
36269#[cfg_attr(
36270    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36271    assert_instr(saddlp)
36272)]
36273#[cfg_attr(
36274    not(target_arch = "arm"),
36275    stable(feature = "neon_intrinsics", since = "1.59.0")
36276)]
36277#[cfg_attr(
36278    target_arch = "arm",
36279    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36280)]
36281pub fn vpaddlq_s32(a: int32x4_t) -> int64x2_t {
36282    unsafe extern "unadjusted" {
36283        #[cfg_attr(
36284            any(target_arch = "aarch64", target_arch = "arm64ec"),
36285            link_name = "llvm.aarch64.neon.saddlp.v2i64.v4i32"
36286        )]
36287        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v2i64.v4i32")]
36288        fn _vpaddlq_s32(a: int32x4_t) -> int64x2_t;
36289    }
36290    unsafe { _vpaddlq_s32(a) }
36291}
36292#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36293#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u8)"]
36294#[inline]
36295#[target_feature(enable = "neon")]
36296#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36297#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u8"))]
36298#[cfg_attr(
36299    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36300    assert_instr(uaddlp)
36301)]
36302#[cfg_attr(
36303    not(target_arch = "arm"),
36304    stable(feature = "neon_intrinsics", since = "1.59.0")
36305)]
36306#[cfg_attr(
36307    target_arch = "arm",
36308    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36309)]
36310pub fn vpaddl_u8(a: uint8x8_t) -> uint16x4_t {
36311    unsafe extern "unadjusted" {
36312        #[cfg_attr(
36313            any(target_arch = "aarch64", target_arch = "arm64ec"),
36314            link_name = "llvm.aarch64.neon.uaddlp.v4i16.v8i8"
36315        )]
36316        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v4i16.v8i8")]
36317        fn _vpaddl_u8(a: uint8x8_t) -> uint16x4_t;
36318    }
36319    unsafe { _vpaddl_u8(a) }
36320}
36321#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u8)"]
36323#[inline]
36324#[target_feature(enable = "neon")]
36325#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36326#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u8"))]
36327#[cfg_attr(
36328    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36329    assert_instr(uaddlp)
36330)]
36331#[cfg_attr(
36332    not(target_arch = "arm"),
36333    stable(feature = "neon_intrinsics", since = "1.59.0")
36334)]
36335#[cfg_attr(
36336    target_arch = "arm",
36337    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36338)]
36339pub fn vpaddlq_u8(a: uint8x16_t) -> uint16x8_t {
36340    unsafe extern "unadjusted" {
36341        #[cfg_attr(
36342            any(target_arch = "aarch64", target_arch = "arm64ec"),
36343            link_name = "llvm.aarch64.neon.uaddlp.v8i16.v16i8"
36344        )]
36345        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v8i16.v16i8")]
36346        fn _vpaddlq_u8(a: uint8x16_t) -> uint16x8_t;
36347    }
36348    unsafe { _vpaddlq_u8(a) }
36349}
36350#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36351#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u16)"]
36352#[inline]
36353#[target_feature(enable = "neon")]
36354#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36355#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u16"))]
36356#[cfg_attr(
36357    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36358    assert_instr(uaddlp)
36359)]
36360#[cfg_attr(
36361    not(target_arch = "arm"),
36362    stable(feature = "neon_intrinsics", since = "1.59.0")
36363)]
36364#[cfg_attr(
36365    target_arch = "arm",
36366    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36367)]
36368pub fn vpaddl_u16(a: uint16x4_t) -> uint32x2_t {
36369    unsafe extern "unadjusted" {
36370        #[cfg_attr(
36371            any(target_arch = "aarch64", target_arch = "arm64ec"),
36372            link_name = "llvm.aarch64.neon.uaddlp.v2i32.v4i16"
36373        )]
36374        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v2i32.v4i16")]
36375        fn _vpaddl_u16(a: uint16x4_t) -> uint32x2_t;
36376    }
36377    unsafe { _vpaddl_u16(a) }
36378}
36379#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36380#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u16)"]
36381#[inline]
36382#[target_feature(enable = "neon")]
36383#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36384#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u16"))]
36385#[cfg_attr(
36386    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36387    assert_instr(uaddlp)
36388)]
36389#[cfg_attr(
36390    not(target_arch = "arm"),
36391    stable(feature = "neon_intrinsics", since = "1.59.0")
36392)]
36393#[cfg_attr(
36394    target_arch = "arm",
36395    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36396)]
36397pub fn vpaddlq_u16(a: uint16x8_t) -> uint32x4_t {
36398    unsafe extern "unadjusted" {
36399        #[cfg_attr(
36400            any(target_arch = "aarch64", target_arch = "arm64ec"),
36401            link_name = "llvm.aarch64.neon.uaddlp.v4i32.v8i16"
36402        )]
36403        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v4i32.v8i16")]
36404        fn _vpaddlq_u16(a: uint16x8_t) -> uint32x4_t;
36405    }
36406    unsafe { _vpaddlq_u16(a) }
36407}
36408#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36409#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u32)"]
36410#[inline]
36411#[target_feature(enable = "neon")]
36412#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36413#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u32"))]
36414#[cfg_attr(
36415    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36416    assert_instr(uaddlp)
36417)]
36418#[cfg_attr(
36419    not(target_arch = "arm"),
36420    stable(feature = "neon_intrinsics", since = "1.59.0")
36421)]
36422#[cfg_attr(
36423    target_arch = "arm",
36424    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36425)]
36426pub fn vpaddl_u32(a: uint32x2_t) -> uint64x1_t {
36427    unsafe extern "unadjusted" {
36428        #[cfg_attr(
36429            any(target_arch = "aarch64", target_arch = "arm64ec"),
36430            link_name = "llvm.aarch64.neon.uaddlp.v1i64.v2i32"
36431        )]
36432        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v1i64.v2i32")]
36433        fn _vpaddl_u32(a: uint32x2_t) -> uint64x1_t;
36434    }
36435    unsafe { _vpaddl_u32(a) }
36436}
36437#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36438#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u32)"]
36439#[inline]
36440#[target_feature(enable = "neon")]
36441#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36442#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u32"))]
36443#[cfg_attr(
36444    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36445    assert_instr(uaddlp)
36446)]
36447#[cfg_attr(
36448    not(target_arch = "arm"),
36449    stable(feature = "neon_intrinsics", since = "1.59.0")
36450)]
36451#[cfg_attr(
36452    target_arch = "arm",
36453    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36454)]
36455pub fn vpaddlq_u32(a: uint32x4_t) -> uint64x2_t {
36456    unsafe extern "unadjusted" {
36457        #[cfg_attr(
36458            any(target_arch = "aarch64", target_arch = "arm64ec"),
36459            link_name = "llvm.aarch64.neon.uaddlp.v2i64.v4i32"
36460        )]
36461        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v2i64.v4i32")]
36462        fn _vpaddlq_u32(a: uint32x4_t) -> uint64x2_t;
36463    }
36464    unsafe { _vpaddlq_u32(a) }
36465}
36466#[doc = "Folding maximum of adjacent pairs"]
36467#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f32)"]
36468#[inline]
36469#[target_feature(enable = "neon")]
36470#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36471#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36472#[cfg_attr(
36473    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36474    assert_instr(fmaxp)
36475)]
36476#[cfg_attr(
36477    not(target_arch = "arm"),
36478    stable(feature = "neon_intrinsics", since = "1.59.0")
36479)]
36480#[cfg_attr(
36481    target_arch = "arm",
36482    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36483)]
36484pub fn vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
36485    unsafe extern "unadjusted" {
36486        #[cfg_attr(
36487            any(target_arch = "aarch64", target_arch = "arm64ec"),
36488            link_name = "llvm.aarch64.neon.fmaxp.v2f32"
36489        )]
36490        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2f32")]
36491        fn _vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
36492    }
36493    unsafe { _vpmax_f32(a, b) }
36494}
36495#[doc = "Folding maximum of adjacent pairs"]
36496#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s8)"]
36497#[inline]
36498#[target_feature(enable = "neon")]
36499#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36500#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36501#[cfg_attr(
36502    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36503    assert_instr(smaxp)
36504)]
36505#[cfg_attr(
36506    not(target_arch = "arm"),
36507    stable(feature = "neon_intrinsics", since = "1.59.0")
36508)]
36509#[cfg_attr(
36510    target_arch = "arm",
36511    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36512)]
36513pub fn vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
36514    unsafe extern "unadjusted" {
36515        #[cfg_attr(
36516            any(target_arch = "aarch64", target_arch = "arm64ec"),
36517            link_name = "llvm.aarch64.neon.smaxp.v8i8"
36518        )]
36519        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v8i8")]
36520        fn _vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
36521    }
36522    unsafe { _vpmax_s8(a, b) }
36523}
36524#[doc = "Folding maximum of adjacent pairs"]
36525#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s16)"]
36526#[inline]
36527#[target_feature(enable = "neon")]
36528#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36529#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36530#[cfg_attr(
36531    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36532    assert_instr(smaxp)
36533)]
36534#[cfg_attr(
36535    not(target_arch = "arm"),
36536    stable(feature = "neon_intrinsics", since = "1.59.0")
36537)]
36538#[cfg_attr(
36539    target_arch = "arm",
36540    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36541)]
36542pub fn vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
36543    unsafe extern "unadjusted" {
36544        #[cfg_attr(
36545            any(target_arch = "aarch64", target_arch = "arm64ec"),
36546            link_name = "llvm.aarch64.neon.smaxp.v4i16"
36547        )]
36548        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v4i16")]
36549        fn _vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
36550    }
36551    unsafe { _vpmax_s16(a, b) }
36552}
36553#[doc = "Folding maximum of adjacent pairs"]
36554#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s32)"]
36555#[inline]
36556#[target_feature(enable = "neon")]
36557#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36558#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36559#[cfg_attr(
36560    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36561    assert_instr(smaxp)
36562)]
36563#[cfg_attr(
36564    not(target_arch = "arm"),
36565    stable(feature = "neon_intrinsics", since = "1.59.0")
36566)]
36567#[cfg_attr(
36568    target_arch = "arm",
36569    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36570)]
36571pub fn vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
36572    unsafe extern "unadjusted" {
36573        #[cfg_attr(
36574            any(target_arch = "aarch64", target_arch = "arm64ec"),
36575            link_name = "llvm.aarch64.neon.smaxp.v2i32"
36576        )]
36577        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2i32")]
36578        fn _vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
36579    }
36580    unsafe { _vpmax_s32(a, b) }
36581}
36582#[doc = "Folding maximum of adjacent pairs"]
36583#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u8)"]
36584#[inline]
36585#[target_feature(enable = "neon")]
36586#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36587#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36588#[cfg_attr(
36589    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36590    assert_instr(umaxp)
36591)]
36592#[cfg_attr(
36593    not(target_arch = "arm"),
36594    stable(feature = "neon_intrinsics", since = "1.59.0")
36595)]
36596#[cfg_attr(
36597    target_arch = "arm",
36598    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36599)]
36600pub fn vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
36601    unsafe extern "unadjusted" {
36602        #[cfg_attr(
36603            any(target_arch = "aarch64", target_arch = "arm64ec"),
36604            link_name = "llvm.aarch64.neon.umaxp.v8i8"
36605        )]
36606        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v8i8")]
36607        fn _vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
36608    }
36609    unsafe { _vpmax_u8(a, b) }
36610}
36611#[doc = "Folding maximum of adjacent pairs"]
36612#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u16)"]
36613#[inline]
36614#[target_feature(enable = "neon")]
36615#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36616#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36617#[cfg_attr(
36618    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36619    assert_instr(umaxp)
36620)]
36621#[cfg_attr(
36622    not(target_arch = "arm"),
36623    stable(feature = "neon_intrinsics", since = "1.59.0")
36624)]
36625#[cfg_attr(
36626    target_arch = "arm",
36627    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36628)]
36629pub fn vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
36630    unsafe extern "unadjusted" {
36631        #[cfg_attr(
36632            any(target_arch = "aarch64", target_arch = "arm64ec"),
36633            link_name = "llvm.aarch64.neon.umaxp.v4i16"
36634        )]
36635        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v4i16")]
36636        fn _vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
36637    }
36638    unsafe { _vpmax_u16(a, b) }
36639}
36640#[doc = "Folding maximum of adjacent pairs"]
36641#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u32)"]
36642#[inline]
36643#[target_feature(enable = "neon")]
36644#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36645#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36646#[cfg_attr(
36647    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36648    assert_instr(umaxp)
36649)]
36650#[cfg_attr(
36651    not(target_arch = "arm"),
36652    stable(feature = "neon_intrinsics", since = "1.59.0")
36653)]
36654#[cfg_attr(
36655    target_arch = "arm",
36656    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36657)]
36658pub fn vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
36659    unsafe extern "unadjusted" {
36660        #[cfg_attr(
36661            any(target_arch = "aarch64", target_arch = "arm64ec"),
36662            link_name = "llvm.aarch64.neon.umaxp.v2i32"
36663        )]
36664        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v2i32")]
36665        fn _vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
36666    }
36667    unsafe { _vpmax_u32(a, b) }
36668}
36669#[doc = "Folding minimum of adjacent pairs"]
36670#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f32)"]
36671#[inline]
36672#[target_feature(enable = "neon")]
36673#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36674#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36675#[cfg_attr(
36676    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36677    assert_instr(fminp)
36678)]
36679#[cfg_attr(
36680    not(target_arch = "arm"),
36681    stable(feature = "neon_intrinsics", since = "1.59.0")
36682)]
36683#[cfg_attr(
36684    target_arch = "arm",
36685    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36686)]
36687pub fn vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
36688    unsafe extern "unadjusted" {
36689        #[cfg_attr(
36690            any(target_arch = "aarch64", target_arch = "arm64ec"),
36691            link_name = "llvm.aarch64.neon.fminp.v2f32"
36692        )]
36693        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2f32")]
36694        fn _vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
36695    }
36696    unsafe { _vpmin_f32(a, b) }
36697}
36698#[doc = "Folding minimum of adjacent pairs"]
36699#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s8)"]
36700#[inline]
36701#[target_feature(enable = "neon")]
36702#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36703#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36704#[cfg_attr(
36705    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36706    assert_instr(sminp)
36707)]
36708#[cfg_attr(
36709    not(target_arch = "arm"),
36710    stable(feature = "neon_intrinsics", since = "1.59.0")
36711)]
36712#[cfg_attr(
36713    target_arch = "arm",
36714    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36715)]
36716pub fn vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
36717    unsafe extern "unadjusted" {
36718        #[cfg_attr(
36719            any(target_arch = "aarch64", target_arch = "arm64ec"),
36720            link_name = "llvm.aarch64.neon.sminp.v8i8"
36721        )]
36722        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v8i8")]
36723        fn _vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
36724    }
36725    unsafe { _vpmin_s8(a, b) }
36726}
36727#[doc = "Folding minimum of adjacent pairs"]
36728#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s16)"]
36729#[inline]
36730#[target_feature(enable = "neon")]
36731#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36732#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36733#[cfg_attr(
36734    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36735    assert_instr(sminp)
36736)]
36737#[cfg_attr(
36738    not(target_arch = "arm"),
36739    stable(feature = "neon_intrinsics", since = "1.59.0")
36740)]
36741#[cfg_attr(
36742    target_arch = "arm",
36743    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36744)]
36745pub fn vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
36746    unsafe extern "unadjusted" {
36747        #[cfg_attr(
36748            any(target_arch = "aarch64", target_arch = "arm64ec"),
36749            link_name = "llvm.aarch64.neon.sminp.v4i16"
36750        )]
36751        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v4i16")]
36752        fn _vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
36753    }
36754    unsafe { _vpmin_s16(a, b) }
36755}
36756#[doc = "Folding minimum of adjacent pairs"]
36757#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s32)"]
36758#[inline]
36759#[target_feature(enable = "neon")]
36760#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36761#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36762#[cfg_attr(
36763    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36764    assert_instr(sminp)
36765)]
36766#[cfg_attr(
36767    not(target_arch = "arm"),
36768    stable(feature = "neon_intrinsics", since = "1.59.0")
36769)]
36770#[cfg_attr(
36771    target_arch = "arm",
36772    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36773)]
36774pub fn vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
36775    unsafe extern "unadjusted" {
36776        #[cfg_attr(
36777            any(target_arch = "aarch64", target_arch = "arm64ec"),
36778            link_name = "llvm.aarch64.neon.sminp.v2i32"
36779        )]
36780        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2i32")]
36781        fn _vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
36782    }
36783    unsafe { _vpmin_s32(a, b) }
36784}
36785#[doc = "Folding minimum of adjacent pairs"]
36786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u8)"]
36787#[inline]
36788#[target_feature(enable = "neon")]
36789#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36790#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36791#[cfg_attr(
36792    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36793    assert_instr(uminp)
36794)]
36795#[cfg_attr(
36796    not(target_arch = "arm"),
36797    stable(feature = "neon_intrinsics", since = "1.59.0")
36798)]
36799#[cfg_attr(
36800    target_arch = "arm",
36801    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36802)]
36803pub fn vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
36804    unsafe extern "unadjusted" {
36805        #[cfg_attr(
36806            any(target_arch = "aarch64", target_arch = "arm64ec"),
36807            link_name = "llvm.aarch64.neon.uminp.v8i8"
36808        )]
36809        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v8i8")]
36810        fn _vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
36811    }
36812    unsafe { _vpmin_u8(a, b) }
36813}
36814#[doc = "Folding minimum of adjacent pairs"]
36815#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u16)"]
36816#[inline]
36817#[target_feature(enable = "neon")]
36818#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36819#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36820#[cfg_attr(
36821    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36822    assert_instr(uminp)
36823)]
36824#[cfg_attr(
36825    not(target_arch = "arm"),
36826    stable(feature = "neon_intrinsics", since = "1.59.0")
36827)]
36828#[cfg_attr(
36829    target_arch = "arm",
36830    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36831)]
36832pub fn vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
36833    unsafe extern "unadjusted" {
36834        #[cfg_attr(
36835            any(target_arch = "aarch64", target_arch = "arm64ec"),
36836            link_name = "llvm.aarch64.neon.uminp.v4i16"
36837        )]
36838        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v4i16")]
36839        fn _vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
36840    }
36841    unsafe { _vpmin_u16(a, b) }
36842}
36843#[doc = "Folding minimum of adjacent pairs"]
36844#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u32)"]
36845#[inline]
36846#[target_feature(enable = "neon")]
36847#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36848#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36849#[cfg_attr(
36850    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36851    assert_instr(uminp)
36852)]
36853#[cfg_attr(
36854    not(target_arch = "arm"),
36855    stable(feature = "neon_intrinsics", since = "1.59.0")
36856)]
36857#[cfg_attr(
36858    target_arch = "arm",
36859    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36860)]
36861pub fn vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
36862    unsafe extern "unadjusted" {
36863        #[cfg_attr(
36864            any(target_arch = "aarch64", target_arch = "arm64ec"),
36865            link_name = "llvm.aarch64.neon.uminp.v2i32"
36866        )]
36867        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v2i32")]
36868        fn _vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
36869    }
36870    unsafe { _vpmin_u32(a, b) }
36871}
36872#[doc = "Signed saturating Absolute value"]
36873#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s8)"]
36874#[inline]
36875#[target_feature(enable = "neon")]
36876#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36877#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))]
36878#[cfg_attr(
36879    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36880    assert_instr(sqabs)
36881)]
36882#[cfg_attr(
36883    not(target_arch = "arm"),
36884    stable(feature = "neon_intrinsics", since = "1.59.0")
36885)]
36886#[cfg_attr(
36887    target_arch = "arm",
36888    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36889)]
36890pub fn vqabs_s8(a: int8x8_t) -> int8x8_t {
36891    unsafe extern "unadjusted" {
36892        #[cfg_attr(
36893            any(target_arch = "aarch64", target_arch = "arm64ec"),
36894            link_name = "llvm.aarch64.neon.sqabs.v8i8"
36895        )]
36896        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v8i8")]
36897        fn _vqabs_s8(a: int8x8_t) -> int8x8_t;
36898    }
36899    unsafe { _vqabs_s8(a) }
36900}
36901#[doc = "Signed saturating Absolute value"]
36902#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s8)"]
36903#[inline]
36904#[target_feature(enable = "neon")]
36905#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36906#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))]
36907#[cfg_attr(
36908    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36909    assert_instr(sqabs)
36910)]
36911#[cfg_attr(
36912    not(target_arch = "arm"),
36913    stable(feature = "neon_intrinsics", since = "1.59.0")
36914)]
36915#[cfg_attr(
36916    target_arch = "arm",
36917    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36918)]
36919pub fn vqabsq_s8(a: int8x16_t) -> int8x16_t {
36920    unsafe extern "unadjusted" {
36921        #[cfg_attr(
36922            any(target_arch = "aarch64", target_arch = "arm64ec"),
36923            link_name = "llvm.aarch64.neon.sqabs.v16i8"
36924        )]
36925        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v16i8")]
36926        fn _vqabsq_s8(a: int8x16_t) -> int8x16_t;
36927    }
36928    unsafe { _vqabsq_s8(a) }
36929}
36930#[doc = "Signed saturating Absolute value"]
36931#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s16)"]
36932#[inline]
36933#[target_feature(enable = "neon")]
36934#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36935#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))]
36936#[cfg_attr(
36937    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36938    assert_instr(sqabs)
36939)]
36940#[cfg_attr(
36941    not(target_arch = "arm"),
36942    stable(feature = "neon_intrinsics", since = "1.59.0")
36943)]
36944#[cfg_attr(
36945    target_arch = "arm",
36946    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36947)]
36948pub fn vqabs_s16(a: int16x4_t) -> int16x4_t {
36949    unsafe extern "unadjusted" {
36950        #[cfg_attr(
36951            any(target_arch = "aarch64", target_arch = "arm64ec"),
36952            link_name = "llvm.aarch64.neon.sqabs.v4i16"
36953        )]
36954        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v4i16")]
36955        fn _vqabs_s16(a: int16x4_t) -> int16x4_t;
36956    }
36957    unsafe { _vqabs_s16(a) }
36958}
36959#[doc = "Signed saturating Absolute value"]
36960#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s16)"]
36961#[inline]
36962#[target_feature(enable = "neon")]
36963#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36964#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))]
36965#[cfg_attr(
36966    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36967    assert_instr(sqabs)
36968)]
36969#[cfg_attr(
36970    not(target_arch = "arm"),
36971    stable(feature = "neon_intrinsics", since = "1.59.0")
36972)]
36973#[cfg_attr(
36974    target_arch = "arm",
36975    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36976)]
36977pub fn vqabsq_s16(a: int16x8_t) -> int16x8_t {
36978    unsafe extern "unadjusted" {
36979        #[cfg_attr(
36980            any(target_arch = "aarch64", target_arch = "arm64ec"),
36981            link_name = "llvm.aarch64.neon.sqabs.v8i16"
36982        )]
36983        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v8i16")]
36984        fn _vqabsq_s16(a: int16x8_t) -> int16x8_t;
36985    }
36986    unsafe { _vqabsq_s16(a) }
36987}
36988#[doc = "Signed saturating Absolute value"]
36989#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s32)"]
36990#[inline]
36991#[target_feature(enable = "neon")]
36992#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36993#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))]
36994#[cfg_attr(
36995    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36996    assert_instr(sqabs)
36997)]
36998#[cfg_attr(
36999    not(target_arch = "arm"),
37000    stable(feature = "neon_intrinsics", since = "1.59.0")
37001)]
37002#[cfg_attr(
37003    target_arch = "arm",
37004    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37005)]
37006pub fn vqabs_s32(a: int32x2_t) -> int32x2_t {
37007    unsafe extern "unadjusted" {
37008        #[cfg_attr(
37009            any(target_arch = "aarch64", target_arch = "arm64ec"),
37010            link_name = "llvm.aarch64.neon.sqabs.v2i32"
37011        )]
37012        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v2i32")]
37013        fn _vqabs_s32(a: int32x2_t) -> int32x2_t;
37014    }
37015    unsafe { _vqabs_s32(a) }
37016}
37017#[doc = "Signed saturating Absolute value"]
37018#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s32)"]
37019#[inline]
37020#[target_feature(enable = "neon")]
37021#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37022#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))]
37023#[cfg_attr(
37024    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37025    assert_instr(sqabs)
37026)]
37027#[cfg_attr(
37028    not(target_arch = "arm"),
37029    stable(feature = "neon_intrinsics", since = "1.59.0")
37030)]
37031#[cfg_attr(
37032    target_arch = "arm",
37033    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37034)]
37035pub fn vqabsq_s32(a: int32x4_t) -> int32x4_t {
37036    unsafe extern "unadjusted" {
37037        #[cfg_attr(
37038            any(target_arch = "aarch64", target_arch = "arm64ec"),
37039            link_name = "llvm.aarch64.neon.sqabs.v4i32"
37040        )]
37041        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v4i32")]
37042        fn _vqabsq_s32(a: int32x4_t) -> int32x4_t;
37043    }
37044    unsafe { _vqabsq_s32(a) }
37045}
37046#[doc = "Saturating add"]
37047#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s8)"]
37048#[inline]
37049#[target_feature(enable = "neon")]
37050#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37051#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))]
37052#[cfg_attr(
37053    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37054    assert_instr(sqadd)
37055)]
37056#[cfg_attr(
37057    not(target_arch = "arm"),
37058    stable(feature = "neon_intrinsics", since = "1.59.0")
37059)]
37060#[cfg_attr(
37061    target_arch = "arm",
37062    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37063)]
37064pub fn vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
37065    unsafe extern "unadjusted" {
37066        #[cfg_attr(
37067            any(target_arch = "aarch64", target_arch = "arm64ec"),
37068            link_name = "llvm.aarch64.neon.sqadd.v8i8"
37069        )]
37070        #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v8i8")]
37071        fn _vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
37072    }
37073    unsafe { _vqadd_s8(a, b) }
37074}
37075#[doc = "Saturating add"]
37076#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s8)"]
37077#[inline]
37078#[target_feature(enable = "neon")]
37079#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37080#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))]
37081#[cfg_attr(
37082    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37083    assert_instr(sqadd)
37084)]
37085#[cfg_attr(
37086    not(target_arch = "arm"),
37087    stable(feature = "neon_intrinsics", since = "1.59.0")
37088)]
37089#[cfg_attr(
37090    target_arch = "arm",
37091    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37092)]
37093pub fn vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
37094    unsafe extern "unadjusted" {
37095        #[cfg_attr(
37096            any(target_arch = "aarch64", target_arch = "arm64ec"),
37097            link_name = "llvm.aarch64.neon.sqadd.v16i8"
37098        )]
37099        #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v16i8")]
37100        fn _vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
37101    }
37102    unsafe { _vqaddq_s8(a, b) }
37103}
37104#[doc = "Saturating add"]
37105#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s16)"]
37106#[inline]
37107#[target_feature(enable = "neon")]
37108#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37109#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))]
37110#[cfg_attr(
37111    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37112    assert_instr(sqadd)
37113)]
37114#[cfg_attr(
37115    not(target_arch = "arm"),
37116    stable(feature = "neon_intrinsics", since = "1.59.0")
37117)]
37118#[cfg_attr(
37119    target_arch = "arm",
37120    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37121)]
37122pub fn vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
37123    unsafe extern "unadjusted" {
37124        #[cfg_attr(
37125            any(target_arch = "aarch64", target_arch = "arm64ec"),
37126            link_name = "llvm.aarch64.neon.sqadd.v4i16"
37127        )]
37128        #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v4i16")]
37129        fn _vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
37130    }
37131    unsafe { _vqadd_s16(a, b) }
37132}
37133#[doc = "Saturating add"]
37134#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s16)"]
37135#[inline]
37136#[target_feature(enable = "neon")]
37137#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37138#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))]
37139#[cfg_attr(
37140    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37141    assert_instr(sqadd)
37142)]
37143#[cfg_attr(
37144    not(target_arch = "arm"),
37145    stable(feature = "neon_intrinsics", since = "1.59.0")
37146)]
37147#[cfg_attr(
37148    target_arch = "arm",
37149    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37150)]
37151pub fn vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
37152    unsafe extern "unadjusted" {
37153        #[cfg_attr(
37154            any(target_arch = "aarch64", target_arch = "arm64ec"),
37155            link_name = "llvm.aarch64.neon.sqadd.v8i16"
37156        )]
37157        #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v8i16")]
37158        fn _vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
37159    }
37160    unsafe { _vqaddq_s16(a, b) }
37161}
37162#[doc = "Saturating add"]
37163#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s32)"]
37164#[inline]
37165#[target_feature(enable = "neon")]
37166#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37167#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))]
37168#[cfg_attr(
37169    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37170    assert_instr(sqadd)
37171)]
37172#[cfg_attr(
37173    not(target_arch = "arm"),
37174    stable(feature = "neon_intrinsics", since = "1.59.0")
37175)]
37176#[cfg_attr(
37177    target_arch = "arm",
37178    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37179)]
37180pub fn vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
37181    unsafe extern "unadjusted" {
37182        #[cfg_attr(
37183            any(target_arch = "aarch64", target_arch = "arm64ec"),
37184            link_name = "llvm.aarch64.neon.sqadd.v2i32"
37185        )]
37186        #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v2i32")]
37187        fn _vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
37188    }
37189    unsafe { _vqadd_s32(a, b) }
37190}
37191#[doc = "Saturating add"]
37192#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s32)"]
37193#[inline]
37194#[target_feature(enable = "neon")]
37195#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37196#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))]
37197#[cfg_attr(
37198    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37199    assert_instr(sqadd)
37200)]
37201#[cfg_attr(
37202    not(target_arch = "arm"),
37203    stable(feature = "neon_intrinsics", since = "1.59.0")
37204)]
37205#[cfg_attr(
37206    target_arch = "arm",
37207    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37208)]
37209pub fn vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
37210    unsafe extern "unadjusted" {
37211        #[cfg_attr(
37212            any(target_arch = "aarch64", target_arch = "arm64ec"),
37213            link_name = "llvm.aarch64.neon.sqadd.v4i32"
37214        )]
37215        #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v4i32")]
37216        fn _vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
37217    }
37218    unsafe { _vqaddq_s32(a, b) }
37219}
37220#[doc = "Saturating add"]
37221#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s64)"]
37222#[inline]
37223#[target_feature(enable = "neon")]
37224#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37225#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))]
37226#[cfg_attr(
37227    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37228    assert_instr(sqadd)
37229)]
37230#[cfg_attr(
37231    not(target_arch = "arm"),
37232    stable(feature = "neon_intrinsics", since = "1.59.0")
37233)]
37234#[cfg_attr(
37235    target_arch = "arm",
37236    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37237)]
37238pub fn vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
37239    unsafe extern "unadjusted" {
37240        #[cfg_attr(
37241            any(target_arch = "aarch64", target_arch = "arm64ec"),
37242            link_name = "llvm.aarch64.neon.sqadd.v1i64"
37243        )]
37244        #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v1i64")]
37245        fn _vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
37246    }
37247    unsafe { _vqadd_s64(a, b) }
37248}
37249#[doc = "Saturating add"]
37250#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s64)"]
37251#[inline]
37252#[target_feature(enable = "neon")]
37253#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37254#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))]
37255#[cfg_attr(
37256    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37257    assert_instr(sqadd)
37258)]
37259#[cfg_attr(
37260    not(target_arch = "arm"),
37261    stable(feature = "neon_intrinsics", since = "1.59.0")
37262)]
37263#[cfg_attr(
37264    target_arch = "arm",
37265    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37266)]
37267pub fn vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
37268    unsafe extern "unadjusted" {
37269        #[cfg_attr(
37270            any(target_arch = "aarch64", target_arch = "arm64ec"),
37271            link_name = "llvm.aarch64.neon.sqadd.v2i64"
37272        )]
37273        #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v2i64")]
37274        fn _vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
37275    }
37276    unsafe { _vqaddq_s64(a, b) }
37277}
37278#[doc = "Saturating add"]
37279#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u8)"]
37280#[inline]
37281#[target_feature(enable = "neon")]
37282#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37283#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))]
37284#[cfg_attr(
37285    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37286    assert_instr(uqadd)
37287)]
37288#[cfg_attr(
37289    not(target_arch = "arm"),
37290    stable(feature = "neon_intrinsics", since = "1.59.0")
37291)]
37292#[cfg_attr(
37293    target_arch = "arm",
37294    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37295)]
37296pub fn vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
37297    unsafe extern "unadjusted" {
37298        #[cfg_attr(
37299            any(target_arch = "aarch64", target_arch = "arm64ec"),
37300            link_name = "llvm.aarch64.neon.uqadd.v8i8"
37301        )]
37302        #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v8i8")]
37303        fn _vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
37304    }
37305    unsafe { _vqadd_u8(a, b) }
37306}
37307#[doc = "Saturating add"]
37308#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u8)"]
37309#[inline]
37310#[target_feature(enable = "neon")]
37311#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37312#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))]
37313#[cfg_attr(
37314    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37315    assert_instr(uqadd)
37316)]
37317#[cfg_attr(
37318    not(target_arch = "arm"),
37319    stable(feature = "neon_intrinsics", since = "1.59.0")
37320)]
37321#[cfg_attr(
37322    target_arch = "arm",
37323    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37324)]
37325pub fn vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
37326    unsafe extern "unadjusted" {
37327        #[cfg_attr(
37328            any(target_arch = "aarch64", target_arch = "arm64ec"),
37329            link_name = "llvm.aarch64.neon.uqadd.v16i8"
37330        )]
37331        #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v16i8")]
37332        fn _vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
37333    }
37334    unsafe { _vqaddq_u8(a, b) }
37335}
37336#[doc = "Saturating add"]
37337#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u16)"]
37338#[inline]
37339#[target_feature(enable = "neon")]
37340#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37341#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))]
37342#[cfg_attr(
37343    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37344    assert_instr(uqadd)
37345)]
37346#[cfg_attr(
37347    not(target_arch = "arm"),
37348    stable(feature = "neon_intrinsics", since = "1.59.0")
37349)]
37350#[cfg_attr(
37351    target_arch = "arm",
37352    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37353)]
37354pub fn vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
37355    unsafe extern "unadjusted" {
37356        #[cfg_attr(
37357            any(target_arch = "aarch64", target_arch = "arm64ec"),
37358            link_name = "llvm.aarch64.neon.uqadd.v4i16"
37359        )]
37360        #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v4i16")]
37361        fn _vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
37362    }
37363    unsafe { _vqadd_u16(a, b) }
37364}
37365#[doc = "Saturating add"]
37366#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u16)"]
37367#[inline]
37368#[target_feature(enable = "neon")]
37369#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37370#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))]
37371#[cfg_attr(
37372    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37373    assert_instr(uqadd)
37374)]
37375#[cfg_attr(
37376    not(target_arch = "arm"),
37377    stable(feature = "neon_intrinsics", since = "1.59.0")
37378)]
37379#[cfg_attr(
37380    target_arch = "arm",
37381    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37382)]
37383pub fn vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
37384    unsafe extern "unadjusted" {
37385        #[cfg_attr(
37386            any(target_arch = "aarch64", target_arch = "arm64ec"),
37387            link_name = "llvm.aarch64.neon.uqadd.v8i16"
37388        )]
37389        #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v8i16")]
37390        fn _vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
37391    }
37392    unsafe { _vqaddq_u16(a, b) }
37393}
37394#[doc = "Saturating add"]
37395#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u32)"]
37396#[inline]
37397#[target_feature(enable = "neon")]
37398#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37399#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))]
37400#[cfg_attr(
37401    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37402    assert_instr(uqadd)
37403)]
37404#[cfg_attr(
37405    not(target_arch = "arm"),
37406    stable(feature = "neon_intrinsics", since = "1.59.0")
37407)]
37408#[cfg_attr(
37409    target_arch = "arm",
37410    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37411)]
37412pub fn vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
37413    unsafe extern "unadjusted" {
37414        #[cfg_attr(
37415            any(target_arch = "aarch64", target_arch = "arm64ec"),
37416            link_name = "llvm.aarch64.neon.uqadd.v2i32"
37417        )]
37418        #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v2i32")]
37419        fn _vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
37420    }
37421    unsafe { _vqadd_u32(a, b) }
37422}
37423#[doc = "Saturating add"]
37424#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u32)"]
37425#[inline]
37426#[target_feature(enable = "neon")]
37427#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37428#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))]
37429#[cfg_attr(
37430    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37431    assert_instr(uqadd)
37432)]
37433#[cfg_attr(
37434    not(target_arch = "arm"),
37435    stable(feature = "neon_intrinsics", since = "1.59.0")
37436)]
37437#[cfg_attr(
37438    target_arch = "arm",
37439    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37440)]
37441pub fn vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
37442    unsafe extern "unadjusted" {
37443        #[cfg_attr(
37444            any(target_arch = "aarch64", target_arch = "arm64ec"),
37445            link_name = "llvm.aarch64.neon.uqadd.v4i32"
37446        )]
37447        #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v4i32")]
37448        fn _vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
37449    }
37450    unsafe { _vqaddq_u32(a, b) }
37451}
37452#[doc = "Saturating add"]
37453#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u64)"]
37454#[inline]
37455#[target_feature(enable = "neon")]
37456#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37457#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))]
37458#[cfg_attr(
37459    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37460    assert_instr(uqadd)
37461)]
37462#[cfg_attr(
37463    not(target_arch = "arm"),
37464    stable(feature = "neon_intrinsics", since = "1.59.0")
37465)]
37466#[cfg_attr(
37467    target_arch = "arm",
37468    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37469)]
37470pub fn vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
37471    unsafe extern "unadjusted" {
37472        #[cfg_attr(
37473            any(target_arch = "aarch64", target_arch = "arm64ec"),
37474            link_name = "llvm.aarch64.neon.uqadd.v1i64"
37475        )]
37476        #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v1i64")]
37477        fn _vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t;
37478    }
37479    unsafe { _vqadd_u64(a, b) }
37480}
37481#[doc = "Saturating add"]
37482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u64)"]
37483#[inline]
37484#[target_feature(enable = "neon")]
37485#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37486#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))]
37487#[cfg_attr(
37488    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37489    assert_instr(uqadd)
37490)]
37491#[cfg_attr(
37492    not(target_arch = "arm"),
37493    stable(feature = "neon_intrinsics", since = "1.59.0")
37494)]
37495#[cfg_attr(
37496    target_arch = "arm",
37497    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37498)]
37499pub fn vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
37500    unsafe extern "unadjusted" {
37501        #[cfg_attr(
37502            any(target_arch = "aarch64", target_arch = "arm64ec"),
37503            link_name = "llvm.aarch64.neon.uqadd.v2i64"
37504        )]
37505        #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v2i64")]
37506        fn _vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t;
37507    }
37508    unsafe { _vqaddq_u64(a, b) }
37509}
37510#[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
37511#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s16)"]
37512#[inline]
37513#[target_feature(enable = "neon")]
37514#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37515#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 2))]
37516#[cfg_attr(
37517    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37518    assert_instr(sqdmlal, N = 2)
37519)]
37520#[rustc_legacy_const_generics(3)]
37521#[cfg_attr(
37522    not(target_arch = "arm"),
37523    stable(feature = "neon_intrinsics", since = "1.59.0")
37524)]
37525#[cfg_attr(
37526    target_arch = "arm",
37527    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37528)]
37529pub fn vqdmlal_lane_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
37530    static_assert_uimm_bits!(N, 2);
37531    vqaddq_s32(a, vqdmull_lane_s16::<N>(b, c))
37532}
37533#[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
37534#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s32)"]
37535#[inline]
37536#[target_feature(enable = "neon")]
37537#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37538#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 1))]
37539#[cfg_attr(
37540    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37541    assert_instr(sqdmlal, N = 1)
37542)]
37543#[rustc_legacy_const_generics(3)]
37544#[cfg_attr(
37545    not(target_arch = "arm"),
37546    stable(feature = "neon_intrinsics", since = "1.59.0")
37547)]
37548#[cfg_attr(
37549    target_arch = "arm",
37550    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37551)]
37552pub fn vqdmlal_lane_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
37553    static_assert_uimm_bits!(N, 1);
37554    vqaddq_s64(a, vqdmull_lane_s32::<N>(b, c))
37555}
37556#[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
37557#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s16)"]
37558#[inline]
37559#[target_feature(enable = "neon")]
37560#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37561#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
37562#[cfg_attr(
37563    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37564    assert_instr(sqdmlal)
37565)]
37566#[cfg_attr(
37567    not(target_arch = "arm"),
37568    stable(feature = "neon_intrinsics", since = "1.59.0")
37569)]
37570#[cfg_attr(
37571    target_arch = "arm",
37572    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37573)]
37574pub fn vqdmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
37575    vqaddq_s32(a, vqdmull_n_s16(b, c))
37576}
37577#[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
37578#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s32)"]
37579#[inline]
37580#[target_feature(enable = "neon")]
37581#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37582#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
37583#[cfg_attr(
37584    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37585    assert_instr(sqdmlal)
37586)]
37587#[cfg_attr(
37588    not(target_arch = "arm"),
37589    stable(feature = "neon_intrinsics", since = "1.59.0")
37590)]
37591#[cfg_attr(
37592    target_arch = "arm",
37593    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37594)]
37595pub fn vqdmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
37596    vqaddq_s64(a, vqdmull_n_s32(b, c))
37597}
37598#[doc = "Signed saturating doubling multiply-add long"]
37599#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s16)"]
37600#[inline]
37601#[target_feature(enable = "neon")]
37602#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37603#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
37604#[cfg_attr(
37605    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37606    assert_instr(sqdmlal)
37607)]
37608#[cfg_attr(
37609    not(target_arch = "arm"),
37610    stable(feature = "neon_intrinsics", since = "1.59.0")
37611)]
37612#[cfg_attr(
37613    target_arch = "arm",
37614    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37615)]
37616pub fn vqdmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
37617    vqaddq_s32(a, vqdmull_s16(b, c))
37618}
37619#[doc = "Signed saturating doubling multiply-add long"]
37620#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s32)"]
37621#[inline]
37622#[target_feature(enable = "neon")]
37623#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37624#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
37625#[cfg_attr(
37626    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37627    assert_instr(sqdmlal)
37628)]
37629#[cfg_attr(
37630    not(target_arch = "arm"),
37631    stable(feature = "neon_intrinsics", since = "1.59.0")
37632)]
37633#[cfg_attr(
37634    target_arch = "arm",
37635    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37636)]
37637pub fn vqdmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
37638    vqaddq_s64(a, vqdmull_s32(b, c))
37639}
37640#[doc = "Vector widening saturating doubling multiply subtract with scalar"]
37641#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s16)"]
37642#[inline]
37643#[target_feature(enable = "neon")]
37644#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37645#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 2))]
37646#[cfg_attr(
37647    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37648    assert_instr(sqdmlsl, N = 2)
37649)]
37650#[rustc_legacy_const_generics(3)]
37651#[cfg_attr(
37652    not(target_arch = "arm"),
37653    stable(feature = "neon_intrinsics", since = "1.59.0")
37654)]
37655#[cfg_attr(
37656    target_arch = "arm",
37657    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37658)]
37659pub fn vqdmlsl_lane_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
37660    static_assert_uimm_bits!(N, 2);
37661    vqsubq_s32(a, vqdmull_lane_s16::<N>(b, c))
37662}
37663#[doc = "Vector widening saturating doubling multiply subtract with scalar"]
37664#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s32)"]
37665#[inline]
37666#[target_feature(enable = "neon")]
37667#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37668#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 1))]
37669#[cfg_attr(
37670    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37671    assert_instr(sqdmlsl, N = 1)
37672)]
37673#[rustc_legacy_const_generics(3)]
37674#[cfg_attr(
37675    not(target_arch = "arm"),
37676    stable(feature = "neon_intrinsics", since = "1.59.0")
37677)]
37678#[cfg_attr(
37679    target_arch = "arm",
37680    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37681)]
37682pub fn vqdmlsl_lane_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
37683    static_assert_uimm_bits!(N, 1);
37684    vqsubq_s64(a, vqdmull_lane_s32::<N>(b, c))
37685}
37686#[doc = "Vector widening saturating doubling multiply subtract with scalar"]
37687#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s16)"]
37688#[inline]
37689#[target_feature(enable = "neon")]
37690#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37691#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
37692#[cfg_attr(
37693    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37694    assert_instr(sqdmlsl)
37695)]
37696#[cfg_attr(
37697    not(target_arch = "arm"),
37698    stable(feature = "neon_intrinsics", since = "1.59.0")
37699)]
37700#[cfg_attr(
37701    target_arch = "arm",
37702    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37703)]
37704pub fn vqdmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
37705    vqsubq_s32(a, vqdmull_n_s16(b, c))
37706}
37707#[doc = "Vector widening saturating doubling multiply subtract with scalar"]
37708#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s32)"]
37709#[inline]
37710#[target_feature(enable = "neon")]
37711#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37712#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
37713#[cfg_attr(
37714    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37715    assert_instr(sqdmlsl)
37716)]
37717#[cfg_attr(
37718    not(target_arch = "arm"),
37719    stable(feature = "neon_intrinsics", since = "1.59.0")
37720)]
37721#[cfg_attr(
37722    target_arch = "arm",
37723    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37724)]
37725pub fn vqdmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
37726    vqsubq_s64(a, vqdmull_n_s32(b, c))
37727}
37728#[doc = "Signed saturating doubling multiply-subtract long"]
37729#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s16)"]
37730#[inline]
37731#[target_feature(enable = "neon")]
37732#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37733#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
37734#[cfg_attr(
37735    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37736    assert_instr(sqdmlsl)
37737)]
37738#[cfg_attr(
37739    not(target_arch = "arm"),
37740    stable(feature = "neon_intrinsics", since = "1.59.0")
37741)]
37742#[cfg_attr(
37743    target_arch = "arm",
37744    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37745)]
37746pub fn vqdmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
37747    vqsubq_s32(a, vqdmull_s16(b, c))
37748}
37749#[doc = "Signed saturating doubling multiply-subtract long"]
37750#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s32)"]
37751#[inline]
37752#[target_feature(enable = "neon")]
37753#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37754#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
37755#[cfg_attr(
37756    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37757    assert_instr(sqdmlsl)
37758)]
37759#[cfg_attr(
37760    not(target_arch = "arm"),
37761    stable(feature = "neon_intrinsics", since = "1.59.0")
37762)]
37763#[cfg_attr(
37764    target_arch = "arm",
37765    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37766)]
37767pub fn vqdmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
37768    vqsubq_s64(a, vqdmull_s32(b, c))
37769}
37770#[doc = "Vector saturating doubling multiply high by scalar"]
37771#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s16)"]
37772#[inline]
37773#[target_feature(enable = "neon")]
37774#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37775#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
37776#[cfg_attr(
37777    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37778    assert_instr(sqdmulh, LANE = 0)
37779)]
37780#[rustc_legacy_const_generics(2)]
37781#[cfg_attr(
37782    not(target_arch = "arm"),
37783    stable(feature = "neon_intrinsics", since = "1.59.0")
37784)]
37785#[cfg_attr(
37786    target_arch = "arm",
37787    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37788)]
37789pub fn vqdmulh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t {
37790    static_assert_uimm_bits!(LANE, 3);
37791    unsafe { vqdmulh_s16(a, vdup_n_s16(simd_extract!(b, LANE as u32))) }
37792}
37793#[doc = "Vector saturating doubling multiply high by scalar"]
37794#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s16)"]
37795#[inline]
37796#[target_feature(enable = "neon")]
37797#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37798#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
37799#[cfg_attr(
37800    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37801    assert_instr(sqdmulh, LANE = 0)
37802)]
37803#[rustc_legacy_const_generics(2)]
37804#[cfg_attr(
37805    not(target_arch = "arm"),
37806    stable(feature = "neon_intrinsics", since = "1.59.0")
37807)]
37808#[cfg_attr(
37809    target_arch = "arm",
37810    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37811)]
37812pub fn vqdmulhq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
37813    static_assert_uimm_bits!(LANE, 3);
37814    unsafe { vqdmulhq_s16(a, vdupq_n_s16(simd_extract!(b, LANE as u32))) }
37815}
37816#[doc = "Vector saturating doubling multiply high by scalar"]
37817#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s32)"]
37818#[inline]
37819#[target_feature(enable = "neon")]
37820#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37821#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
37822#[cfg_attr(
37823    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37824    assert_instr(sqdmulh, LANE = 0)
37825)]
37826#[rustc_legacy_const_generics(2)]
37827#[cfg_attr(
37828    not(target_arch = "arm"),
37829    stable(feature = "neon_intrinsics", since = "1.59.0")
37830)]
37831#[cfg_attr(
37832    target_arch = "arm",
37833    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37834)]
37835pub fn vqdmulh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t {
37836    static_assert_uimm_bits!(LANE, 2);
37837    unsafe { vqdmulh_s32(a, vdup_n_s32(simd_extract!(b, LANE as u32))) }
37838}
37839#[doc = "Vector saturating doubling multiply high by scalar"]
37840#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s32)"]
37841#[inline]
37842#[target_feature(enable = "neon")]
37843#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37844#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
37845#[cfg_attr(
37846    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37847    assert_instr(sqdmulh, LANE = 0)
37848)]
37849#[rustc_legacy_const_generics(2)]
37850#[cfg_attr(
37851    not(target_arch = "arm"),
37852    stable(feature = "neon_intrinsics", since = "1.59.0")
37853)]
37854#[cfg_attr(
37855    target_arch = "arm",
37856    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37857)]
37858pub fn vqdmulhq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
37859    static_assert_uimm_bits!(LANE, 2);
37860    unsafe { vqdmulhq_s32(a, vdupq_n_s32(simd_extract!(b, LANE as u32))) }
37861}
37862#[doc = "Vector saturating doubling multiply high with scalar"]
37863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s16)"]
37864#[inline]
37865#[target_feature(enable = "neon")]
37866#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37867#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
37868#[cfg_attr(
37869    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37870    assert_instr(sqdmulh)
37871)]
37872#[cfg_attr(
37873    not(target_arch = "arm"),
37874    stable(feature = "neon_intrinsics", since = "1.59.0")
37875)]
37876#[cfg_attr(
37877    target_arch = "arm",
37878    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37879)]
37880pub fn vqdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
37881    let b: int16x4_t = vdup_n_s16(b);
37882    vqdmulh_s16(a, b)
37883}
37884#[doc = "Vector saturating doubling multiply high with scalar"]
37885#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s16)"]
37886#[inline]
37887#[target_feature(enable = "neon")]
37888#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37889#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
37890#[cfg_attr(
37891    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37892    assert_instr(sqdmulh)
37893)]
37894#[cfg_attr(
37895    not(target_arch = "arm"),
37896    stable(feature = "neon_intrinsics", since = "1.59.0")
37897)]
37898#[cfg_attr(
37899    target_arch = "arm",
37900    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37901)]
37902pub fn vqdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
37903    let b: int16x8_t = vdupq_n_s16(b);
37904    vqdmulhq_s16(a, b)
37905}
37906#[doc = "Vector saturating doubling multiply high with scalar"]
37907#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s32)"]
37908#[inline]
37909#[target_feature(enable = "neon")]
37910#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37911#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
37912#[cfg_attr(
37913    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37914    assert_instr(sqdmulh)
37915)]
37916#[cfg_attr(
37917    not(target_arch = "arm"),
37918    stable(feature = "neon_intrinsics", since = "1.59.0")
37919)]
37920#[cfg_attr(
37921    target_arch = "arm",
37922    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37923)]
37924pub fn vqdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
37925    let b: int32x2_t = vdup_n_s32(b);
37926    vqdmulh_s32(a, b)
37927}
37928#[doc = "Vector saturating doubling multiply high with scalar"]
37929#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s32)"]
37930#[inline]
37931#[target_feature(enable = "neon")]
37932#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37933#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
37934#[cfg_attr(
37935    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37936    assert_instr(sqdmulh)
37937)]
37938#[cfg_attr(
37939    not(target_arch = "arm"),
37940    stable(feature = "neon_intrinsics", since = "1.59.0")
37941)]
37942#[cfg_attr(
37943    target_arch = "arm",
37944    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37945)]
37946pub fn vqdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
37947    let b: int32x4_t = vdupq_n_s32(b);
37948    vqdmulhq_s32(a, b)
37949}
37950#[doc = "Signed saturating doubling multiply returning high half"]
37951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s16)"]
37952#[inline]
37953#[target_feature(enable = "neon")]
37954#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37955#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
37956#[cfg_attr(
37957    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37958    assert_instr(sqdmulh)
37959)]
37960#[cfg_attr(
37961    not(target_arch = "arm"),
37962    stable(feature = "neon_intrinsics", since = "1.59.0")
37963)]
37964#[cfg_attr(
37965    target_arch = "arm",
37966    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37967)]
37968pub fn vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
37969    unsafe extern "unadjusted" {
37970        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v4i16")]
37971        #[cfg_attr(
37972            any(target_arch = "aarch64", target_arch = "arm64ec"),
37973            link_name = "llvm.aarch64.neon.sqdmulh.v4i16"
37974        )]
37975        fn _vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
37976    }
37977    unsafe { _vqdmulh_s16(a, b) }
37978}
37979#[doc = "Signed saturating doubling multiply returning high half"]
37980#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s16)"]
37981#[inline]
37982#[target_feature(enable = "neon")]
37983#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37984#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
37985#[cfg_attr(
37986    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37987    assert_instr(sqdmulh)
37988)]
37989#[cfg_attr(
37990    not(target_arch = "arm"),
37991    stable(feature = "neon_intrinsics", since = "1.59.0")
37992)]
37993#[cfg_attr(
37994    target_arch = "arm",
37995    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37996)]
37997pub fn vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
37998    unsafe extern "unadjusted" {
37999        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v8i16")]
38000        #[cfg_attr(
38001            any(target_arch = "aarch64", target_arch = "arm64ec"),
38002            link_name = "llvm.aarch64.neon.sqdmulh.v8i16"
38003        )]
38004        fn _vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
38005    }
38006    unsafe { _vqdmulhq_s16(a, b) }
38007}
38008#[doc = "Signed saturating doubling multiply returning high half"]
38009#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s32)"]
38010#[inline]
38011#[target_feature(enable = "neon")]
38012#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38013#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
38014#[cfg_attr(
38015    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38016    assert_instr(sqdmulh)
38017)]
38018#[cfg_attr(
38019    not(target_arch = "arm"),
38020    stable(feature = "neon_intrinsics", since = "1.59.0")
38021)]
38022#[cfg_attr(
38023    target_arch = "arm",
38024    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38025)]
38026pub fn vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
38027    unsafe extern "unadjusted" {
38028        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v2i32")]
38029        #[cfg_attr(
38030            any(target_arch = "aarch64", target_arch = "arm64ec"),
38031            link_name = "llvm.aarch64.neon.sqdmulh.v2i32"
38032        )]
38033        fn _vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
38034    }
38035    unsafe { _vqdmulh_s32(a, b) }
38036}
38037#[doc = "Signed saturating doubling multiply returning high half"]
38038#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s32)"]
38039#[inline]
38040#[target_feature(enable = "neon")]
38041#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38042#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
38043#[cfg_attr(
38044    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38045    assert_instr(sqdmulh)
38046)]
38047#[cfg_attr(
38048    not(target_arch = "arm"),
38049    stable(feature = "neon_intrinsics", since = "1.59.0")
38050)]
38051#[cfg_attr(
38052    target_arch = "arm",
38053    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38054)]
38055pub fn vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
38056    unsafe extern "unadjusted" {
38057        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v4i32")]
38058        #[cfg_attr(
38059            any(target_arch = "aarch64", target_arch = "arm64ec"),
38060            link_name = "llvm.aarch64.neon.sqdmulh.v4i32"
38061        )]
38062        fn _vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
38063    }
38064    unsafe { _vqdmulhq_s32(a, b) }
38065}
38066#[doc = "Vector saturating doubling long multiply by scalar"]
38067#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s16)"]
38068#[inline]
38069#[target_feature(enable = "neon")]
38070#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38071#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 2))]
38072#[cfg_attr(
38073    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38074    assert_instr(sqdmull, N = 2)
38075)]
38076#[rustc_legacy_const_generics(2)]
38077#[cfg_attr(
38078    not(target_arch = "arm"),
38079    stable(feature = "neon_intrinsics", since = "1.59.0")
38080)]
38081#[cfg_attr(
38082    target_arch = "arm",
38083    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38084)]
38085pub fn vqdmull_lane_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int32x4_t {
38086    static_assert_uimm_bits!(N, 2);
38087    unsafe {
38088        let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]);
38089        vqdmull_s16(a, b)
38090    }
38091}
38092#[doc = "Vector saturating doubling long multiply by scalar"]
38093#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s32)"]
38094#[inline]
38095#[target_feature(enable = "neon")]
38096#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38097#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 1))]
38098#[cfg_attr(
38099    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38100    assert_instr(sqdmull, N = 1)
38101)]
38102#[rustc_legacy_const_generics(2)]
38103#[cfg_attr(
38104    not(target_arch = "arm"),
38105    stable(feature = "neon_intrinsics", since = "1.59.0")
38106)]
38107#[cfg_attr(
38108    target_arch = "arm",
38109    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38110)]
38111pub fn vqdmull_lane_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int64x2_t {
38112    static_assert_uimm_bits!(N, 1);
38113    unsafe {
38114        let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]);
38115        vqdmull_s32(a, b)
38116    }
38117}
38118#[doc = "Vector saturating doubling long multiply with scalar"]
38119#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s16)"]
38120#[inline]
38121#[target_feature(enable = "neon")]
38122#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38123#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
38124#[cfg_attr(
38125    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38126    assert_instr(sqdmull)
38127)]
38128#[cfg_attr(
38129    not(target_arch = "arm"),
38130    stable(feature = "neon_intrinsics", since = "1.59.0")
38131)]
38132#[cfg_attr(
38133    target_arch = "arm",
38134    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38135)]
38136pub fn vqdmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t {
38137    vqdmull_s16(a, vdup_n_s16(b))
38138}
38139#[doc = "Vector saturating doubling long multiply with scalar"]
38140#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s32)"]
38141#[inline]
38142#[target_feature(enable = "neon")]
38143#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38144#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
38145#[cfg_attr(
38146    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38147    assert_instr(sqdmull)
38148)]
38149#[cfg_attr(
38150    not(target_arch = "arm"),
38151    stable(feature = "neon_intrinsics", since = "1.59.0")
38152)]
38153#[cfg_attr(
38154    target_arch = "arm",
38155    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38156)]
38157pub fn vqdmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t {
38158    vqdmull_s32(a, vdup_n_s32(b))
38159}
38160#[doc = "Signed saturating doubling multiply long"]
38161#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s16)"]
38162#[inline]
38163#[target_feature(enable = "neon")]
38164#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38165#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
38166#[cfg_attr(
38167    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38168    assert_instr(sqdmull)
38169)]
38170#[cfg_attr(
38171    not(target_arch = "arm"),
38172    stable(feature = "neon_intrinsics", since = "1.59.0")
38173)]
38174#[cfg_attr(
38175    target_arch = "arm",
38176    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38177)]
38178pub fn vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
38179    unsafe extern "unadjusted" {
38180        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmull.v4i32")]
38181        #[cfg_attr(
38182            any(target_arch = "aarch64", target_arch = "arm64ec"),
38183            link_name = "llvm.aarch64.neon.sqdmull.v4i32"
38184        )]
38185        fn _vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t;
38186    }
38187    unsafe { _vqdmull_s16(a, b) }
38188}
38189#[doc = "Signed saturating doubling multiply long"]
38190#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s32)"]
38191#[inline]
38192#[target_feature(enable = "neon")]
38193#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38194#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
38195#[cfg_attr(
38196    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38197    assert_instr(sqdmull)
38198)]
38199#[cfg_attr(
38200    not(target_arch = "arm"),
38201    stable(feature = "neon_intrinsics", since = "1.59.0")
38202)]
38203#[cfg_attr(
38204    target_arch = "arm",
38205    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38206)]
38207pub fn vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
38208    unsafe extern "unadjusted" {
38209        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmull.v2i64")]
38210        #[cfg_attr(
38211            any(target_arch = "aarch64", target_arch = "arm64ec"),
38212            link_name = "llvm.aarch64.neon.sqdmull.v2i64"
38213        )]
38214        fn _vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t;
38215    }
38216    unsafe { _vqdmull_s32(a, b) }
38217}
38218#[doc = "Signed saturating extract narrow"]
38219#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s16)"]
38220#[inline]
38221#[target_feature(enable = "neon")]
38222#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38223#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
38224#[cfg_attr(
38225    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38226    assert_instr(sqxtn)
38227)]
38228#[cfg_attr(
38229    not(target_arch = "arm"),
38230    stable(feature = "neon_intrinsics", since = "1.59.0")
38231)]
38232#[cfg_attr(
38233    target_arch = "arm",
38234    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38235)]
38236pub fn vqmovn_s16(a: int16x8_t) -> int8x8_t {
38237    unsafe extern "unadjusted" {
38238        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v8i8")]
38239        #[cfg_attr(
38240            any(target_arch = "aarch64", target_arch = "arm64ec"),
38241            link_name = "llvm.aarch64.neon.sqxtn.v8i8"
38242        )]
38243        fn _vqmovn_s16(a: int16x8_t) -> int8x8_t;
38244    }
38245    unsafe { _vqmovn_s16(a) }
38246}
38247#[doc = "Signed saturating extract narrow"]
38248#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s32)"]
38249#[inline]
38250#[target_feature(enable = "neon")]
38251#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38252#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
38253#[cfg_attr(
38254    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38255    assert_instr(sqxtn)
38256)]
38257#[cfg_attr(
38258    not(target_arch = "arm"),
38259    stable(feature = "neon_intrinsics", since = "1.59.0")
38260)]
38261#[cfg_attr(
38262    target_arch = "arm",
38263    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38264)]
38265pub fn vqmovn_s32(a: int32x4_t) -> int16x4_t {
38266    unsafe extern "unadjusted" {
38267        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v4i16")]
38268        #[cfg_attr(
38269            any(target_arch = "aarch64", target_arch = "arm64ec"),
38270            link_name = "llvm.aarch64.neon.sqxtn.v4i16"
38271        )]
38272        fn _vqmovn_s32(a: int32x4_t) -> int16x4_t;
38273    }
38274    unsafe { _vqmovn_s32(a) }
38275}
38276#[doc = "Signed saturating extract narrow"]
38277#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s64)"]
38278#[inline]
38279#[target_feature(enable = "neon")]
38280#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38281#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
38282#[cfg_attr(
38283    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38284    assert_instr(sqxtn)
38285)]
38286#[cfg_attr(
38287    not(target_arch = "arm"),
38288    stable(feature = "neon_intrinsics", since = "1.59.0")
38289)]
38290#[cfg_attr(
38291    target_arch = "arm",
38292    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38293)]
38294pub fn vqmovn_s64(a: int64x2_t) -> int32x2_t {
38295    unsafe extern "unadjusted" {
38296        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v2i32")]
38297        #[cfg_attr(
38298            any(target_arch = "aarch64", target_arch = "arm64ec"),
38299            link_name = "llvm.aarch64.neon.sqxtn.v2i32"
38300        )]
38301        fn _vqmovn_s64(a: int64x2_t) -> int32x2_t;
38302    }
38303    unsafe { _vqmovn_s64(a) }
38304}
38305#[doc = "Unsigned saturating extract narrow"]
38306#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u16)"]
38307#[inline]
38308#[target_feature(enable = "neon")]
38309#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38310#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
38311#[cfg_attr(
38312    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38313    assert_instr(uqxtn)
38314)]
38315#[cfg_attr(
38316    not(target_arch = "arm"),
38317    stable(feature = "neon_intrinsics", since = "1.59.0")
38318)]
38319#[cfg_attr(
38320    target_arch = "arm",
38321    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38322)]
38323pub fn vqmovn_u16(a: uint16x8_t) -> uint8x8_t {
38324    unsafe extern "unadjusted" {
38325        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v8i8")]
38326        #[cfg_attr(
38327            any(target_arch = "aarch64", target_arch = "arm64ec"),
38328            link_name = "llvm.aarch64.neon.uqxtn.v8i8"
38329        )]
38330        fn _vqmovn_u16(a: uint16x8_t) -> uint8x8_t;
38331    }
38332    unsafe { _vqmovn_u16(a) }
38333}
38334#[doc = "Unsigned saturating extract narrow"]
38335#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u32)"]
38336#[inline]
38337#[target_feature(enable = "neon")]
38338#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38339#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
38340#[cfg_attr(
38341    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38342    assert_instr(uqxtn)
38343)]
38344#[cfg_attr(
38345    not(target_arch = "arm"),
38346    stable(feature = "neon_intrinsics", since = "1.59.0")
38347)]
38348#[cfg_attr(
38349    target_arch = "arm",
38350    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38351)]
38352pub fn vqmovn_u32(a: uint32x4_t) -> uint16x4_t {
38353    unsafe extern "unadjusted" {
38354        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v4i16")]
38355        #[cfg_attr(
38356            any(target_arch = "aarch64", target_arch = "arm64ec"),
38357            link_name = "llvm.aarch64.neon.uqxtn.v4i16"
38358        )]
38359        fn _vqmovn_u32(a: uint32x4_t) -> uint16x4_t;
38360    }
38361    unsafe { _vqmovn_u32(a) }
38362}
38363#[doc = "Unsigned saturating extract narrow"]
38364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u64)"]
38365#[inline]
38366#[target_feature(enable = "neon")]
38367#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38368#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
38369#[cfg_attr(
38370    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38371    assert_instr(uqxtn)
38372)]
38373#[cfg_attr(
38374    not(target_arch = "arm"),
38375    stable(feature = "neon_intrinsics", since = "1.59.0")
38376)]
38377#[cfg_attr(
38378    target_arch = "arm",
38379    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38380)]
38381pub fn vqmovn_u64(a: uint64x2_t) -> uint32x2_t {
38382    unsafe extern "unadjusted" {
38383        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v2i32")]
38384        #[cfg_attr(
38385            any(target_arch = "aarch64", target_arch = "arm64ec"),
38386            link_name = "llvm.aarch64.neon.uqxtn.v2i32"
38387        )]
38388        fn _vqmovn_u64(a: uint64x2_t) -> uint32x2_t;
38389    }
38390    unsafe { _vqmovn_u64(a) }
38391}
38392#[doc = "Signed saturating extract unsigned narrow"]
38393#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s16)"]
38394#[inline]
38395#[target_feature(enable = "neon")]
38396#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38397#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
38398#[cfg_attr(
38399    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38400    assert_instr(sqxtun)
38401)]
38402#[cfg_attr(
38403    not(target_arch = "arm"),
38404    stable(feature = "neon_intrinsics", since = "1.59.0")
38405)]
38406#[cfg_attr(
38407    target_arch = "arm",
38408    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38409)]
38410pub fn vqmovun_s16(a: int16x8_t) -> uint8x8_t {
38411    unsafe extern "unadjusted" {
38412        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v8i8")]
38413        #[cfg_attr(
38414            any(target_arch = "aarch64", target_arch = "arm64ec"),
38415            link_name = "llvm.aarch64.neon.sqxtun.v8i8"
38416        )]
38417        fn _vqmovun_s16(a: int16x8_t) -> uint8x8_t;
38418    }
38419    unsafe { _vqmovun_s16(a) }
38420}
38421#[doc = "Signed saturating extract unsigned narrow"]
38422#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s32)"]
38423#[inline]
38424#[target_feature(enable = "neon")]
38425#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38426#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
38427#[cfg_attr(
38428    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38429    assert_instr(sqxtun)
38430)]
38431#[cfg_attr(
38432    not(target_arch = "arm"),
38433    stable(feature = "neon_intrinsics", since = "1.59.0")
38434)]
38435#[cfg_attr(
38436    target_arch = "arm",
38437    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38438)]
38439pub fn vqmovun_s32(a: int32x4_t) -> uint16x4_t {
38440    unsafe extern "unadjusted" {
38441        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v4i16")]
38442        #[cfg_attr(
38443            any(target_arch = "aarch64", target_arch = "arm64ec"),
38444            link_name = "llvm.aarch64.neon.sqxtun.v4i16"
38445        )]
38446        fn _vqmovun_s32(a: int32x4_t) -> uint16x4_t;
38447    }
38448    unsafe { _vqmovun_s32(a) }
38449}
38450#[doc = "Signed saturating extract unsigned narrow"]
38451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s64)"]
38452#[inline]
38453#[target_feature(enable = "neon")]
38454#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38455#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
38456#[cfg_attr(
38457    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38458    assert_instr(sqxtun)
38459)]
38460#[cfg_attr(
38461    not(target_arch = "arm"),
38462    stable(feature = "neon_intrinsics", since = "1.59.0")
38463)]
38464#[cfg_attr(
38465    target_arch = "arm",
38466    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38467)]
38468pub fn vqmovun_s64(a: int64x2_t) -> uint32x2_t {
38469    unsafe extern "unadjusted" {
38470        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v2i32")]
38471        #[cfg_attr(
38472            any(target_arch = "aarch64", target_arch = "arm64ec"),
38473            link_name = "llvm.aarch64.neon.sqxtun.v2i32"
38474        )]
38475        fn _vqmovun_s64(a: int64x2_t) -> uint32x2_t;
38476    }
38477    unsafe { _vqmovun_s64(a) }
38478}
38479#[doc = "Signed saturating negate"]
38480#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s8)"]
38481#[inline]
38482#[target_feature(enable = "neon")]
38483#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38484#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))]
38485#[cfg_attr(
38486    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38487    assert_instr(sqneg)
38488)]
38489#[cfg_attr(
38490    not(target_arch = "arm"),
38491    stable(feature = "neon_intrinsics", since = "1.59.0")
38492)]
38493#[cfg_attr(
38494    target_arch = "arm",
38495    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38496)]
38497pub fn vqneg_s8(a: int8x8_t) -> int8x8_t {
38498    unsafe extern "unadjusted" {
38499        #[cfg_attr(
38500            any(target_arch = "aarch64", target_arch = "arm64ec"),
38501            link_name = "llvm.aarch64.neon.sqneg.v8i8"
38502        )]
38503        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v8i8")]
38504        fn _vqneg_s8(a: int8x8_t) -> int8x8_t;
38505    }
38506    unsafe { _vqneg_s8(a) }
38507}
38508#[doc = "Signed saturating negate"]
38509#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s8)"]
38510#[inline]
38511#[target_feature(enable = "neon")]
38512#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38513#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))]
38514#[cfg_attr(
38515    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38516    assert_instr(sqneg)
38517)]
38518#[cfg_attr(
38519    not(target_arch = "arm"),
38520    stable(feature = "neon_intrinsics", since = "1.59.0")
38521)]
38522#[cfg_attr(
38523    target_arch = "arm",
38524    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38525)]
38526pub fn vqnegq_s8(a: int8x16_t) -> int8x16_t {
38527    unsafe extern "unadjusted" {
38528        #[cfg_attr(
38529            any(target_arch = "aarch64", target_arch = "arm64ec"),
38530            link_name = "llvm.aarch64.neon.sqneg.v16i8"
38531        )]
38532        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v16i8")]
38533        fn _vqnegq_s8(a: int8x16_t) -> int8x16_t;
38534    }
38535    unsafe { _vqnegq_s8(a) }
38536}
38537#[doc = "Signed saturating negate"]
38538#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s16)"]
38539#[inline]
38540#[target_feature(enable = "neon")]
38541#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38542#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))]
38543#[cfg_attr(
38544    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38545    assert_instr(sqneg)
38546)]
38547#[cfg_attr(
38548    not(target_arch = "arm"),
38549    stable(feature = "neon_intrinsics", since = "1.59.0")
38550)]
38551#[cfg_attr(
38552    target_arch = "arm",
38553    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38554)]
38555pub fn vqneg_s16(a: int16x4_t) -> int16x4_t {
38556    unsafe extern "unadjusted" {
38557        #[cfg_attr(
38558            any(target_arch = "aarch64", target_arch = "arm64ec"),
38559            link_name = "llvm.aarch64.neon.sqneg.v4i16"
38560        )]
38561        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v4i16")]
38562        fn _vqneg_s16(a: int16x4_t) -> int16x4_t;
38563    }
38564    unsafe { _vqneg_s16(a) }
38565}
38566#[doc = "Signed saturating negate"]
38567#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s16)"]
38568#[inline]
38569#[target_feature(enable = "neon")]
38570#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38571#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))]
38572#[cfg_attr(
38573    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38574    assert_instr(sqneg)
38575)]
38576#[cfg_attr(
38577    not(target_arch = "arm"),
38578    stable(feature = "neon_intrinsics", since = "1.59.0")
38579)]
38580#[cfg_attr(
38581    target_arch = "arm",
38582    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38583)]
38584pub fn vqnegq_s16(a: int16x8_t) -> int16x8_t {
38585    unsafe extern "unadjusted" {
38586        #[cfg_attr(
38587            any(target_arch = "aarch64", target_arch = "arm64ec"),
38588            link_name = "llvm.aarch64.neon.sqneg.v8i16"
38589        )]
38590        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v8i16")]
38591        fn _vqnegq_s16(a: int16x8_t) -> int16x8_t;
38592    }
38593    unsafe { _vqnegq_s16(a) }
38594}
38595#[doc = "Signed saturating negate"]
38596#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s32)"]
38597#[inline]
38598#[target_feature(enable = "neon")]
38599#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38600#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))]
38601#[cfg_attr(
38602    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38603    assert_instr(sqneg)
38604)]
38605#[cfg_attr(
38606    not(target_arch = "arm"),
38607    stable(feature = "neon_intrinsics", since = "1.59.0")
38608)]
38609#[cfg_attr(
38610    target_arch = "arm",
38611    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38612)]
38613pub fn vqneg_s32(a: int32x2_t) -> int32x2_t {
38614    unsafe extern "unadjusted" {
38615        #[cfg_attr(
38616            any(target_arch = "aarch64", target_arch = "arm64ec"),
38617            link_name = "llvm.aarch64.neon.sqneg.v2i32"
38618        )]
38619        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v2i32")]
38620        fn _vqneg_s32(a: int32x2_t) -> int32x2_t;
38621    }
38622    unsafe { _vqneg_s32(a) }
38623}
38624#[doc = "Signed saturating negate"]
38625#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s32)"]
38626#[inline]
38627#[target_feature(enable = "neon")]
38628#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38629#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))]
38630#[cfg_attr(
38631    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38632    assert_instr(sqneg)
38633)]
38634#[cfg_attr(
38635    not(target_arch = "arm"),
38636    stable(feature = "neon_intrinsics", since = "1.59.0")
38637)]
38638#[cfg_attr(
38639    target_arch = "arm",
38640    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38641)]
38642pub fn vqnegq_s32(a: int32x4_t) -> int32x4_t {
38643    unsafe extern "unadjusted" {
38644        #[cfg_attr(
38645            any(target_arch = "aarch64", target_arch = "arm64ec"),
38646            link_name = "llvm.aarch64.neon.sqneg.v4i32"
38647        )]
38648        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v4i32")]
38649        fn _vqnegq_s32(a: int32x4_t) -> int32x4_t;
38650    }
38651    unsafe { _vqnegq_s32(a) }
38652}
38653#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38654#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s16)"]
38655#[inline]
38656#[target_feature(enable = "neon")]
38657#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38658#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38659#[cfg_attr(
38660    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38661    assert_instr(sqrdmulh, LANE = 1)
38662)]
38663#[rustc_legacy_const_generics(2)]
38664#[cfg_attr(
38665    not(target_arch = "arm"),
38666    stable(feature = "neon_intrinsics", since = "1.59.0")
38667)]
38668#[cfg_attr(
38669    target_arch = "arm",
38670    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38671)]
38672pub fn vqrdmulh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
38673    static_assert_uimm_bits!(LANE, 2);
38674    unsafe {
38675        let b: int16x4_t =
38676            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
38677        vqrdmulh_s16(a, b)
38678    }
38679}
38680#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38681#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s32)"]
38682#[inline]
38683#[target_feature(enable = "neon")]
38684#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38685#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38686#[cfg_attr(
38687    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38688    assert_instr(sqrdmulh, LANE = 1)
38689)]
38690#[rustc_legacy_const_generics(2)]
38691#[cfg_attr(
38692    not(target_arch = "arm"),
38693    stable(feature = "neon_intrinsics", since = "1.59.0")
38694)]
38695#[cfg_attr(
38696    target_arch = "arm",
38697    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38698)]
38699pub fn vqrdmulh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
38700    static_assert_uimm_bits!(LANE, 1);
38701    unsafe {
38702        let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]);
38703        vqrdmulh_s32(a, b)
38704    }
38705}
38706#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38707#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s16)"]
38708#[inline]
38709#[target_feature(enable = "neon")]
38710#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38711#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38712#[cfg_attr(
38713    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38714    assert_instr(sqrdmulh, LANE = 1)
38715)]
38716#[rustc_legacy_const_generics(2)]
38717#[cfg_attr(
38718    not(target_arch = "arm"),
38719    stable(feature = "neon_intrinsics", since = "1.59.0")
38720)]
38721#[cfg_attr(
38722    target_arch = "arm",
38723    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38724)]
38725pub fn vqrdmulh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t {
38726    static_assert_uimm_bits!(LANE, 3);
38727    unsafe {
38728        let b: int16x4_t =
38729            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
38730        vqrdmulh_s16(a, b)
38731    }
38732}
38733#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38734#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s32)"]
38735#[inline]
38736#[target_feature(enable = "neon")]
38737#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38738#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38739#[cfg_attr(
38740    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38741    assert_instr(sqrdmulh, LANE = 1)
38742)]
38743#[rustc_legacy_const_generics(2)]
38744#[cfg_attr(
38745    not(target_arch = "arm"),
38746    stable(feature = "neon_intrinsics", since = "1.59.0")
38747)]
38748#[cfg_attr(
38749    target_arch = "arm",
38750    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38751)]
38752pub fn vqrdmulh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t {
38753    static_assert_uimm_bits!(LANE, 2);
38754    unsafe {
38755        let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]);
38756        vqrdmulh_s32(a, b)
38757    }
38758}
38759#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38760#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s16)"]
38761#[inline]
38762#[target_feature(enable = "neon")]
38763#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38764#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38765#[cfg_attr(
38766    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38767    assert_instr(sqrdmulh, LANE = 1)
38768)]
38769#[rustc_legacy_const_generics(2)]
38770#[cfg_attr(
38771    not(target_arch = "arm"),
38772    stable(feature = "neon_intrinsics", since = "1.59.0")
38773)]
38774#[cfg_attr(
38775    target_arch = "arm",
38776    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38777)]
38778pub fn vqrdmulhq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x8_t {
38779    static_assert_uimm_bits!(LANE, 2);
38780    unsafe {
38781        let b: int16x8_t = simd_shuffle!(
38782            b,
38783            b,
38784            [
38785                LANE as u32,
38786                LANE as u32,
38787                LANE as u32,
38788                LANE as u32,
38789                LANE as u32,
38790                LANE as u32,
38791                LANE as u32,
38792                LANE as u32
38793            ]
38794        );
38795        vqrdmulhq_s16(a, b)
38796    }
38797}
38798#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38799#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s32)"]
38800#[inline]
38801#[target_feature(enable = "neon")]
38802#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38803#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38804#[cfg_attr(
38805    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38806    assert_instr(sqrdmulh, LANE = 1)
38807)]
38808#[rustc_legacy_const_generics(2)]
38809#[cfg_attr(
38810    not(target_arch = "arm"),
38811    stable(feature = "neon_intrinsics", since = "1.59.0")
38812)]
38813#[cfg_attr(
38814    target_arch = "arm",
38815    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38816)]
38817pub fn vqrdmulhq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x4_t {
38818    static_assert_uimm_bits!(LANE, 1);
38819    unsafe {
38820        let b: int32x4_t =
38821            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
38822        vqrdmulhq_s32(a, b)
38823    }
38824}
38825#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38826#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s16)"]
38827#[inline]
38828#[target_feature(enable = "neon")]
38829#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38830#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38831#[cfg_attr(
38832    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38833    assert_instr(sqrdmulh, LANE = 1)
38834)]
38835#[rustc_legacy_const_generics(2)]
38836#[cfg_attr(
38837    not(target_arch = "arm"),
38838    stable(feature = "neon_intrinsics", since = "1.59.0")
38839)]
38840#[cfg_attr(
38841    target_arch = "arm",
38842    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38843)]
38844pub fn vqrdmulhq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
38845    static_assert_uimm_bits!(LANE, 3);
38846    unsafe {
38847        let b: int16x8_t = simd_shuffle!(
38848            b,
38849            b,
38850            [
38851                LANE as u32,
38852                LANE as u32,
38853                LANE as u32,
38854                LANE as u32,
38855                LANE as u32,
38856                LANE as u32,
38857                LANE as u32,
38858                LANE as u32
38859            ]
38860        );
38861        vqrdmulhq_s16(a, b)
38862    }
38863}
38864#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38865#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s32)"]
38866#[inline]
38867#[target_feature(enable = "neon")]
38868#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38869#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38870#[cfg_attr(
38871    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38872    assert_instr(sqrdmulh, LANE = 1)
38873)]
38874#[rustc_legacy_const_generics(2)]
38875#[cfg_attr(
38876    not(target_arch = "arm"),
38877    stable(feature = "neon_intrinsics", since = "1.59.0")
38878)]
38879#[cfg_attr(
38880    target_arch = "arm",
38881    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38882)]
38883pub fn vqrdmulhq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
38884    static_assert_uimm_bits!(LANE, 2);
38885    unsafe {
38886        let b: int32x4_t =
38887            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
38888        vqrdmulhq_s32(a, b)
38889    }
38890}
38891#[doc = "Vector saturating rounding doubling multiply high with scalar"]
38892#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s16)"]
38893#[inline]
38894#[target_feature(enable = "neon")]
38895#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38896#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
38897#[cfg_attr(
38898    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38899    assert_instr(sqrdmulh)
38900)]
38901#[cfg_attr(
38902    not(target_arch = "arm"),
38903    stable(feature = "neon_intrinsics", since = "1.59.0")
38904)]
38905#[cfg_attr(
38906    target_arch = "arm",
38907    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38908)]
38909pub fn vqrdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
38910    vqrdmulh_s16(a, vdup_n_s16(b))
38911}
38912#[doc = "Vector saturating rounding doubling multiply high with scalar"]
38913#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s16)"]
38914#[inline]
38915#[target_feature(enable = "neon")]
38916#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38917#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
38918#[cfg_attr(
38919    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38920    assert_instr(sqrdmulh)
38921)]
38922#[cfg_attr(
38923    not(target_arch = "arm"),
38924    stable(feature = "neon_intrinsics", since = "1.59.0")
38925)]
38926#[cfg_attr(
38927    target_arch = "arm",
38928    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38929)]
38930pub fn vqrdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
38931    vqrdmulhq_s16(a, vdupq_n_s16(b))
38932}
38933#[doc = "Vector saturating rounding doubling multiply high with scalar"]
38934#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s32)"]
38935#[inline]
38936#[target_feature(enable = "neon")]
38937#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38938#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
38939#[cfg_attr(
38940    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38941    assert_instr(sqrdmulh)
38942)]
38943#[cfg_attr(
38944    not(target_arch = "arm"),
38945    stable(feature = "neon_intrinsics", since = "1.59.0")
38946)]
38947#[cfg_attr(
38948    target_arch = "arm",
38949    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38950)]
38951pub fn vqrdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
38952    vqrdmulh_s32(a, vdup_n_s32(b))
38953}
38954#[doc = "Vector saturating rounding doubling multiply high with scalar"]
38955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s32)"]
38956#[inline]
38957#[target_feature(enable = "neon")]
38958#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38959#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
38960#[cfg_attr(
38961    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38962    assert_instr(sqrdmulh)
38963)]
38964#[cfg_attr(
38965    not(target_arch = "arm"),
38966    stable(feature = "neon_intrinsics", since = "1.59.0")
38967)]
38968#[cfg_attr(
38969    target_arch = "arm",
38970    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38971)]
38972pub fn vqrdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
38973    vqrdmulhq_s32(a, vdupq_n_s32(b))
38974}
38975#[doc = "Signed saturating rounding doubling multiply returning high half"]
38976#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s16)"]
38977#[inline]
38978#[target_feature(enable = "neon")]
38979#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38980#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
38981#[cfg_attr(
38982    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38983    assert_instr(sqrdmulh)
38984)]
38985#[cfg_attr(
38986    not(target_arch = "arm"),
38987    stable(feature = "neon_intrinsics", since = "1.59.0")
38988)]
38989#[cfg_attr(
38990    target_arch = "arm",
38991    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38992)]
38993pub fn vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
38994    unsafe extern "unadjusted" {
38995        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v4i16")]
38996        #[cfg_attr(
38997            any(target_arch = "aarch64", target_arch = "arm64ec"),
38998            link_name = "llvm.aarch64.neon.sqrdmulh.v4i16"
38999        )]
39000        fn _vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
39001    }
39002    unsafe { _vqrdmulh_s16(a, b) }
39003}
39004#[doc = "Signed saturating rounding doubling multiply returning high half"]
39005#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s16)"]
39006#[inline]
39007#[target_feature(enable = "neon")]
39008#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39009#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
39010#[cfg_attr(
39011    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39012    assert_instr(sqrdmulh)
39013)]
39014#[cfg_attr(
39015    not(target_arch = "arm"),
39016    stable(feature = "neon_intrinsics", since = "1.59.0")
39017)]
39018#[cfg_attr(
39019    target_arch = "arm",
39020    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39021)]
39022pub fn vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
39023    unsafe extern "unadjusted" {
39024        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v8i16")]
39025        #[cfg_attr(
39026            any(target_arch = "aarch64", target_arch = "arm64ec"),
39027            link_name = "llvm.aarch64.neon.sqrdmulh.v8i16"
39028        )]
39029        fn _vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
39030    }
39031    unsafe { _vqrdmulhq_s16(a, b) }
39032}
39033#[doc = "Signed saturating rounding doubling multiply returning high half"]
39034#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s32)"]
39035#[inline]
39036#[target_feature(enable = "neon")]
39037#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39038#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
39039#[cfg_attr(
39040    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39041    assert_instr(sqrdmulh)
39042)]
39043#[cfg_attr(
39044    not(target_arch = "arm"),
39045    stable(feature = "neon_intrinsics", since = "1.59.0")
39046)]
39047#[cfg_attr(
39048    target_arch = "arm",
39049    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39050)]
39051pub fn vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
39052    unsafe extern "unadjusted" {
39053        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v2i32")]
39054        #[cfg_attr(
39055            any(target_arch = "aarch64", target_arch = "arm64ec"),
39056            link_name = "llvm.aarch64.neon.sqrdmulh.v2i32"
39057        )]
39058        fn _vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
39059    }
39060    unsafe { _vqrdmulh_s32(a, b) }
39061}
39062#[doc = "Signed saturating rounding doubling multiply returning high half"]
39063#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s32)"]
39064#[inline]
39065#[target_feature(enable = "neon")]
39066#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39067#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
39068#[cfg_attr(
39069    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39070    assert_instr(sqrdmulh)
39071)]
39072#[cfg_attr(
39073    not(target_arch = "arm"),
39074    stable(feature = "neon_intrinsics", since = "1.59.0")
39075)]
39076#[cfg_attr(
39077    target_arch = "arm",
39078    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39079)]
39080pub fn vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
39081    unsafe extern "unadjusted" {
39082        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v4i32")]
39083        #[cfg_attr(
39084            any(target_arch = "aarch64", target_arch = "arm64ec"),
39085            link_name = "llvm.aarch64.neon.sqrdmulh.v4i32"
39086        )]
39087        fn _vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
39088    }
39089    unsafe { _vqrdmulhq_s32(a, b) }
39090}
39091#[doc = "Signed saturating rounding shift left"]
39092#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s8)"]
39093#[inline]
39094#[target_feature(enable = "neon")]
39095#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39096#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39097#[cfg_attr(
39098    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39099    assert_instr(sqrshl)
39100)]
39101#[cfg_attr(
39102    not(target_arch = "arm"),
39103    stable(feature = "neon_intrinsics", since = "1.59.0")
39104)]
39105#[cfg_attr(
39106    target_arch = "arm",
39107    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39108)]
39109pub fn vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
39110    unsafe extern "unadjusted" {
39111        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v8i8")]
39112        #[cfg_attr(
39113            any(target_arch = "aarch64", target_arch = "arm64ec"),
39114            link_name = "llvm.aarch64.neon.sqrshl.v8i8"
39115        )]
39116        fn _vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
39117    }
39118    unsafe { _vqrshl_s8(a, b) }
39119}
39120#[doc = "Signed saturating rounding shift left"]
39121#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s8)"]
39122#[inline]
39123#[target_feature(enable = "neon")]
39124#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39125#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39126#[cfg_attr(
39127    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39128    assert_instr(sqrshl)
39129)]
39130#[cfg_attr(
39131    not(target_arch = "arm"),
39132    stable(feature = "neon_intrinsics", since = "1.59.0")
39133)]
39134#[cfg_attr(
39135    target_arch = "arm",
39136    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39137)]
39138pub fn vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
39139    unsafe extern "unadjusted" {
39140        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v16i8")]
39141        #[cfg_attr(
39142            any(target_arch = "aarch64", target_arch = "arm64ec"),
39143            link_name = "llvm.aarch64.neon.sqrshl.v16i8"
39144        )]
39145        fn _vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
39146    }
39147    unsafe { _vqrshlq_s8(a, b) }
39148}
39149#[doc = "Signed saturating rounding shift left"]
39150#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s16)"]
39151#[inline]
39152#[target_feature(enable = "neon")]
39153#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39154#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39155#[cfg_attr(
39156    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39157    assert_instr(sqrshl)
39158)]
39159#[cfg_attr(
39160    not(target_arch = "arm"),
39161    stable(feature = "neon_intrinsics", since = "1.59.0")
39162)]
39163#[cfg_attr(
39164    target_arch = "arm",
39165    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39166)]
39167pub fn vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
39168    unsafe extern "unadjusted" {
39169        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v4i16")]
39170        #[cfg_attr(
39171            any(target_arch = "aarch64", target_arch = "arm64ec"),
39172            link_name = "llvm.aarch64.neon.sqrshl.v4i16"
39173        )]
39174        fn _vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
39175    }
39176    unsafe { _vqrshl_s16(a, b) }
39177}
39178#[doc = "Signed saturating rounding shift left"]
39179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s16)"]
39180#[inline]
39181#[target_feature(enable = "neon")]
39182#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39183#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39184#[cfg_attr(
39185    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39186    assert_instr(sqrshl)
39187)]
39188#[cfg_attr(
39189    not(target_arch = "arm"),
39190    stable(feature = "neon_intrinsics", since = "1.59.0")
39191)]
39192#[cfg_attr(
39193    target_arch = "arm",
39194    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39195)]
39196pub fn vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
39197    unsafe extern "unadjusted" {
39198        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v8i16")]
39199        #[cfg_attr(
39200            any(target_arch = "aarch64", target_arch = "arm64ec"),
39201            link_name = "llvm.aarch64.neon.sqrshl.v8i16"
39202        )]
39203        fn _vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
39204    }
39205    unsafe { _vqrshlq_s16(a, b) }
39206}
39207#[doc = "Signed saturating rounding shift left"]
39208#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s32)"]
39209#[inline]
39210#[target_feature(enable = "neon")]
39211#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39212#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39213#[cfg_attr(
39214    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39215    assert_instr(sqrshl)
39216)]
39217#[cfg_attr(
39218    not(target_arch = "arm"),
39219    stable(feature = "neon_intrinsics", since = "1.59.0")
39220)]
39221#[cfg_attr(
39222    target_arch = "arm",
39223    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39224)]
39225pub fn vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
39226    unsafe extern "unadjusted" {
39227        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v2i32")]
39228        #[cfg_attr(
39229            any(target_arch = "aarch64", target_arch = "arm64ec"),
39230            link_name = "llvm.aarch64.neon.sqrshl.v2i32"
39231        )]
39232        fn _vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
39233    }
39234    unsafe { _vqrshl_s32(a, b) }
39235}
39236#[doc = "Signed saturating rounding shift left"]
39237#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s32)"]
39238#[inline]
39239#[target_feature(enable = "neon")]
39240#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39241#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39242#[cfg_attr(
39243    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39244    assert_instr(sqrshl)
39245)]
39246#[cfg_attr(
39247    not(target_arch = "arm"),
39248    stable(feature = "neon_intrinsics", since = "1.59.0")
39249)]
39250#[cfg_attr(
39251    target_arch = "arm",
39252    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39253)]
39254pub fn vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
39255    unsafe extern "unadjusted" {
39256        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v4i32")]
39257        #[cfg_attr(
39258            any(target_arch = "aarch64", target_arch = "arm64ec"),
39259            link_name = "llvm.aarch64.neon.sqrshl.v4i32"
39260        )]
39261        fn _vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
39262    }
39263    unsafe { _vqrshlq_s32(a, b) }
39264}
39265#[doc = "Signed saturating rounding shift left"]
39266#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s64)"]
39267#[inline]
39268#[target_feature(enable = "neon")]
39269#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39270#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39271#[cfg_attr(
39272    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39273    assert_instr(sqrshl)
39274)]
39275#[cfg_attr(
39276    not(target_arch = "arm"),
39277    stable(feature = "neon_intrinsics", since = "1.59.0")
39278)]
39279#[cfg_attr(
39280    target_arch = "arm",
39281    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39282)]
39283pub fn vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
39284    unsafe extern "unadjusted" {
39285        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v1i64")]
39286        #[cfg_attr(
39287            any(target_arch = "aarch64", target_arch = "arm64ec"),
39288            link_name = "llvm.aarch64.neon.sqrshl.v1i64"
39289        )]
39290        fn _vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
39291    }
39292    unsafe { _vqrshl_s64(a, b) }
39293}
39294#[doc = "Signed saturating rounding shift left"]
39295#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s64)"]
39296#[inline]
39297#[target_feature(enable = "neon")]
39298#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39299#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39300#[cfg_attr(
39301    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39302    assert_instr(sqrshl)
39303)]
39304#[cfg_attr(
39305    not(target_arch = "arm"),
39306    stable(feature = "neon_intrinsics", since = "1.59.0")
39307)]
39308#[cfg_attr(
39309    target_arch = "arm",
39310    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39311)]
39312pub fn vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
39313    unsafe extern "unadjusted" {
39314        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v2i64")]
39315        #[cfg_attr(
39316            any(target_arch = "aarch64", target_arch = "arm64ec"),
39317            link_name = "llvm.aarch64.neon.sqrshl.v2i64"
39318        )]
39319        fn _vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
39320    }
39321    unsafe { _vqrshlq_s64(a, b) }
39322}
39323#[doc = "Unsigned signed saturating rounding shift left"]
39324#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u8)"]
39325#[inline]
39326#[target_feature(enable = "neon")]
39327#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39328#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39329#[cfg_attr(
39330    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39331    assert_instr(uqrshl)
39332)]
39333#[cfg_attr(
39334    not(target_arch = "arm"),
39335    stable(feature = "neon_intrinsics", since = "1.59.0")
39336)]
39337#[cfg_attr(
39338    target_arch = "arm",
39339    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39340)]
39341pub fn vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
39342    unsafe extern "unadjusted" {
39343        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v8i8")]
39344        #[cfg_attr(
39345            any(target_arch = "aarch64", target_arch = "arm64ec"),
39346            link_name = "llvm.aarch64.neon.uqrshl.v8i8"
39347        )]
39348        fn _vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t;
39349    }
39350    unsafe { _vqrshl_u8(a, b) }
39351}
39352#[doc = "Unsigned signed saturating rounding shift left"]
39353#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u8)"]
39354#[inline]
39355#[target_feature(enable = "neon")]
39356#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39357#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39358#[cfg_attr(
39359    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39360    assert_instr(uqrshl)
39361)]
39362#[cfg_attr(
39363    not(target_arch = "arm"),
39364    stable(feature = "neon_intrinsics", since = "1.59.0")
39365)]
39366#[cfg_attr(
39367    target_arch = "arm",
39368    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39369)]
39370pub fn vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
39371    unsafe extern "unadjusted" {
39372        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v16i8")]
39373        #[cfg_attr(
39374            any(target_arch = "aarch64", target_arch = "arm64ec"),
39375            link_name = "llvm.aarch64.neon.uqrshl.v16i8"
39376        )]
39377        fn _vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t;
39378    }
39379    unsafe { _vqrshlq_u8(a, b) }
39380}
39381#[doc = "Unsigned signed saturating rounding shift left"]
39382#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u16)"]
39383#[inline]
39384#[target_feature(enable = "neon")]
39385#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39386#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39387#[cfg_attr(
39388    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39389    assert_instr(uqrshl)
39390)]
39391#[cfg_attr(
39392    not(target_arch = "arm"),
39393    stable(feature = "neon_intrinsics", since = "1.59.0")
39394)]
39395#[cfg_attr(
39396    target_arch = "arm",
39397    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39398)]
39399pub fn vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
39400    unsafe extern "unadjusted" {
39401        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v4i16")]
39402        #[cfg_attr(
39403            any(target_arch = "aarch64", target_arch = "arm64ec"),
39404            link_name = "llvm.aarch64.neon.uqrshl.v4i16"
39405        )]
39406        fn _vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t;
39407    }
39408    unsafe { _vqrshl_u16(a, b) }
39409}
39410#[doc = "Unsigned signed saturating rounding shift left"]
39411#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u16)"]
39412#[inline]
39413#[target_feature(enable = "neon")]
39414#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39415#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39416#[cfg_attr(
39417    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39418    assert_instr(uqrshl)
39419)]
39420#[cfg_attr(
39421    not(target_arch = "arm"),
39422    stable(feature = "neon_intrinsics", since = "1.59.0")
39423)]
39424#[cfg_attr(
39425    target_arch = "arm",
39426    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39427)]
39428pub fn vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
39429    unsafe extern "unadjusted" {
39430        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v8i16")]
39431        #[cfg_attr(
39432            any(target_arch = "aarch64", target_arch = "arm64ec"),
39433            link_name = "llvm.aarch64.neon.uqrshl.v8i16"
39434        )]
39435        fn _vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t;
39436    }
39437    unsafe { _vqrshlq_u16(a, b) }
39438}
39439#[doc = "Unsigned signed saturating rounding shift left"]
39440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u32)"]
39441#[inline]
39442#[target_feature(enable = "neon")]
39443#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39444#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39445#[cfg_attr(
39446    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39447    assert_instr(uqrshl)
39448)]
39449#[cfg_attr(
39450    not(target_arch = "arm"),
39451    stable(feature = "neon_intrinsics", since = "1.59.0")
39452)]
39453#[cfg_attr(
39454    target_arch = "arm",
39455    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39456)]
39457pub fn vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
39458    unsafe extern "unadjusted" {
39459        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v2i32")]
39460        #[cfg_attr(
39461            any(target_arch = "aarch64", target_arch = "arm64ec"),
39462            link_name = "llvm.aarch64.neon.uqrshl.v2i32"
39463        )]
39464        fn _vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t;
39465    }
39466    unsafe { _vqrshl_u32(a, b) }
39467}
39468#[doc = "Unsigned signed saturating rounding shift left"]
39469#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u32)"]
39470#[inline]
39471#[target_feature(enable = "neon")]
39472#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39473#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39474#[cfg_attr(
39475    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39476    assert_instr(uqrshl)
39477)]
39478#[cfg_attr(
39479    not(target_arch = "arm"),
39480    stable(feature = "neon_intrinsics", since = "1.59.0")
39481)]
39482#[cfg_attr(
39483    target_arch = "arm",
39484    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39485)]
39486pub fn vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
39487    unsafe extern "unadjusted" {
39488        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v4i32")]
39489        #[cfg_attr(
39490            any(target_arch = "aarch64", target_arch = "arm64ec"),
39491            link_name = "llvm.aarch64.neon.uqrshl.v4i32"
39492        )]
39493        fn _vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t;
39494    }
39495    unsafe { _vqrshlq_u32(a, b) }
39496}
39497#[doc = "Unsigned signed saturating rounding shift left"]
39498#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u64)"]
39499#[inline]
39500#[target_feature(enable = "neon")]
39501#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39502#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39503#[cfg_attr(
39504    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39505    assert_instr(uqrshl)
39506)]
39507#[cfg_attr(
39508    not(target_arch = "arm"),
39509    stable(feature = "neon_intrinsics", since = "1.59.0")
39510)]
39511#[cfg_attr(
39512    target_arch = "arm",
39513    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39514)]
39515pub fn vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
39516    unsafe extern "unadjusted" {
39517        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v1i64")]
39518        #[cfg_attr(
39519            any(target_arch = "aarch64", target_arch = "arm64ec"),
39520            link_name = "llvm.aarch64.neon.uqrshl.v1i64"
39521        )]
39522        fn _vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t;
39523    }
39524    unsafe { _vqrshl_u64(a, b) }
39525}
39526#[doc = "Unsigned signed saturating rounding shift left"]
39527#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u64)"]
39528#[inline]
39529#[target_feature(enable = "neon")]
39530#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39531#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39532#[cfg_attr(
39533    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39534    assert_instr(uqrshl)
39535)]
39536#[cfg_attr(
39537    not(target_arch = "arm"),
39538    stable(feature = "neon_intrinsics", since = "1.59.0")
39539)]
39540#[cfg_attr(
39541    target_arch = "arm",
39542    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39543)]
39544pub fn vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
39545    unsafe extern "unadjusted" {
39546        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v2i64")]
39547        #[cfg_attr(
39548            any(target_arch = "aarch64", target_arch = "arm64ec"),
39549            link_name = "llvm.aarch64.neon.uqrshl.v2i64"
39550        )]
39551        fn _vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t;
39552    }
39553    unsafe { _vqrshlq_u64(a, b) }
39554}
39555#[doc = "Signed saturating rounded shift right narrow"]
39556#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"]
39557#[inline]
39558#[cfg(target_arch = "arm")]
39559#[target_feature(enable = "neon,v7")]
39560#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39561#[rustc_legacy_const_generics(1)]
39562#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39563pub fn vqrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
39564    static_assert!(N >= 1 && N <= 8);
39565    unsafe extern "unadjusted" {
39566        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v8i8")]
39567        fn _vqrshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t;
39568    }
39569    unsafe {
39570        _vqrshrn_n_s16(
39571            a,
39572            const {
39573                int16x8_t([
39574                    -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
39575                    -N as i16,
39576                ])
39577            },
39578        )
39579    }
39580}
39581#[doc = "Signed saturating rounded shift right narrow"]
39582#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"]
39583#[inline]
39584#[cfg(target_arch = "arm")]
39585#[target_feature(enable = "neon,v7")]
39586#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39587#[rustc_legacy_const_generics(1)]
39588#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39589pub fn vqrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
39590    static_assert!(N >= 1 && N <= 16);
39591    unsafe extern "unadjusted" {
39592        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v4i16")]
39593        fn _vqrshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t;
39594    }
39595    unsafe {
39596        _vqrshrn_n_s32(
39597            a,
39598            const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
39599        )
39600    }
39601}
39602#[doc = "Signed saturating rounded shift right narrow"]
39603#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"]
39604#[inline]
39605#[cfg(target_arch = "arm")]
39606#[target_feature(enable = "neon,v7")]
39607#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39608#[rustc_legacy_const_generics(1)]
39609#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39610pub fn vqrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
39611    static_assert!(N >= 1 && N <= 32);
39612    unsafe extern "unadjusted" {
39613        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v2i32")]
39614        fn _vqrshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t;
39615    }
39616    unsafe { _vqrshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
39617}
39618#[doc = "Signed saturating rounded shift right narrow"]
39619#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"]
39620#[inline]
39621#[target_feature(enable = "neon")]
39622#[cfg(not(target_arch = "arm"))]
39623#[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
39624#[rustc_legacy_const_generics(1)]
39625#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39626pub fn vqrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
39627    static_assert!(N >= 1 && N <= 8);
39628    unsafe extern "unadjusted" {
39629        #[cfg_attr(
39630            any(target_arch = "aarch64", target_arch = "arm64ec"),
39631            link_name = "llvm.aarch64.neon.sqrshrn.v8i8"
39632        )]
39633        fn _vqrshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t;
39634    }
39635    unsafe { _vqrshrn_n_s16(a, N) }
39636}
39637#[doc = "Signed saturating rounded shift right narrow"]
39638#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"]
39639#[inline]
39640#[target_feature(enable = "neon")]
39641#[cfg(not(target_arch = "arm"))]
39642#[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
39643#[rustc_legacy_const_generics(1)]
39644#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39645pub fn vqrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
39646    static_assert!(N >= 1 && N <= 16);
39647    unsafe extern "unadjusted" {
39648        #[cfg_attr(
39649            any(target_arch = "aarch64", target_arch = "arm64ec"),
39650            link_name = "llvm.aarch64.neon.sqrshrn.v4i16"
39651        )]
39652        fn _vqrshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t;
39653    }
39654    unsafe { _vqrshrn_n_s32(a, N) }
39655}
39656#[doc = "Signed saturating rounded shift right narrow"]
39657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"]
39658#[inline]
39659#[target_feature(enable = "neon")]
39660#[cfg(not(target_arch = "arm"))]
39661#[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
39662#[rustc_legacy_const_generics(1)]
39663#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39664pub fn vqrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
39665    static_assert!(N >= 1 && N <= 32);
39666    unsafe extern "unadjusted" {
39667        #[cfg_attr(
39668            any(target_arch = "aarch64", target_arch = "arm64ec"),
39669            link_name = "llvm.aarch64.neon.sqrshrn.v2i32"
39670        )]
39671        fn _vqrshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t;
39672    }
39673    unsafe { _vqrshrn_n_s64(a, N) }
39674}
39675#[doc = "Unsigned signed saturating rounded shift right narrow"]
39676#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"]
39677#[inline]
39678#[cfg(target_arch = "arm")]
39679#[target_feature(enable = "neon,v7")]
39680#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39681#[rustc_legacy_const_generics(1)]
39682#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39683pub fn vqrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
39684    static_assert!(N >= 1 && N <= 8);
39685    unsafe extern "unadjusted" {
39686        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v8i8")]
39687        fn _vqrshrn_n_u16(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t;
39688    }
39689    unsafe {
39690        _vqrshrn_n_u16(
39691            a,
39692            const {
39693                uint16x8_t([
39694                    -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16,
39695                    -N as u16,
39696                ])
39697            },
39698        )
39699    }
39700}
39701#[doc = "Unsigned signed saturating rounded shift right narrow"]
39702#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"]
39703#[inline]
39704#[cfg(target_arch = "arm")]
39705#[target_feature(enable = "neon,v7")]
39706#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39707#[rustc_legacy_const_generics(1)]
39708#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39709pub fn vqrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
39710    static_assert!(N >= 1 && N <= 16);
39711    unsafe extern "unadjusted" {
39712        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v4i16")]
39713        fn _vqrshrn_n_u32(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t;
39714    }
39715    unsafe {
39716        _vqrshrn_n_u32(
39717            a,
39718            const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) },
39719        )
39720    }
39721}
39722#[doc = "Unsigned signed saturating rounded shift right narrow"]
39723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"]
39724#[inline]
39725#[cfg(target_arch = "arm")]
39726#[target_feature(enable = "neon,v7")]
39727#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39728#[rustc_legacy_const_generics(1)]
39729#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39730pub fn vqrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
39731    static_assert!(N >= 1 && N <= 32);
39732    unsafe extern "unadjusted" {
39733        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v2i32")]
39734        fn _vqrshrn_n_u64(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t;
39735    }
39736    unsafe { _vqrshrn_n_u64(a, const { uint64x2_t([-N as u64, -N as u64]) }) }
39737}
39738#[doc = "Unsigned signed saturating rounded shift right narrow"]
39739#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"]
39740#[inline]
39741#[target_feature(enable = "neon")]
39742#[cfg(not(target_arch = "arm"))]
39743#[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
39744#[rustc_legacy_const_generics(1)]
39745#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39746pub fn vqrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
39747    static_assert!(N >= 1 && N <= 8);
39748    unsafe extern "unadjusted" {
39749        #[cfg_attr(
39750            any(target_arch = "aarch64", target_arch = "arm64ec"),
39751            link_name = "llvm.aarch64.neon.uqrshrn.v8i8"
39752        )]
39753        fn _vqrshrn_n_u16(a: uint16x8_t, n: i32) -> uint8x8_t;
39754    }
39755    unsafe { _vqrshrn_n_u16(a, N) }
39756}
39757#[doc = "Unsigned signed saturating rounded shift right narrow"]
39758#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"]
39759#[inline]
39760#[target_feature(enable = "neon")]
39761#[cfg(not(target_arch = "arm"))]
39762#[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
39763#[rustc_legacy_const_generics(1)]
39764#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39765pub fn vqrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
39766    static_assert!(N >= 1 && N <= 16);
39767    unsafe extern "unadjusted" {
39768        #[cfg_attr(
39769            any(target_arch = "aarch64", target_arch = "arm64ec"),
39770            link_name = "llvm.aarch64.neon.uqrshrn.v4i16"
39771        )]
39772        fn _vqrshrn_n_u32(a: uint32x4_t, n: i32) -> uint16x4_t;
39773    }
39774    unsafe { _vqrshrn_n_u32(a, N) }
39775}
39776#[doc = "Unsigned signed saturating rounded shift right narrow"]
39777#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"]
39778#[inline]
39779#[target_feature(enable = "neon")]
39780#[cfg(not(target_arch = "arm"))]
39781#[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
39782#[rustc_legacy_const_generics(1)]
39783#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39784pub fn vqrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
39785    static_assert!(N >= 1 && N <= 32);
39786    unsafe extern "unadjusted" {
39787        #[cfg_attr(
39788            any(target_arch = "aarch64", target_arch = "arm64ec"),
39789            link_name = "llvm.aarch64.neon.uqrshrn.v2i32"
39790        )]
39791        fn _vqrshrn_n_u64(a: uint64x2_t, n: i32) -> uint32x2_t;
39792    }
39793    unsafe { _vqrshrn_n_u64(a, N) }
39794}
39795#[doc = "Signed saturating rounded shift right unsigned narrow"]
39796#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"]
39797#[inline]
39798#[cfg(target_arch = "arm")]
39799#[target_feature(enable = "neon,v7")]
39800#[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
39801#[rustc_legacy_const_generics(1)]
39802#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39803pub fn vqrshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
39804    static_assert!(N >= 1 && N <= 8);
39805    unsafe extern "unadjusted" {
39806        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v8i8")]
39807        fn _vqrshrun_n_s16(a: int16x8_t, n: int16x8_t) -> uint8x8_t;
39808    }
39809    unsafe {
39810        _vqrshrun_n_s16(
39811            a,
39812            const {
39813                int16x8_t([
39814                    -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
39815                    -N as i16,
39816                ])
39817            },
39818        )
39819    }
39820}
39821#[doc = "Signed saturating rounded shift right unsigned narrow"]
39822#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"]
39823#[inline]
39824#[cfg(target_arch = "arm")]
39825#[target_feature(enable = "neon,v7")]
39826#[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
39827#[rustc_legacy_const_generics(1)]
39828#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39829pub fn vqrshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
39830    static_assert!(N >= 1 && N <= 16);
39831    unsafe extern "unadjusted" {
39832        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v4i16")]
39833        fn _vqrshrun_n_s32(a: int32x4_t, n: int32x4_t) -> uint16x4_t;
39834    }
39835    unsafe {
39836        _vqrshrun_n_s32(
39837            a,
39838            const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
39839        )
39840    }
39841}
39842#[doc = "Signed saturating rounded shift right unsigned narrow"]
39843#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"]
39844#[inline]
39845#[cfg(target_arch = "arm")]
39846#[target_feature(enable = "neon,v7")]
39847#[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
39848#[rustc_legacy_const_generics(1)]
39849#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39850pub fn vqrshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
39851    static_assert!(N >= 1 && N <= 32);
39852    unsafe extern "unadjusted" {
39853        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v2i32")]
39854        fn _vqrshrun_n_s64(a: int64x2_t, n: int64x2_t) -> uint32x2_t;
39855    }
39856    unsafe { _vqrshrun_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
39857}
39858#[doc = "Signed saturating rounded shift right unsigned narrow"]
39859#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"]
39860#[inline]
39861#[target_feature(enable = "neon")]
39862#[cfg(not(target_arch = "arm"))]
39863#[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
39864#[rustc_legacy_const_generics(1)]
39865#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39866pub fn vqrshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
39867    static_assert!(N >= 1 && N <= 8);
39868    unsafe extern "unadjusted" {
39869        #[cfg_attr(
39870            any(target_arch = "aarch64", target_arch = "arm64ec"),
39871            link_name = "llvm.aarch64.neon.sqrshrun.v8i8"
39872        )]
39873        fn _vqrshrun_n_s16(a: int16x8_t, n: i32) -> uint8x8_t;
39874    }
39875    unsafe { _vqrshrun_n_s16(a, N) }
39876}
39877#[doc = "Signed saturating rounded shift right unsigned narrow"]
39878#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"]
39879#[inline]
39880#[target_feature(enable = "neon")]
39881#[cfg(not(target_arch = "arm"))]
39882#[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
39883#[rustc_legacy_const_generics(1)]
39884#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39885pub fn vqrshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
39886    static_assert!(N >= 1 && N <= 16);
39887    unsafe extern "unadjusted" {
39888        #[cfg_attr(
39889            any(target_arch = "aarch64", target_arch = "arm64ec"),
39890            link_name = "llvm.aarch64.neon.sqrshrun.v4i16"
39891        )]
39892        fn _vqrshrun_n_s32(a: int32x4_t, n: i32) -> uint16x4_t;
39893    }
39894    unsafe { _vqrshrun_n_s32(a, N) }
39895}
39896#[doc = "Signed saturating rounded shift right unsigned narrow"]
39897#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"]
39898#[inline]
39899#[target_feature(enable = "neon")]
39900#[cfg(not(target_arch = "arm"))]
39901#[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
39902#[rustc_legacy_const_generics(1)]
39903#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39904pub fn vqrshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
39905    static_assert!(N >= 1 && N <= 32);
39906    unsafe extern "unadjusted" {
39907        #[cfg_attr(
39908            any(target_arch = "aarch64", target_arch = "arm64ec"),
39909            link_name = "llvm.aarch64.neon.sqrshrun.v2i32"
39910        )]
39911        fn _vqrshrun_n_s64(a: int64x2_t, n: i32) -> uint32x2_t;
39912    }
39913    unsafe { _vqrshrun_n_s64(a, N) }
39914}
39915#[doc = "Signed saturating shift left"]
39916#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s8)"]
39917#[inline]
39918#[target_feature(enable = "neon")]
39919#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39920#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
39921#[cfg_attr(
39922    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39923    assert_instr(sqshl, N = 2)
39924)]
39925#[rustc_legacy_const_generics(1)]
39926#[cfg_attr(
39927    not(target_arch = "arm"),
39928    stable(feature = "neon_intrinsics", since = "1.59.0")
39929)]
39930#[cfg_attr(
39931    target_arch = "arm",
39932    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39933)]
39934pub fn vqshl_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
39935    static_assert_uimm_bits!(N, 3);
39936    vqshl_s8(a, vdup_n_s8(N as _))
39937}
39938#[doc = "Signed saturating shift left"]
39939#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s8)"]
39940#[inline]
39941#[target_feature(enable = "neon")]
39942#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39943#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
39944#[cfg_attr(
39945    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39946    assert_instr(sqshl, N = 2)
39947)]
39948#[rustc_legacy_const_generics(1)]
39949#[cfg_attr(
39950    not(target_arch = "arm"),
39951    stable(feature = "neon_intrinsics", since = "1.59.0")
39952)]
39953#[cfg_attr(
39954    target_arch = "arm",
39955    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39956)]
39957pub fn vqshlq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
39958    static_assert_uimm_bits!(N, 3);
39959    vqshlq_s8(a, vdupq_n_s8(N as _))
39960}
39961#[doc = "Signed saturating shift left"]
39962#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s16)"]
39963#[inline]
39964#[target_feature(enable = "neon")]
39965#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39966#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
39967#[cfg_attr(
39968    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39969    assert_instr(sqshl, N = 2)
39970)]
39971#[rustc_legacy_const_generics(1)]
39972#[cfg_attr(
39973    not(target_arch = "arm"),
39974    stable(feature = "neon_intrinsics", since = "1.59.0")
39975)]
39976#[cfg_attr(
39977    target_arch = "arm",
39978    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39979)]
39980pub fn vqshl_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
39981    static_assert_uimm_bits!(N, 4);
39982    vqshl_s16(a, vdup_n_s16(N as _))
39983}
39984#[doc = "Signed saturating shift left"]
39985#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s16)"]
39986#[inline]
39987#[target_feature(enable = "neon")]
39988#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39989#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
39990#[cfg_attr(
39991    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39992    assert_instr(sqshl, N = 2)
39993)]
39994#[rustc_legacy_const_generics(1)]
39995#[cfg_attr(
39996    not(target_arch = "arm"),
39997    stable(feature = "neon_intrinsics", since = "1.59.0")
39998)]
39999#[cfg_attr(
40000    target_arch = "arm",
40001    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40002)]
40003pub fn vqshlq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
40004    static_assert_uimm_bits!(N, 4);
40005    vqshlq_s16(a, vdupq_n_s16(N as _))
40006}
40007#[doc = "Signed saturating shift left"]
40008#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s32)"]
40009#[inline]
40010#[target_feature(enable = "neon")]
40011#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40012#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40013#[cfg_attr(
40014    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40015    assert_instr(sqshl, N = 2)
40016)]
40017#[rustc_legacy_const_generics(1)]
40018#[cfg_attr(
40019    not(target_arch = "arm"),
40020    stable(feature = "neon_intrinsics", since = "1.59.0")
40021)]
40022#[cfg_attr(
40023    target_arch = "arm",
40024    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40025)]
40026pub fn vqshl_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
40027    static_assert_uimm_bits!(N, 5);
40028    vqshl_s32(a, vdup_n_s32(N as _))
40029}
40030#[doc = "Signed saturating shift left"]
40031#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s32)"]
40032#[inline]
40033#[target_feature(enable = "neon")]
40034#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40035#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40036#[cfg_attr(
40037    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40038    assert_instr(sqshl, N = 2)
40039)]
40040#[rustc_legacy_const_generics(1)]
40041#[cfg_attr(
40042    not(target_arch = "arm"),
40043    stable(feature = "neon_intrinsics", since = "1.59.0")
40044)]
40045#[cfg_attr(
40046    target_arch = "arm",
40047    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40048)]
40049pub fn vqshlq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
40050    static_assert_uimm_bits!(N, 5);
40051    vqshlq_s32(a, vdupq_n_s32(N as _))
40052}
40053#[doc = "Signed saturating shift left"]
40054#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s64)"]
40055#[inline]
40056#[target_feature(enable = "neon")]
40057#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40058#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40059#[cfg_attr(
40060    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40061    assert_instr(sqshl, N = 2)
40062)]
40063#[rustc_legacy_const_generics(1)]
40064#[cfg_attr(
40065    not(target_arch = "arm"),
40066    stable(feature = "neon_intrinsics", since = "1.59.0")
40067)]
40068#[cfg_attr(
40069    target_arch = "arm",
40070    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40071)]
40072pub fn vqshl_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
40073    static_assert_uimm_bits!(N, 6);
40074    vqshl_s64(a, vdup_n_s64(N as _))
40075}
40076#[doc = "Signed saturating shift left"]
40077#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s64)"]
40078#[inline]
40079#[target_feature(enable = "neon")]
40080#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40081#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40082#[cfg_attr(
40083    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40084    assert_instr(sqshl, N = 2)
40085)]
40086#[rustc_legacy_const_generics(1)]
40087#[cfg_attr(
40088    not(target_arch = "arm"),
40089    stable(feature = "neon_intrinsics", since = "1.59.0")
40090)]
40091#[cfg_attr(
40092    target_arch = "arm",
40093    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40094)]
40095pub fn vqshlq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
40096    static_assert_uimm_bits!(N, 6);
40097    vqshlq_s64(a, vdupq_n_s64(N as _))
40098}
40099#[doc = "Unsigned saturating shift left"]
40100#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u8)"]
40101#[inline]
40102#[target_feature(enable = "neon")]
40103#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40104#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40105#[cfg_attr(
40106    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40107    assert_instr(uqshl, N = 2)
40108)]
40109#[rustc_legacy_const_generics(1)]
40110#[cfg_attr(
40111    not(target_arch = "arm"),
40112    stable(feature = "neon_intrinsics", since = "1.59.0")
40113)]
40114#[cfg_attr(
40115    target_arch = "arm",
40116    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40117)]
40118pub fn vqshl_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
40119    static_assert_uimm_bits!(N, 3);
40120    vqshl_u8(a, vdup_n_s8(N as _))
40121}
40122#[doc = "Unsigned saturating shift left"]
40123#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u8)"]
40124#[inline]
40125#[target_feature(enable = "neon")]
40126#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40127#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40128#[cfg_attr(
40129    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40130    assert_instr(uqshl, N = 2)
40131)]
40132#[rustc_legacy_const_generics(1)]
40133#[cfg_attr(
40134    not(target_arch = "arm"),
40135    stable(feature = "neon_intrinsics", since = "1.59.0")
40136)]
40137#[cfg_attr(
40138    target_arch = "arm",
40139    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40140)]
40141pub fn vqshlq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
40142    static_assert_uimm_bits!(N, 3);
40143    vqshlq_u8(a, vdupq_n_s8(N as _))
40144}
40145#[doc = "Unsigned saturating shift left"]
40146#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u16)"]
40147#[inline]
40148#[target_feature(enable = "neon")]
40149#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40150#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40151#[cfg_attr(
40152    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40153    assert_instr(uqshl, N = 2)
40154)]
40155#[rustc_legacy_const_generics(1)]
40156#[cfg_attr(
40157    not(target_arch = "arm"),
40158    stable(feature = "neon_intrinsics", since = "1.59.0")
40159)]
40160#[cfg_attr(
40161    target_arch = "arm",
40162    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40163)]
40164pub fn vqshl_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
40165    static_assert_uimm_bits!(N, 4);
40166    vqshl_u16(a, vdup_n_s16(N as _))
40167}
40168#[doc = "Unsigned saturating shift left"]
40169#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u16)"]
40170#[inline]
40171#[target_feature(enable = "neon")]
40172#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40173#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40174#[cfg_attr(
40175    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40176    assert_instr(uqshl, N = 2)
40177)]
40178#[rustc_legacy_const_generics(1)]
40179#[cfg_attr(
40180    not(target_arch = "arm"),
40181    stable(feature = "neon_intrinsics", since = "1.59.0")
40182)]
40183#[cfg_attr(
40184    target_arch = "arm",
40185    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40186)]
40187pub fn vqshlq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
40188    static_assert_uimm_bits!(N, 4);
40189    vqshlq_u16(a, vdupq_n_s16(N as _))
40190}
40191#[doc = "Unsigned saturating shift left"]
40192#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u32)"]
40193#[inline]
40194#[target_feature(enable = "neon")]
40195#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40196#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40197#[cfg_attr(
40198    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40199    assert_instr(uqshl, N = 2)
40200)]
40201#[rustc_legacy_const_generics(1)]
40202#[cfg_attr(
40203    not(target_arch = "arm"),
40204    stable(feature = "neon_intrinsics", since = "1.59.0")
40205)]
40206#[cfg_attr(
40207    target_arch = "arm",
40208    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40209)]
40210pub fn vqshl_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
40211    static_assert_uimm_bits!(N, 5);
40212    vqshl_u32(a, vdup_n_s32(N as _))
40213}
40214#[doc = "Unsigned saturating shift left"]
40215#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u32)"]
40216#[inline]
40217#[target_feature(enable = "neon")]
40218#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40219#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40220#[cfg_attr(
40221    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40222    assert_instr(uqshl, N = 2)
40223)]
40224#[rustc_legacy_const_generics(1)]
40225#[cfg_attr(
40226    not(target_arch = "arm"),
40227    stable(feature = "neon_intrinsics", since = "1.59.0")
40228)]
40229#[cfg_attr(
40230    target_arch = "arm",
40231    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40232)]
40233pub fn vqshlq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
40234    static_assert_uimm_bits!(N, 5);
40235    vqshlq_u32(a, vdupq_n_s32(N as _))
40236}
40237#[doc = "Unsigned saturating shift left"]
40238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u64)"]
40239#[inline]
40240#[target_feature(enable = "neon")]
40241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40242#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40243#[cfg_attr(
40244    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40245    assert_instr(uqshl, N = 2)
40246)]
40247#[rustc_legacy_const_generics(1)]
40248#[cfg_attr(
40249    not(target_arch = "arm"),
40250    stable(feature = "neon_intrinsics", since = "1.59.0")
40251)]
40252#[cfg_attr(
40253    target_arch = "arm",
40254    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40255)]
40256pub fn vqshl_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
40257    static_assert_uimm_bits!(N, 6);
40258    vqshl_u64(a, vdup_n_s64(N as _))
40259}
40260#[doc = "Unsigned saturating shift left"]
40261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u64)"]
40262#[inline]
40263#[target_feature(enable = "neon")]
40264#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40265#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40266#[cfg_attr(
40267    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40268    assert_instr(uqshl, N = 2)
40269)]
40270#[rustc_legacy_const_generics(1)]
40271#[cfg_attr(
40272    not(target_arch = "arm"),
40273    stable(feature = "neon_intrinsics", since = "1.59.0")
40274)]
40275#[cfg_attr(
40276    target_arch = "arm",
40277    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40278)]
40279pub fn vqshlq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
40280    static_assert_uimm_bits!(N, 6);
40281    vqshlq_u64(a, vdupq_n_s64(N as _))
40282}
40283#[doc = "Signed saturating shift left"]
40284#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s8)"]
40285#[inline]
40286#[target_feature(enable = "neon")]
40287#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40288#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40289#[cfg_attr(
40290    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40291    assert_instr(sqshl)
40292)]
40293#[cfg_attr(
40294    not(target_arch = "arm"),
40295    stable(feature = "neon_intrinsics", since = "1.59.0")
40296)]
40297#[cfg_attr(
40298    target_arch = "arm",
40299    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40300)]
40301pub fn vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
40302    unsafe extern "unadjusted" {
40303        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v8i8")]
40304        #[cfg_attr(
40305            any(target_arch = "aarch64", target_arch = "arm64ec"),
40306            link_name = "llvm.aarch64.neon.sqshl.v8i8"
40307        )]
40308        fn _vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
40309    }
40310    unsafe { _vqshl_s8(a, b) }
40311}
40312#[doc = "Signed saturating shift left"]
40313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s8)"]
40314#[inline]
40315#[target_feature(enable = "neon")]
40316#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40317#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40318#[cfg_attr(
40319    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40320    assert_instr(sqshl)
40321)]
40322#[cfg_attr(
40323    not(target_arch = "arm"),
40324    stable(feature = "neon_intrinsics", since = "1.59.0")
40325)]
40326#[cfg_attr(
40327    target_arch = "arm",
40328    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40329)]
40330pub fn vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
40331    unsafe extern "unadjusted" {
40332        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v16i8")]
40333        #[cfg_attr(
40334            any(target_arch = "aarch64", target_arch = "arm64ec"),
40335            link_name = "llvm.aarch64.neon.sqshl.v16i8"
40336        )]
40337        fn _vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
40338    }
40339    unsafe { _vqshlq_s8(a, b) }
40340}
40341#[doc = "Signed saturating shift left"]
40342#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s16)"]
40343#[inline]
40344#[target_feature(enable = "neon")]
40345#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40346#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40347#[cfg_attr(
40348    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40349    assert_instr(sqshl)
40350)]
40351#[cfg_attr(
40352    not(target_arch = "arm"),
40353    stable(feature = "neon_intrinsics", since = "1.59.0")
40354)]
40355#[cfg_attr(
40356    target_arch = "arm",
40357    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40358)]
40359pub fn vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
40360    unsafe extern "unadjusted" {
40361        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v4i16")]
40362        #[cfg_attr(
40363            any(target_arch = "aarch64", target_arch = "arm64ec"),
40364            link_name = "llvm.aarch64.neon.sqshl.v4i16"
40365        )]
40366        fn _vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
40367    }
40368    unsafe { _vqshl_s16(a, b) }
40369}
40370#[doc = "Signed saturating shift left"]
40371#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s16)"]
40372#[inline]
40373#[target_feature(enable = "neon")]
40374#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40375#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40376#[cfg_attr(
40377    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40378    assert_instr(sqshl)
40379)]
40380#[cfg_attr(
40381    not(target_arch = "arm"),
40382    stable(feature = "neon_intrinsics", since = "1.59.0")
40383)]
40384#[cfg_attr(
40385    target_arch = "arm",
40386    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40387)]
40388pub fn vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
40389    unsafe extern "unadjusted" {
40390        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v8i16")]
40391        #[cfg_attr(
40392            any(target_arch = "aarch64", target_arch = "arm64ec"),
40393            link_name = "llvm.aarch64.neon.sqshl.v8i16"
40394        )]
40395        fn _vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
40396    }
40397    unsafe { _vqshlq_s16(a, b) }
40398}
40399#[doc = "Signed saturating shift left"]
40400#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s32)"]
40401#[inline]
40402#[target_feature(enable = "neon")]
40403#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40404#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40405#[cfg_attr(
40406    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40407    assert_instr(sqshl)
40408)]
40409#[cfg_attr(
40410    not(target_arch = "arm"),
40411    stable(feature = "neon_intrinsics", since = "1.59.0")
40412)]
40413#[cfg_attr(
40414    target_arch = "arm",
40415    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40416)]
40417pub fn vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
40418    unsafe extern "unadjusted" {
40419        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v2i32")]
40420        #[cfg_attr(
40421            any(target_arch = "aarch64", target_arch = "arm64ec"),
40422            link_name = "llvm.aarch64.neon.sqshl.v2i32"
40423        )]
40424        fn _vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
40425    }
40426    unsafe { _vqshl_s32(a, b) }
40427}
40428#[doc = "Signed saturating shift left"]
40429#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s32)"]
40430#[inline]
40431#[target_feature(enable = "neon")]
40432#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40433#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40434#[cfg_attr(
40435    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40436    assert_instr(sqshl)
40437)]
40438#[cfg_attr(
40439    not(target_arch = "arm"),
40440    stable(feature = "neon_intrinsics", since = "1.59.0")
40441)]
40442#[cfg_attr(
40443    target_arch = "arm",
40444    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40445)]
40446pub fn vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
40447    unsafe extern "unadjusted" {
40448        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v4i32")]
40449        #[cfg_attr(
40450            any(target_arch = "aarch64", target_arch = "arm64ec"),
40451            link_name = "llvm.aarch64.neon.sqshl.v4i32"
40452        )]
40453        fn _vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
40454    }
40455    unsafe { _vqshlq_s32(a, b) }
40456}
40457#[doc = "Signed saturating shift left"]
40458#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s64)"]
40459#[inline]
40460#[target_feature(enable = "neon")]
40461#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40462#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40463#[cfg_attr(
40464    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40465    assert_instr(sqshl)
40466)]
40467#[cfg_attr(
40468    not(target_arch = "arm"),
40469    stable(feature = "neon_intrinsics", since = "1.59.0")
40470)]
40471#[cfg_attr(
40472    target_arch = "arm",
40473    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40474)]
40475pub fn vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
40476    unsafe extern "unadjusted" {
40477        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v1i64")]
40478        #[cfg_attr(
40479            any(target_arch = "aarch64", target_arch = "arm64ec"),
40480            link_name = "llvm.aarch64.neon.sqshl.v1i64"
40481        )]
40482        fn _vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
40483    }
40484    unsafe { _vqshl_s64(a, b) }
40485}
40486#[doc = "Signed saturating shift left"]
40487#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s64)"]
40488#[inline]
40489#[target_feature(enable = "neon")]
40490#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40491#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40492#[cfg_attr(
40493    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40494    assert_instr(sqshl)
40495)]
40496#[cfg_attr(
40497    not(target_arch = "arm"),
40498    stable(feature = "neon_intrinsics", since = "1.59.0")
40499)]
40500#[cfg_attr(
40501    target_arch = "arm",
40502    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40503)]
40504pub fn vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
40505    unsafe extern "unadjusted" {
40506        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v2i64")]
40507        #[cfg_attr(
40508            any(target_arch = "aarch64", target_arch = "arm64ec"),
40509            link_name = "llvm.aarch64.neon.sqshl.v2i64"
40510        )]
40511        fn _vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
40512    }
40513    unsafe { _vqshlq_s64(a, b) }
40514}
40515#[doc = "Unsigned saturating shift left"]
40516#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u8)"]
40517#[inline]
40518#[target_feature(enable = "neon")]
40519#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40520#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40521#[cfg_attr(
40522    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40523    assert_instr(uqshl)
40524)]
40525#[cfg_attr(
40526    not(target_arch = "arm"),
40527    stable(feature = "neon_intrinsics", since = "1.59.0")
40528)]
40529#[cfg_attr(
40530    target_arch = "arm",
40531    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40532)]
40533pub fn vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
40534    unsafe extern "unadjusted" {
40535        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v8i8")]
40536        #[cfg_attr(
40537            any(target_arch = "aarch64", target_arch = "arm64ec"),
40538            link_name = "llvm.aarch64.neon.uqshl.v8i8"
40539        )]
40540        fn _vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t;
40541    }
40542    unsafe { _vqshl_u8(a, b) }
40543}
40544#[doc = "Unsigned saturating shift left"]
40545#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u8)"]
40546#[inline]
40547#[target_feature(enable = "neon")]
40548#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40549#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40550#[cfg_attr(
40551    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40552    assert_instr(uqshl)
40553)]
40554#[cfg_attr(
40555    not(target_arch = "arm"),
40556    stable(feature = "neon_intrinsics", since = "1.59.0")
40557)]
40558#[cfg_attr(
40559    target_arch = "arm",
40560    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40561)]
40562pub fn vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
40563    unsafe extern "unadjusted" {
40564        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v16i8")]
40565        #[cfg_attr(
40566            any(target_arch = "aarch64", target_arch = "arm64ec"),
40567            link_name = "llvm.aarch64.neon.uqshl.v16i8"
40568        )]
40569        fn _vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t;
40570    }
40571    unsafe { _vqshlq_u8(a, b) }
40572}
40573#[doc = "Unsigned saturating shift left"]
40574#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u16)"]
40575#[inline]
40576#[target_feature(enable = "neon")]
40577#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40578#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40579#[cfg_attr(
40580    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40581    assert_instr(uqshl)
40582)]
40583#[cfg_attr(
40584    not(target_arch = "arm"),
40585    stable(feature = "neon_intrinsics", since = "1.59.0")
40586)]
40587#[cfg_attr(
40588    target_arch = "arm",
40589    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40590)]
40591pub fn vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
40592    unsafe extern "unadjusted" {
40593        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v4i16")]
40594        #[cfg_attr(
40595            any(target_arch = "aarch64", target_arch = "arm64ec"),
40596            link_name = "llvm.aarch64.neon.uqshl.v4i16"
40597        )]
40598        fn _vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t;
40599    }
40600    unsafe { _vqshl_u16(a, b) }
40601}
40602#[doc = "Unsigned saturating shift left"]
40603#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u16)"]
40604#[inline]
40605#[target_feature(enable = "neon")]
40606#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40607#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40608#[cfg_attr(
40609    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40610    assert_instr(uqshl)
40611)]
40612#[cfg_attr(
40613    not(target_arch = "arm"),
40614    stable(feature = "neon_intrinsics", since = "1.59.0")
40615)]
40616#[cfg_attr(
40617    target_arch = "arm",
40618    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40619)]
40620pub fn vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
40621    unsafe extern "unadjusted" {
40622        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v8i16")]
40623        #[cfg_attr(
40624            any(target_arch = "aarch64", target_arch = "arm64ec"),
40625            link_name = "llvm.aarch64.neon.uqshl.v8i16"
40626        )]
40627        fn _vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t;
40628    }
40629    unsafe { _vqshlq_u16(a, b) }
40630}
40631#[doc = "Unsigned saturating shift left"]
40632#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u32)"]
40633#[inline]
40634#[target_feature(enable = "neon")]
40635#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40636#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40637#[cfg_attr(
40638    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40639    assert_instr(uqshl)
40640)]
40641#[cfg_attr(
40642    not(target_arch = "arm"),
40643    stable(feature = "neon_intrinsics", since = "1.59.0")
40644)]
40645#[cfg_attr(
40646    target_arch = "arm",
40647    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40648)]
40649pub fn vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
40650    unsafe extern "unadjusted" {
40651        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v2i32")]
40652        #[cfg_attr(
40653            any(target_arch = "aarch64", target_arch = "arm64ec"),
40654            link_name = "llvm.aarch64.neon.uqshl.v2i32"
40655        )]
40656        fn _vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t;
40657    }
40658    unsafe { _vqshl_u32(a, b) }
40659}
40660#[doc = "Unsigned saturating shift left"]
40661#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u32)"]
40662#[inline]
40663#[target_feature(enable = "neon")]
40664#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40665#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40666#[cfg_attr(
40667    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40668    assert_instr(uqshl)
40669)]
40670#[cfg_attr(
40671    not(target_arch = "arm"),
40672    stable(feature = "neon_intrinsics", since = "1.59.0")
40673)]
40674#[cfg_attr(
40675    target_arch = "arm",
40676    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40677)]
40678pub fn vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
40679    unsafe extern "unadjusted" {
40680        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v4i32")]
40681        #[cfg_attr(
40682            any(target_arch = "aarch64", target_arch = "arm64ec"),
40683            link_name = "llvm.aarch64.neon.uqshl.v4i32"
40684        )]
40685        fn _vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t;
40686    }
40687    unsafe { _vqshlq_u32(a, b) }
40688}
40689#[doc = "Unsigned saturating shift left"]
40690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u64)"]
40691#[inline]
40692#[target_feature(enable = "neon")]
40693#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40694#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40695#[cfg_attr(
40696    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40697    assert_instr(uqshl)
40698)]
40699#[cfg_attr(
40700    not(target_arch = "arm"),
40701    stable(feature = "neon_intrinsics", since = "1.59.0")
40702)]
40703#[cfg_attr(
40704    target_arch = "arm",
40705    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40706)]
40707pub fn vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
40708    unsafe extern "unadjusted" {
40709        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v1i64")]
40710        #[cfg_attr(
40711            any(target_arch = "aarch64", target_arch = "arm64ec"),
40712            link_name = "llvm.aarch64.neon.uqshl.v1i64"
40713        )]
40714        fn _vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t;
40715    }
40716    unsafe { _vqshl_u64(a, b) }
40717}
40718#[doc = "Unsigned saturating shift left"]
40719#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u64)"]
40720#[inline]
40721#[target_feature(enable = "neon")]
40722#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40723#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40724#[cfg_attr(
40725    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40726    assert_instr(uqshl)
40727)]
40728#[cfg_attr(
40729    not(target_arch = "arm"),
40730    stable(feature = "neon_intrinsics", since = "1.59.0")
40731)]
40732#[cfg_attr(
40733    target_arch = "arm",
40734    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40735)]
40736pub fn vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
40737    unsafe extern "unadjusted" {
40738        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v2i64")]
40739        #[cfg_attr(
40740            any(target_arch = "aarch64", target_arch = "arm64ec"),
40741            link_name = "llvm.aarch64.neon.uqshl.v2i64"
40742        )]
40743        fn _vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t;
40744    }
40745    unsafe { _vqshlq_u64(a, b) }
40746}
40747#[doc = "Signed saturating shift left unsigned"]
40748#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"]
40749#[inline]
40750#[cfg(target_arch = "arm")]
40751#[target_feature(enable = "neon,v7")]
40752#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40753#[rustc_legacy_const_generics(1)]
40754#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40755pub fn vqshlu_n_s8<const N: i32>(a: int8x8_t) -> uint8x8_t {
40756    static_assert_uimm_bits!(N, 3);
40757    unsafe extern "unadjusted" {
40758        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i8")]
40759        fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> uint8x8_t;
40760    }
40761    unsafe {
40762        _vqshlu_n_s8(
40763            a,
40764            const {
40765                int8x8_t([
40766                    N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
40767                ])
40768            },
40769        )
40770    }
40771}
40772#[doc = "Signed saturating shift left unsigned"]
40773#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"]
40774#[inline]
40775#[cfg(target_arch = "arm")]
40776#[target_feature(enable = "neon,v7")]
40777#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40778#[rustc_legacy_const_generics(1)]
40779#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40780pub fn vqshluq_n_s8<const N: i32>(a: int8x16_t) -> uint8x16_t {
40781    static_assert_uimm_bits!(N, 3);
40782    unsafe extern "unadjusted" {
40783        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v16i8")]
40784        fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> uint8x16_t;
40785    }
40786    unsafe {
40787        _vqshluq_n_s8(
40788            a,
40789            const {
40790                int8x16_t([
40791                    N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
40792                    N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
40793                ])
40794            },
40795        )
40796    }
40797}
40798#[doc = "Signed saturating shift left unsigned"]
40799#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"]
40800#[inline]
40801#[cfg(target_arch = "arm")]
40802#[target_feature(enable = "neon,v7")]
40803#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40804#[rustc_legacy_const_generics(1)]
40805#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40806pub fn vqshlu_n_s16<const N: i32>(a: int16x4_t) -> uint16x4_t {
40807    static_assert_uimm_bits!(N, 4);
40808    unsafe extern "unadjusted" {
40809        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i16")]
40810        fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> uint16x4_t;
40811    }
40812    unsafe {
40813        _vqshlu_n_s16(
40814            a,
40815            const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) },
40816        )
40817    }
40818}
40819#[doc = "Signed saturating shift left unsigned"]
40820#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"]
40821#[inline]
40822#[cfg(target_arch = "arm")]
40823#[target_feature(enable = "neon,v7")]
40824#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40825#[rustc_legacy_const_generics(1)]
40826#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40827pub fn vqshluq_n_s16<const N: i32>(a: int16x8_t) -> uint16x8_t {
40828    static_assert_uimm_bits!(N, 4);
40829    unsafe extern "unadjusted" {
40830        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i16")]
40831        fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> uint16x8_t;
40832    }
40833    unsafe {
40834        _vqshluq_n_s16(
40835            a,
40836            const {
40837                int16x8_t([
40838                    N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16,
40839                ])
40840            },
40841        )
40842    }
40843}
40844#[doc = "Signed saturating shift left unsigned"]
40845#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"]
40846#[inline]
40847#[cfg(target_arch = "arm")]
40848#[target_feature(enable = "neon,v7")]
40849#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40850#[rustc_legacy_const_generics(1)]
40851#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40852pub fn vqshlu_n_s32<const N: i32>(a: int32x2_t) -> uint32x2_t {
40853    static_assert_uimm_bits!(N, 5);
40854    unsafe extern "unadjusted" {
40855        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i32")]
40856        fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> uint32x2_t;
40857    }
40858    unsafe { _vqshlu_n_s32(a, const { int32x2_t([N as i32, N as i32]) }) }
40859}
40860#[doc = "Signed saturating shift left unsigned"]
40861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"]
40862#[inline]
40863#[cfg(target_arch = "arm")]
40864#[target_feature(enable = "neon,v7")]
40865#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40866#[rustc_legacy_const_generics(1)]
40867#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40868pub fn vqshluq_n_s32<const N: i32>(a: int32x4_t) -> uint32x4_t {
40869    static_assert_uimm_bits!(N, 5);
40870    unsafe extern "unadjusted" {
40871        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i32")]
40872        fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> uint32x4_t;
40873    }
40874    unsafe {
40875        _vqshluq_n_s32(
40876            a,
40877            const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) },
40878        )
40879    }
40880}
40881#[doc = "Signed saturating shift left unsigned"]
40882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"]
40883#[inline]
40884#[cfg(target_arch = "arm")]
40885#[target_feature(enable = "neon,v7")]
40886#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40887#[rustc_legacy_const_generics(1)]
40888#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40889pub fn vqshlu_n_s64<const N: i32>(a: int64x1_t) -> uint64x1_t {
40890    static_assert_uimm_bits!(N, 6);
40891    unsafe extern "unadjusted" {
40892        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v1i64")]
40893        fn _vqshlu_n_s64(a: int64x1_t, n: int64x1_t) -> uint64x1_t;
40894    }
40895    unsafe { _vqshlu_n_s64(a, const { int64x1_t([N as i64]) }) }
40896}
40897#[doc = "Signed saturating shift left unsigned"]
40898#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"]
40899#[inline]
40900#[cfg(target_arch = "arm")]
40901#[target_feature(enable = "neon,v7")]
40902#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40903#[rustc_legacy_const_generics(1)]
40904#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40905pub fn vqshluq_n_s64<const N: i32>(a: int64x2_t) -> uint64x2_t {
40906    static_assert_uimm_bits!(N, 6);
40907    unsafe extern "unadjusted" {
40908        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i64")]
40909        fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> uint64x2_t;
40910    }
40911    unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64, N as i64]) }) }
40912}
40913#[doc = "Signed saturating shift left unsigned"]
40914#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"]
40915#[inline]
40916#[target_feature(enable = "neon")]
40917#[cfg(not(target_arch = "arm"))]
40918#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
40919#[rustc_legacy_const_generics(1)]
40920#[stable(feature = "neon_intrinsics", since = "1.59.0")]
40921pub fn vqshlu_n_s8<const N: i32>(a: int8x8_t) -> uint8x8_t {
40922    static_assert_uimm_bits!(N, 3);
40923    unsafe extern "unadjusted" {
40924        #[cfg_attr(
40925            any(target_arch = "aarch64", target_arch = "arm64ec"),
40926            link_name = "llvm.aarch64.neon.sqshlu.v8i8"
40927        )]
40928        fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> uint8x8_t;
40929    }
40930    unsafe {
40931        _vqshlu_n_s8(
40932            a,
40933            const {
40934                int8x8_t([
40935                    N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
40936                ])
40937            },
40938        )
40939    }
40940}
40941#[doc = "Signed saturating shift left unsigned"]
40942#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"]
40943#[inline]
40944#[target_feature(enable = "neon")]
40945#[cfg(not(target_arch = "arm"))]
40946#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
40947#[rustc_legacy_const_generics(1)]
40948#[stable(feature = "neon_intrinsics", since = "1.59.0")]
40949pub fn vqshluq_n_s8<const N: i32>(a: int8x16_t) -> uint8x16_t {
40950    static_assert_uimm_bits!(N, 3);
40951    unsafe extern "unadjusted" {
40952        #[cfg_attr(
40953            any(target_arch = "aarch64", target_arch = "arm64ec"),
40954            link_name = "llvm.aarch64.neon.sqshlu.v16i8"
40955        )]
40956        fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> uint8x16_t;
40957    }
40958    unsafe {
40959        _vqshluq_n_s8(
40960            a,
40961            const {
40962                int8x16_t([
40963                    N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
40964                    N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
40965                ])
40966            },
40967        )
40968    }
40969}
40970#[doc = "Signed saturating shift left unsigned"]
40971#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"]
40972#[inline]
40973#[target_feature(enable = "neon")]
40974#[cfg(not(target_arch = "arm"))]
40975#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
40976#[rustc_legacy_const_generics(1)]
40977#[stable(feature = "neon_intrinsics", since = "1.59.0")]
40978pub fn vqshlu_n_s16<const N: i32>(a: int16x4_t) -> uint16x4_t {
40979    static_assert_uimm_bits!(N, 4);
40980    unsafe extern "unadjusted" {
40981        #[cfg_attr(
40982            any(target_arch = "aarch64", target_arch = "arm64ec"),
40983            link_name = "llvm.aarch64.neon.sqshlu.v4i16"
40984        )]
40985        fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> uint16x4_t;
40986    }
40987    unsafe {
40988        _vqshlu_n_s16(
40989            a,
40990            const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) },
40991        )
40992    }
40993}
40994#[doc = "Signed saturating shift left unsigned"]
40995#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"]
40996#[inline]
40997#[target_feature(enable = "neon")]
40998#[cfg(not(target_arch = "arm"))]
40999#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
41000#[rustc_legacy_const_generics(1)]
41001#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41002pub fn vqshluq_n_s16<const N: i32>(a: int16x8_t) -> uint16x8_t {
41003    static_assert_uimm_bits!(N, 4);
41004    unsafe extern "unadjusted" {
41005        #[cfg_attr(
41006            any(target_arch = "aarch64", target_arch = "arm64ec"),
41007            link_name = "llvm.aarch64.neon.sqshlu.v8i16"
41008        )]
41009        fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> uint16x8_t;
41010    }
41011    unsafe {
41012        _vqshluq_n_s16(
41013            a,
41014            const {
41015                int16x8_t([
41016                    N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16,
41017                ])
41018            },
41019        )
41020    }
41021}
41022#[doc = "Signed saturating shift left unsigned"]
41023#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"]
41024#[inline]
41025#[target_feature(enable = "neon")]
41026#[cfg(not(target_arch = "arm"))]
41027#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
41028#[rustc_legacy_const_generics(1)]
41029#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41030pub fn vqshlu_n_s32<const N: i32>(a: int32x2_t) -> uint32x2_t {
41031    static_assert_uimm_bits!(N, 5);
41032    unsafe extern "unadjusted" {
41033        #[cfg_attr(
41034            any(target_arch = "aarch64", target_arch = "arm64ec"),
41035            link_name = "llvm.aarch64.neon.sqshlu.v2i32"
41036        )]
41037        fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> uint32x2_t;
41038    }
41039    unsafe { _vqshlu_n_s32(a, const { int32x2_t([N as i32, N as i32]) }) }
41040}
41041#[doc = "Signed saturating shift left unsigned"]
41042#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"]
41043#[inline]
41044#[target_feature(enable = "neon")]
41045#[cfg(not(target_arch = "arm"))]
41046#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
41047#[rustc_legacy_const_generics(1)]
41048#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41049pub fn vqshluq_n_s32<const N: i32>(a: int32x4_t) -> uint32x4_t {
41050    static_assert_uimm_bits!(N, 5);
41051    unsafe extern "unadjusted" {
41052        #[cfg_attr(
41053            any(target_arch = "aarch64", target_arch = "arm64ec"),
41054            link_name = "llvm.aarch64.neon.sqshlu.v4i32"
41055        )]
41056        fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> uint32x4_t;
41057    }
41058    unsafe {
41059        _vqshluq_n_s32(
41060            a,
41061            const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) },
41062        )
41063    }
41064}
41065#[doc = "Signed saturating shift left unsigned"]
41066#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"]
41067#[inline]
41068#[target_feature(enable = "neon")]
41069#[cfg(not(target_arch = "arm"))]
41070#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
41071#[rustc_legacy_const_generics(1)]
41072#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41073pub fn vqshlu_n_s64<const N: i32>(a: int64x1_t) -> uint64x1_t {
41074    static_assert_uimm_bits!(N, 6);
41075    unsafe extern "unadjusted" {
41076        #[cfg_attr(
41077            any(target_arch = "aarch64", target_arch = "arm64ec"),
41078            link_name = "llvm.aarch64.neon.sqshlu.v1i64"
41079        )]
41080        fn _vqshlu_n_s64(a: int64x1_t, n: int64x1_t) -> uint64x1_t;
41081    }
41082    unsafe { _vqshlu_n_s64(a, const { int64x1_t([N as i64]) }) }
41083}
41084#[doc = "Signed saturating shift left unsigned"]
41085#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"]
41086#[inline]
41087#[target_feature(enable = "neon")]
41088#[cfg(not(target_arch = "arm"))]
41089#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
41090#[rustc_legacy_const_generics(1)]
41091#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41092pub fn vqshluq_n_s64<const N: i32>(a: int64x2_t) -> uint64x2_t {
41093    static_assert_uimm_bits!(N, 6);
41094    unsafe extern "unadjusted" {
41095        #[cfg_attr(
41096            any(target_arch = "aarch64", target_arch = "arm64ec"),
41097            link_name = "llvm.aarch64.neon.sqshlu.v2i64"
41098        )]
41099        fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> uint64x2_t;
41100    }
41101    unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64, N as i64]) }) }
41102}
41103#[doc = "Signed saturating shift right narrow"]
41104#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"]
41105#[inline]
41106#[cfg(target_arch = "arm")]
41107#[target_feature(enable = "neon,v7")]
41108#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
41109#[rustc_legacy_const_generics(1)]
41110#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41111pub fn vqshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
41112    static_assert!(N >= 1 && N <= 8);
41113    unsafe extern "unadjusted" {
41114        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v8i8")]
41115        fn _vqshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t;
41116    }
41117    unsafe {
41118        _vqshrn_n_s16(
41119            a,
41120            const {
41121                int16x8_t([
41122                    -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
41123                    -N as i16,
41124                ])
41125            },
41126        )
41127    }
41128}
41129#[doc = "Signed saturating shift right narrow"]
41130#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"]
41131#[inline]
41132#[cfg(target_arch = "arm")]
41133#[target_feature(enable = "neon,v7")]
41134#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
41135#[rustc_legacy_const_generics(1)]
41136#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41137pub fn vqshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
41138    static_assert!(N >= 1 && N <= 16);
41139    unsafe extern "unadjusted" {
41140        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v4i16")]
41141        fn _vqshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t;
41142    }
41143    unsafe {
41144        _vqshrn_n_s32(
41145            a,
41146            const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
41147        )
41148    }
41149}
41150#[doc = "Signed saturating shift right narrow"]
41151#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"]
41152#[inline]
41153#[cfg(target_arch = "arm")]
41154#[target_feature(enable = "neon,v7")]
41155#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
41156#[rustc_legacy_const_generics(1)]
41157#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41158pub fn vqshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
41159    static_assert!(N >= 1 && N <= 32);
41160    unsafe extern "unadjusted" {
41161        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v2i32")]
41162        fn _vqshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t;
41163    }
41164    unsafe { _vqshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
41165}
41166#[doc = "Signed saturating shift right narrow"]
41167#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"]
41168#[inline]
41169#[target_feature(enable = "neon")]
41170#[cfg(not(target_arch = "arm"))]
41171#[cfg_attr(test, assert_instr(sqshrn, N = 2))]
41172#[rustc_legacy_const_generics(1)]
41173#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41174pub fn vqshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
41175    static_assert!(N >= 1 && N <= 8);
41176    unsafe extern "unadjusted" {
41177        #[cfg_attr(
41178            any(target_arch = "aarch64", target_arch = "arm64ec"),
41179            link_name = "llvm.aarch64.neon.sqshrn.v8i8"
41180        )]
41181        fn _vqshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t;
41182    }
41183    unsafe { _vqshrn_n_s16(a, N) }
41184}
41185#[doc = "Signed saturating shift right narrow"]
41186#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"]
41187#[inline]
41188#[target_feature(enable = "neon")]
41189#[cfg(not(target_arch = "arm"))]
41190#[cfg_attr(test, assert_instr(sqshrn, N = 2))]
41191#[rustc_legacy_const_generics(1)]
41192#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41193pub fn vqshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
41194    static_assert!(N >= 1 && N <= 16);
41195    unsafe extern "unadjusted" {
41196        #[cfg_attr(
41197            any(target_arch = "aarch64", target_arch = "arm64ec"),
41198            link_name = "llvm.aarch64.neon.sqshrn.v4i16"
41199        )]
41200        fn _vqshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t;
41201    }
41202    unsafe { _vqshrn_n_s32(a, N) }
41203}
41204#[doc = "Signed saturating shift right narrow"]
41205#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"]
41206#[inline]
41207#[target_feature(enable = "neon")]
41208#[cfg(not(target_arch = "arm"))]
41209#[cfg_attr(test, assert_instr(sqshrn, N = 2))]
41210#[rustc_legacy_const_generics(1)]
41211#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41212pub fn vqshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
41213    static_assert!(N >= 1 && N <= 32);
41214    unsafe extern "unadjusted" {
41215        #[cfg_attr(
41216            any(target_arch = "aarch64", target_arch = "arm64ec"),
41217            link_name = "llvm.aarch64.neon.sqshrn.v2i32"
41218        )]
41219        fn _vqshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t;
41220    }
41221    unsafe { _vqshrn_n_s64(a, N) }
41222}
41223#[doc = "Unsigned saturating shift right narrow"]
41224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"]
41225#[inline]
41226#[cfg(target_arch = "arm")]
41227#[target_feature(enable = "neon,v7")]
41228#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
41229#[rustc_legacy_const_generics(1)]
41230#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41231pub fn vqshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
41232    static_assert!(N >= 1 && N <= 8);
41233    unsafe extern "unadjusted" {
41234        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v8i8")]
41235        fn _vqshrn_n_u16(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t;
41236    }
41237    unsafe {
41238        _vqshrn_n_u16(
41239            a,
41240            const {
41241                uint16x8_t([
41242                    -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16,
41243                    -N as u16,
41244                ])
41245            },
41246        )
41247    }
41248}
41249#[doc = "Unsigned saturating shift right narrow"]
41250#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"]
41251#[inline]
41252#[cfg(target_arch = "arm")]
41253#[target_feature(enable = "neon,v7")]
41254#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
41255#[rustc_legacy_const_generics(1)]
41256#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41257pub fn vqshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
41258    static_assert!(N >= 1 && N <= 16);
41259    unsafe extern "unadjusted" {
41260        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v4i16")]
41261        fn _vqshrn_n_u32(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t;
41262    }
41263    unsafe {
41264        _vqshrn_n_u32(
41265            a,
41266            const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) },
41267        )
41268    }
41269}
41270#[doc = "Unsigned saturating shift right narrow"]
41271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"]
41272#[inline]
41273#[cfg(target_arch = "arm")]
41274#[target_feature(enable = "neon,v7")]
41275#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
41276#[rustc_legacy_const_generics(1)]
41277#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41278pub fn vqshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
41279    static_assert!(N >= 1 && N <= 32);
41280    unsafe extern "unadjusted" {
41281        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v2i32")]
41282        fn _vqshrn_n_u64(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t;
41283    }
41284    unsafe { _vqshrn_n_u64(a, const { uint64x2_t([-N as u64, -N as u64]) }) }
41285}
41286#[doc = "Unsigned saturating shift right narrow"]
41287#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"]
41288#[inline]
41289#[target_feature(enable = "neon")]
41290#[cfg(not(target_arch = "arm"))]
41291#[cfg_attr(test, assert_instr(uqshrn, N = 2))]
41292#[rustc_legacy_const_generics(1)]
41293#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41294pub fn vqshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
41295    static_assert!(N >= 1 && N <= 8);
41296    unsafe extern "unadjusted" {
41297        #[cfg_attr(
41298            any(target_arch = "aarch64", target_arch = "arm64ec"),
41299            link_name = "llvm.aarch64.neon.uqshrn.v8i8"
41300        )]
41301        fn _vqshrn_n_u16(a: uint16x8_t, n: i32) -> uint8x8_t;
41302    }
41303    unsafe { _vqshrn_n_u16(a, N) }
41304}
41305#[doc = "Unsigned saturating shift right narrow"]
41306#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"]
41307#[inline]
41308#[target_feature(enable = "neon")]
41309#[cfg(not(target_arch = "arm"))]
41310#[cfg_attr(test, assert_instr(uqshrn, N = 2))]
41311#[rustc_legacy_const_generics(1)]
41312#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41313pub fn vqshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
41314    static_assert!(N >= 1 && N <= 16);
41315    unsafe extern "unadjusted" {
41316        #[cfg_attr(
41317            any(target_arch = "aarch64", target_arch = "arm64ec"),
41318            link_name = "llvm.aarch64.neon.uqshrn.v4i16"
41319        )]
41320        fn _vqshrn_n_u32(a: uint32x4_t, n: i32) -> uint16x4_t;
41321    }
41322    unsafe { _vqshrn_n_u32(a, N) }
41323}
41324#[doc = "Unsigned saturating shift right narrow"]
41325#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"]
41326#[inline]
41327#[target_feature(enable = "neon")]
41328#[cfg(not(target_arch = "arm"))]
41329#[cfg_attr(test, assert_instr(uqshrn, N = 2))]
41330#[rustc_legacy_const_generics(1)]
41331#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41332pub fn vqshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
41333    static_assert!(N >= 1 && N <= 32);
41334    unsafe extern "unadjusted" {
41335        #[cfg_attr(
41336            any(target_arch = "aarch64", target_arch = "arm64ec"),
41337            link_name = "llvm.aarch64.neon.uqshrn.v2i32"
41338        )]
41339        fn _vqshrn_n_u64(a: uint64x2_t, n: i32) -> uint32x2_t;
41340    }
41341    unsafe { _vqshrn_n_u64(a, N) }
41342}
41343#[doc = "Signed saturating shift right unsigned narrow"]
41344#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"]
41345#[inline]
41346#[cfg(target_arch = "arm")]
41347#[target_feature(enable = "neon,v7")]
41348#[cfg_attr(test, assert_instr(vqshrun, N = 2))]
41349#[rustc_legacy_const_generics(1)]
41350#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41351pub fn vqshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
41352    static_assert!(N >= 1 && N <= 8);
41353    unsafe extern "unadjusted" {
41354        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v8i8")]
41355        fn _vqshrun_n_s16(a: int16x8_t, n: int16x8_t) -> uint8x8_t;
41356    }
41357    unsafe {
41358        _vqshrun_n_s16(
41359            a,
41360            const {
41361                int16x8_t([
41362                    -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
41363                    -N as i16,
41364                ])
41365            },
41366        )
41367    }
41368}
41369#[doc = "Signed saturating shift right unsigned narrow"]
41370#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"]
41371#[inline]
41372#[cfg(target_arch = "arm")]
41373#[target_feature(enable = "neon,v7")]
41374#[cfg_attr(test, assert_instr(vqshrun, N = 2))]
41375#[rustc_legacy_const_generics(1)]
41376#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41377pub fn vqshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
41378    static_assert!(N >= 1 && N <= 16);
41379    unsafe extern "unadjusted" {
41380        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v4i16")]
41381        fn _vqshrun_n_s32(a: int32x4_t, n: int32x4_t) -> uint16x4_t;
41382    }
41383    unsafe {
41384        _vqshrun_n_s32(
41385            a,
41386            const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
41387        )
41388    }
41389}
41390#[doc = "Signed saturating shift right unsigned narrow"]
41391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"]
41392#[inline]
41393#[cfg(target_arch = "arm")]
41394#[target_feature(enable = "neon,v7")]
41395#[cfg_attr(test, assert_instr(vqshrun, N = 2))]
41396#[rustc_legacy_const_generics(1)]
41397#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41398pub fn vqshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
41399    static_assert!(N >= 1 && N <= 32);
41400    unsafe extern "unadjusted" {
41401        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v2i32")]
41402        fn _vqshrun_n_s64(a: int64x2_t, n: int64x2_t) -> uint32x2_t;
41403    }
41404    unsafe { _vqshrun_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
41405}
41406#[doc = "Signed saturating shift right unsigned narrow"]
41407#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"]
41408#[inline]
41409#[target_feature(enable = "neon")]
41410#[cfg(not(target_arch = "arm"))]
41411#[cfg_attr(test, assert_instr(sqshrun, N = 2))]
41412#[rustc_legacy_const_generics(1)]
41413#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41414pub fn vqshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
41415    static_assert!(N >= 1 && N <= 8);
41416    unsafe extern "unadjusted" {
41417        #[cfg_attr(
41418            any(target_arch = "aarch64", target_arch = "arm64ec"),
41419            link_name = "llvm.aarch64.neon.sqshrun.v8i8"
41420        )]
41421        fn _vqshrun_n_s16(a: int16x8_t, n: i32) -> uint8x8_t;
41422    }
41423    unsafe { _vqshrun_n_s16(a, N) }
41424}
41425#[doc = "Signed saturating shift right unsigned narrow"]
41426#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"]
41427#[inline]
41428#[target_feature(enable = "neon")]
41429#[cfg(not(target_arch = "arm"))]
41430#[cfg_attr(test, assert_instr(sqshrun, N = 2))]
41431#[rustc_legacy_const_generics(1)]
41432#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41433pub fn vqshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
41434    static_assert!(N >= 1 && N <= 16);
41435    unsafe extern "unadjusted" {
41436        #[cfg_attr(
41437            any(target_arch = "aarch64", target_arch = "arm64ec"),
41438            link_name = "llvm.aarch64.neon.sqshrun.v4i16"
41439        )]
41440        fn _vqshrun_n_s32(a: int32x4_t, n: i32) -> uint16x4_t;
41441    }
41442    unsafe { _vqshrun_n_s32(a, N) }
41443}
41444#[doc = "Signed saturating shift right unsigned narrow"]
41445#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"]
41446#[inline]
41447#[target_feature(enable = "neon")]
41448#[cfg(not(target_arch = "arm"))]
41449#[cfg_attr(test, assert_instr(sqshrun, N = 2))]
41450#[rustc_legacy_const_generics(1)]
41451#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41452pub fn vqshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
41453    static_assert!(N >= 1 && N <= 32);
41454    unsafe extern "unadjusted" {
41455        #[cfg_attr(
41456            any(target_arch = "aarch64", target_arch = "arm64ec"),
41457            link_name = "llvm.aarch64.neon.sqshrun.v2i32"
41458        )]
41459        fn _vqshrun_n_s64(a: int64x2_t, n: i32) -> uint32x2_t;
41460    }
41461    unsafe { _vqshrun_n_s64(a, N) }
41462}
41463#[doc = "Saturating subtract"]
41464#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s8)"]
41465#[inline]
41466#[target_feature(enable = "neon")]
41467#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41468#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))]
41469#[cfg_attr(
41470    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41471    assert_instr(sqsub)
41472)]
41473#[cfg_attr(
41474    not(target_arch = "arm"),
41475    stable(feature = "neon_intrinsics", since = "1.59.0")
41476)]
41477#[cfg_attr(
41478    target_arch = "arm",
41479    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41480)]
41481pub fn vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
41482    unsafe extern "unadjusted" {
41483        #[cfg_attr(
41484            any(target_arch = "aarch64", target_arch = "arm64ec"),
41485            link_name = "llvm.aarch64.neon.sqsub.v8i8"
41486        )]
41487        #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v8i8")]
41488        fn _vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
41489    }
41490    unsafe { _vqsub_s8(a, b) }
41491}
41492#[doc = "Saturating subtract"]
41493#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s8)"]
41494#[inline]
41495#[target_feature(enable = "neon")]
41496#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41497#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))]
41498#[cfg_attr(
41499    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41500    assert_instr(sqsub)
41501)]
41502#[cfg_attr(
41503    not(target_arch = "arm"),
41504    stable(feature = "neon_intrinsics", since = "1.59.0")
41505)]
41506#[cfg_attr(
41507    target_arch = "arm",
41508    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41509)]
41510pub fn vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
41511    unsafe extern "unadjusted" {
41512        #[cfg_attr(
41513            any(target_arch = "aarch64", target_arch = "arm64ec"),
41514            link_name = "llvm.aarch64.neon.sqsub.v16i8"
41515        )]
41516        #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v16i8")]
41517        fn _vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
41518    }
41519    unsafe { _vqsubq_s8(a, b) }
41520}
41521#[doc = "Saturating subtract"]
41522#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s16)"]
41523#[inline]
41524#[target_feature(enable = "neon")]
41525#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41526#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))]
41527#[cfg_attr(
41528    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41529    assert_instr(sqsub)
41530)]
41531#[cfg_attr(
41532    not(target_arch = "arm"),
41533    stable(feature = "neon_intrinsics", since = "1.59.0")
41534)]
41535#[cfg_attr(
41536    target_arch = "arm",
41537    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41538)]
41539pub fn vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
41540    unsafe extern "unadjusted" {
41541        #[cfg_attr(
41542            any(target_arch = "aarch64", target_arch = "arm64ec"),
41543            link_name = "llvm.aarch64.neon.sqsub.v4i16"
41544        )]
41545        #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v4i16")]
41546        fn _vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
41547    }
41548    unsafe { _vqsub_s16(a, b) }
41549}
41550#[doc = "Saturating subtract"]
41551#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s16)"]
41552#[inline]
41553#[target_feature(enable = "neon")]
41554#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41555#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))]
41556#[cfg_attr(
41557    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41558    assert_instr(sqsub)
41559)]
41560#[cfg_attr(
41561    not(target_arch = "arm"),
41562    stable(feature = "neon_intrinsics", since = "1.59.0")
41563)]
41564#[cfg_attr(
41565    target_arch = "arm",
41566    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41567)]
41568pub fn vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
41569    unsafe extern "unadjusted" {
41570        #[cfg_attr(
41571            any(target_arch = "aarch64", target_arch = "arm64ec"),
41572            link_name = "llvm.aarch64.neon.sqsub.v8i16"
41573        )]
41574        #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v8i16")]
41575        fn _vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
41576    }
41577    unsafe { _vqsubq_s16(a, b) }
41578}
41579#[doc = "Saturating subtract"]
41580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s32)"]
41581#[inline]
41582#[target_feature(enable = "neon")]
41583#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41584#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))]
41585#[cfg_attr(
41586    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41587    assert_instr(sqsub)
41588)]
41589#[cfg_attr(
41590    not(target_arch = "arm"),
41591    stable(feature = "neon_intrinsics", since = "1.59.0")
41592)]
41593#[cfg_attr(
41594    target_arch = "arm",
41595    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41596)]
41597pub fn vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
41598    unsafe extern "unadjusted" {
41599        #[cfg_attr(
41600            any(target_arch = "aarch64", target_arch = "arm64ec"),
41601            link_name = "llvm.aarch64.neon.sqsub.v2i32"
41602        )]
41603        #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v2i32")]
41604        fn _vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
41605    }
41606    unsafe { _vqsub_s32(a, b) }
41607}
41608#[doc = "Saturating subtract"]
41609#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s32)"]
41610#[inline]
41611#[target_feature(enable = "neon")]
41612#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41613#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))]
41614#[cfg_attr(
41615    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41616    assert_instr(sqsub)
41617)]
41618#[cfg_attr(
41619    not(target_arch = "arm"),
41620    stable(feature = "neon_intrinsics", since = "1.59.0")
41621)]
41622#[cfg_attr(
41623    target_arch = "arm",
41624    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41625)]
41626pub fn vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
41627    unsafe extern "unadjusted" {
41628        #[cfg_attr(
41629            any(target_arch = "aarch64", target_arch = "arm64ec"),
41630            link_name = "llvm.aarch64.neon.sqsub.v4i32"
41631        )]
41632        #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v4i32")]
41633        fn _vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
41634    }
41635    unsafe { _vqsubq_s32(a, b) }
41636}
41637#[doc = "Saturating subtract"]
41638#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s64)"]
41639#[inline]
41640#[target_feature(enable = "neon")]
41641#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41642#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))]
41643#[cfg_attr(
41644    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41645    assert_instr(sqsub)
41646)]
41647#[cfg_attr(
41648    not(target_arch = "arm"),
41649    stable(feature = "neon_intrinsics", since = "1.59.0")
41650)]
41651#[cfg_attr(
41652    target_arch = "arm",
41653    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41654)]
41655pub fn vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
41656    unsafe extern "unadjusted" {
41657        #[cfg_attr(
41658            any(target_arch = "aarch64", target_arch = "arm64ec"),
41659            link_name = "llvm.aarch64.neon.sqsub.v1i64"
41660        )]
41661        #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v1i64")]
41662        fn _vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
41663    }
41664    unsafe { _vqsub_s64(a, b) }
41665}
41666#[doc = "Saturating subtract"]
41667#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s64)"]
41668#[inline]
41669#[target_feature(enable = "neon")]
41670#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41671#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))]
41672#[cfg_attr(
41673    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41674    assert_instr(sqsub)
41675)]
41676#[cfg_attr(
41677    not(target_arch = "arm"),
41678    stable(feature = "neon_intrinsics", since = "1.59.0")
41679)]
41680#[cfg_attr(
41681    target_arch = "arm",
41682    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41683)]
41684pub fn vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
41685    unsafe extern "unadjusted" {
41686        #[cfg_attr(
41687            any(target_arch = "aarch64", target_arch = "arm64ec"),
41688            link_name = "llvm.aarch64.neon.sqsub.v2i64"
41689        )]
41690        #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v2i64")]
41691        fn _vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
41692    }
41693    unsafe { _vqsubq_s64(a, b) }
41694}
41695#[doc = "Saturating subtract"]
41696#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u8)"]
41697#[inline]
41698#[target_feature(enable = "neon")]
41699#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41700#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))]
41701#[cfg_attr(
41702    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41703    assert_instr(uqsub)
41704)]
41705#[cfg_attr(
41706    not(target_arch = "arm"),
41707    stable(feature = "neon_intrinsics", since = "1.59.0")
41708)]
41709#[cfg_attr(
41710    target_arch = "arm",
41711    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41712)]
41713pub fn vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
41714    unsafe extern "unadjusted" {
41715        #[cfg_attr(
41716            any(target_arch = "aarch64", target_arch = "arm64ec"),
41717            link_name = "llvm.aarch64.neon.uqsub.v8i8"
41718        )]
41719        #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v8i8")]
41720        fn _vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
41721    }
41722    unsafe { _vqsub_u8(a, b) }
41723}
41724#[doc = "Saturating subtract"]
41725#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u8)"]
41726#[inline]
41727#[target_feature(enable = "neon")]
41728#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41729#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))]
41730#[cfg_attr(
41731    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41732    assert_instr(uqsub)
41733)]
41734#[cfg_attr(
41735    not(target_arch = "arm"),
41736    stable(feature = "neon_intrinsics", since = "1.59.0")
41737)]
41738#[cfg_attr(
41739    target_arch = "arm",
41740    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41741)]
41742pub fn vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
41743    unsafe extern "unadjusted" {
41744        #[cfg_attr(
41745            any(target_arch = "aarch64", target_arch = "arm64ec"),
41746            link_name = "llvm.aarch64.neon.uqsub.v16i8"
41747        )]
41748        #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v16i8")]
41749        fn _vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
41750    }
41751    unsafe { _vqsubq_u8(a, b) }
41752}
41753#[doc = "Saturating subtract"]
41754#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u16)"]
41755#[inline]
41756#[target_feature(enable = "neon")]
41757#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41758#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))]
41759#[cfg_attr(
41760    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41761    assert_instr(uqsub)
41762)]
41763#[cfg_attr(
41764    not(target_arch = "arm"),
41765    stable(feature = "neon_intrinsics", since = "1.59.0")
41766)]
41767#[cfg_attr(
41768    target_arch = "arm",
41769    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41770)]
41771pub fn vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
41772    unsafe extern "unadjusted" {
41773        #[cfg_attr(
41774            any(target_arch = "aarch64", target_arch = "arm64ec"),
41775            link_name = "llvm.aarch64.neon.uqsub.v4i16"
41776        )]
41777        #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v4i16")]
41778        fn _vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
41779    }
41780    unsafe { _vqsub_u16(a, b) }
41781}
41782#[doc = "Saturating subtract"]
41783#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u16)"]
41784#[inline]
41785#[target_feature(enable = "neon")]
41786#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41787#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))]
41788#[cfg_attr(
41789    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41790    assert_instr(uqsub)
41791)]
41792#[cfg_attr(
41793    not(target_arch = "arm"),
41794    stable(feature = "neon_intrinsics", since = "1.59.0")
41795)]
41796#[cfg_attr(
41797    target_arch = "arm",
41798    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41799)]
41800pub fn vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
41801    unsafe extern "unadjusted" {
41802        #[cfg_attr(
41803            any(target_arch = "aarch64", target_arch = "arm64ec"),
41804            link_name = "llvm.aarch64.neon.uqsub.v8i16"
41805        )]
41806        #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v8i16")]
41807        fn _vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
41808    }
41809    unsafe { _vqsubq_u16(a, b) }
41810}
41811#[doc = "Saturating subtract"]
41812#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u32)"]
41813#[inline]
41814#[target_feature(enable = "neon")]
41815#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41816#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))]
41817#[cfg_attr(
41818    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41819    assert_instr(uqsub)
41820)]
41821#[cfg_attr(
41822    not(target_arch = "arm"),
41823    stable(feature = "neon_intrinsics", since = "1.59.0")
41824)]
41825#[cfg_attr(
41826    target_arch = "arm",
41827    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41828)]
41829pub fn vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
41830    unsafe extern "unadjusted" {
41831        #[cfg_attr(
41832            any(target_arch = "aarch64", target_arch = "arm64ec"),
41833            link_name = "llvm.aarch64.neon.uqsub.v2i32"
41834        )]
41835        #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v2i32")]
41836        fn _vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
41837    }
41838    unsafe { _vqsub_u32(a, b) }
41839}
41840#[doc = "Saturating subtract"]
41841#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u32)"]
41842#[inline]
41843#[target_feature(enable = "neon")]
41844#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41845#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))]
41846#[cfg_attr(
41847    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41848    assert_instr(uqsub)
41849)]
41850#[cfg_attr(
41851    not(target_arch = "arm"),
41852    stable(feature = "neon_intrinsics", since = "1.59.0")
41853)]
41854#[cfg_attr(
41855    target_arch = "arm",
41856    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41857)]
41858pub fn vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
41859    unsafe extern "unadjusted" {
41860        #[cfg_attr(
41861            any(target_arch = "aarch64", target_arch = "arm64ec"),
41862            link_name = "llvm.aarch64.neon.uqsub.v4i32"
41863        )]
41864        #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v4i32")]
41865        fn _vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
41866    }
41867    unsafe { _vqsubq_u32(a, b) }
41868}
41869#[doc = "Saturating subtract"]
41870#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u64)"]
41871#[inline]
41872#[target_feature(enable = "neon")]
41873#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41874#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))]
41875#[cfg_attr(
41876    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41877    assert_instr(uqsub)
41878)]
41879#[cfg_attr(
41880    not(target_arch = "arm"),
41881    stable(feature = "neon_intrinsics", since = "1.59.0")
41882)]
41883#[cfg_attr(
41884    target_arch = "arm",
41885    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41886)]
41887pub fn vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
41888    unsafe extern "unadjusted" {
41889        #[cfg_attr(
41890            any(target_arch = "aarch64", target_arch = "arm64ec"),
41891            link_name = "llvm.aarch64.neon.uqsub.v1i64"
41892        )]
41893        #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v1i64")]
41894        fn _vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t;
41895    }
41896    unsafe { _vqsub_u64(a, b) }
41897}
41898#[doc = "Saturating subtract"]
41899#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u64)"]
41900#[inline]
41901#[target_feature(enable = "neon")]
41902#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41903#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))]
41904#[cfg_attr(
41905    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41906    assert_instr(uqsub)
41907)]
41908#[cfg_attr(
41909    not(target_arch = "arm"),
41910    stable(feature = "neon_intrinsics", since = "1.59.0")
41911)]
41912#[cfg_attr(
41913    target_arch = "arm",
41914    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41915)]
41916pub fn vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
41917    unsafe extern "unadjusted" {
41918        #[cfg_attr(
41919            any(target_arch = "aarch64", target_arch = "arm64ec"),
41920            link_name = "llvm.aarch64.neon.uqsub.v2i64"
41921        )]
41922        #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v2i64")]
41923        fn _vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t;
41924    }
41925    unsafe { _vqsubq_u64(a, b) }
41926}
41927#[doc = "Rounding Add returning High Narrow (high half)."]
41928#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s16)"]
41929#[inline]
41930#[target_feature(enable = "neon")]
41931#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41932#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
41933#[cfg_attr(
41934    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41935    assert_instr(raddhn2)
41936)]
41937#[cfg_attr(
41938    not(target_arch = "arm"),
41939    stable(feature = "neon_intrinsics", since = "1.59.0")
41940)]
41941#[cfg_attr(
41942    target_arch = "arm",
41943    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41944)]
41945pub fn vraddhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
41946    let x = vraddhn_s16(b, c);
41947    unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
41948}
41949#[doc = "Rounding Add returning High Narrow (high half)."]
41950#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s32)"]
41951#[inline]
41952#[target_feature(enable = "neon")]
41953#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41954#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
41955#[cfg_attr(
41956    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41957    assert_instr(raddhn2)
41958)]
41959#[cfg_attr(
41960    not(target_arch = "arm"),
41961    stable(feature = "neon_intrinsics", since = "1.59.0")
41962)]
41963#[cfg_attr(
41964    target_arch = "arm",
41965    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41966)]
41967pub fn vraddhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
41968    let x = vraddhn_s32(b, c);
41969    unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) }
41970}
41971#[doc = "Rounding Add returning High Narrow (high half)."]
41972#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s64)"]
41973#[inline]
41974#[target_feature(enable = "neon")]
41975#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41976#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
41977#[cfg_attr(
41978    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41979    assert_instr(raddhn2)
41980)]
41981#[cfg_attr(
41982    not(target_arch = "arm"),
41983    stable(feature = "neon_intrinsics", since = "1.59.0")
41984)]
41985#[cfg_attr(
41986    target_arch = "arm",
41987    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41988)]
41989pub fn vraddhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
41990    let x = vraddhn_s64(b, c);
41991    unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) }
41992}
41993#[doc = "Rounding Add returning High Narrow (high half)."]
41994#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u16)"]
41995#[inline]
41996#[target_feature(enable = "neon")]
41997#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41998#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
41999#[cfg_attr(
42000    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42001    assert_instr(raddhn2)
42002)]
42003#[cfg_attr(
42004    not(target_arch = "arm"),
42005    stable(feature = "neon_intrinsics", since = "1.59.0")
42006)]
42007#[cfg_attr(
42008    target_arch = "arm",
42009    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42010)]
42011pub fn vraddhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t {
42012    unsafe {
42013        let x: uint8x8_t = transmute(vraddhn_s16(transmute(b), transmute(c)));
42014        simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15])
42015    }
42016}
42017#[doc = "Rounding Add returning High Narrow (high half)."]
42018#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u32)"]
42019#[inline]
42020#[target_feature(enable = "neon")]
42021#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42022#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
42023#[cfg_attr(
42024    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42025    assert_instr(raddhn2)
42026)]
42027#[cfg_attr(
42028    not(target_arch = "arm"),
42029    stable(feature = "neon_intrinsics", since = "1.59.0")
42030)]
42031#[cfg_attr(
42032    target_arch = "arm",
42033    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42034)]
42035pub fn vraddhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t {
42036    unsafe {
42037        let x: uint16x4_t = transmute(vraddhn_s32(transmute(b), transmute(c)));
42038        simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7])
42039    }
42040}
42041#[doc = "Rounding Add returning High Narrow (high half)."]
42042#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u64)"]
42043#[inline]
42044#[target_feature(enable = "neon")]
42045#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42046#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
42047#[cfg_attr(
42048    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42049    assert_instr(raddhn2)
42050)]
42051#[cfg_attr(
42052    not(target_arch = "arm"),
42053    stable(feature = "neon_intrinsics", since = "1.59.0")
42054)]
42055#[cfg_attr(
42056    target_arch = "arm",
42057    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42058)]
42059pub fn vraddhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t {
42060    unsafe {
42061        let x: uint32x2_t = transmute(vraddhn_s64(transmute(b), transmute(c)));
42062        simd_shuffle!(a, x, [0, 1, 2, 3])
42063    }
42064}
42065#[doc = "Rounding Add returning High Narrow."]
42066#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s16)"]
42067#[inline]
42068#[target_feature(enable = "neon")]
42069#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42070#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
42071#[cfg_attr(
42072    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42073    assert_instr(raddhn)
42074)]
42075#[cfg_attr(
42076    not(target_arch = "arm"),
42077    stable(feature = "neon_intrinsics", since = "1.59.0")
42078)]
42079#[cfg_attr(
42080    target_arch = "arm",
42081    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42082)]
42083pub fn vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
42084    unsafe extern "unadjusted" {
42085        #[cfg_attr(
42086            any(target_arch = "aarch64", target_arch = "arm64ec"),
42087            link_name = "llvm.aarch64.neon.raddhn.v8i8"
42088        )]
42089        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v8i8")]
42090        fn _vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t;
42091    }
42092    unsafe { _vraddhn_s16(a, b) }
42093}
42094#[doc = "Rounding Add returning High Narrow."]
42095#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s32)"]
42096#[inline]
42097#[target_feature(enable = "neon")]
42098#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42099#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
42100#[cfg_attr(
42101    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42102    assert_instr(raddhn)
42103)]
42104#[cfg_attr(
42105    not(target_arch = "arm"),
42106    stable(feature = "neon_intrinsics", since = "1.59.0")
42107)]
42108#[cfg_attr(
42109    target_arch = "arm",
42110    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42111)]
42112pub fn vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
42113    unsafe extern "unadjusted" {
42114        #[cfg_attr(
42115            any(target_arch = "aarch64", target_arch = "arm64ec"),
42116            link_name = "llvm.aarch64.neon.raddhn.v4i16"
42117        )]
42118        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v4i16")]
42119        fn _vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t;
42120    }
42121    unsafe { _vraddhn_s32(a, b) }
42122}
42123#[doc = "Rounding Add returning High Narrow."]
42124#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s64)"]
42125#[inline]
42126#[target_feature(enable = "neon")]
42127#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42128#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
42129#[cfg_attr(
42130    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42131    assert_instr(raddhn)
42132)]
42133#[cfg_attr(
42134    not(target_arch = "arm"),
42135    stable(feature = "neon_intrinsics", since = "1.59.0")
42136)]
42137#[cfg_attr(
42138    target_arch = "arm",
42139    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42140)]
42141pub fn vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
42142    unsafe extern "unadjusted" {
42143        #[cfg_attr(
42144            any(target_arch = "aarch64", target_arch = "arm64ec"),
42145            link_name = "llvm.aarch64.neon.raddhn.v2i32"
42146        )]
42147        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v2i32")]
42148        fn _vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t;
42149    }
42150    unsafe { _vraddhn_s64(a, b) }
42151}
42152#[doc = "Rounding Add returning High Narrow."]
42153#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"]
42154#[inline]
42155#[cfg(target_endian = "little")]
42156#[target_feature(enable = "neon")]
42157#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42158#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
42159#[cfg_attr(
42160    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42161    assert_instr(raddhn)
42162)]
42163#[cfg_attr(
42164    not(target_arch = "arm"),
42165    stable(feature = "neon_intrinsics", since = "1.59.0")
42166)]
42167#[cfg_attr(
42168    target_arch = "arm",
42169    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42170)]
42171pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
42172    unsafe { transmute(vraddhn_s16(transmute(a), transmute(b))) }
42173}
42174#[doc = "Rounding Add returning High Narrow."]
42175#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"]
42176#[inline]
42177#[cfg(target_endian = "big")]
42178#[target_feature(enable = "neon")]
42179#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42180#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
42181#[cfg_attr(
42182    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42183    assert_instr(raddhn)
42184)]
42185#[cfg_attr(
42186    not(target_arch = "arm"),
42187    stable(feature = "neon_intrinsics", since = "1.59.0")
42188)]
42189#[cfg_attr(
42190    target_arch = "arm",
42191    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42192)]
42193pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
42194    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
42195    let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
42196    unsafe {
42197        let ret_val: uint8x8_t = transmute(vraddhn_s16(transmute(a), transmute(b)));
42198        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42199    }
42200}
42201#[doc = "Rounding Add returning High Narrow."]
42202#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"]
42203#[inline]
42204#[cfg(target_endian = "little")]
42205#[target_feature(enable = "neon")]
42206#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42207#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
42208#[cfg_attr(
42209    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42210    assert_instr(raddhn)
42211)]
42212#[cfg_attr(
42213    not(target_arch = "arm"),
42214    stable(feature = "neon_intrinsics", since = "1.59.0")
42215)]
42216#[cfg_attr(
42217    target_arch = "arm",
42218    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42219)]
42220pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
42221    unsafe { transmute(vraddhn_s32(transmute(a), transmute(b))) }
42222}
42223#[doc = "Rounding Add returning High Narrow."]
42224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"]
42225#[inline]
42226#[cfg(target_endian = "big")]
42227#[target_feature(enable = "neon")]
42228#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42229#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
42230#[cfg_attr(
42231    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42232    assert_instr(raddhn)
42233)]
42234#[cfg_attr(
42235    not(target_arch = "arm"),
42236    stable(feature = "neon_intrinsics", since = "1.59.0")
42237)]
42238#[cfg_attr(
42239    target_arch = "arm",
42240    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42241)]
42242pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
42243    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42244    let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) };
42245    unsafe {
42246        let ret_val: uint16x4_t = transmute(vraddhn_s32(transmute(a), transmute(b)));
42247        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42248    }
42249}
42250#[doc = "Rounding Add returning High Narrow."]
42251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"]
42252#[inline]
42253#[cfg(target_endian = "little")]
42254#[target_feature(enable = "neon")]
42255#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42256#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
42257#[cfg_attr(
42258    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42259    assert_instr(raddhn)
42260)]
42261#[cfg_attr(
42262    not(target_arch = "arm"),
42263    stable(feature = "neon_intrinsics", since = "1.59.0")
42264)]
42265#[cfg_attr(
42266    target_arch = "arm",
42267    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42268)]
42269pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
42270    unsafe { transmute(vraddhn_s64(transmute(a), transmute(b))) }
42271}
42272#[doc = "Rounding Add returning High Narrow."]
42273#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"]
42274#[inline]
42275#[cfg(target_endian = "big")]
42276#[target_feature(enable = "neon")]
42277#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42278#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
42279#[cfg_attr(
42280    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42281    assert_instr(raddhn)
42282)]
42283#[cfg_attr(
42284    not(target_arch = "arm"),
42285    stable(feature = "neon_intrinsics", since = "1.59.0")
42286)]
42287#[cfg_attr(
42288    target_arch = "arm",
42289    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42290)]
42291pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
42292    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
42293    let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) };
42294    unsafe {
42295        let ret_val: uint32x2_t = transmute(vraddhn_s64(transmute(a), transmute(b)));
42296        simd_shuffle!(ret_val, ret_val, [1, 0])
42297    }
42298}
42299#[doc = "Reciprocal estimate."]
42300#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f16)"]
42301#[inline]
42302#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
42303#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
42304#[cfg_attr(
42305    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42306    assert_instr(frecpe)
42307)]
42308#[target_feature(enable = "neon,fp16")]
42309#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42310pub fn vrecpe_f16(a: float16x4_t) -> float16x4_t {
42311    unsafe extern "unadjusted" {
42312        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4f16")]
42313        #[cfg_attr(
42314            any(target_arch = "aarch64", target_arch = "arm64ec"),
42315            link_name = "llvm.aarch64.neon.frecpe.v4f16"
42316        )]
42317        fn _vrecpe_f16(a: float16x4_t) -> float16x4_t;
42318    }
42319    unsafe { _vrecpe_f16(a) }
42320}
42321#[doc = "Reciprocal estimate."]
42322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f16)"]
42323#[inline]
42324#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
42325#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
42326#[cfg_attr(
42327    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42328    assert_instr(frecpe)
42329)]
42330#[target_feature(enable = "neon,fp16")]
42331#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42332pub fn vrecpeq_f16(a: float16x8_t) -> float16x8_t {
42333    unsafe extern "unadjusted" {
42334        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v8f16")]
42335        #[cfg_attr(
42336            any(target_arch = "aarch64", target_arch = "arm64ec"),
42337            link_name = "llvm.aarch64.neon.frecpe.v8f16"
42338        )]
42339        fn _vrecpeq_f16(a: float16x8_t) -> float16x8_t;
42340    }
42341    unsafe { _vrecpeq_f16(a) }
42342}
42343#[doc = "Reciprocal estimate."]
42344#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f32)"]
42345#[inline]
42346#[target_feature(enable = "neon")]
42347#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42348#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
42349#[cfg_attr(
42350    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42351    assert_instr(frecpe)
42352)]
42353#[cfg_attr(
42354    not(target_arch = "arm"),
42355    stable(feature = "neon_intrinsics", since = "1.59.0")
42356)]
42357#[cfg_attr(
42358    target_arch = "arm",
42359    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42360)]
42361pub fn vrecpe_f32(a: float32x2_t) -> float32x2_t {
42362    unsafe extern "unadjusted" {
42363        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v2f32")]
42364        #[cfg_attr(
42365            any(target_arch = "aarch64", target_arch = "arm64ec"),
42366            link_name = "llvm.aarch64.neon.frecpe.v2f32"
42367        )]
42368        fn _vrecpe_f32(a: float32x2_t) -> float32x2_t;
42369    }
42370    unsafe { _vrecpe_f32(a) }
42371}
42372#[doc = "Reciprocal estimate."]
42373#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f32)"]
42374#[inline]
42375#[target_feature(enable = "neon")]
42376#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42377#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
42378#[cfg_attr(
42379    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42380    assert_instr(frecpe)
42381)]
42382#[cfg_attr(
42383    not(target_arch = "arm"),
42384    stable(feature = "neon_intrinsics", since = "1.59.0")
42385)]
42386#[cfg_attr(
42387    target_arch = "arm",
42388    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42389)]
42390pub fn vrecpeq_f32(a: float32x4_t) -> float32x4_t {
42391    unsafe extern "unadjusted" {
42392        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4f32")]
42393        #[cfg_attr(
42394            any(target_arch = "aarch64", target_arch = "arm64ec"),
42395            link_name = "llvm.aarch64.neon.frecpe.v4f32"
42396        )]
42397        fn _vrecpeq_f32(a: float32x4_t) -> float32x4_t;
42398    }
42399    unsafe { _vrecpeq_f32(a) }
42400}
42401#[doc = "Unsigned reciprocal estimate"]
42402#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_u32)"]
42403#[inline]
42404#[target_feature(enable = "neon")]
42405#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42406#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
42407#[cfg_attr(
42408    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42409    assert_instr(urecpe)
42410)]
42411#[cfg_attr(
42412    not(target_arch = "arm"),
42413    stable(feature = "neon_intrinsics", since = "1.59.0")
42414)]
42415#[cfg_attr(
42416    target_arch = "arm",
42417    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42418)]
42419pub fn vrecpe_u32(a: uint32x2_t) -> uint32x2_t {
42420    unsafe extern "unadjusted" {
42421        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v2i32")]
42422        #[cfg_attr(
42423            any(target_arch = "aarch64", target_arch = "arm64ec"),
42424            link_name = "llvm.aarch64.neon.urecpe.v2i32"
42425        )]
42426        fn _vrecpe_u32(a: uint32x2_t) -> uint32x2_t;
42427    }
42428    unsafe { _vrecpe_u32(a) }
42429}
42430#[doc = "Unsigned reciprocal estimate"]
42431#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_u32)"]
42432#[inline]
42433#[target_feature(enable = "neon")]
42434#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42435#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
42436#[cfg_attr(
42437    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42438    assert_instr(urecpe)
42439)]
42440#[cfg_attr(
42441    not(target_arch = "arm"),
42442    stable(feature = "neon_intrinsics", since = "1.59.0")
42443)]
42444#[cfg_attr(
42445    target_arch = "arm",
42446    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42447)]
42448pub fn vrecpeq_u32(a: uint32x4_t) -> uint32x4_t {
42449    unsafe extern "unadjusted" {
42450        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4i32")]
42451        #[cfg_attr(
42452            any(target_arch = "aarch64", target_arch = "arm64ec"),
42453            link_name = "llvm.aarch64.neon.urecpe.v4i32"
42454        )]
42455        fn _vrecpeq_u32(a: uint32x4_t) -> uint32x4_t;
42456    }
42457    unsafe { _vrecpeq_u32(a) }
42458}
42459#[doc = "Floating-point reciprocal step"]
42460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f16)"]
42461#[inline]
42462#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
42463#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
42464#[cfg_attr(
42465    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42466    assert_instr(frecps)
42467)]
42468#[target_feature(enable = "neon,fp16")]
42469#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42470pub fn vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
42471    unsafe extern "unadjusted" {
42472        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v4f16")]
42473        #[cfg_attr(
42474            any(target_arch = "aarch64", target_arch = "arm64ec"),
42475            link_name = "llvm.aarch64.neon.frecps.v4f16"
42476        )]
42477        fn _vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
42478    }
42479    unsafe { _vrecps_f16(a, b) }
42480}
42481#[doc = "Floating-point reciprocal step"]
42482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f16)"]
42483#[inline]
42484#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
42485#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
42486#[cfg_attr(
42487    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42488    assert_instr(frecps)
42489)]
42490#[target_feature(enable = "neon,fp16")]
42491#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42492pub fn vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
42493    unsafe extern "unadjusted" {
42494        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v8f16")]
42495        #[cfg_attr(
42496            any(target_arch = "aarch64", target_arch = "arm64ec"),
42497            link_name = "llvm.aarch64.neon.frecps.v8f16"
42498        )]
42499        fn _vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
42500    }
42501    unsafe { _vrecpsq_f16(a, b) }
42502}
42503#[doc = "Floating-point reciprocal step"]
42504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f32)"]
42505#[inline]
42506#[target_feature(enable = "neon")]
42507#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42508#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
42509#[cfg_attr(
42510    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42511    assert_instr(frecps)
42512)]
42513#[cfg_attr(
42514    not(target_arch = "arm"),
42515    stable(feature = "neon_intrinsics", since = "1.59.0")
42516)]
42517#[cfg_attr(
42518    target_arch = "arm",
42519    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42520)]
42521pub fn vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
42522    unsafe extern "unadjusted" {
42523        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v2f32")]
42524        #[cfg_attr(
42525            any(target_arch = "aarch64", target_arch = "arm64ec"),
42526            link_name = "llvm.aarch64.neon.frecps.v2f32"
42527        )]
42528        fn _vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
42529    }
42530    unsafe { _vrecps_f32(a, b) }
42531}
42532#[doc = "Floating-point reciprocal step"]
42533#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f32)"]
42534#[inline]
42535#[target_feature(enable = "neon")]
42536#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42537#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
42538#[cfg_attr(
42539    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42540    assert_instr(frecps)
42541)]
42542#[cfg_attr(
42543    not(target_arch = "arm"),
42544    stable(feature = "neon_intrinsics", since = "1.59.0")
42545)]
42546#[cfg_attr(
42547    target_arch = "arm",
42548    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42549)]
42550pub fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
42551    unsafe extern "unadjusted" {
42552        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v4f32")]
42553        #[cfg_attr(
42554            any(target_arch = "aarch64", target_arch = "arm64ec"),
42555            link_name = "llvm.aarch64.neon.frecps.v4f32"
42556        )]
42557        fn _vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
42558    }
42559    unsafe { _vrecpsq_f32(a, b) }
42560}
42561#[doc = "Vector reinterpret cast operation"]
42562#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"]
42563#[inline]
42564#[cfg(target_endian = "little")]
42565#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42566#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42567#[cfg_attr(
42568    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42569    assert_instr(nop)
42570)]
42571#[target_feature(enable = "neon,fp16")]
42572#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42573pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
42574    unsafe { transmute(a) }
42575}
42576#[doc = "Vector reinterpret cast operation"]
42577#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"]
42578#[inline]
42579#[cfg(target_endian = "big")]
42580#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42581#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42582#[cfg_attr(
42583    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42584    assert_instr(nop)
42585)]
42586#[target_feature(enable = "neon,fp16")]
42587#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42588pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
42589    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42590    unsafe {
42591        let ret_val: float32x2_t = transmute(a);
42592        simd_shuffle!(ret_val, ret_val, [1, 0])
42593    }
42594}
42595#[doc = "Vector reinterpret cast operation"]
42596#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"]
42597#[inline]
42598#[cfg(target_endian = "little")]
42599#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42600#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42601#[cfg_attr(
42602    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42603    assert_instr(nop)
42604)]
42605#[target_feature(enable = "neon,fp16")]
42606#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42607pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
42608    unsafe { transmute(a) }
42609}
42610#[doc = "Vector reinterpret cast operation"]
42611#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"]
42612#[inline]
42613#[cfg(target_endian = "big")]
42614#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42615#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42616#[cfg_attr(
42617    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42618    assert_instr(nop)
42619)]
42620#[target_feature(enable = "neon,fp16")]
42621#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42622pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
42623    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42624    unsafe {
42625        let ret_val: int8x8_t = transmute(a);
42626        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42627    }
42628}
42629#[doc = "Vector reinterpret cast operation"]
42630#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
42631#[inline]
42632#[cfg(target_endian = "little")]
42633#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42634#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42635#[cfg_attr(
42636    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42637    assert_instr(nop)
42638)]
42639#[target_feature(enable = "neon,fp16")]
42640#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42641pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
42642    unsafe { transmute(a) }
42643}
42644#[doc = "Vector reinterpret cast operation"]
42645#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
42646#[inline]
42647#[cfg(target_endian = "big")]
42648#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42649#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42650#[cfg_attr(
42651    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42652    assert_instr(nop)
42653)]
42654#[target_feature(enable = "neon,fp16")]
42655#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42656pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
42657    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42658    unsafe {
42659        let ret_val: int16x4_t = transmute(a);
42660        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42661    }
42662}
42663#[doc = "Vector reinterpret cast operation"]
42664#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
42665#[inline]
42666#[cfg(target_endian = "little")]
42667#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42668#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42669#[cfg_attr(
42670    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42671    assert_instr(nop)
42672)]
42673#[target_feature(enable = "neon,fp16")]
42674#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42675pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
42676    unsafe { transmute(a) }
42677}
42678#[doc = "Vector reinterpret cast operation"]
42679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
42680#[inline]
42681#[cfg(target_endian = "big")]
42682#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42683#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42684#[cfg_attr(
42685    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42686    assert_instr(nop)
42687)]
42688#[target_feature(enable = "neon,fp16")]
42689#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42690pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
42691    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42692    unsafe {
42693        let ret_val: int32x2_t = transmute(a);
42694        simd_shuffle!(ret_val, ret_val, [1, 0])
42695    }
42696}
42697#[doc = "Vector reinterpret cast operation"]
42698#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
42699#[inline]
42700#[cfg(target_endian = "little")]
42701#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42702#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42703#[cfg_attr(
42704    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42705    assert_instr(nop)
42706)]
42707#[target_feature(enable = "neon,fp16")]
42708#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42709pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
42710    unsafe { transmute(a) }
42711}
42712#[doc = "Vector reinterpret cast operation"]
42713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
42714#[inline]
42715#[cfg(target_endian = "big")]
42716#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42717#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42718#[cfg_attr(
42719    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42720    assert_instr(nop)
42721)]
42722#[target_feature(enable = "neon,fp16")]
42723#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42724pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
42725    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42726    unsafe { transmute(a) }
42727}
42728#[doc = "Vector reinterpret cast operation"]
42729#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
42730#[inline]
42731#[cfg(target_endian = "little")]
42732#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42733#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42734#[cfg_attr(
42735    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42736    assert_instr(nop)
42737)]
42738#[target_feature(enable = "neon,fp16")]
42739#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42740pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
42741    unsafe { transmute(a) }
42742}
42743#[doc = "Vector reinterpret cast operation"]
42744#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
42745#[inline]
42746#[cfg(target_endian = "big")]
42747#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42748#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42749#[cfg_attr(
42750    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42751    assert_instr(nop)
42752)]
42753#[target_feature(enable = "neon,fp16")]
42754#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42755pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
42756    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42757    unsafe {
42758        let ret_val: uint8x8_t = transmute(a);
42759        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42760    }
42761}
42762#[doc = "Vector reinterpret cast operation"]
42763#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
42764#[inline]
42765#[cfg(target_endian = "little")]
42766#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42767#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42768#[cfg_attr(
42769    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42770    assert_instr(nop)
42771)]
42772#[target_feature(enable = "neon,fp16")]
42773#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42774pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
42775    unsafe { transmute(a) }
42776}
42777#[doc = "Vector reinterpret cast operation"]
42778#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
42779#[inline]
42780#[cfg(target_endian = "big")]
42781#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42782#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42783#[cfg_attr(
42784    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42785    assert_instr(nop)
42786)]
42787#[target_feature(enable = "neon,fp16")]
42788#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42789pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
42790    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42791    unsafe {
42792        let ret_val: uint16x4_t = transmute(a);
42793        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42794    }
42795}
42796#[doc = "Vector reinterpret cast operation"]
42797#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
42798#[inline]
42799#[cfg(target_endian = "little")]
42800#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42801#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42802#[cfg_attr(
42803    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42804    assert_instr(nop)
42805)]
42806#[target_feature(enable = "neon,fp16")]
42807#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42808pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
42809    unsafe { transmute(a) }
42810}
42811#[doc = "Vector reinterpret cast operation"]
42812#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
42813#[inline]
42814#[cfg(target_endian = "big")]
42815#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42816#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42817#[cfg_attr(
42818    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42819    assert_instr(nop)
42820)]
42821#[target_feature(enable = "neon,fp16")]
42822#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42823pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
42824    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42825    unsafe {
42826        let ret_val: uint32x2_t = transmute(a);
42827        simd_shuffle!(ret_val, ret_val, [1, 0])
42828    }
42829}
42830#[doc = "Vector reinterpret cast operation"]
42831#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
42832#[inline]
42833#[cfg(target_endian = "little")]
42834#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42835#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42836#[cfg_attr(
42837    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42838    assert_instr(nop)
42839)]
42840#[target_feature(enable = "neon,fp16")]
42841#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42842pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
42843    unsafe { transmute(a) }
42844}
42845#[doc = "Vector reinterpret cast operation"]
42846#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
42847#[inline]
42848#[cfg(target_endian = "big")]
42849#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42850#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42851#[cfg_attr(
42852    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42853    assert_instr(nop)
42854)]
42855#[target_feature(enable = "neon,fp16")]
42856#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42857pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
42858    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42859    unsafe { transmute(a) }
42860}
42861#[doc = "Vector reinterpret cast operation"]
42862#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
42863#[inline]
42864#[cfg(target_endian = "little")]
42865#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42866#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42867#[cfg_attr(
42868    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42869    assert_instr(nop)
42870)]
42871#[target_feature(enable = "neon,fp16")]
42872#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42873pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
42874    unsafe { transmute(a) }
42875}
42876#[doc = "Vector reinterpret cast operation"]
42877#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
42878#[inline]
42879#[cfg(target_endian = "big")]
42880#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42881#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42882#[cfg_attr(
42883    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42884    assert_instr(nop)
42885)]
42886#[target_feature(enable = "neon,fp16")]
42887#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42888pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
42889    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42890    unsafe {
42891        let ret_val: poly8x8_t = transmute(a);
42892        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42893    }
42894}
42895#[doc = "Vector reinterpret cast operation"]
42896#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
42897#[inline]
42898#[cfg(target_endian = "little")]
42899#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42900#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42901#[cfg_attr(
42902    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42903    assert_instr(nop)
42904)]
42905#[target_feature(enable = "neon,fp16")]
42906#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42907pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
42908    unsafe { transmute(a) }
42909}
42910#[doc = "Vector reinterpret cast operation"]
42911#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
42912#[inline]
42913#[cfg(target_endian = "big")]
42914#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42915#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42916#[cfg_attr(
42917    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42918    assert_instr(nop)
42919)]
42920#[target_feature(enable = "neon,fp16")]
42921#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42922pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
42923    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42924    unsafe {
42925        let ret_val: poly16x4_t = transmute(a);
42926        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42927    }
42928}
42929#[doc = "Vector reinterpret cast operation"]
42930#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
42931#[inline]
42932#[cfg(target_endian = "little")]
42933#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42934#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42935#[cfg_attr(
42936    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42937    assert_instr(nop)
42938)]
42939#[target_feature(enable = "neon,fp16")]
42940#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42941pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
42942    unsafe { transmute(a) }
42943}
42944#[doc = "Vector reinterpret cast operation"]
42945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
42946#[inline]
42947#[cfg(target_endian = "big")]
42948#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42949#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42950#[cfg_attr(
42951    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42952    assert_instr(nop)
42953)]
42954#[target_feature(enable = "neon,fp16")]
42955#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42956pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
42957    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
42958    unsafe {
42959        let ret_val: float32x4_t = transmute(a);
42960        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42961    }
42962}
42963#[doc = "Vector reinterpret cast operation"]
42964#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
42965#[inline]
42966#[cfg(target_endian = "little")]
42967#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42968#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42969#[cfg_attr(
42970    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42971    assert_instr(nop)
42972)]
42973#[target_feature(enable = "neon,fp16")]
42974#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42975pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
42976    unsafe { transmute(a) }
42977}
42978#[doc = "Vector reinterpret cast operation"]
42979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
42980#[inline]
42981#[cfg(target_endian = "big")]
42982#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42983#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42984#[cfg_attr(
42985    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42986    assert_instr(nop)
42987)]
42988#[target_feature(enable = "neon,fp16")]
42989#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42990pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
42991    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
42992    unsafe {
42993        let ret_val: int8x16_t = transmute(a);
42994        simd_shuffle!(
42995            ret_val,
42996            ret_val,
42997            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
42998        )
42999    }
43000}
43001#[doc = "Vector reinterpret cast operation"]
43002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
43003#[inline]
43004#[cfg(target_endian = "little")]
43005#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43006#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43007#[cfg_attr(
43008    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43009    assert_instr(nop)
43010)]
43011#[target_feature(enable = "neon,fp16")]
43012#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43013pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
43014    unsafe { transmute(a) }
43015}
43016#[doc = "Vector reinterpret cast operation"]
43017#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
43018#[inline]
43019#[cfg(target_endian = "big")]
43020#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43021#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43022#[cfg_attr(
43023    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43024    assert_instr(nop)
43025)]
43026#[target_feature(enable = "neon,fp16")]
43027#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43028pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
43029    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43030    unsafe {
43031        let ret_val: int16x8_t = transmute(a);
43032        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43033    }
43034}
43035#[doc = "Vector reinterpret cast operation"]
43036#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
43037#[inline]
43038#[cfg(target_endian = "little")]
43039#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43040#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43041#[cfg_attr(
43042    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43043    assert_instr(nop)
43044)]
43045#[target_feature(enable = "neon,fp16")]
43046#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43047pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
43048    unsafe { transmute(a) }
43049}
43050#[doc = "Vector reinterpret cast operation"]
43051#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
43052#[inline]
43053#[cfg(target_endian = "big")]
43054#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43055#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43056#[cfg_attr(
43057    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43058    assert_instr(nop)
43059)]
43060#[target_feature(enable = "neon,fp16")]
43061#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43062pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
43063    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43064    unsafe {
43065        let ret_val: int32x4_t = transmute(a);
43066        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43067    }
43068}
43069#[doc = "Vector reinterpret cast operation"]
43070#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
43071#[inline]
43072#[cfg(target_endian = "little")]
43073#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43074#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43075#[cfg_attr(
43076    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43077    assert_instr(nop)
43078)]
43079#[target_feature(enable = "neon,fp16")]
43080#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43081pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
43082    unsafe { transmute(a) }
43083}
43084#[doc = "Vector reinterpret cast operation"]
43085#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
43086#[inline]
43087#[cfg(target_endian = "big")]
43088#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43089#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43090#[cfg_attr(
43091    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43092    assert_instr(nop)
43093)]
43094#[target_feature(enable = "neon,fp16")]
43095#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43096pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
43097    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43098    unsafe {
43099        let ret_val: int64x2_t = transmute(a);
43100        simd_shuffle!(ret_val, ret_val, [1, 0])
43101    }
43102}
43103#[doc = "Vector reinterpret cast operation"]
43104#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
43105#[inline]
43106#[cfg(target_endian = "little")]
43107#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43108#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43109#[cfg_attr(
43110    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43111    assert_instr(nop)
43112)]
43113#[target_feature(enable = "neon,fp16")]
43114#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43115pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
43116    unsafe { transmute(a) }
43117}
43118#[doc = "Vector reinterpret cast operation"]
43119#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
43120#[inline]
43121#[cfg(target_endian = "big")]
43122#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43123#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43124#[cfg_attr(
43125    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43126    assert_instr(nop)
43127)]
43128#[target_feature(enable = "neon,fp16")]
43129#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43130pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
43131    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43132    unsafe {
43133        let ret_val: uint8x16_t = transmute(a);
43134        simd_shuffle!(
43135            ret_val,
43136            ret_val,
43137            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
43138        )
43139    }
43140}
43141#[doc = "Vector reinterpret cast operation"]
43142#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
43143#[inline]
43144#[cfg(target_endian = "little")]
43145#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43146#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43147#[cfg_attr(
43148    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43149    assert_instr(nop)
43150)]
43151#[target_feature(enable = "neon,fp16")]
43152#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43153pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
43154    unsafe { transmute(a) }
43155}
43156#[doc = "Vector reinterpret cast operation"]
43157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
43158#[inline]
43159#[cfg(target_endian = "big")]
43160#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43161#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43162#[cfg_attr(
43163    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43164    assert_instr(nop)
43165)]
43166#[target_feature(enable = "neon,fp16")]
43167#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43168pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
43169    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43170    unsafe {
43171        let ret_val: uint16x8_t = transmute(a);
43172        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43173    }
43174}
43175#[doc = "Vector reinterpret cast operation"]
43176#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
43177#[inline]
43178#[cfg(target_endian = "little")]
43179#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43180#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43181#[cfg_attr(
43182    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43183    assert_instr(nop)
43184)]
43185#[target_feature(enable = "neon,fp16")]
43186#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43187pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
43188    unsafe { transmute(a) }
43189}
43190#[doc = "Vector reinterpret cast operation"]
43191#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
43192#[inline]
43193#[cfg(target_endian = "big")]
43194#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43195#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43196#[cfg_attr(
43197    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43198    assert_instr(nop)
43199)]
43200#[target_feature(enable = "neon,fp16")]
43201#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43202pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
43203    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43204    unsafe {
43205        let ret_val: uint32x4_t = transmute(a);
43206        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43207    }
43208}
43209#[doc = "Vector reinterpret cast operation"]
43210#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
43211#[inline]
43212#[cfg(target_endian = "little")]
43213#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43214#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43215#[cfg_attr(
43216    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43217    assert_instr(nop)
43218)]
43219#[target_feature(enable = "neon,fp16")]
43220#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43221pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
43222    unsafe { transmute(a) }
43223}
43224#[doc = "Vector reinterpret cast operation"]
43225#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
43226#[inline]
43227#[cfg(target_endian = "big")]
43228#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43229#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43230#[cfg_attr(
43231    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43232    assert_instr(nop)
43233)]
43234#[target_feature(enable = "neon,fp16")]
43235#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43236pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
43237    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43238    unsafe {
43239        let ret_val: uint64x2_t = transmute(a);
43240        simd_shuffle!(ret_val, ret_val, [1, 0])
43241    }
43242}
43243#[doc = "Vector reinterpret cast operation"]
43244#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
43245#[inline]
43246#[cfg(target_endian = "little")]
43247#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43248#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43249#[cfg_attr(
43250    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43251    assert_instr(nop)
43252)]
43253#[target_feature(enable = "neon,fp16")]
43254#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43255pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
43256    unsafe { transmute(a) }
43257}
43258#[doc = "Vector reinterpret cast operation"]
43259#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
43260#[inline]
43261#[cfg(target_endian = "big")]
43262#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43263#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43264#[cfg_attr(
43265    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43266    assert_instr(nop)
43267)]
43268#[target_feature(enable = "neon,fp16")]
43269#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43270pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
43271    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43272    unsafe {
43273        let ret_val: poly8x16_t = transmute(a);
43274        simd_shuffle!(
43275            ret_val,
43276            ret_val,
43277            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
43278        )
43279    }
43280}
43281#[doc = "Vector reinterpret cast operation"]
43282#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
43283#[inline]
43284#[cfg(target_endian = "little")]
43285#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43286#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43287#[cfg_attr(
43288    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43289    assert_instr(nop)
43290)]
43291#[target_feature(enable = "neon,fp16")]
43292#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43293pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
43294    unsafe { transmute(a) }
43295}
43296#[doc = "Vector reinterpret cast operation"]
43297#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
43298#[inline]
43299#[cfg(target_endian = "big")]
43300#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43301#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43302#[cfg_attr(
43303    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43304    assert_instr(nop)
43305)]
43306#[target_feature(enable = "neon,fp16")]
43307#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43308pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
43309    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43310    unsafe {
43311        let ret_val: poly16x8_t = transmute(a);
43312        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43313    }
43314}
43315#[doc = "Vector reinterpret cast operation"]
43316#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
43317#[inline]
43318#[cfg(target_endian = "little")]
43319#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43320#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43321#[cfg_attr(
43322    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43323    assert_instr(nop)
43324)]
43325#[target_feature(enable = "neon,fp16")]
43326#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43327pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
43328    unsafe { transmute(a) }
43329}
43330#[doc = "Vector reinterpret cast operation"]
43331#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
43332#[inline]
43333#[cfg(target_endian = "big")]
43334#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43335#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43336#[cfg_attr(
43337    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43338    assert_instr(nop)
43339)]
43340#[target_feature(enable = "neon,fp16")]
43341#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43342pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
43343    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
43344    unsafe {
43345        let ret_val: float16x4_t = transmute(a);
43346        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43347    }
43348}
43349#[doc = "Vector reinterpret cast operation"]
43350#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
43351#[inline]
43352#[cfg(target_endian = "little")]
43353#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43354#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43355#[cfg_attr(
43356    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43357    assert_instr(nop)
43358)]
43359#[target_feature(enable = "neon,fp16")]
43360#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43361pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
43362    unsafe { transmute(a) }
43363}
43364#[doc = "Vector reinterpret cast operation"]
43365#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
43366#[inline]
43367#[cfg(target_endian = "big")]
43368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43369#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43370#[cfg_attr(
43371    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43372    assert_instr(nop)
43373)]
43374#[target_feature(enable = "neon,fp16")]
43375#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43376pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
43377    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43378    unsafe {
43379        let ret_val: float16x8_t = transmute(a);
43380        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43381    }
43382}
43383#[doc = "Vector reinterpret cast operation"]
43384#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
43385#[inline]
43386#[cfg(target_endian = "little")]
43387#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43388#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43389#[cfg_attr(
43390    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43391    assert_instr(nop)
43392)]
43393#[target_feature(enable = "neon,fp16")]
43394#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43395pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
43396    unsafe { transmute(a) }
43397}
43398#[doc = "Vector reinterpret cast operation"]
43399#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
43400#[inline]
43401#[cfg(target_endian = "big")]
43402#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43403#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43404#[cfg_attr(
43405    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43406    assert_instr(nop)
43407)]
43408#[target_feature(enable = "neon,fp16")]
43409#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43410pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
43411    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43412    unsafe {
43413        let ret_val: float16x4_t = transmute(a);
43414        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43415    }
43416}
43417#[doc = "Vector reinterpret cast operation"]
43418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
43419#[inline]
43420#[cfg(target_endian = "little")]
43421#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43422#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43423#[cfg_attr(
43424    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43425    assert_instr(nop)
43426)]
43427#[target_feature(enable = "neon,fp16")]
43428#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43429pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
43430    unsafe { transmute(a) }
43431}
43432#[doc = "Vector reinterpret cast operation"]
43433#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
43434#[inline]
43435#[cfg(target_endian = "big")]
43436#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43437#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43438#[cfg_attr(
43439    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43440    assert_instr(nop)
43441)]
43442#[target_feature(enable = "neon,fp16")]
43443#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43444pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
43445    let a: int8x16_t =
43446        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
43447    unsafe {
43448        let ret_val: float16x8_t = transmute(a);
43449        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43450    }
43451}
43452#[doc = "Vector reinterpret cast operation"]
43453#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
43454#[inline]
43455#[cfg(target_endian = "little")]
43456#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43457#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43458#[cfg_attr(
43459    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43460    assert_instr(nop)
43461)]
43462#[target_feature(enable = "neon,fp16")]
43463#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43464pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
43465    unsafe { transmute(a) }
43466}
43467#[doc = "Vector reinterpret cast operation"]
43468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
43469#[inline]
43470#[cfg(target_endian = "big")]
43471#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43472#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43473#[cfg_attr(
43474    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43475    assert_instr(nop)
43476)]
43477#[target_feature(enable = "neon,fp16")]
43478#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43479pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
43480    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43481    unsafe {
43482        let ret_val: float16x4_t = transmute(a);
43483        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43484    }
43485}
43486#[doc = "Vector reinterpret cast operation"]
43487#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
43488#[inline]
43489#[cfg(target_endian = "little")]
43490#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43491#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43492#[cfg_attr(
43493    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43494    assert_instr(nop)
43495)]
43496#[target_feature(enable = "neon,fp16")]
43497#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43498pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
43499    unsafe { transmute(a) }
43500}
43501#[doc = "Vector reinterpret cast operation"]
43502#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
43503#[inline]
43504#[cfg(target_endian = "big")]
43505#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43506#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43507#[cfg_attr(
43508    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43509    assert_instr(nop)
43510)]
43511#[target_feature(enable = "neon,fp16")]
43512#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43513pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
43514    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43515    unsafe {
43516        let ret_val: float16x8_t = transmute(a);
43517        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43518    }
43519}
43520#[doc = "Vector reinterpret cast operation"]
43521#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
43522#[inline]
43523#[cfg(target_endian = "little")]
43524#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43525#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43526#[cfg_attr(
43527    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43528    assert_instr(nop)
43529)]
43530#[target_feature(enable = "neon,fp16")]
43531#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43532pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
43533    unsafe { transmute(a) }
43534}
43535#[doc = "Vector reinterpret cast operation"]
43536#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
43537#[inline]
43538#[cfg(target_endian = "big")]
43539#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43540#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43541#[cfg_attr(
43542    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43543    assert_instr(nop)
43544)]
43545#[target_feature(enable = "neon,fp16")]
43546#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43547pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
43548    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
43549    unsafe {
43550        let ret_val: float16x4_t = transmute(a);
43551        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43552    }
43553}
43554#[doc = "Vector reinterpret cast operation"]
43555#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
43556#[inline]
43557#[cfg(target_endian = "little")]
43558#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43559#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43560#[cfg_attr(
43561    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43562    assert_instr(nop)
43563)]
43564#[target_feature(enable = "neon,fp16")]
43565#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43566pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
43567    unsafe { transmute(a) }
43568}
43569#[doc = "Vector reinterpret cast operation"]
43570#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
43571#[inline]
43572#[cfg(target_endian = "big")]
43573#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43574#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43575#[cfg_attr(
43576    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43577    assert_instr(nop)
43578)]
43579#[target_feature(enable = "neon,fp16")]
43580#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43581pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
43582    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43583    unsafe {
43584        let ret_val: float16x8_t = transmute(a);
43585        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43586    }
43587}
43588#[doc = "Vector reinterpret cast operation"]
43589#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
43590#[inline]
43591#[cfg(target_endian = "little")]
43592#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43593#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43594#[cfg_attr(
43595    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43596    assert_instr(nop)
43597)]
43598#[target_feature(enable = "neon,fp16")]
43599#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43600pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
43601    unsafe { transmute(a) }
43602}
43603#[doc = "Vector reinterpret cast operation"]
43604#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
43605#[inline]
43606#[cfg(target_endian = "big")]
43607#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43608#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43609#[cfg_attr(
43610    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43611    assert_instr(nop)
43612)]
43613#[target_feature(enable = "neon,fp16")]
43614#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43615pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
43616    unsafe {
43617        let ret_val: float16x4_t = transmute(a);
43618        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43619    }
43620}
43621#[doc = "Vector reinterpret cast operation"]
43622#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
43623#[inline]
43624#[cfg(target_endian = "little")]
43625#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43626#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43627#[cfg_attr(
43628    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43629    assert_instr(nop)
43630)]
43631#[target_feature(enable = "neon,fp16")]
43632#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43633pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
43634    unsafe { transmute(a) }
43635}
43636#[doc = "Vector reinterpret cast operation"]
43637#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
43638#[inline]
43639#[cfg(target_endian = "big")]
43640#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43641#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43642#[cfg_attr(
43643    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43644    assert_instr(nop)
43645)]
43646#[target_feature(enable = "neon,fp16")]
43647#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43648pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
43649    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
43650    unsafe {
43651        let ret_val: float16x8_t = transmute(a);
43652        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43653    }
43654}
43655#[doc = "Vector reinterpret cast operation"]
43656#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
43657#[inline]
43658#[cfg(target_endian = "little")]
43659#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43660#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43661#[cfg_attr(
43662    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43663    assert_instr(nop)
43664)]
43665#[target_feature(enable = "neon,fp16")]
43666#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43667pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
43668    unsafe { transmute(a) }
43669}
43670#[doc = "Vector reinterpret cast operation"]
43671#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
43672#[inline]
43673#[cfg(target_endian = "big")]
43674#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43675#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43676#[cfg_attr(
43677    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43678    assert_instr(nop)
43679)]
43680#[target_feature(enable = "neon,fp16")]
43681#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43682pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
43683    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43684    unsafe {
43685        let ret_val: float16x4_t = transmute(a);
43686        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43687    }
43688}
43689#[doc = "Vector reinterpret cast operation"]
43690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
43691#[inline]
43692#[cfg(target_endian = "little")]
43693#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43694#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43695#[cfg_attr(
43696    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43697    assert_instr(nop)
43698)]
43699#[target_feature(enable = "neon,fp16")]
43700#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43701pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
43702    unsafe { transmute(a) }
43703}
43704#[doc = "Vector reinterpret cast operation"]
43705#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
43706#[inline]
43707#[cfg(target_endian = "big")]
43708#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43709#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43710#[cfg_attr(
43711    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43712    assert_instr(nop)
43713)]
43714#[target_feature(enable = "neon,fp16")]
43715#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43716pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
43717    let a: uint8x16_t =
43718        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
43719    unsafe {
43720        let ret_val: float16x8_t = transmute(a);
43721        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43722    }
43723}
43724#[doc = "Vector reinterpret cast operation"]
43725#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
43726#[inline]
43727#[cfg(target_endian = "little")]
43728#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43729#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43730#[cfg_attr(
43731    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43732    assert_instr(nop)
43733)]
43734#[target_feature(enable = "neon,fp16")]
43735#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43736pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
43737    unsafe { transmute(a) }
43738}
43739#[doc = "Vector reinterpret cast operation"]
43740#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
43741#[inline]
43742#[cfg(target_endian = "big")]
43743#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43744#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43745#[cfg_attr(
43746    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43747    assert_instr(nop)
43748)]
43749#[target_feature(enable = "neon,fp16")]
43750#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43751pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
43752    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43753    unsafe {
43754        let ret_val: float16x4_t = transmute(a);
43755        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43756    }
43757}
43758#[doc = "Vector reinterpret cast operation"]
43759#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
43760#[inline]
43761#[cfg(target_endian = "little")]
43762#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43763#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43764#[cfg_attr(
43765    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43766    assert_instr(nop)
43767)]
43768#[target_feature(enable = "neon,fp16")]
43769#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43770pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
43771    unsafe { transmute(a) }
43772}
43773#[doc = "Vector reinterpret cast operation"]
43774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
43775#[inline]
43776#[cfg(target_endian = "big")]
43777#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43778#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43779#[cfg_attr(
43780    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43781    assert_instr(nop)
43782)]
43783#[target_feature(enable = "neon,fp16")]
43784#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43785pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
43786    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43787    unsafe {
43788        let ret_val: float16x8_t = transmute(a);
43789        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43790    }
43791}
43792#[doc = "Vector reinterpret cast operation"]
43793#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
43794#[inline]
43795#[cfg(target_endian = "little")]
43796#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43797#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43798#[cfg_attr(
43799    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43800    assert_instr(nop)
43801)]
43802#[target_feature(enable = "neon,fp16")]
43803#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43804pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
43805    unsafe { transmute(a) }
43806}
43807#[doc = "Vector reinterpret cast operation"]
43808#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
43809#[inline]
43810#[cfg(target_endian = "big")]
43811#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43812#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43813#[cfg_attr(
43814    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43815    assert_instr(nop)
43816)]
43817#[target_feature(enable = "neon,fp16")]
43818#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43819pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
43820    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
43821    unsafe {
43822        let ret_val: float16x4_t = transmute(a);
43823        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43824    }
43825}
43826#[doc = "Vector reinterpret cast operation"]
43827#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
43828#[inline]
43829#[cfg(target_endian = "little")]
43830#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43831#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43832#[cfg_attr(
43833    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43834    assert_instr(nop)
43835)]
43836#[target_feature(enable = "neon,fp16")]
43837#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43838pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
43839    unsafe { transmute(a) }
43840}
43841#[doc = "Vector reinterpret cast operation"]
43842#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
43843#[inline]
43844#[cfg(target_endian = "big")]
43845#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43846#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43847#[cfg_attr(
43848    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43849    assert_instr(nop)
43850)]
43851#[target_feature(enable = "neon,fp16")]
43852#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43853pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
43854    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43855    unsafe {
43856        let ret_val: float16x8_t = transmute(a);
43857        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43858    }
43859}
43860#[doc = "Vector reinterpret cast operation"]
43861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
43862#[inline]
43863#[cfg(target_endian = "little")]
43864#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43865#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43866#[cfg_attr(
43867    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43868    assert_instr(nop)
43869)]
43870#[target_feature(enable = "neon,fp16")]
43871#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43872pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
43873    unsafe { transmute(a) }
43874}
43875#[doc = "Vector reinterpret cast operation"]
43876#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
43877#[inline]
43878#[cfg(target_endian = "big")]
43879#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43880#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43881#[cfg_attr(
43882    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43883    assert_instr(nop)
43884)]
43885#[target_feature(enable = "neon,fp16")]
43886#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43887pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
43888    unsafe {
43889        let ret_val: float16x4_t = transmute(a);
43890        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43891    }
43892}
43893#[doc = "Vector reinterpret cast operation"]
43894#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
43895#[inline]
43896#[cfg(target_endian = "little")]
43897#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43898#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43899#[cfg_attr(
43900    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43901    assert_instr(nop)
43902)]
43903#[target_feature(enable = "neon,fp16")]
43904#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43905pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
43906    unsafe { transmute(a) }
43907}
43908#[doc = "Vector reinterpret cast operation"]
43909#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
43910#[inline]
43911#[cfg(target_endian = "big")]
43912#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43913#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43914#[cfg_attr(
43915    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43916    assert_instr(nop)
43917)]
43918#[target_feature(enable = "neon,fp16")]
43919#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43920pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
43921    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
43922    unsafe {
43923        let ret_val: float16x8_t = transmute(a);
43924        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43925    }
43926}
43927#[doc = "Vector reinterpret cast operation"]
43928#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
43929#[inline]
43930#[cfg(target_endian = "little")]
43931#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43932#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43933#[cfg_attr(
43934    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43935    assert_instr(nop)
43936)]
43937#[target_feature(enable = "neon,fp16")]
43938#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43939pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
43940    unsafe { transmute(a) }
43941}
43942#[doc = "Vector reinterpret cast operation"]
43943#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
43944#[inline]
43945#[cfg(target_endian = "big")]
43946#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43947#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43948#[cfg_attr(
43949    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43950    assert_instr(nop)
43951)]
43952#[target_feature(enable = "neon,fp16")]
43953#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43954pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
43955    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43956    unsafe {
43957        let ret_val: float16x4_t = transmute(a);
43958        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43959    }
43960}
43961#[doc = "Vector reinterpret cast operation"]
43962#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
43963#[inline]
43964#[cfg(target_endian = "little")]
43965#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43966#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43967#[cfg_attr(
43968    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43969    assert_instr(nop)
43970)]
43971#[target_feature(enable = "neon,fp16")]
43972#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43973pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
43974    unsafe { transmute(a) }
43975}
43976#[doc = "Vector reinterpret cast operation"]
43977#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
43978#[inline]
43979#[cfg(target_endian = "big")]
43980#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43981#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43982#[cfg_attr(
43983    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43984    assert_instr(nop)
43985)]
43986#[target_feature(enable = "neon,fp16")]
43987#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43988pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
43989    let a: poly8x16_t =
43990        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
43991    unsafe {
43992        let ret_val: float16x8_t = transmute(a);
43993        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43994    }
43995}
43996#[doc = "Vector reinterpret cast operation"]
43997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
43998#[inline]
43999#[cfg(target_endian = "little")]
44000#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44001#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44002#[cfg_attr(
44003    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44004    assert_instr(nop)
44005)]
44006#[target_feature(enable = "neon,fp16")]
44007#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44008pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
44009    unsafe { transmute(a) }
44010}
44011#[doc = "Vector reinterpret cast operation"]
44012#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
44013#[inline]
44014#[cfg(target_endian = "big")]
44015#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44016#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44017#[cfg_attr(
44018    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44019    assert_instr(nop)
44020)]
44021#[target_feature(enable = "neon,fp16")]
44022#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44023pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
44024    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44025    unsafe {
44026        let ret_val: float16x4_t = transmute(a);
44027        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44028    }
44029}
44030#[doc = "Vector reinterpret cast operation"]
44031#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
44032#[inline]
44033#[cfg(target_endian = "little")]
44034#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44035#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44036#[cfg_attr(
44037    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44038    assert_instr(nop)
44039)]
44040#[target_feature(enable = "neon,fp16")]
44041#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44042pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
44043    unsafe { transmute(a) }
44044}
44045#[doc = "Vector reinterpret cast operation"]
44046#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
44047#[inline]
44048#[cfg(target_endian = "big")]
44049#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44050#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44051#[cfg_attr(
44052    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44053    assert_instr(nop)
44054)]
44055#[target_feature(enable = "neon,fp16")]
44056#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44057pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
44058    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
44059    unsafe {
44060        let ret_val: float16x8_t = transmute(a);
44061        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44062    }
44063}
44064#[doc = "Vector reinterpret cast operation"]
44065#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
44066#[inline]
44067#[cfg(target_endian = "little")]
44068#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44069#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44070#[cfg_attr(
44071    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44072    assert_instr(nop)
44073)]
44074#[target_feature(enable = "neon,fp16")]
44075#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44076pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
44077    unsafe { transmute(a) }
44078}
44079#[doc = "Vector reinterpret cast operation"]
44080#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
44081#[inline]
44082#[cfg(target_endian = "big")]
44083#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44084#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44085#[cfg_attr(
44086    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44087    assert_instr(nop)
44088)]
44089#[target_feature(enable = "neon,fp16")]
44090#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44091pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
44092    unsafe {
44093        let ret_val: float16x8_t = transmute(a);
44094        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44095    }
44096}
44097#[doc = "Vector reinterpret cast operation"]
44098#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
44099#[inline]
44100#[cfg(target_endian = "little")]
44101#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44102#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44103#[cfg_attr(
44104    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44105    assert_instr(nop)
44106)]
44107#[target_feature(enable = "neon,fp16")]
44108#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44109pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
44110    unsafe { transmute(a) }
44111}
44112#[doc = "Vector reinterpret cast operation"]
44113#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
44114#[inline]
44115#[cfg(target_endian = "big")]
44116#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44117#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44118#[cfg_attr(
44119    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44120    assert_instr(nop)
44121)]
44122#[target_feature(enable = "neon,fp16")]
44123#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44124pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
44125    let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44126    unsafe { transmute(a) }
44127}
44128#[doc = "Vector reinterpret cast operation"]
44129#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
44130#[inline]
44131#[cfg(target_endian = "little")]
44132#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44133#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44134#[cfg_attr(
44135    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44136    assert_instr(nop)
44137)]
44138#[target_feature(enable = "neon,fp16")]
44139#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44140pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
44141    unsafe { transmute(a) }
44142}
44143#[doc = "Vector reinterpret cast operation"]
44144#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
44145#[inline]
44146#[cfg(target_endian = "big")]
44147#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44148#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44149#[cfg_attr(
44150    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44151    assert_instr(nop)
44152)]
44153#[target_feature(enable = "neon,fp16")]
44154#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44155pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
44156    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
44157    unsafe { transmute(a) }
44158}
44159#[doc = "Vector reinterpret cast operation"]
44160#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
44161#[inline]
44162#[cfg(target_endian = "little")]
44163#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44164#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44165#[cfg_attr(
44166    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44167    assert_instr(nop)
44168)]
44169#[target_feature(enable = "neon,fp16")]
44170#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44171pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
44172    unsafe { transmute(a) }
44173}
44174#[doc = "Vector reinterpret cast operation"]
44175#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
44176#[inline]
44177#[cfg(target_endian = "big")]
44178#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44179#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44180#[cfg_attr(
44181    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44182    assert_instr(nop)
44183)]
44184#[target_feature(enable = "neon,fp16")]
44185#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44186pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
44187    let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
44188    unsafe {
44189        let ret_val: poly64x2_t = transmute(a);
44190        simd_shuffle!(ret_val, ret_val, [1, 0])
44191    }
44192}
44193#[doc = "Vector reinterpret cast operation"]
44194#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
44195#[inline]
44196#[cfg(target_endian = "little")]
44197#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44198#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44199#[cfg_attr(
44200    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44201    assert_instr(nop)
44202)]
44203#[target_feature(enable = "neon,fp16")]
44204#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44205pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
44206    unsafe { transmute(a) }
44207}
44208#[doc = "Vector reinterpret cast operation"]
44209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
44210#[inline]
44211#[cfg(target_endian = "big")]
44212#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44213#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44214#[cfg_attr(
44215    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44216    assert_instr(nop)
44217)]
44218#[target_feature(enable = "neon,fp16")]
44219#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44220pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
44221    unsafe {
44222        let ret_val: float16x4_t = transmute(a);
44223        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44224    }
44225}
44226#[doc = "Vector reinterpret cast operation"]
44227#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
44228#[inline]
44229#[cfg(target_endian = "little")]
44230#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44231#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44232#[cfg_attr(
44233    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44234    assert_instr(nop)
44235)]
44236#[target_feature(enable = "neon,fp16")]
44237#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44238pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
44239    unsafe { transmute(a) }
44240}
44241#[doc = "Vector reinterpret cast operation"]
44242#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
44243#[inline]
44244#[cfg(target_endian = "big")]
44245#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44246#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44247#[cfg_attr(
44248    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44249    assert_instr(nop)
44250)]
44251#[target_feature(enable = "neon,fp16")]
44252#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44253pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
44254    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44255    unsafe {
44256        let ret_val: float16x8_t = transmute(a);
44257        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44258    }
44259}
44260#[doc = "Vector reinterpret cast operation"]
44261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"]
44262#[inline]
44263#[cfg(target_endian = "little")]
44264#[target_feature(enable = "neon")]
44265#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44266#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44267#[cfg_attr(
44268    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44269    assert_instr(nop)
44270)]
44271#[cfg_attr(
44272    not(target_arch = "arm"),
44273    stable(feature = "neon_intrinsics", since = "1.59.0")
44274)]
44275#[cfg_attr(
44276    target_arch = "arm",
44277    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44278)]
44279pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t {
44280    unsafe { transmute(a) }
44281}
44282#[doc = "Vector reinterpret cast operation"]
44283#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"]
44284#[inline]
44285#[cfg(target_endian = "big")]
44286#[target_feature(enable = "neon")]
44287#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44288#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44289#[cfg_attr(
44290    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44291    assert_instr(nop)
44292)]
44293#[cfg_attr(
44294    not(target_arch = "arm"),
44295    stable(feature = "neon_intrinsics", since = "1.59.0")
44296)]
44297#[cfg_attr(
44298    target_arch = "arm",
44299    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44300)]
44301pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t {
44302    unsafe {
44303        let ret_val: float32x4_t = transmute(a);
44304        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44305    }
44306}
44307#[doc = "Vector reinterpret cast operation"]
44308#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"]
44309#[inline]
44310#[cfg(target_endian = "little")]
44311#[target_feature(enable = "neon")]
44312#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44313#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44314#[cfg_attr(
44315    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44316    assert_instr(nop)
44317)]
44318#[cfg_attr(
44319    not(target_arch = "arm"),
44320    stable(feature = "neon_intrinsics", since = "1.59.0")
44321)]
44322#[cfg_attr(
44323    target_arch = "arm",
44324    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44325)]
44326pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
44327    unsafe { transmute(a) }
44328}
44329#[doc = "Vector reinterpret cast operation"]
44330#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"]
44331#[inline]
44332#[cfg(target_endian = "big")]
44333#[target_feature(enable = "neon")]
44334#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44335#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44336#[cfg_attr(
44337    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44338    assert_instr(nop)
44339)]
44340#[cfg_attr(
44341    not(target_arch = "arm"),
44342    stable(feature = "neon_intrinsics", since = "1.59.0")
44343)]
44344#[cfg_attr(
44345    target_arch = "arm",
44346    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44347)]
44348pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
44349    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44350    unsafe {
44351        let ret_val: int8x8_t = transmute(a);
44352        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44353    }
44354}
44355#[doc = "Vector reinterpret cast operation"]
44356#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"]
44357#[inline]
44358#[cfg(target_endian = "little")]
44359#[target_feature(enable = "neon")]
44360#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44361#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44362#[cfg_attr(
44363    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44364    assert_instr(nop)
44365)]
44366#[cfg_attr(
44367    not(target_arch = "arm"),
44368    stable(feature = "neon_intrinsics", since = "1.59.0")
44369)]
44370#[cfg_attr(
44371    target_arch = "arm",
44372    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44373)]
44374pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
44375    unsafe { transmute(a) }
44376}
44377#[doc = "Vector reinterpret cast operation"]
44378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"]
44379#[inline]
44380#[cfg(target_endian = "big")]
44381#[target_feature(enable = "neon")]
44382#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44383#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44384#[cfg_attr(
44385    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44386    assert_instr(nop)
44387)]
44388#[cfg_attr(
44389    not(target_arch = "arm"),
44390    stable(feature = "neon_intrinsics", since = "1.59.0")
44391)]
44392#[cfg_attr(
44393    target_arch = "arm",
44394    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44395)]
44396pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
44397    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44398    unsafe {
44399        let ret_val: int16x4_t = transmute(a);
44400        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44401    }
44402}
44403#[doc = "Vector reinterpret cast operation"]
44404#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"]
44405#[inline]
44406#[cfg(target_endian = "little")]
44407#[target_feature(enable = "neon")]
44408#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44409#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44410#[cfg_attr(
44411    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44412    assert_instr(nop)
44413)]
44414#[cfg_attr(
44415    not(target_arch = "arm"),
44416    stable(feature = "neon_intrinsics", since = "1.59.0")
44417)]
44418#[cfg_attr(
44419    target_arch = "arm",
44420    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44421)]
44422pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t {
44423    unsafe { transmute(a) }
44424}
44425#[doc = "Vector reinterpret cast operation"]
44426#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"]
44427#[inline]
44428#[cfg(target_endian = "big")]
44429#[target_feature(enable = "neon")]
44430#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44431#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44432#[cfg_attr(
44433    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44434    assert_instr(nop)
44435)]
44436#[cfg_attr(
44437    not(target_arch = "arm"),
44438    stable(feature = "neon_intrinsics", since = "1.59.0")
44439)]
44440#[cfg_attr(
44441    target_arch = "arm",
44442    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44443)]
44444pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t {
44445    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44446    unsafe {
44447        let ret_val: int32x2_t = transmute(a);
44448        simd_shuffle!(ret_val, ret_val, [1, 0])
44449    }
44450}
44451#[doc = "Vector reinterpret cast operation"]
44452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"]
44453#[inline]
44454#[cfg(target_endian = "little")]
44455#[target_feature(enable = "neon")]
44456#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44457#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44458#[cfg_attr(
44459    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44460    assert_instr(nop)
44461)]
44462#[cfg_attr(
44463    not(target_arch = "arm"),
44464    stable(feature = "neon_intrinsics", since = "1.59.0")
44465)]
44466#[cfg_attr(
44467    target_arch = "arm",
44468    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44469)]
44470pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
44471    unsafe { transmute(a) }
44472}
44473#[doc = "Vector reinterpret cast operation"]
44474#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"]
44475#[inline]
44476#[cfg(target_endian = "big")]
44477#[target_feature(enable = "neon")]
44478#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44479#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44480#[cfg_attr(
44481    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44482    assert_instr(nop)
44483)]
44484#[cfg_attr(
44485    not(target_arch = "arm"),
44486    stable(feature = "neon_intrinsics", since = "1.59.0")
44487)]
44488#[cfg_attr(
44489    target_arch = "arm",
44490    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44491)]
44492pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
44493    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44494    unsafe { transmute(a) }
44495}
44496#[doc = "Vector reinterpret cast operation"]
44497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"]
44498#[inline]
44499#[cfg(target_endian = "little")]
44500#[target_feature(enable = "neon")]
44501#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44502#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44503#[cfg_attr(
44504    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44505    assert_instr(nop)
44506)]
44507#[cfg_attr(
44508    not(target_arch = "arm"),
44509    stable(feature = "neon_intrinsics", since = "1.59.0")
44510)]
44511#[cfg_attr(
44512    target_arch = "arm",
44513    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44514)]
44515pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
44516    unsafe { transmute(a) }
44517}
44518#[doc = "Vector reinterpret cast operation"]
44519#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"]
44520#[inline]
44521#[cfg(target_endian = "big")]
44522#[target_feature(enable = "neon")]
44523#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44524#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44525#[cfg_attr(
44526    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44527    assert_instr(nop)
44528)]
44529#[cfg_attr(
44530    not(target_arch = "arm"),
44531    stable(feature = "neon_intrinsics", since = "1.59.0")
44532)]
44533#[cfg_attr(
44534    target_arch = "arm",
44535    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44536)]
44537pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
44538    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44539    unsafe {
44540        let ret_val: uint8x8_t = transmute(a);
44541        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44542    }
44543}
44544#[doc = "Vector reinterpret cast operation"]
44545#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"]
44546#[inline]
44547#[cfg(target_endian = "little")]
44548#[target_feature(enable = "neon")]
44549#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44550#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44551#[cfg_attr(
44552    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44553    assert_instr(nop)
44554)]
44555#[cfg_attr(
44556    not(target_arch = "arm"),
44557    stable(feature = "neon_intrinsics", since = "1.59.0")
44558)]
44559#[cfg_attr(
44560    target_arch = "arm",
44561    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44562)]
44563pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
44564    unsafe { transmute(a) }
44565}
44566#[doc = "Vector reinterpret cast operation"]
44567#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"]
44568#[inline]
44569#[cfg(target_endian = "big")]
44570#[target_feature(enable = "neon")]
44571#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44572#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44573#[cfg_attr(
44574    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44575    assert_instr(nop)
44576)]
44577#[cfg_attr(
44578    not(target_arch = "arm"),
44579    stable(feature = "neon_intrinsics", since = "1.59.0")
44580)]
44581#[cfg_attr(
44582    target_arch = "arm",
44583    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44584)]
44585pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
44586    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44587    unsafe {
44588        let ret_val: uint16x4_t = transmute(a);
44589        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44590    }
44591}
44592#[doc = "Vector reinterpret cast operation"]
44593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"]
44594#[inline]
44595#[cfg(target_endian = "little")]
44596#[target_feature(enable = "neon")]
44597#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44598#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44599#[cfg_attr(
44600    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44601    assert_instr(nop)
44602)]
44603#[cfg_attr(
44604    not(target_arch = "arm"),
44605    stable(feature = "neon_intrinsics", since = "1.59.0")
44606)]
44607#[cfg_attr(
44608    target_arch = "arm",
44609    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44610)]
44611pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t {
44612    unsafe { transmute(a) }
44613}
44614#[doc = "Vector reinterpret cast operation"]
44615#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"]
44616#[inline]
44617#[cfg(target_endian = "big")]
44618#[target_feature(enable = "neon")]
44619#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44620#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44621#[cfg_attr(
44622    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44623    assert_instr(nop)
44624)]
44625#[cfg_attr(
44626    not(target_arch = "arm"),
44627    stable(feature = "neon_intrinsics", since = "1.59.0")
44628)]
44629#[cfg_attr(
44630    target_arch = "arm",
44631    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44632)]
44633pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t {
44634    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44635    unsafe {
44636        let ret_val: uint32x2_t = transmute(a);
44637        simd_shuffle!(ret_val, ret_val, [1, 0])
44638    }
44639}
44640#[doc = "Vector reinterpret cast operation"]
44641#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"]
44642#[inline]
44643#[cfg(target_endian = "little")]
44644#[target_feature(enable = "neon")]
44645#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44646#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44647#[cfg_attr(
44648    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44649    assert_instr(nop)
44650)]
44651#[cfg_attr(
44652    not(target_arch = "arm"),
44653    stable(feature = "neon_intrinsics", since = "1.59.0")
44654)]
44655#[cfg_attr(
44656    target_arch = "arm",
44657    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44658)]
44659pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
44660    unsafe { transmute(a) }
44661}
44662#[doc = "Vector reinterpret cast operation"]
44663#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"]
44664#[inline]
44665#[cfg(target_endian = "big")]
44666#[target_feature(enable = "neon")]
44667#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44668#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44669#[cfg_attr(
44670    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44671    assert_instr(nop)
44672)]
44673#[cfg_attr(
44674    not(target_arch = "arm"),
44675    stable(feature = "neon_intrinsics", since = "1.59.0")
44676)]
44677#[cfg_attr(
44678    target_arch = "arm",
44679    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44680)]
44681pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
44682    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44683    unsafe { transmute(a) }
44684}
44685#[doc = "Vector reinterpret cast operation"]
44686#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"]
44687#[inline]
44688#[cfg(target_endian = "little")]
44689#[target_feature(enable = "neon")]
44690#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44691#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44692#[cfg_attr(
44693    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44694    assert_instr(nop)
44695)]
44696#[cfg_attr(
44697    not(target_arch = "arm"),
44698    stable(feature = "neon_intrinsics", since = "1.59.0")
44699)]
44700#[cfg_attr(
44701    target_arch = "arm",
44702    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44703)]
44704pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
44705    unsafe { transmute(a) }
44706}
44707#[doc = "Vector reinterpret cast operation"]
44708#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"]
44709#[inline]
44710#[cfg(target_endian = "big")]
44711#[target_feature(enable = "neon")]
44712#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44713#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44714#[cfg_attr(
44715    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44716    assert_instr(nop)
44717)]
44718#[cfg_attr(
44719    not(target_arch = "arm"),
44720    stable(feature = "neon_intrinsics", since = "1.59.0")
44721)]
44722#[cfg_attr(
44723    target_arch = "arm",
44724    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44725)]
44726pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
44727    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44728    unsafe {
44729        let ret_val: poly8x8_t = transmute(a);
44730        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44731    }
44732}
44733#[doc = "Vector reinterpret cast operation"]
44734#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"]
44735#[inline]
44736#[cfg(target_endian = "little")]
44737#[target_feature(enable = "neon")]
44738#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44739#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44740#[cfg_attr(
44741    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44742    assert_instr(nop)
44743)]
44744#[cfg_attr(
44745    not(target_arch = "arm"),
44746    stable(feature = "neon_intrinsics", since = "1.59.0")
44747)]
44748#[cfg_attr(
44749    target_arch = "arm",
44750    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44751)]
44752pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
44753    unsafe { transmute(a) }
44754}
44755#[doc = "Vector reinterpret cast operation"]
44756#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"]
44757#[inline]
44758#[cfg(target_endian = "big")]
44759#[target_feature(enable = "neon")]
44760#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44761#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44762#[cfg_attr(
44763    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44764    assert_instr(nop)
44765)]
44766#[cfg_attr(
44767    not(target_arch = "arm"),
44768    stable(feature = "neon_intrinsics", since = "1.59.0")
44769)]
44770#[cfg_attr(
44771    target_arch = "arm",
44772    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44773)]
44774pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
44775    let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44776    unsafe {
44777        let ret_val: poly16x4_t = transmute(a);
44778        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44779    }
44780}
44781#[doc = "Vector reinterpret cast operation"]
44782#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"]
44783#[inline]
44784#[cfg(target_endian = "little")]
44785#[target_feature(enable = "neon")]
44786#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44787#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44788#[cfg_attr(
44789    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44790    assert_instr(nop)
44791)]
44792#[cfg_attr(
44793    not(target_arch = "arm"),
44794    stable(feature = "neon_intrinsics", since = "1.59.0")
44795)]
44796#[cfg_attr(
44797    target_arch = "arm",
44798    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44799)]
44800pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
44801    unsafe { transmute(a) }
44802}
44803#[doc = "Vector reinterpret cast operation"]
44804#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"]
44805#[inline]
44806#[cfg(target_endian = "big")]
44807#[target_feature(enable = "neon")]
44808#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44809#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44810#[cfg_attr(
44811    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44812    assert_instr(nop)
44813)]
44814#[cfg_attr(
44815    not(target_arch = "arm"),
44816    stable(feature = "neon_intrinsics", since = "1.59.0")
44817)]
44818#[cfg_attr(
44819    target_arch = "arm",
44820    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44821)]
44822pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
44823    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44824    unsafe { transmute(a) }
44825}
44826#[doc = "Vector reinterpret cast operation"]
44827#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"]
44828#[inline]
44829#[cfg(target_endian = "little")]
44830#[target_feature(enable = "neon")]
44831#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44832#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44833#[cfg_attr(
44834    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44835    assert_instr(nop)
44836)]
44837#[cfg_attr(
44838    not(target_arch = "arm"),
44839    stable(feature = "neon_intrinsics", since = "1.59.0")
44840)]
44841#[cfg_attr(
44842    target_arch = "arm",
44843    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44844)]
44845pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
44846    unsafe { transmute(a) }
44847}
44848#[doc = "Vector reinterpret cast operation"]
44849#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"]
44850#[inline]
44851#[cfg(target_endian = "big")]
44852#[target_feature(enable = "neon")]
44853#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44854#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44855#[cfg_attr(
44856    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44857    assert_instr(nop)
44858)]
44859#[cfg_attr(
44860    not(target_arch = "arm"),
44861    stable(feature = "neon_intrinsics", since = "1.59.0")
44862)]
44863#[cfg_attr(
44864    target_arch = "arm",
44865    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44866)]
44867pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
44868    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44869    unsafe {
44870        let ret_val: int8x16_t = transmute(a);
44871        simd_shuffle!(
44872            ret_val,
44873            ret_val,
44874            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
44875        )
44876    }
44877}
44878#[doc = "Vector reinterpret cast operation"]
44879#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"]
44880#[inline]
44881#[cfg(target_endian = "little")]
44882#[target_feature(enable = "neon")]
44883#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44884#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44885#[cfg_attr(
44886    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44887    assert_instr(nop)
44888)]
44889#[cfg_attr(
44890    not(target_arch = "arm"),
44891    stable(feature = "neon_intrinsics", since = "1.59.0")
44892)]
44893#[cfg_attr(
44894    target_arch = "arm",
44895    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44896)]
44897pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
44898    unsafe { transmute(a) }
44899}
44900#[doc = "Vector reinterpret cast operation"]
44901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"]
44902#[inline]
44903#[cfg(target_endian = "big")]
44904#[target_feature(enable = "neon")]
44905#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44906#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44907#[cfg_attr(
44908    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44909    assert_instr(nop)
44910)]
44911#[cfg_attr(
44912    not(target_arch = "arm"),
44913    stable(feature = "neon_intrinsics", since = "1.59.0")
44914)]
44915#[cfg_attr(
44916    target_arch = "arm",
44917    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44918)]
44919pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
44920    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44921    unsafe {
44922        let ret_val: int16x8_t = transmute(a);
44923        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44924    }
44925}
44926#[doc = "Vector reinterpret cast operation"]
44927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"]
44928#[inline]
44929#[cfg(target_endian = "little")]
44930#[target_feature(enable = "neon")]
44931#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44932#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44933#[cfg_attr(
44934    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44935    assert_instr(nop)
44936)]
44937#[cfg_attr(
44938    not(target_arch = "arm"),
44939    stable(feature = "neon_intrinsics", since = "1.59.0")
44940)]
44941#[cfg_attr(
44942    target_arch = "arm",
44943    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44944)]
44945pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t {
44946    unsafe { transmute(a) }
44947}
44948#[doc = "Vector reinterpret cast operation"]
44949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"]
44950#[inline]
44951#[cfg(target_endian = "big")]
44952#[target_feature(enable = "neon")]
44953#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44954#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44955#[cfg_attr(
44956    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44957    assert_instr(nop)
44958)]
44959#[cfg_attr(
44960    not(target_arch = "arm"),
44961    stable(feature = "neon_intrinsics", since = "1.59.0")
44962)]
44963#[cfg_attr(
44964    target_arch = "arm",
44965    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44966)]
44967pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t {
44968    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44969    unsafe {
44970        let ret_val: int32x4_t = transmute(a);
44971        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44972    }
44973}
44974#[doc = "Vector reinterpret cast operation"]
44975#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"]
44976#[inline]
44977#[cfg(target_endian = "little")]
44978#[target_feature(enable = "neon")]
44979#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44980#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44981#[cfg_attr(
44982    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44983    assert_instr(nop)
44984)]
44985#[cfg_attr(
44986    not(target_arch = "arm"),
44987    stable(feature = "neon_intrinsics", since = "1.59.0")
44988)]
44989#[cfg_attr(
44990    target_arch = "arm",
44991    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44992)]
44993pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
44994    unsafe { transmute(a) }
44995}
44996#[doc = "Vector reinterpret cast operation"]
44997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"]
44998#[inline]
44999#[cfg(target_endian = "big")]
45000#[target_feature(enable = "neon")]
45001#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45002#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45003#[cfg_attr(
45004    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45005    assert_instr(nop)
45006)]
45007#[cfg_attr(
45008    not(target_arch = "arm"),
45009    stable(feature = "neon_intrinsics", since = "1.59.0")
45010)]
45011#[cfg_attr(
45012    target_arch = "arm",
45013    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45014)]
45015pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
45016    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45017    unsafe {
45018        let ret_val: int64x2_t = transmute(a);
45019        simd_shuffle!(ret_val, ret_val, [1, 0])
45020    }
45021}
45022#[doc = "Vector reinterpret cast operation"]
45023#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"]
45024#[inline]
45025#[cfg(target_endian = "little")]
45026#[target_feature(enable = "neon")]
45027#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45028#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45029#[cfg_attr(
45030    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45031    assert_instr(nop)
45032)]
45033#[cfg_attr(
45034    not(target_arch = "arm"),
45035    stable(feature = "neon_intrinsics", since = "1.59.0")
45036)]
45037#[cfg_attr(
45038    target_arch = "arm",
45039    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45040)]
45041pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
45042    unsafe { transmute(a) }
45043}
45044#[doc = "Vector reinterpret cast operation"]
45045#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"]
45046#[inline]
45047#[cfg(target_endian = "big")]
45048#[target_feature(enable = "neon")]
45049#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45050#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45051#[cfg_attr(
45052    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45053    assert_instr(nop)
45054)]
45055#[cfg_attr(
45056    not(target_arch = "arm"),
45057    stable(feature = "neon_intrinsics", since = "1.59.0")
45058)]
45059#[cfg_attr(
45060    target_arch = "arm",
45061    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45062)]
45063pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
45064    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45065    unsafe {
45066        let ret_val: uint8x16_t = transmute(a);
45067        simd_shuffle!(
45068            ret_val,
45069            ret_val,
45070            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
45071        )
45072    }
45073}
45074#[doc = "Vector reinterpret cast operation"]
45075#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"]
45076#[inline]
45077#[cfg(target_endian = "little")]
45078#[target_feature(enable = "neon")]
45079#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45080#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45081#[cfg_attr(
45082    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45083    assert_instr(nop)
45084)]
45085#[cfg_attr(
45086    not(target_arch = "arm"),
45087    stable(feature = "neon_intrinsics", since = "1.59.0")
45088)]
45089#[cfg_attr(
45090    target_arch = "arm",
45091    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45092)]
45093pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
45094    unsafe { transmute(a) }
45095}
45096#[doc = "Vector reinterpret cast operation"]
45097#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"]
45098#[inline]
45099#[cfg(target_endian = "big")]
45100#[target_feature(enable = "neon")]
45101#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45102#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45103#[cfg_attr(
45104    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45105    assert_instr(nop)
45106)]
45107#[cfg_attr(
45108    not(target_arch = "arm"),
45109    stable(feature = "neon_intrinsics", since = "1.59.0")
45110)]
45111#[cfg_attr(
45112    target_arch = "arm",
45113    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45114)]
45115pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
45116    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45117    unsafe {
45118        let ret_val: uint16x8_t = transmute(a);
45119        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45120    }
45121}
45122#[doc = "Vector reinterpret cast operation"]
45123#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"]
45124#[inline]
45125#[cfg(target_endian = "little")]
45126#[target_feature(enable = "neon")]
45127#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45128#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45129#[cfg_attr(
45130    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45131    assert_instr(nop)
45132)]
45133#[cfg_attr(
45134    not(target_arch = "arm"),
45135    stable(feature = "neon_intrinsics", since = "1.59.0")
45136)]
45137#[cfg_attr(
45138    target_arch = "arm",
45139    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45140)]
45141pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t {
45142    unsafe { transmute(a) }
45143}
45144#[doc = "Vector reinterpret cast operation"]
45145#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"]
45146#[inline]
45147#[cfg(target_endian = "big")]
45148#[target_feature(enable = "neon")]
45149#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45150#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45151#[cfg_attr(
45152    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45153    assert_instr(nop)
45154)]
45155#[cfg_attr(
45156    not(target_arch = "arm"),
45157    stable(feature = "neon_intrinsics", since = "1.59.0")
45158)]
45159#[cfg_attr(
45160    target_arch = "arm",
45161    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45162)]
45163pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t {
45164    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45165    unsafe {
45166        let ret_val: uint32x4_t = transmute(a);
45167        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45168    }
45169}
45170#[doc = "Vector reinterpret cast operation"]
45171#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"]
45172#[inline]
45173#[cfg(target_endian = "little")]
45174#[target_feature(enable = "neon")]
45175#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45176#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45177#[cfg_attr(
45178    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45179    assert_instr(nop)
45180)]
45181#[cfg_attr(
45182    not(target_arch = "arm"),
45183    stable(feature = "neon_intrinsics", since = "1.59.0")
45184)]
45185#[cfg_attr(
45186    target_arch = "arm",
45187    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45188)]
45189pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
45190    unsafe { transmute(a) }
45191}
45192#[doc = "Vector reinterpret cast operation"]
45193#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"]
45194#[inline]
45195#[cfg(target_endian = "big")]
45196#[target_feature(enable = "neon")]
45197#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45198#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45199#[cfg_attr(
45200    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45201    assert_instr(nop)
45202)]
45203#[cfg_attr(
45204    not(target_arch = "arm"),
45205    stable(feature = "neon_intrinsics", since = "1.59.0")
45206)]
45207#[cfg_attr(
45208    target_arch = "arm",
45209    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45210)]
45211pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
45212    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45213    unsafe {
45214        let ret_val: uint64x2_t = transmute(a);
45215        simd_shuffle!(ret_val, ret_val, [1, 0])
45216    }
45217}
45218#[doc = "Vector reinterpret cast operation"]
45219#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"]
45220#[inline]
45221#[cfg(target_endian = "little")]
45222#[target_feature(enable = "neon")]
45223#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45224#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45225#[cfg_attr(
45226    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45227    assert_instr(nop)
45228)]
45229#[cfg_attr(
45230    not(target_arch = "arm"),
45231    stable(feature = "neon_intrinsics", since = "1.59.0")
45232)]
45233#[cfg_attr(
45234    target_arch = "arm",
45235    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45236)]
45237pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
45238    unsafe { transmute(a) }
45239}
45240#[doc = "Vector reinterpret cast operation"]
45241#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"]
45242#[inline]
45243#[cfg(target_endian = "big")]
45244#[target_feature(enable = "neon")]
45245#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45246#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45247#[cfg_attr(
45248    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45249    assert_instr(nop)
45250)]
45251#[cfg_attr(
45252    not(target_arch = "arm"),
45253    stable(feature = "neon_intrinsics", since = "1.59.0")
45254)]
45255#[cfg_attr(
45256    target_arch = "arm",
45257    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45258)]
45259pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
45260    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45261    unsafe {
45262        let ret_val: poly8x16_t = transmute(a);
45263        simd_shuffle!(
45264            ret_val,
45265            ret_val,
45266            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
45267        )
45268    }
45269}
45270#[doc = "Vector reinterpret cast operation"]
45271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"]
45272#[inline]
45273#[cfg(target_endian = "little")]
45274#[target_feature(enable = "neon")]
45275#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45276#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45277#[cfg_attr(
45278    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45279    assert_instr(nop)
45280)]
45281#[cfg_attr(
45282    not(target_arch = "arm"),
45283    stable(feature = "neon_intrinsics", since = "1.59.0")
45284)]
45285#[cfg_attr(
45286    target_arch = "arm",
45287    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45288)]
45289pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
45290    unsafe { transmute(a) }
45291}
45292#[doc = "Vector reinterpret cast operation"]
45293#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"]
45294#[inline]
45295#[cfg(target_endian = "big")]
45296#[target_feature(enable = "neon")]
45297#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45298#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45299#[cfg_attr(
45300    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45301    assert_instr(nop)
45302)]
45303#[cfg_attr(
45304    not(target_arch = "arm"),
45305    stable(feature = "neon_intrinsics", since = "1.59.0")
45306)]
45307#[cfg_attr(
45308    target_arch = "arm",
45309    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45310)]
45311pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
45312    let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45313    unsafe {
45314        let ret_val: poly16x8_t = transmute(a);
45315        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45316    }
45317}
45318#[doc = "Vector reinterpret cast operation"]
45319#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"]
45320#[inline]
45321#[cfg(target_endian = "little")]
45322#[target_feature(enable = "neon")]
45323#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45324#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45325#[cfg_attr(
45326    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45327    assert_instr(nop)
45328)]
45329#[cfg_attr(
45330    not(target_arch = "arm"),
45331    stable(feature = "neon_intrinsics", since = "1.59.0")
45332)]
45333#[cfg_attr(
45334    target_arch = "arm",
45335    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45336)]
45337pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
45338    unsafe { transmute(a) }
45339}
45340#[doc = "Vector reinterpret cast operation"]
45341#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"]
45342#[inline]
45343#[cfg(target_endian = "big")]
45344#[target_feature(enable = "neon")]
45345#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45346#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45347#[cfg_attr(
45348    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45349    assert_instr(nop)
45350)]
45351#[cfg_attr(
45352    not(target_arch = "arm"),
45353    stable(feature = "neon_intrinsics", since = "1.59.0")
45354)]
45355#[cfg_attr(
45356    target_arch = "arm",
45357    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45358)]
45359pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
45360    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45361    unsafe {
45362        let ret_val: float32x2_t = transmute(a);
45363        simd_shuffle!(ret_val, ret_val, [1, 0])
45364    }
45365}
45366#[doc = "Vector reinterpret cast operation"]
45367#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"]
45368#[inline]
45369#[cfg(target_endian = "little")]
45370#[target_feature(enable = "neon")]
45371#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45372#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45373#[cfg_attr(
45374    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45375    assert_instr(nop)
45376)]
45377#[cfg_attr(
45378    not(target_arch = "arm"),
45379    stable(feature = "neon_intrinsics", since = "1.59.0")
45380)]
45381#[cfg_attr(
45382    target_arch = "arm",
45383    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45384)]
45385pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
45386    unsafe { transmute(a) }
45387}
45388#[doc = "Vector reinterpret cast operation"]
45389#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"]
45390#[inline]
45391#[cfg(target_endian = "big")]
45392#[target_feature(enable = "neon")]
45393#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45394#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45395#[cfg_attr(
45396    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45397    assert_instr(nop)
45398)]
45399#[cfg_attr(
45400    not(target_arch = "arm"),
45401    stable(feature = "neon_intrinsics", since = "1.59.0")
45402)]
45403#[cfg_attr(
45404    target_arch = "arm",
45405    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45406)]
45407pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
45408    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45409    unsafe {
45410        let ret_val: int16x4_t = transmute(a);
45411        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45412    }
45413}
45414#[doc = "Vector reinterpret cast operation"]
45415#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"]
45416#[inline]
45417#[cfg(target_endian = "little")]
45418#[target_feature(enable = "neon")]
45419#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45420#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45421#[cfg_attr(
45422    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45423    assert_instr(nop)
45424)]
45425#[cfg_attr(
45426    not(target_arch = "arm"),
45427    stable(feature = "neon_intrinsics", since = "1.59.0")
45428)]
45429#[cfg_attr(
45430    target_arch = "arm",
45431    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45432)]
45433pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
45434    unsafe { transmute(a) }
45435}
45436#[doc = "Vector reinterpret cast operation"]
45437#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"]
45438#[inline]
45439#[cfg(target_endian = "big")]
45440#[target_feature(enable = "neon")]
45441#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45442#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45443#[cfg_attr(
45444    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45445    assert_instr(nop)
45446)]
45447#[cfg_attr(
45448    not(target_arch = "arm"),
45449    stable(feature = "neon_intrinsics", since = "1.59.0")
45450)]
45451#[cfg_attr(
45452    target_arch = "arm",
45453    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45454)]
45455pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
45456    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45457    unsafe {
45458        let ret_val: int32x2_t = transmute(a);
45459        simd_shuffle!(ret_val, ret_val, [1, 0])
45460    }
45461}
45462#[doc = "Vector reinterpret cast operation"]
45463#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"]
45464#[inline]
45465#[cfg(target_endian = "little")]
45466#[target_feature(enable = "neon")]
45467#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45468#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45469#[cfg_attr(
45470    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45471    assert_instr(nop)
45472)]
45473#[cfg_attr(
45474    not(target_arch = "arm"),
45475    stable(feature = "neon_intrinsics", since = "1.59.0")
45476)]
45477#[cfg_attr(
45478    target_arch = "arm",
45479    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45480)]
45481pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
45482    unsafe { transmute(a) }
45483}
45484#[doc = "Vector reinterpret cast operation"]
45485#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"]
45486#[inline]
45487#[cfg(target_endian = "big")]
45488#[target_feature(enable = "neon")]
45489#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45490#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45491#[cfg_attr(
45492    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45493    assert_instr(nop)
45494)]
45495#[cfg_attr(
45496    not(target_arch = "arm"),
45497    stable(feature = "neon_intrinsics", since = "1.59.0")
45498)]
45499#[cfg_attr(
45500    target_arch = "arm",
45501    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45502)]
45503pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
45504    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45505    unsafe { transmute(a) }
45506}
45507#[doc = "Vector reinterpret cast operation"]
45508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"]
45509#[inline]
45510#[cfg(target_endian = "little")]
45511#[target_feature(enable = "neon")]
45512#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45513#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45514#[cfg_attr(
45515    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45516    assert_instr(nop)
45517)]
45518#[cfg_attr(
45519    not(target_arch = "arm"),
45520    stable(feature = "neon_intrinsics", since = "1.59.0")
45521)]
45522#[cfg_attr(
45523    target_arch = "arm",
45524    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45525)]
45526pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
45527    unsafe { transmute(a) }
45528}
45529#[doc = "Vector reinterpret cast operation"]
45530#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"]
45531#[inline]
45532#[cfg(target_endian = "big")]
45533#[target_feature(enable = "neon")]
45534#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45535#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45536#[cfg_attr(
45537    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45538    assert_instr(nop)
45539)]
45540#[cfg_attr(
45541    not(target_arch = "arm"),
45542    stable(feature = "neon_intrinsics", since = "1.59.0")
45543)]
45544#[cfg_attr(
45545    target_arch = "arm",
45546    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45547)]
45548pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
45549    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45550    unsafe {
45551        let ret_val: uint8x8_t = transmute(a);
45552        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45553    }
45554}
45555#[doc = "Vector reinterpret cast operation"]
45556#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"]
45557#[inline]
45558#[cfg(target_endian = "little")]
45559#[target_feature(enable = "neon")]
45560#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45561#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45562#[cfg_attr(
45563    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45564    assert_instr(nop)
45565)]
45566#[cfg_attr(
45567    not(target_arch = "arm"),
45568    stable(feature = "neon_intrinsics", since = "1.59.0")
45569)]
45570#[cfg_attr(
45571    target_arch = "arm",
45572    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45573)]
45574pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
45575    unsafe { transmute(a) }
45576}
45577#[doc = "Vector reinterpret cast operation"]
45578#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"]
45579#[inline]
45580#[cfg(target_endian = "big")]
45581#[target_feature(enable = "neon")]
45582#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45583#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45584#[cfg_attr(
45585    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45586    assert_instr(nop)
45587)]
45588#[cfg_attr(
45589    not(target_arch = "arm"),
45590    stable(feature = "neon_intrinsics", since = "1.59.0")
45591)]
45592#[cfg_attr(
45593    target_arch = "arm",
45594    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45595)]
45596pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
45597    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45598    unsafe {
45599        let ret_val: uint16x4_t = transmute(a);
45600        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45601    }
45602}
45603#[doc = "Vector reinterpret cast operation"]
45604#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"]
45605#[inline]
45606#[cfg(target_endian = "little")]
45607#[target_feature(enable = "neon")]
45608#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45609#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45610#[cfg_attr(
45611    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45612    assert_instr(nop)
45613)]
45614#[cfg_attr(
45615    not(target_arch = "arm"),
45616    stable(feature = "neon_intrinsics", since = "1.59.0")
45617)]
45618#[cfg_attr(
45619    target_arch = "arm",
45620    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45621)]
45622pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
45623    unsafe { transmute(a) }
45624}
45625#[doc = "Vector reinterpret cast operation"]
45626#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"]
45627#[inline]
45628#[cfg(target_endian = "big")]
45629#[target_feature(enable = "neon")]
45630#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45631#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45632#[cfg_attr(
45633    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45634    assert_instr(nop)
45635)]
45636#[cfg_attr(
45637    not(target_arch = "arm"),
45638    stable(feature = "neon_intrinsics", since = "1.59.0")
45639)]
45640#[cfg_attr(
45641    target_arch = "arm",
45642    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45643)]
45644pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
45645    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45646    unsafe {
45647        let ret_val: uint32x2_t = transmute(a);
45648        simd_shuffle!(ret_val, ret_val, [1, 0])
45649    }
45650}
45651#[doc = "Vector reinterpret cast operation"]
45652#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"]
45653#[inline]
45654#[cfg(target_endian = "little")]
45655#[target_feature(enable = "neon")]
45656#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45657#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45658#[cfg_attr(
45659    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45660    assert_instr(nop)
45661)]
45662#[cfg_attr(
45663    not(target_arch = "arm"),
45664    stable(feature = "neon_intrinsics", since = "1.59.0")
45665)]
45666#[cfg_attr(
45667    target_arch = "arm",
45668    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45669)]
45670pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
45671    unsafe { transmute(a) }
45672}
45673#[doc = "Vector reinterpret cast operation"]
45674#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"]
45675#[inline]
45676#[cfg(target_endian = "big")]
45677#[target_feature(enable = "neon")]
45678#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45679#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45680#[cfg_attr(
45681    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45682    assert_instr(nop)
45683)]
45684#[cfg_attr(
45685    not(target_arch = "arm"),
45686    stable(feature = "neon_intrinsics", since = "1.59.0")
45687)]
45688#[cfg_attr(
45689    target_arch = "arm",
45690    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45691)]
45692pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
45693    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45694    unsafe { transmute(a) }
45695}
45696#[doc = "Vector reinterpret cast operation"]
45697#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"]
45698#[inline]
45699#[cfg(target_endian = "little")]
45700#[target_feature(enable = "neon")]
45701#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45702#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45703#[cfg_attr(
45704    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45705    assert_instr(nop)
45706)]
45707#[cfg_attr(
45708    not(target_arch = "arm"),
45709    stable(feature = "neon_intrinsics", since = "1.59.0")
45710)]
45711#[cfg_attr(
45712    target_arch = "arm",
45713    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45714)]
45715pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
45716    unsafe { transmute(a) }
45717}
45718#[doc = "Vector reinterpret cast operation"]
45719#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"]
45720#[inline]
45721#[cfg(target_endian = "big")]
45722#[target_feature(enable = "neon")]
45723#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45724#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45725#[cfg_attr(
45726    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45727    assert_instr(nop)
45728)]
45729#[cfg_attr(
45730    not(target_arch = "arm"),
45731    stable(feature = "neon_intrinsics", since = "1.59.0")
45732)]
45733#[cfg_attr(
45734    target_arch = "arm",
45735    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45736)]
45737pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
45738    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45739    unsafe {
45740        let ret_val: poly8x8_t = transmute(a);
45741        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45742    }
45743}
45744#[doc = "Vector reinterpret cast operation"]
45745#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"]
45746#[inline]
45747#[cfg(target_endian = "little")]
45748#[target_feature(enable = "neon")]
45749#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45750#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45751#[cfg_attr(
45752    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45753    assert_instr(nop)
45754)]
45755#[cfg_attr(
45756    not(target_arch = "arm"),
45757    stable(feature = "neon_intrinsics", since = "1.59.0")
45758)]
45759#[cfg_attr(
45760    target_arch = "arm",
45761    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45762)]
45763pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
45764    unsafe { transmute(a) }
45765}
45766#[doc = "Vector reinterpret cast operation"]
45767#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"]
45768#[inline]
45769#[cfg(target_endian = "big")]
45770#[target_feature(enable = "neon")]
45771#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45772#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45773#[cfg_attr(
45774    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45775    assert_instr(nop)
45776)]
45777#[cfg_attr(
45778    not(target_arch = "arm"),
45779    stable(feature = "neon_intrinsics", since = "1.59.0")
45780)]
45781#[cfg_attr(
45782    target_arch = "arm",
45783    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45784)]
45785pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
45786    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45787    unsafe {
45788        let ret_val: poly16x4_t = transmute(a);
45789        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45790    }
45791}
45792#[doc = "Vector reinterpret cast operation"]
45793#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"]
45794#[inline]
45795#[cfg(target_endian = "little")]
45796#[target_feature(enable = "neon")]
45797#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45798#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45799#[cfg_attr(
45800    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45801    assert_instr(nop)
45802)]
45803#[cfg_attr(
45804    not(target_arch = "arm"),
45805    stable(feature = "neon_intrinsics", since = "1.59.0")
45806)]
45807#[cfg_attr(
45808    target_arch = "arm",
45809    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45810)]
45811pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
45812    unsafe { transmute(a) }
45813}
45814#[doc = "Vector reinterpret cast operation"]
45815#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"]
45816#[inline]
45817#[cfg(target_endian = "big")]
45818#[target_feature(enable = "neon")]
45819#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45820#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45821#[cfg_attr(
45822    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45823    assert_instr(nop)
45824)]
45825#[cfg_attr(
45826    not(target_arch = "arm"),
45827    stable(feature = "neon_intrinsics", since = "1.59.0")
45828)]
45829#[cfg_attr(
45830    target_arch = "arm",
45831    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45832)]
45833pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
45834    let a: int8x16_t =
45835        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
45836    unsafe {
45837        let ret_val: float32x4_t = transmute(a);
45838        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45839    }
45840}
45841#[doc = "Vector reinterpret cast operation"]
45842#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"]
45843#[inline]
45844#[cfg(target_endian = "little")]
45845#[target_feature(enable = "neon")]
45846#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45847#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45848#[cfg_attr(
45849    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45850    assert_instr(nop)
45851)]
45852#[cfg_attr(
45853    not(target_arch = "arm"),
45854    stable(feature = "neon_intrinsics", since = "1.59.0")
45855)]
45856#[cfg_attr(
45857    target_arch = "arm",
45858    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45859)]
45860pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
45861    unsafe { transmute(a) }
45862}
45863#[doc = "Vector reinterpret cast operation"]
45864#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"]
45865#[inline]
45866#[cfg(target_endian = "big")]
45867#[target_feature(enable = "neon")]
45868#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45869#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45870#[cfg_attr(
45871    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45872    assert_instr(nop)
45873)]
45874#[cfg_attr(
45875    not(target_arch = "arm"),
45876    stable(feature = "neon_intrinsics", since = "1.59.0")
45877)]
45878#[cfg_attr(
45879    target_arch = "arm",
45880    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45881)]
45882pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
45883    let a: int8x16_t =
45884        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
45885    unsafe {
45886        let ret_val: int16x8_t = transmute(a);
45887        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45888    }
45889}
45890#[doc = "Vector reinterpret cast operation"]
45891#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"]
45892#[inline]
45893#[cfg(target_endian = "little")]
45894#[target_feature(enable = "neon")]
45895#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45896#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45897#[cfg_attr(
45898    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45899    assert_instr(nop)
45900)]
45901#[cfg_attr(
45902    not(target_arch = "arm"),
45903    stable(feature = "neon_intrinsics", since = "1.59.0")
45904)]
45905#[cfg_attr(
45906    target_arch = "arm",
45907    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45908)]
45909pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
45910    unsafe { transmute(a) }
45911}
45912#[doc = "Vector reinterpret cast operation"]
45913#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"]
45914#[inline]
45915#[cfg(target_endian = "big")]
45916#[target_feature(enable = "neon")]
45917#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45918#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45919#[cfg_attr(
45920    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45921    assert_instr(nop)
45922)]
45923#[cfg_attr(
45924    not(target_arch = "arm"),
45925    stable(feature = "neon_intrinsics", since = "1.59.0")
45926)]
45927#[cfg_attr(
45928    target_arch = "arm",
45929    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45930)]
45931pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
45932    let a: int8x16_t =
45933        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
45934    unsafe {
45935        let ret_val: int32x4_t = transmute(a);
45936        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45937    }
45938}
45939#[doc = "Vector reinterpret cast operation"]
45940#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"]
45941#[inline]
45942#[cfg(target_endian = "little")]
45943#[target_feature(enable = "neon")]
45944#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45945#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45946#[cfg_attr(
45947    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45948    assert_instr(nop)
45949)]
45950#[cfg_attr(
45951    not(target_arch = "arm"),
45952    stable(feature = "neon_intrinsics", since = "1.59.0")
45953)]
45954#[cfg_attr(
45955    target_arch = "arm",
45956    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45957)]
45958pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
45959    unsafe { transmute(a) }
45960}
45961#[doc = "Vector reinterpret cast operation"]
45962#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"]
45963#[inline]
45964#[cfg(target_endian = "big")]
45965#[target_feature(enable = "neon")]
45966#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45967#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45968#[cfg_attr(
45969    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45970    assert_instr(nop)
45971)]
45972#[cfg_attr(
45973    not(target_arch = "arm"),
45974    stable(feature = "neon_intrinsics", since = "1.59.0")
45975)]
45976#[cfg_attr(
45977    target_arch = "arm",
45978    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45979)]
45980pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
45981    let a: int8x16_t =
45982        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
45983    unsafe {
45984        let ret_val: int64x2_t = transmute(a);
45985        simd_shuffle!(ret_val, ret_val, [1, 0])
45986    }
45987}
45988#[doc = "Vector reinterpret cast operation"]
45989#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"]
45990#[inline]
45991#[cfg(target_endian = "little")]
45992#[target_feature(enable = "neon")]
45993#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45994#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45995#[cfg_attr(
45996    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45997    assert_instr(nop)
45998)]
45999#[cfg_attr(
46000    not(target_arch = "arm"),
46001    stable(feature = "neon_intrinsics", since = "1.59.0")
46002)]
46003#[cfg_attr(
46004    target_arch = "arm",
46005    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46006)]
46007pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
46008    unsafe { transmute(a) }
46009}
46010#[doc = "Vector reinterpret cast operation"]
46011#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"]
46012#[inline]
46013#[cfg(target_endian = "big")]
46014#[target_feature(enable = "neon")]
46015#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46016#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46017#[cfg_attr(
46018    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46019    assert_instr(nop)
46020)]
46021#[cfg_attr(
46022    not(target_arch = "arm"),
46023    stable(feature = "neon_intrinsics", since = "1.59.0")
46024)]
46025#[cfg_attr(
46026    target_arch = "arm",
46027    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46028)]
46029pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
46030    let a: int8x16_t =
46031        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
46032    unsafe {
46033        let ret_val: uint8x16_t = transmute(a);
46034        simd_shuffle!(
46035            ret_val,
46036            ret_val,
46037            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
46038        )
46039    }
46040}
46041#[doc = "Vector reinterpret cast operation"]
46042#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"]
46043#[inline]
46044#[cfg(target_endian = "little")]
46045#[target_feature(enable = "neon")]
46046#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46047#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46048#[cfg_attr(
46049    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46050    assert_instr(nop)
46051)]
46052#[cfg_attr(
46053    not(target_arch = "arm"),
46054    stable(feature = "neon_intrinsics", since = "1.59.0")
46055)]
46056#[cfg_attr(
46057    target_arch = "arm",
46058    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46059)]
46060pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
46061    unsafe { transmute(a) }
46062}
46063#[doc = "Vector reinterpret cast operation"]
46064#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"]
46065#[inline]
46066#[cfg(target_endian = "big")]
46067#[target_feature(enable = "neon")]
46068#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46069#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46070#[cfg_attr(
46071    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46072    assert_instr(nop)
46073)]
46074#[cfg_attr(
46075    not(target_arch = "arm"),
46076    stable(feature = "neon_intrinsics", since = "1.59.0")
46077)]
46078#[cfg_attr(
46079    target_arch = "arm",
46080    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46081)]
46082pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
46083    let a: int8x16_t =
46084        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
46085    unsafe {
46086        let ret_val: uint16x8_t = transmute(a);
46087        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46088    }
46089}
46090#[doc = "Vector reinterpret cast operation"]
46091#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"]
46092#[inline]
46093#[cfg(target_endian = "little")]
46094#[target_feature(enable = "neon")]
46095#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46096#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46097#[cfg_attr(
46098    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46099    assert_instr(nop)
46100)]
46101#[cfg_attr(
46102    not(target_arch = "arm"),
46103    stable(feature = "neon_intrinsics", since = "1.59.0")
46104)]
46105#[cfg_attr(
46106    target_arch = "arm",
46107    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46108)]
46109pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
46110    unsafe { transmute(a) }
46111}
46112#[doc = "Vector reinterpret cast operation"]
46113#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"]
46114#[inline]
46115#[cfg(target_endian = "big")]
46116#[target_feature(enable = "neon")]
46117#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46118#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46119#[cfg_attr(
46120    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46121    assert_instr(nop)
46122)]
46123#[cfg_attr(
46124    not(target_arch = "arm"),
46125    stable(feature = "neon_intrinsics", since = "1.59.0")
46126)]
46127#[cfg_attr(
46128    target_arch = "arm",
46129    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46130)]
46131pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
46132    let a: int8x16_t =
46133        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
46134    unsafe {
46135        let ret_val: uint32x4_t = transmute(a);
46136        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46137    }
46138}
46139#[doc = "Vector reinterpret cast operation"]
46140#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"]
46141#[inline]
46142#[cfg(target_endian = "little")]
46143#[target_feature(enable = "neon")]
46144#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46145#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46146#[cfg_attr(
46147    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46148    assert_instr(nop)
46149)]
46150#[cfg_attr(
46151    not(target_arch = "arm"),
46152    stable(feature = "neon_intrinsics", since = "1.59.0")
46153)]
46154#[cfg_attr(
46155    target_arch = "arm",
46156    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46157)]
46158pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
46159    unsafe { transmute(a) }
46160}
46161#[doc = "Vector reinterpret cast operation"]
46162#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"]
46163#[inline]
46164#[cfg(target_endian = "big")]
46165#[target_feature(enable = "neon")]
46166#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46167#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46168#[cfg_attr(
46169    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46170    assert_instr(nop)
46171)]
46172#[cfg_attr(
46173    not(target_arch = "arm"),
46174    stable(feature = "neon_intrinsics", since = "1.59.0")
46175)]
46176#[cfg_attr(
46177    target_arch = "arm",
46178    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46179)]
46180pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
46181    let a: int8x16_t =
46182        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
46183    unsafe {
46184        let ret_val: uint64x2_t = transmute(a);
46185        simd_shuffle!(ret_val, ret_val, [1, 0])
46186    }
46187}
46188#[doc = "Vector reinterpret cast operation"]
46189#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"]
46190#[inline]
46191#[cfg(target_endian = "little")]
46192#[target_feature(enable = "neon")]
46193#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46194#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46195#[cfg_attr(
46196    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46197    assert_instr(nop)
46198)]
46199#[cfg_attr(
46200    not(target_arch = "arm"),
46201    stable(feature = "neon_intrinsics", since = "1.59.0")
46202)]
46203#[cfg_attr(
46204    target_arch = "arm",
46205    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46206)]
46207pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
46208    unsafe { transmute(a) }
46209}
46210#[doc = "Vector reinterpret cast operation"]
46211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"]
46212#[inline]
46213#[cfg(target_endian = "big")]
46214#[target_feature(enable = "neon")]
46215#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46216#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46217#[cfg_attr(
46218    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46219    assert_instr(nop)
46220)]
46221#[cfg_attr(
46222    not(target_arch = "arm"),
46223    stable(feature = "neon_intrinsics", since = "1.59.0")
46224)]
46225#[cfg_attr(
46226    target_arch = "arm",
46227    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46228)]
46229pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
46230    let a: int8x16_t =
46231        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
46232    unsafe {
46233        let ret_val: poly8x16_t = transmute(a);
46234        simd_shuffle!(
46235            ret_val,
46236            ret_val,
46237            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
46238        )
46239    }
46240}
46241#[doc = "Vector reinterpret cast operation"]
46242#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"]
46243#[inline]
46244#[cfg(target_endian = "little")]
46245#[target_feature(enable = "neon")]
46246#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46247#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46248#[cfg_attr(
46249    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46250    assert_instr(nop)
46251)]
46252#[cfg_attr(
46253    not(target_arch = "arm"),
46254    stable(feature = "neon_intrinsics", since = "1.59.0")
46255)]
46256#[cfg_attr(
46257    target_arch = "arm",
46258    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46259)]
46260pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
46261    unsafe { transmute(a) }
46262}
46263#[doc = "Vector reinterpret cast operation"]
46264#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"]
46265#[inline]
46266#[cfg(target_endian = "big")]
46267#[target_feature(enable = "neon")]
46268#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46269#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46270#[cfg_attr(
46271    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46272    assert_instr(nop)
46273)]
46274#[cfg_attr(
46275    not(target_arch = "arm"),
46276    stable(feature = "neon_intrinsics", since = "1.59.0")
46277)]
46278#[cfg_attr(
46279    target_arch = "arm",
46280    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46281)]
46282pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
46283    let a: int8x16_t =
46284        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
46285    unsafe {
46286        let ret_val: poly16x8_t = transmute(a);
46287        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46288    }
46289}
46290#[doc = "Vector reinterpret cast operation"]
46291#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"]
46292#[inline]
46293#[cfg(target_endian = "little")]
46294#[target_feature(enable = "neon")]
46295#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46296#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46297#[cfg_attr(
46298    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46299    assert_instr(nop)
46300)]
46301#[cfg_attr(
46302    not(target_arch = "arm"),
46303    stable(feature = "neon_intrinsics", since = "1.59.0")
46304)]
46305#[cfg_attr(
46306    target_arch = "arm",
46307    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46308)]
46309pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
46310    unsafe { transmute(a) }
46311}
46312#[doc = "Vector reinterpret cast operation"]
46313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"]
46314#[inline]
46315#[cfg(target_endian = "big")]
46316#[target_feature(enable = "neon")]
46317#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46318#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46319#[cfg_attr(
46320    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46321    assert_instr(nop)
46322)]
46323#[cfg_attr(
46324    not(target_arch = "arm"),
46325    stable(feature = "neon_intrinsics", since = "1.59.0")
46326)]
46327#[cfg_attr(
46328    target_arch = "arm",
46329    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46330)]
46331pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
46332    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46333    unsafe {
46334        let ret_val: float32x2_t = transmute(a);
46335        simd_shuffle!(ret_val, ret_val, [1, 0])
46336    }
46337}
46338#[doc = "Vector reinterpret cast operation"]
46339#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"]
46340#[inline]
46341#[cfg(target_endian = "little")]
46342#[target_feature(enable = "neon")]
46343#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46344#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46345#[cfg_attr(
46346    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46347    assert_instr(nop)
46348)]
46349#[cfg_attr(
46350    not(target_arch = "arm"),
46351    stable(feature = "neon_intrinsics", since = "1.59.0")
46352)]
46353#[cfg_attr(
46354    target_arch = "arm",
46355    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46356)]
46357pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
46358    unsafe { transmute(a) }
46359}
46360#[doc = "Vector reinterpret cast operation"]
46361#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"]
46362#[inline]
46363#[cfg(target_endian = "big")]
46364#[target_feature(enable = "neon")]
46365#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46366#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46367#[cfg_attr(
46368    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46369    assert_instr(nop)
46370)]
46371#[cfg_attr(
46372    not(target_arch = "arm"),
46373    stable(feature = "neon_intrinsics", since = "1.59.0")
46374)]
46375#[cfg_attr(
46376    target_arch = "arm",
46377    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46378)]
46379pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
46380    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46381    unsafe {
46382        let ret_val: int8x8_t = transmute(a);
46383        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46384    }
46385}
46386#[doc = "Vector reinterpret cast operation"]
46387#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"]
46388#[inline]
46389#[cfg(target_endian = "little")]
46390#[target_feature(enable = "neon")]
46391#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46392#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46393#[cfg_attr(
46394    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46395    assert_instr(nop)
46396)]
46397#[cfg_attr(
46398    not(target_arch = "arm"),
46399    stable(feature = "neon_intrinsics", since = "1.59.0")
46400)]
46401#[cfg_attr(
46402    target_arch = "arm",
46403    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46404)]
46405pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
46406    unsafe { transmute(a) }
46407}
46408#[doc = "Vector reinterpret cast operation"]
46409#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"]
46410#[inline]
46411#[cfg(target_endian = "big")]
46412#[target_feature(enable = "neon")]
46413#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46414#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46415#[cfg_attr(
46416    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46417    assert_instr(nop)
46418)]
46419#[cfg_attr(
46420    not(target_arch = "arm"),
46421    stable(feature = "neon_intrinsics", since = "1.59.0")
46422)]
46423#[cfg_attr(
46424    target_arch = "arm",
46425    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46426)]
46427pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
46428    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46429    unsafe {
46430        let ret_val: int32x2_t = transmute(a);
46431        simd_shuffle!(ret_val, ret_val, [1, 0])
46432    }
46433}
46434#[doc = "Vector reinterpret cast operation"]
46435#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"]
46436#[inline]
46437#[cfg(target_endian = "little")]
46438#[target_feature(enable = "neon")]
46439#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46440#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46441#[cfg_attr(
46442    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46443    assert_instr(nop)
46444)]
46445#[cfg_attr(
46446    not(target_arch = "arm"),
46447    stable(feature = "neon_intrinsics", since = "1.59.0")
46448)]
46449#[cfg_attr(
46450    target_arch = "arm",
46451    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46452)]
46453pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
46454    unsafe { transmute(a) }
46455}
46456#[doc = "Vector reinterpret cast operation"]
46457#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"]
46458#[inline]
46459#[cfg(target_endian = "big")]
46460#[target_feature(enable = "neon")]
46461#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46462#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46463#[cfg_attr(
46464    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46465    assert_instr(nop)
46466)]
46467#[cfg_attr(
46468    not(target_arch = "arm"),
46469    stable(feature = "neon_intrinsics", since = "1.59.0")
46470)]
46471#[cfg_attr(
46472    target_arch = "arm",
46473    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46474)]
46475pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
46476    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46477    unsafe { transmute(a) }
46478}
46479#[doc = "Vector reinterpret cast operation"]
46480#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"]
46481#[inline]
46482#[cfg(target_endian = "little")]
46483#[target_feature(enable = "neon")]
46484#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46485#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46486#[cfg_attr(
46487    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46488    assert_instr(nop)
46489)]
46490#[cfg_attr(
46491    not(target_arch = "arm"),
46492    stable(feature = "neon_intrinsics", since = "1.59.0")
46493)]
46494#[cfg_attr(
46495    target_arch = "arm",
46496    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46497)]
46498pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
46499    unsafe { transmute(a) }
46500}
46501#[doc = "Vector reinterpret cast operation"]
46502#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"]
46503#[inline]
46504#[cfg(target_endian = "big")]
46505#[target_feature(enable = "neon")]
46506#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46507#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46508#[cfg_attr(
46509    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46510    assert_instr(nop)
46511)]
46512#[cfg_attr(
46513    not(target_arch = "arm"),
46514    stable(feature = "neon_intrinsics", since = "1.59.0")
46515)]
46516#[cfg_attr(
46517    target_arch = "arm",
46518    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46519)]
46520pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
46521    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46522    unsafe {
46523        let ret_val: uint8x8_t = transmute(a);
46524        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46525    }
46526}
46527#[doc = "Vector reinterpret cast operation"]
46528#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"]
46529#[inline]
46530#[cfg(target_endian = "little")]
46531#[target_feature(enable = "neon")]
46532#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46533#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46534#[cfg_attr(
46535    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46536    assert_instr(nop)
46537)]
46538#[cfg_attr(
46539    not(target_arch = "arm"),
46540    stable(feature = "neon_intrinsics", since = "1.59.0")
46541)]
46542#[cfg_attr(
46543    target_arch = "arm",
46544    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46545)]
46546pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
46547    unsafe { transmute(a) }
46548}
46549#[doc = "Vector reinterpret cast operation"]
46550#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"]
46551#[inline]
46552#[cfg(target_endian = "big")]
46553#[target_feature(enable = "neon")]
46554#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46555#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46556#[cfg_attr(
46557    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46558    assert_instr(nop)
46559)]
46560#[cfg_attr(
46561    not(target_arch = "arm"),
46562    stable(feature = "neon_intrinsics", since = "1.59.0")
46563)]
46564#[cfg_attr(
46565    target_arch = "arm",
46566    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46567)]
46568pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
46569    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46570    unsafe {
46571        let ret_val: uint16x4_t = transmute(a);
46572        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46573    }
46574}
46575#[doc = "Vector reinterpret cast operation"]
46576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"]
46577#[inline]
46578#[cfg(target_endian = "little")]
46579#[target_feature(enable = "neon")]
46580#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46581#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46582#[cfg_attr(
46583    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46584    assert_instr(nop)
46585)]
46586#[cfg_attr(
46587    not(target_arch = "arm"),
46588    stable(feature = "neon_intrinsics", since = "1.59.0")
46589)]
46590#[cfg_attr(
46591    target_arch = "arm",
46592    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46593)]
46594pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
46595    unsafe { transmute(a) }
46596}
46597#[doc = "Vector reinterpret cast operation"]
46598#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"]
46599#[inline]
46600#[cfg(target_endian = "big")]
46601#[target_feature(enable = "neon")]
46602#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46603#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46604#[cfg_attr(
46605    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46606    assert_instr(nop)
46607)]
46608#[cfg_attr(
46609    not(target_arch = "arm"),
46610    stable(feature = "neon_intrinsics", since = "1.59.0")
46611)]
46612#[cfg_attr(
46613    target_arch = "arm",
46614    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46615)]
46616pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
46617    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46618    unsafe {
46619        let ret_val: uint32x2_t = transmute(a);
46620        simd_shuffle!(ret_val, ret_val, [1, 0])
46621    }
46622}
46623#[doc = "Vector reinterpret cast operation"]
46624#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"]
46625#[inline]
46626#[cfg(target_endian = "little")]
46627#[target_feature(enable = "neon")]
46628#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46629#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46630#[cfg_attr(
46631    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46632    assert_instr(nop)
46633)]
46634#[cfg_attr(
46635    not(target_arch = "arm"),
46636    stable(feature = "neon_intrinsics", since = "1.59.0")
46637)]
46638#[cfg_attr(
46639    target_arch = "arm",
46640    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46641)]
46642pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
46643    unsafe { transmute(a) }
46644}
46645#[doc = "Vector reinterpret cast operation"]
46646#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"]
46647#[inline]
46648#[cfg(target_endian = "big")]
46649#[target_feature(enable = "neon")]
46650#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46651#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46652#[cfg_attr(
46653    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46654    assert_instr(nop)
46655)]
46656#[cfg_attr(
46657    not(target_arch = "arm"),
46658    stable(feature = "neon_intrinsics", since = "1.59.0")
46659)]
46660#[cfg_attr(
46661    target_arch = "arm",
46662    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46663)]
46664pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
46665    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46666    unsafe { transmute(a) }
46667}
46668#[doc = "Vector reinterpret cast operation"]
46669#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"]
46670#[inline]
46671#[cfg(target_endian = "little")]
46672#[target_feature(enable = "neon")]
46673#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46674#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46675#[cfg_attr(
46676    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46677    assert_instr(nop)
46678)]
46679#[cfg_attr(
46680    not(target_arch = "arm"),
46681    stable(feature = "neon_intrinsics", since = "1.59.0")
46682)]
46683#[cfg_attr(
46684    target_arch = "arm",
46685    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46686)]
46687pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
46688    unsafe { transmute(a) }
46689}
46690#[doc = "Vector reinterpret cast operation"]
46691#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"]
46692#[inline]
46693#[cfg(target_endian = "big")]
46694#[target_feature(enable = "neon")]
46695#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46696#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46697#[cfg_attr(
46698    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46699    assert_instr(nop)
46700)]
46701#[cfg_attr(
46702    not(target_arch = "arm"),
46703    stable(feature = "neon_intrinsics", since = "1.59.0")
46704)]
46705#[cfg_attr(
46706    target_arch = "arm",
46707    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46708)]
46709pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
46710    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46711    unsafe {
46712        let ret_val: poly8x8_t = transmute(a);
46713        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46714    }
46715}
46716#[doc = "Vector reinterpret cast operation"]
46717#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"]
46718#[inline]
46719#[cfg(target_endian = "little")]
46720#[target_feature(enable = "neon")]
46721#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46722#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46723#[cfg_attr(
46724    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46725    assert_instr(nop)
46726)]
46727#[cfg_attr(
46728    not(target_arch = "arm"),
46729    stable(feature = "neon_intrinsics", since = "1.59.0")
46730)]
46731#[cfg_attr(
46732    target_arch = "arm",
46733    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46734)]
46735pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
46736    unsafe { transmute(a) }
46737}
46738#[doc = "Vector reinterpret cast operation"]
46739#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"]
46740#[inline]
46741#[cfg(target_endian = "big")]
46742#[target_feature(enable = "neon")]
46743#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46744#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46745#[cfg_attr(
46746    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46747    assert_instr(nop)
46748)]
46749#[cfg_attr(
46750    not(target_arch = "arm"),
46751    stable(feature = "neon_intrinsics", since = "1.59.0")
46752)]
46753#[cfg_attr(
46754    target_arch = "arm",
46755    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46756)]
46757pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
46758    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46759    unsafe {
46760        let ret_val: poly16x4_t = transmute(a);
46761        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46762    }
46763}
46764#[doc = "Vector reinterpret cast operation"]
46765#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"]
46766#[inline]
46767#[cfg(target_endian = "little")]
46768#[target_feature(enable = "neon")]
46769#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46770#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46771#[cfg_attr(
46772    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46773    assert_instr(nop)
46774)]
46775#[cfg_attr(
46776    not(target_arch = "arm"),
46777    stable(feature = "neon_intrinsics", since = "1.59.0")
46778)]
46779#[cfg_attr(
46780    target_arch = "arm",
46781    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46782)]
46783pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
46784    unsafe { transmute(a) }
46785}
46786#[doc = "Vector reinterpret cast operation"]
46787#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"]
46788#[inline]
46789#[cfg(target_endian = "big")]
46790#[target_feature(enable = "neon")]
46791#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46792#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46793#[cfg_attr(
46794    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46795    assert_instr(nop)
46796)]
46797#[cfg_attr(
46798    not(target_arch = "arm"),
46799    stable(feature = "neon_intrinsics", since = "1.59.0")
46800)]
46801#[cfg_attr(
46802    target_arch = "arm",
46803    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46804)]
46805pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
46806    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46807    unsafe {
46808        let ret_val: float32x4_t = transmute(a);
46809        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46810    }
46811}
46812#[doc = "Vector reinterpret cast operation"]
46813#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"]
46814#[inline]
46815#[cfg(target_endian = "little")]
46816#[target_feature(enable = "neon")]
46817#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46818#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46819#[cfg_attr(
46820    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46821    assert_instr(nop)
46822)]
46823#[cfg_attr(
46824    not(target_arch = "arm"),
46825    stable(feature = "neon_intrinsics", since = "1.59.0")
46826)]
46827#[cfg_attr(
46828    target_arch = "arm",
46829    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46830)]
46831pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
46832    unsafe { transmute(a) }
46833}
46834#[doc = "Vector reinterpret cast operation"]
46835#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"]
46836#[inline]
46837#[cfg(target_endian = "big")]
46838#[target_feature(enable = "neon")]
46839#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46840#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46841#[cfg_attr(
46842    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46843    assert_instr(nop)
46844)]
46845#[cfg_attr(
46846    not(target_arch = "arm"),
46847    stable(feature = "neon_intrinsics", since = "1.59.0")
46848)]
46849#[cfg_attr(
46850    target_arch = "arm",
46851    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46852)]
46853pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
46854    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46855    unsafe {
46856        let ret_val: int8x16_t = transmute(a);
46857        simd_shuffle!(
46858            ret_val,
46859            ret_val,
46860            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
46861        )
46862    }
46863}
46864#[doc = "Vector reinterpret cast operation"]
46865#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"]
46866#[inline]
46867#[cfg(target_endian = "little")]
46868#[target_feature(enable = "neon")]
46869#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46870#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46871#[cfg_attr(
46872    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46873    assert_instr(nop)
46874)]
46875#[cfg_attr(
46876    not(target_arch = "arm"),
46877    stable(feature = "neon_intrinsics", since = "1.59.0")
46878)]
46879#[cfg_attr(
46880    target_arch = "arm",
46881    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46882)]
46883pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
46884    unsafe { transmute(a) }
46885}
46886#[doc = "Vector reinterpret cast operation"]
46887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"]
46888#[inline]
46889#[cfg(target_endian = "big")]
46890#[target_feature(enable = "neon")]
46891#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46892#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46893#[cfg_attr(
46894    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46895    assert_instr(nop)
46896)]
46897#[cfg_attr(
46898    not(target_arch = "arm"),
46899    stable(feature = "neon_intrinsics", since = "1.59.0")
46900)]
46901#[cfg_attr(
46902    target_arch = "arm",
46903    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46904)]
46905pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
46906    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46907    unsafe {
46908        let ret_val: int32x4_t = transmute(a);
46909        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46910    }
46911}
46912#[doc = "Vector reinterpret cast operation"]
46913#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"]
46914#[inline]
46915#[cfg(target_endian = "little")]
46916#[target_feature(enable = "neon")]
46917#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46918#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46919#[cfg_attr(
46920    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46921    assert_instr(nop)
46922)]
46923#[cfg_attr(
46924    not(target_arch = "arm"),
46925    stable(feature = "neon_intrinsics", since = "1.59.0")
46926)]
46927#[cfg_attr(
46928    target_arch = "arm",
46929    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46930)]
46931pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
46932    unsafe { transmute(a) }
46933}
46934#[doc = "Vector reinterpret cast operation"]
46935#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"]
46936#[inline]
46937#[cfg(target_endian = "big")]
46938#[target_feature(enable = "neon")]
46939#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46940#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46941#[cfg_attr(
46942    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46943    assert_instr(nop)
46944)]
46945#[cfg_attr(
46946    not(target_arch = "arm"),
46947    stable(feature = "neon_intrinsics", since = "1.59.0")
46948)]
46949#[cfg_attr(
46950    target_arch = "arm",
46951    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46952)]
46953pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
46954    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46955    unsafe {
46956        let ret_val: int64x2_t = transmute(a);
46957        simd_shuffle!(ret_val, ret_val, [1, 0])
46958    }
46959}
46960#[doc = "Vector reinterpret cast operation"]
46961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"]
46962#[inline]
46963#[cfg(target_endian = "little")]
46964#[target_feature(enable = "neon")]
46965#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46966#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46967#[cfg_attr(
46968    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46969    assert_instr(nop)
46970)]
46971#[cfg_attr(
46972    not(target_arch = "arm"),
46973    stable(feature = "neon_intrinsics", since = "1.59.0")
46974)]
46975#[cfg_attr(
46976    target_arch = "arm",
46977    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46978)]
46979pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
46980    unsafe { transmute(a) }
46981}
46982#[doc = "Vector reinterpret cast operation"]
46983#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"]
46984#[inline]
46985#[cfg(target_endian = "big")]
46986#[target_feature(enable = "neon")]
46987#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46988#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46989#[cfg_attr(
46990    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46991    assert_instr(nop)
46992)]
46993#[cfg_attr(
46994    not(target_arch = "arm"),
46995    stable(feature = "neon_intrinsics", since = "1.59.0")
46996)]
46997#[cfg_attr(
46998    target_arch = "arm",
46999    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47000)]
47001pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
47002    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
47003    unsafe {
47004        let ret_val: uint8x16_t = transmute(a);
47005        simd_shuffle!(
47006            ret_val,
47007            ret_val,
47008            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
47009        )
47010    }
47011}
47012#[doc = "Vector reinterpret cast operation"]
47013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"]
47014#[inline]
47015#[cfg(target_endian = "little")]
47016#[target_feature(enable = "neon")]
47017#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47018#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47019#[cfg_attr(
47020    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47021    assert_instr(nop)
47022)]
47023#[cfg_attr(
47024    not(target_arch = "arm"),
47025    stable(feature = "neon_intrinsics", since = "1.59.0")
47026)]
47027#[cfg_attr(
47028    target_arch = "arm",
47029    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47030)]
47031pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
47032    unsafe { transmute(a) }
47033}
47034#[doc = "Vector reinterpret cast operation"]
47035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"]
47036#[inline]
47037#[cfg(target_endian = "big")]
47038#[target_feature(enable = "neon")]
47039#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47040#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47041#[cfg_attr(
47042    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47043    assert_instr(nop)
47044)]
47045#[cfg_attr(
47046    not(target_arch = "arm"),
47047    stable(feature = "neon_intrinsics", since = "1.59.0")
47048)]
47049#[cfg_attr(
47050    target_arch = "arm",
47051    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47052)]
47053pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
47054    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
47055    unsafe {
47056        let ret_val: uint16x8_t = transmute(a);
47057        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47058    }
47059}
47060#[doc = "Vector reinterpret cast operation"]
47061#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"]
47062#[inline]
47063#[cfg(target_endian = "little")]
47064#[target_feature(enable = "neon")]
47065#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47066#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47067#[cfg_attr(
47068    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47069    assert_instr(nop)
47070)]
47071#[cfg_attr(
47072    not(target_arch = "arm"),
47073    stable(feature = "neon_intrinsics", since = "1.59.0")
47074)]
47075#[cfg_attr(
47076    target_arch = "arm",
47077    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47078)]
47079pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
47080    unsafe { transmute(a) }
47081}
47082#[doc = "Vector reinterpret cast operation"]
47083#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"]
47084#[inline]
47085#[cfg(target_endian = "big")]
47086#[target_feature(enable = "neon")]
47087#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47088#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47089#[cfg_attr(
47090    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47091    assert_instr(nop)
47092)]
47093#[cfg_attr(
47094    not(target_arch = "arm"),
47095    stable(feature = "neon_intrinsics", since = "1.59.0")
47096)]
47097#[cfg_attr(
47098    target_arch = "arm",
47099    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47100)]
47101pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
47102    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
47103    unsafe {
47104        let ret_val: uint32x4_t = transmute(a);
47105        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47106    }
47107}
47108#[doc = "Vector reinterpret cast operation"]
47109#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"]
47110#[inline]
47111#[cfg(target_endian = "little")]
47112#[target_feature(enable = "neon")]
47113#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47114#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47115#[cfg_attr(
47116    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47117    assert_instr(nop)
47118)]
47119#[cfg_attr(
47120    not(target_arch = "arm"),
47121    stable(feature = "neon_intrinsics", since = "1.59.0")
47122)]
47123#[cfg_attr(
47124    target_arch = "arm",
47125    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47126)]
47127pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
47128    unsafe { transmute(a) }
47129}
47130#[doc = "Vector reinterpret cast operation"]
47131#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"]
47132#[inline]
47133#[cfg(target_endian = "big")]
47134#[target_feature(enable = "neon")]
47135#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47136#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47137#[cfg_attr(
47138    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47139    assert_instr(nop)
47140)]
47141#[cfg_attr(
47142    not(target_arch = "arm"),
47143    stable(feature = "neon_intrinsics", since = "1.59.0")
47144)]
47145#[cfg_attr(
47146    target_arch = "arm",
47147    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47148)]
47149pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
47150    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
47151    unsafe {
47152        let ret_val: uint64x2_t = transmute(a);
47153        simd_shuffle!(ret_val, ret_val, [1, 0])
47154    }
47155}
47156#[doc = "Vector reinterpret cast operation"]
47157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"]
47158#[inline]
47159#[cfg(target_endian = "little")]
47160#[target_feature(enable = "neon")]
47161#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47162#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47163#[cfg_attr(
47164    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47165    assert_instr(nop)
47166)]
47167#[cfg_attr(
47168    not(target_arch = "arm"),
47169    stable(feature = "neon_intrinsics", since = "1.59.0")
47170)]
47171#[cfg_attr(
47172    target_arch = "arm",
47173    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47174)]
47175pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
47176    unsafe { transmute(a) }
47177}
47178#[doc = "Vector reinterpret cast operation"]
47179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"]
47180#[inline]
47181#[cfg(target_endian = "big")]
47182#[target_feature(enable = "neon")]
47183#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47184#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47185#[cfg_attr(
47186    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47187    assert_instr(nop)
47188)]
47189#[cfg_attr(
47190    not(target_arch = "arm"),
47191    stable(feature = "neon_intrinsics", since = "1.59.0")
47192)]
47193#[cfg_attr(
47194    target_arch = "arm",
47195    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47196)]
47197pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
47198    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
47199    unsafe {
47200        let ret_val: poly8x16_t = transmute(a);
47201        simd_shuffle!(
47202            ret_val,
47203            ret_val,
47204            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
47205        )
47206    }
47207}
47208#[doc = "Vector reinterpret cast operation"]
47209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"]
47210#[inline]
47211#[cfg(target_endian = "little")]
47212#[target_feature(enable = "neon")]
47213#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47214#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47215#[cfg_attr(
47216    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47217    assert_instr(nop)
47218)]
47219#[cfg_attr(
47220    not(target_arch = "arm"),
47221    stable(feature = "neon_intrinsics", since = "1.59.0")
47222)]
47223#[cfg_attr(
47224    target_arch = "arm",
47225    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47226)]
47227pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
47228    unsafe { transmute(a) }
47229}
47230#[doc = "Vector reinterpret cast operation"]
47231#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"]
47232#[inline]
47233#[cfg(target_endian = "big")]
47234#[target_feature(enable = "neon")]
47235#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47236#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47237#[cfg_attr(
47238    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47239    assert_instr(nop)
47240)]
47241#[cfg_attr(
47242    not(target_arch = "arm"),
47243    stable(feature = "neon_intrinsics", since = "1.59.0")
47244)]
47245#[cfg_attr(
47246    target_arch = "arm",
47247    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47248)]
47249pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
47250    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
47251    unsafe {
47252        let ret_val: poly16x8_t = transmute(a);
47253        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47254    }
47255}
47256#[doc = "Vector reinterpret cast operation"]
47257#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"]
47258#[inline]
47259#[cfg(target_endian = "little")]
47260#[target_feature(enable = "neon")]
47261#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47262#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47263#[cfg_attr(
47264    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47265    assert_instr(nop)
47266)]
47267#[cfg_attr(
47268    not(target_arch = "arm"),
47269    stable(feature = "neon_intrinsics", since = "1.59.0")
47270)]
47271#[cfg_attr(
47272    target_arch = "arm",
47273    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47274)]
47275pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
47276    unsafe { transmute(a) }
47277}
47278#[doc = "Vector reinterpret cast operation"]
47279#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"]
47280#[inline]
47281#[cfg(target_endian = "big")]
47282#[target_feature(enable = "neon")]
47283#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47284#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47285#[cfg_attr(
47286    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47287    assert_instr(nop)
47288)]
47289#[cfg_attr(
47290    not(target_arch = "arm"),
47291    stable(feature = "neon_intrinsics", since = "1.59.0")
47292)]
47293#[cfg_attr(
47294    target_arch = "arm",
47295    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47296)]
47297pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
47298    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47299    unsafe {
47300        let ret_val: float32x2_t = transmute(a);
47301        simd_shuffle!(ret_val, ret_val, [1, 0])
47302    }
47303}
47304#[doc = "Vector reinterpret cast operation"]
47305#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"]
47306#[inline]
47307#[cfg(target_endian = "little")]
47308#[target_feature(enable = "neon")]
47309#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47310#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47311#[cfg_attr(
47312    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47313    assert_instr(nop)
47314)]
47315#[cfg_attr(
47316    not(target_arch = "arm"),
47317    stable(feature = "neon_intrinsics", since = "1.59.0")
47318)]
47319#[cfg_attr(
47320    target_arch = "arm",
47321    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47322)]
47323pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
47324    unsafe { transmute(a) }
47325}
47326#[doc = "Vector reinterpret cast operation"]
47327#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"]
47328#[inline]
47329#[cfg(target_endian = "big")]
47330#[target_feature(enable = "neon")]
47331#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47332#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47333#[cfg_attr(
47334    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47335    assert_instr(nop)
47336)]
47337#[cfg_attr(
47338    not(target_arch = "arm"),
47339    stable(feature = "neon_intrinsics", since = "1.59.0")
47340)]
47341#[cfg_attr(
47342    target_arch = "arm",
47343    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47344)]
47345pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
47346    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47347    unsafe {
47348        let ret_val: int8x8_t = transmute(a);
47349        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47350    }
47351}
47352#[doc = "Vector reinterpret cast operation"]
47353#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"]
47354#[inline]
47355#[cfg(target_endian = "little")]
47356#[target_feature(enable = "neon")]
47357#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47358#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47359#[cfg_attr(
47360    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47361    assert_instr(nop)
47362)]
47363#[cfg_attr(
47364    not(target_arch = "arm"),
47365    stable(feature = "neon_intrinsics", since = "1.59.0")
47366)]
47367#[cfg_attr(
47368    target_arch = "arm",
47369    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47370)]
47371pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
47372    unsafe { transmute(a) }
47373}
47374#[doc = "Vector reinterpret cast operation"]
47375#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"]
47376#[inline]
47377#[cfg(target_endian = "big")]
47378#[target_feature(enable = "neon")]
47379#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47380#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47381#[cfg_attr(
47382    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47383    assert_instr(nop)
47384)]
47385#[cfg_attr(
47386    not(target_arch = "arm"),
47387    stable(feature = "neon_intrinsics", since = "1.59.0")
47388)]
47389#[cfg_attr(
47390    target_arch = "arm",
47391    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47392)]
47393pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
47394    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47395    unsafe {
47396        let ret_val: int16x4_t = transmute(a);
47397        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47398    }
47399}
47400#[doc = "Vector reinterpret cast operation"]
47401#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"]
47402#[inline]
47403#[cfg(target_endian = "little")]
47404#[target_feature(enable = "neon")]
47405#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47406#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47407#[cfg_attr(
47408    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47409    assert_instr(nop)
47410)]
47411#[cfg_attr(
47412    not(target_arch = "arm"),
47413    stable(feature = "neon_intrinsics", since = "1.59.0")
47414)]
47415#[cfg_attr(
47416    target_arch = "arm",
47417    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47418)]
47419pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
47420    unsafe { transmute(a) }
47421}
47422#[doc = "Vector reinterpret cast operation"]
47423#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"]
47424#[inline]
47425#[cfg(target_endian = "big")]
47426#[target_feature(enable = "neon")]
47427#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47428#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47429#[cfg_attr(
47430    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47431    assert_instr(nop)
47432)]
47433#[cfg_attr(
47434    not(target_arch = "arm"),
47435    stable(feature = "neon_intrinsics", since = "1.59.0")
47436)]
47437#[cfg_attr(
47438    target_arch = "arm",
47439    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47440)]
47441pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
47442    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47443    unsafe { transmute(a) }
47444}
47445#[doc = "Vector reinterpret cast operation"]
47446#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"]
47447#[inline]
47448#[cfg(target_endian = "little")]
47449#[target_feature(enable = "neon")]
47450#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47451#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47452#[cfg_attr(
47453    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47454    assert_instr(nop)
47455)]
47456#[cfg_attr(
47457    not(target_arch = "arm"),
47458    stable(feature = "neon_intrinsics", since = "1.59.0")
47459)]
47460#[cfg_attr(
47461    target_arch = "arm",
47462    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47463)]
47464pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
47465    unsafe { transmute(a) }
47466}
47467#[doc = "Vector reinterpret cast operation"]
47468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"]
47469#[inline]
47470#[cfg(target_endian = "big")]
47471#[target_feature(enable = "neon")]
47472#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47473#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47474#[cfg_attr(
47475    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47476    assert_instr(nop)
47477)]
47478#[cfg_attr(
47479    not(target_arch = "arm"),
47480    stable(feature = "neon_intrinsics", since = "1.59.0")
47481)]
47482#[cfg_attr(
47483    target_arch = "arm",
47484    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47485)]
47486pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
47487    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47488    unsafe {
47489        let ret_val: uint8x8_t = transmute(a);
47490        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47491    }
47492}
47493#[doc = "Vector reinterpret cast operation"]
47494#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"]
47495#[inline]
47496#[cfg(target_endian = "little")]
47497#[target_feature(enable = "neon")]
47498#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47499#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47500#[cfg_attr(
47501    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47502    assert_instr(nop)
47503)]
47504#[cfg_attr(
47505    not(target_arch = "arm"),
47506    stable(feature = "neon_intrinsics", since = "1.59.0")
47507)]
47508#[cfg_attr(
47509    target_arch = "arm",
47510    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47511)]
47512pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
47513    unsafe { transmute(a) }
47514}
47515#[doc = "Vector reinterpret cast operation"]
47516#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"]
47517#[inline]
47518#[cfg(target_endian = "big")]
47519#[target_feature(enable = "neon")]
47520#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47521#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47522#[cfg_attr(
47523    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47524    assert_instr(nop)
47525)]
47526#[cfg_attr(
47527    not(target_arch = "arm"),
47528    stable(feature = "neon_intrinsics", since = "1.59.0")
47529)]
47530#[cfg_attr(
47531    target_arch = "arm",
47532    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47533)]
47534pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
47535    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47536    unsafe {
47537        let ret_val: uint16x4_t = transmute(a);
47538        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47539    }
47540}
47541#[doc = "Vector reinterpret cast operation"]
47542#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"]
47543#[inline]
47544#[cfg(target_endian = "little")]
47545#[target_feature(enable = "neon")]
47546#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47547#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47548#[cfg_attr(
47549    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47550    assert_instr(nop)
47551)]
47552#[cfg_attr(
47553    not(target_arch = "arm"),
47554    stable(feature = "neon_intrinsics", since = "1.59.0")
47555)]
47556#[cfg_attr(
47557    target_arch = "arm",
47558    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47559)]
47560pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
47561    unsafe { transmute(a) }
47562}
47563#[doc = "Vector reinterpret cast operation"]
47564#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"]
47565#[inline]
47566#[cfg(target_endian = "big")]
47567#[target_feature(enable = "neon")]
47568#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47569#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47570#[cfg_attr(
47571    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47572    assert_instr(nop)
47573)]
47574#[cfg_attr(
47575    not(target_arch = "arm"),
47576    stable(feature = "neon_intrinsics", since = "1.59.0")
47577)]
47578#[cfg_attr(
47579    target_arch = "arm",
47580    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47581)]
47582pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
47583    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47584    unsafe {
47585        let ret_val: uint32x2_t = transmute(a);
47586        simd_shuffle!(ret_val, ret_val, [1, 0])
47587    }
47588}
47589#[doc = "Vector reinterpret cast operation"]
47590#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"]
47591#[inline]
47592#[cfg(target_endian = "little")]
47593#[target_feature(enable = "neon")]
47594#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47595#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47596#[cfg_attr(
47597    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47598    assert_instr(nop)
47599)]
47600#[cfg_attr(
47601    not(target_arch = "arm"),
47602    stable(feature = "neon_intrinsics", since = "1.59.0")
47603)]
47604#[cfg_attr(
47605    target_arch = "arm",
47606    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47607)]
47608pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
47609    unsafe { transmute(a) }
47610}
47611#[doc = "Vector reinterpret cast operation"]
47612#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"]
47613#[inline]
47614#[cfg(target_endian = "big")]
47615#[target_feature(enable = "neon")]
47616#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47617#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47618#[cfg_attr(
47619    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47620    assert_instr(nop)
47621)]
47622#[cfg_attr(
47623    not(target_arch = "arm"),
47624    stable(feature = "neon_intrinsics", since = "1.59.0")
47625)]
47626#[cfg_attr(
47627    target_arch = "arm",
47628    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47629)]
47630pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
47631    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47632    unsafe { transmute(a) }
47633}
47634#[doc = "Vector reinterpret cast operation"]
47635#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"]
47636#[inline]
47637#[cfg(target_endian = "little")]
47638#[target_feature(enable = "neon")]
47639#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47640#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47641#[cfg_attr(
47642    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47643    assert_instr(nop)
47644)]
47645#[cfg_attr(
47646    not(target_arch = "arm"),
47647    stable(feature = "neon_intrinsics", since = "1.59.0")
47648)]
47649#[cfg_attr(
47650    target_arch = "arm",
47651    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47652)]
47653pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
47654    unsafe { transmute(a) }
47655}
47656#[doc = "Vector reinterpret cast operation"]
47657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"]
47658#[inline]
47659#[cfg(target_endian = "big")]
47660#[target_feature(enable = "neon")]
47661#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47662#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47663#[cfg_attr(
47664    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47665    assert_instr(nop)
47666)]
47667#[cfg_attr(
47668    not(target_arch = "arm"),
47669    stable(feature = "neon_intrinsics", since = "1.59.0")
47670)]
47671#[cfg_attr(
47672    target_arch = "arm",
47673    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47674)]
47675pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
47676    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47677    unsafe {
47678        let ret_val: poly8x8_t = transmute(a);
47679        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47680    }
47681}
47682#[doc = "Vector reinterpret cast operation"]
47683#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"]
47684#[inline]
47685#[cfg(target_endian = "little")]
47686#[target_feature(enable = "neon")]
47687#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47688#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47689#[cfg_attr(
47690    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47691    assert_instr(nop)
47692)]
47693#[cfg_attr(
47694    not(target_arch = "arm"),
47695    stable(feature = "neon_intrinsics", since = "1.59.0")
47696)]
47697#[cfg_attr(
47698    target_arch = "arm",
47699    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47700)]
47701pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
47702    unsafe { transmute(a) }
47703}
47704#[doc = "Vector reinterpret cast operation"]
47705#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"]
47706#[inline]
47707#[cfg(target_endian = "big")]
47708#[target_feature(enable = "neon")]
47709#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47710#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47711#[cfg_attr(
47712    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47713    assert_instr(nop)
47714)]
47715#[cfg_attr(
47716    not(target_arch = "arm"),
47717    stable(feature = "neon_intrinsics", since = "1.59.0")
47718)]
47719#[cfg_attr(
47720    target_arch = "arm",
47721    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47722)]
47723pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
47724    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47725    unsafe {
47726        let ret_val: poly16x4_t = transmute(a);
47727        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47728    }
47729}
47730#[doc = "Vector reinterpret cast operation"]
47731#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"]
47732#[inline]
47733#[cfg(target_endian = "little")]
47734#[target_feature(enable = "neon")]
47735#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47736#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47737#[cfg_attr(
47738    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47739    assert_instr(nop)
47740)]
47741#[cfg_attr(
47742    not(target_arch = "arm"),
47743    stable(feature = "neon_intrinsics", since = "1.59.0")
47744)]
47745#[cfg_attr(
47746    target_arch = "arm",
47747    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47748)]
47749pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
47750    unsafe { transmute(a) }
47751}
47752#[doc = "Vector reinterpret cast operation"]
47753#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"]
47754#[inline]
47755#[cfg(target_endian = "big")]
47756#[target_feature(enable = "neon")]
47757#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47758#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47759#[cfg_attr(
47760    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47761    assert_instr(nop)
47762)]
47763#[cfg_attr(
47764    not(target_arch = "arm"),
47765    stable(feature = "neon_intrinsics", since = "1.59.0")
47766)]
47767#[cfg_attr(
47768    target_arch = "arm",
47769    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47770)]
47771pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
47772    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47773    unsafe {
47774        let ret_val: float32x4_t = transmute(a);
47775        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47776    }
47777}
47778#[doc = "Vector reinterpret cast operation"]
47779#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"]
47780#[inline]
47781#[cfg(target_endian = "little")]
47782#[target_feature(enable = "neon")]
47783#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47784#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47785#[cfg_attr(
47786    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47787    assert_instr(nop)
47788)]
47789#[cfg_attr(
47790    not(target_arch = "arm"),
47791    stable(feature = "neon_intrinsics", since = "1.59.0")
47792)]
47793#[cfg_attr(
47794    target_arch = "arm",
47795    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47796)]
47797pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
47798    unsafe { transmute(a) }
47799}
47800#[doc = "Vector reinterpret cast operation"]
47801#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"]
47802#[inline]
47803#[cfg(target_endian = "big")]
47804#[target_feature(enable = "neon")]
47805#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47806#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47807#[cfg_attr(
47808    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47809    assert_instr(nop)
47810)]
47811#[cfg_attr(
47812    not(target_arch = "arm"),
47813    stable(feature = "neon_intrinsics", since = "1.59.0")
47814)]
47815#[cfg_attr(
47816    target_arch = "arm",
47817    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47818)]
47819pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
47820    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47821    unsafe {
47822        let ret_val: int8x16_t = transmute(a);
47823        simd_shuffle!(
47824            ret_val,
47825            ret_val,
47826            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
47827        )
47828    }
47829}
47830#[doc = "Vector reinterpret cast operation"]
47831#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"]
47832#[inline]
47833#[cfg(target_endian = "little")]
47834#[target_feature(enable = "neon")]
47835#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47836#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47837#[cfg_attr(
47838    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47839    assert_instr(nop)
47840)]
47841#[cfg_attr(
47842    not(target_arch = "arm"),
47843    stable(feature = "neon_intrinsics", since = "1.59.0")
47844)]
47845#[cfg_attr(
47846    target_arch = "arm",
47847    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47848)]
47849pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
47850    unsafe { transmute(a) }
47851}
47852#[doc = "Vector reinterpret cast operation"]
47853#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"]
47854#[inline]
47855#[cfg(target_endian = "big")]
47856#[target_feature(enable = "neon")]
47857#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47858#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47859#[cfg_attr(
47860    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47861    assert_instr(nop)
47862)]
47863#[cfg_attr(
47864    not(target_arch = "arm"),
47865    stable(feature = "neon_intrinsics", since = "1.59.0")
47866)]
47867#[cfg_attr(
47868    target_arch = "arm",
47869    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47870)]
47871pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
47872    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47873    unsafe {
47874        let ret_val: int16x8_t = transmute(a);
47875        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47876    }
47877}
47878#[doc = "Vector reinterpret cast operation"]
47879#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"]
47880#[inline]
47881#[cfg(target_endian = "little")]
47882#[target_feature(enable = "neon")]
47883#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47884#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47885#[cfg_attr(
47886    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47887    assert_instr(nop)
47888)]
47889#[cfg_attr(
47890    not(target_arch = "arm"),
47891    stable(feature = "neon_intrinsics", since = "1.59.0")
47892)]
47893#[cfg_attr(
47894    target_arch = "arm",
47895    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47896)]
47897pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
47898    unsafe { transmute(a) }
47899}
47900#[doc = "Vector reinterpret cast operation"]
47901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"]
47902#[inline]
47903#[cfg(target_endian = "big")]
47904#[target_feature(enable = "neon")]
47905#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47906#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47907#[cfg_attr(
47908    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47909    assert_instr(nop)
47910)]
47911#[cfg_attr(
47912    not(target_arch = "arm"),
47913    stable(feature = "neon_intrinsics", since = "1.59.0")
47914)]
47915#[cfg_attr(
47916    target_arch = "arm",
47917    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47918)]
47919pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
47920    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47921    unsafe {
47922        let ret_val: int64x2_t = transmute(a);
47923        simd_shuffle!(ret_val, ret_val, [1, 0])
47924    }
47925}
47926#[doc = "Vector reinterpret cast operation"]
47927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"]
47928#[inline]
47929#[cfg(target_endian = "little")]
47930#[target_feature(enable = "neon")]
47931#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47932#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47933#[cfg_attr(
47934    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47935    assert_instr(nop)
47936)]
47937#[cfg_attr(
47938    not(target_arch = "arm"),
47939    stable(feature = "neon_intrinsics", since = "1.59.0")
47940)]
47941#[cfg_attr(
47942    target_arch = "arm",
47943    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47944)]
47945pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
47946    unsafe { transmute(a) }
47947}
47948#[doc = "Vector reinterpret cast operation"]
47949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"]
47950#[inline]
47951#[cfg(target_endian = "big")]
47952#[target_feature(enable = "neon")]
47953#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47954#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47955#[cfg_attr(
47956    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47957    assert_instr(nop)
47958)]
47959#[cfg_attr(
47960    not(target_arch = "arm"),
47961    stable(feature = "neon_intrinsics", since = "1.59.0")
47962)]
47963#[cfg_attr(
47964    target_arch = "arm",
47965    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47966)]
47967pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
47968    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47969    unsafe {
47970        let ret_val: uint8x16_t = transmute(a);
47971        simd_shuffle!(
47972            ret_val,
47973            ret_val,
47974            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
47975        )
47976    }
47977}
47978#[doc = "Vector reinterpret cast operation"]
47979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"]
47980#[inline]
47981#[cfg(target_endian = "little")]
47982#[target_feature(enable = "neon")]
47983#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47984#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47985#[cfg_attr(
47986    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47987    assert_instr(nop)
47988)]
47989#[cfg_attr(
47990    not(target_arch = "arm"),
47991    stable(feature = "neon_intrinsics", since = "1.59.0")
47992)]
47993#[cfg_attr(
47994    target_arch = "arm",
47995    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47996)]
47997pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
47998    unsafe { transmute(a) }
47999}
48000#[doc = "Vector reinterpret cast operation"]
48001#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"]
48002#[inline]
48003#[cfg(target_endian = "big")]
48004#[target_feature(enable = "neon")]
48005#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48006#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48007#[cfg_attr(
48008    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48009    assert_instr(nop)
48010)]
48011#[cfg_attr(
48012    not(target_arch = "arm"),
48013    stable(feature = "neon_intrinsics", since = "1.59.0")
48014)]
48015#[cfg_attr(
48016    target_arch = "arm",
48017    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48018)]
48019pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
48020    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
48021    unsafe {
48022        let ret_val: uint16x8_t = transmute(a);
48023        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48024    }
48025}
48026#[doc = "Vector reinterpret cast operation"]
48027#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"]
48028#[inline]
48029#[cfg(target_endian = "little")]
48030#[target_feature(enable = "neon")]
48031#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48032#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48033#[cfg_attr(
48034    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48035    assert_instr(nop)
48036)]
48037#[cfg_attr(
48038    not(target_arch = "arm"),
48039    stable(feature = "neon_intrinsics", since = "1.59.0")
48040)]
48041#[cfg_attr(
48042    target_arch = "arm",
48043    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48044)]
48045pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
48046    unsafe { transmute(a) }
48047}
48048#[doc = "Vector reinterpret cast operation"]
48049#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"]
48050#[inline]
48051#[cfg(target_endian = "big")]
48052#[target_feature(enable = "neon")]
48053#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48054#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48055#[cfg_attr(
48056    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48057    assert_instr(nop)
48058)]
48059#[cfg_attr(
48060    not(target_arch = "arm"),
48061    stable(feature = "neon_intrinsics", since = "1.59.0")
48062)]
48063#[cfg_attr(
48064    target_arch = "arm",
48065    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48066)]
48067pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
48068    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
48069    unsafe {
48070        let ret_val: uint32x4_t = transmute(a);
48071        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48072    }
48073}
48074#[doc = "Vector reinterpret cast operation"]
48075#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"]
48076#[inline]
48077#[cfg(target_endian = "little")]
48078#[target_feature(enable = "neon")]
48079#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48080#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48081#[cfg_attr(
48082    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48083    assert_instr(nop)
48084)]
48085#[cfg_attr(
48086    not(target_arch = "arm"),
48087    stable(feature = "neon_intrinsics", since = "1.59.0")
48088)]
48089#[cfg_attr(
48090    target_arch = "arm",
48091    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48092)]
48093pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
48094    unsafe { transmute(a) }
48095}
48096#[doc = "Vector reinterpret cast operation"]
48097#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"]
48098#[inline]
48099#[cfg(target_endian = "big")]
48100#[target_feature(enable = "neon")]
48101#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48102#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48103#[cfg_attr(
48104    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48105    assert_instr(nop)
48106)]
48107#[cfg_attr(
48108    not(target_arch = "arm"),
48109    stable(feature = "neon_intrinsics", since = "1.59.0")
48110)]
48111#[cfg_attr(
48112    target_arch = "arm",
48113    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48114)]
48115pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
48116    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
48117    unsafe {
48118        let ret_val: uint64x2_t = transmute(a);
48119        simd_shuffle!(ret_val, ret_val, [1, 0])
48120    }
48121}
48122#[doc = "Vector reinterpret cast operation"]
48123#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"]
48124#[inline]
48125#[cfg(target_endian = "little")]
48126#[target_feature(enable = "neon")]
48127#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48128#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48129#[cfg_attr(
48130    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48131    assert_instr(nop)
48132)]
48133#[cfg_attr(
48134    not(target_arch = "arm"),
48135    stable(feature = "neon_intrinsics", since = "1.59.0")
48136)]
48137#[cfg_attr(
48138    target_arch = "arm",
48139    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48140)]
48141pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
48142    unsafe { transmute(a) }
48143}
48144#[doc = "Vector reinterpret cast operation"]
48145#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"]
48146#[inline]
48147#[cfg(target_endian = "big")]
48148#[target_feature(enable = "neon")]
48149#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48150#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48151#[cfg_attr(
48152    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48153    assert_instr(nop)
48154)]
48155#[cfg_attr(
48156    not(target_arch = "arm"),
48157    stable(feature = "neon_intrinsics", since = "1.59.0")
48158)]
48159#[cfg_attr(
48160    target_arch = "arm",
48161    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48162)]
48163pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
48164    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
48165    unsafe {
48166        let ret_val: poly8x16_t = transmute(a);
48167        simd_shuffle!(
48168            ret_val,
48169            ret_val,
48170            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
48171        )
48172    }
48173}
48174#[doc = "Vector reinterpret cast operation"]
48175#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"]
48176#[inline]
48177#[cfg(target_endian = "little")]
48178#[target_feature(enable = "neon")]
48179#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48180#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48181#[cfg_attr(
48182    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48183    assert_instr(nop)
48184)]
48185#[cfg_attr(
48186    not(target_arch = "arm"),
48187    stable(feature = "neon_intrinsics", since = "1.59.0")
48188)]
48189#[cfg_attr(
48190    target_arch = "arm",
48191    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48192)]
48193pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
48194    unsafe { transmute(a) }
48195}
48196#[doc = "Vector reinterpret cast operation"]
48197#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"]
48198#[inline]
48199#[cfg(target_endian = "big")]
48200#[target_feature(enable = "neon")]
48201#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48202#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48203#[cfg_attr(
48204    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48205    assert_instr(nop)
48206)]
48207#[cfg_attr(
48208    not(target_arch = "arm"),
48209    stable(feature = "neon_intrinsics", since = "1.59.0")
48210)]
48211#[cfg_attr(
48212    target_arch = "arm",
48213    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48214)]
48215pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
48216    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
48217    unsafe {
48218        let ret_val: poly16x8_t = transmute(a);
48219        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48220    }
48221}
48222#[doc = "Vector reinterpret cast operation"]
48223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"]
48224#[inline]
48225#[cfg(target_endian = "little")]
48226#[target_feature(enable = "neon")]
48227#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48228#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48229#[cfg_attr(
48230    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48231    assert_instr(nop)
48232)]
48233#[cfg_attr(
48234    not(target_arch = "arm"),
48235    stable(feature = "neon_intrinsics", since = "1.59.0")
48236)]
48237#[cfg_attr(
48238    target_arch = "arm",
48239    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48240)]
48241pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
48242    unsafe { transmute(a) }
48243}
48244#[doc = "Vector reinterpret cast operation"]
48245#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"]
48246#[inline]
48247#[cfg(target_endian = "big")]
48248#[target_feature(enable = "neon")]
48249#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48250#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48251#[cfg_attr(
48252    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48253    assert_instr(nop)
48254)]
48255#[cfg_attr(
48256    not(target_arch = "arm"),
48257    stable(feature = "neon_intrinsics", since = "1.59.0")
48258)]
48259#[cfg_attr(
48260    target_arch = "arm",
48261    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48262)]
48263pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
48264    unsafe {
48265        let ret_val: float32x2_t = transmute(a);
48266        simd_shuffle!(ret_val, ret_val, [1, 0])
48267    }
48268}
48269#[doc = "Vector reinterpret cast operation"]
48270#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"]
48271#[inline]
48272#[cfg(target_endian = "little")]
48273#[target_feature(enable = "neon")]
48274#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48275#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48276#[cfg_attr(
48277    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48278    assert_instr(nop)
48279)]
48280#[cfg_attr(
48281    not(target_arch = "arm"),
48282    stable(feature = "neon_intrinsics", since = "1.59.0")
48283)]
48284#[cfg_attr(
48285    target_arch = "arm",
48286    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48287)]
48288pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
48289    unsafe { transmute(a) }
48290}
48291#[doc = "Vector reinterpret cast operation"]
48292#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"]
48293#[inline]
48294#[cfg(target_endian = "big")]
48295#[target_feature(enable = "neon")]
48296#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48297#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48298#[cfg_attr(
48299    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48300    assert_instr(nop)
48301)]
48302#[cfg_attr(
48303    not(target_arch = "arm"),
48304    stable(feature = "neon_intrinsics", since = "1.59.0")
48305)]
48306#[cfg_attr(
48307    target_arch = "arm",
48308    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48309)]
48310pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
48311    unsafe {
48312        let ret_val: int8x8_t = transmute(a);
48313        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48314    }
48315}
48316#[doc = "Vector reinterpret cast operation"]
48317#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"]
48318#[inline]
48319#[cfg(target_endian = "little")]
48320#[target_feature(enable = "neon")]
48321#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48322#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48323#[cfg_attr(
48324    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48325    assert_instr(nop)
48326)]
48327#[cfg_attr(
48328    not(target_arch = "arm"),
48329    stable(feature = "neon_intrinsics", since = "1.59.0")
48330)]
48331#[cfg_attr(
48332    target_arch = "arm",
48333    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48334)]
48335pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
48336    unsafe { transmute(a) }
48337}
48338#[doc = "Vector reinterpret cast operation"]
48339#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"]
48340#[inline]
48341#[cfg(target_endian = "big")]
48342#[target_feature(enable = "neon")]
48343#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48344#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48345#[cfg_attr(
48346    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48347    assert_instr(nop)
48348)]
48349#[cfg_attr(
48350    not(target_arch = "arm"),
48351    stable(feature = "neon_intrinsics", since = "1.59.0")
48352)]
48353#[cfg_attr(
48354    target_arch = "arm",
48355    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48356)]
48357pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
48358    unsafe {
48359        let ret_val: int16x4_t = transmute(a);
48360        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48361    }
48362}
48363#[doc = "Vector reinterpret cast operation"]
48364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"]
48365#[inline]
48366#[cfg(target_endian = "little")]
48367#[target_feature(enable = "neon")]
48368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48369#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48370#[cfg_attr(
48371    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48372    assert_instr(nop)
48373)]
48374#[cfg_attr(
48375    not(target_arch = "arm"),
48376    stable(feature = "neon_intrinsics", since = "1.59.0")
48377)]
48378#[cfg_attr(
48379    target_arch = "arm",
48380    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48381)]
48382pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
48383    unsafe { transmute(a) }
48384}
48385#[doc = "Vector reinterpret cast operation"]
48386#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"]
48387#[inline]
48388#[cfg(target_endian = "big")]
48389#[target_feature(enable = "neon")]
48390#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48391#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48392#[cfg_attr(
48393    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48394    assert_instr(nop)
48395)]
48396#[cfg_attr(
48397    not(target_arch = "arm"),
48398    stable(feature = "neon_intrinsics", since = "1.59.0")
48399)]
48400#[cfg_attr(
48401    target_arch = "arm",
48402    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48403)]
48404pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
48405    unsafe {
48406        let ret_val: int32x2_t = transmute(a);
48407        simd_shuffle!(ret_val, ret_val, [1, 0])
48408    }
48409}
48410#[doc = "Vector reinterpret cast operation"]
48411#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"]
48412#[inline]
48413#[cfg(target_endian = "little")]
48414#[target_feature(enable = "neon")]
48415#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48416#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48417#[cfg_attr(
48418    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48419    assert_instr(nop)
48420)]
48421#[cfg_attr(
48422    not(target_arch = "arm"),
48423    stable(feature = "neon_intrinsics", since = "1.59.0")
48424)]
48425#[cfg_attr(
48426    target_arch = "arm",
48427    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48428)]
48429pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
48430    unsafe { transmute(a) }
48431}
48432#[doc = "Vector reinterpret cast operation"]
48433#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"]
48434#[inline]
48435#[cfg(target_endian = "big")]
48436#[target_feature(enable = "neon")]
48437#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48438#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48439#[cfg_attr(
48440    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48441    assert_instr(nop)
48442)]
48443#[cfg_attr(
48444    not(target_arch = "arm"),
48445    stable(feature = "neon_intrinsics", since = "1.59.0")
48446)]
48447#[cfg_attr(
48448    target_arch = "arm",
48449    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48450)]
48451pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
48452    unsafe {
48453        let ret_val: uint8x8_t = transmute(a);
48454        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48455    }
48456}
48457#[doc = "Vector reinterpret cast operation"]
48458#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"]
48459#[inline]
48460#[cfg(target_endian = "little")]
48461#[target_feature(enable = "neon")]
48462#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48463#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48464#[cfg_attr(
48465    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48466    assert_instr(nop)
48467)]
48468#[cfg_attr(
48469    not(target_arch = "arm"),
48470    stable(feature = "neon_intrinsics", since = "1.59.0")
48471)]
48472#[cfg_attr(
48473    target_arch = "arm",
48474    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48475)]
48476pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
48477    unsafe { transmute(a) }
48478}
48479#[doc = "Vector reinterpret cast operation"]
48480#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"]
48481#[inline]
48482#[cfg(target_endian = "big")]
48483#[target_feature(enable = "neon")]
48484#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48485#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48486#[cfg_attr(
48487    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48488    assert_instr(nop)
48489)]
48490#[cfg_attr(
48491    not(target_arch = "arm"),
48492    stable(feature = "neon_intrinsics", since = "1.59.0")
48493)]
48494#[cfg_attr(
48495    target_arch = "arm",
48496    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48497)]
48498pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
48499    unsafe {
48500        let ret_val: uint16x4_t = transmute(a);
48501        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48502    }
48503}
48504#[doc = "Vector reinterpret cast operation"]
48505#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"]
48506#[inline]
48507#[cfg(target_endian = "little")]
48508#[target_feature(enable = "neon")]
48509#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48510#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48511#[cfg_attr(
48512    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48513    assert_instr(nop)
48514)]
48515#[cfg_attr(
48516    not(target_arch = "arm"),
48517    stable(feature = "neon_intrinsics", since = "1.59.0")
48518)]
48519#[cfg_attr(
48520    target_arch = "arm",
48521    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48522)]
48523pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t {
48524    unsafe { transmute(a) }
48525}
48526#[doc = "Vector reinterpret cast operation"]
48527#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"]
48528#[inline]
48529#[cfg(target_endian = "big")]
48530#[target_feature(enable = "neon")]
48531#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48532#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48533#[cfg_attr(
48534    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48535    assert_instr(nop)
48536)]
48537#[cfg_attr(
48538    not(target_arch = "arm"),
48539    stable(feature = "neon_intrinsics", since = "1.59.0")
48540)]
48541#[cfg_attr(
48542    target_arch = "arm",
48543    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48544)]
48545pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t {
48546    unsafe {
48547        let ret_val: uint32x2_t = transmute(a);
48548        simd_shuffle!(ret_val, ret_val, [1, 0])
48549    }
48550}
48551#[doc = "Vector reinterpret cast operation"]
48552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s64)"]
48553#[inline]
48554#[target_feature(enable = "neon")]
48555#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48556#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48557#[cfg_attr(
48558    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48559    assert_instr(nop)
48560)]
48561#[cfg_attr(
48562    not(target_arch = "arm"),
48563    stable(feature = "neon_intrinsics", since = "1.59.0")
48564)]
48565#[cfg_attr(
48566    target_arch = "arm",
48567    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48568)]
48569pub fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t {
48570    unsafe { transmute(a) }
48571}
48572#[doc = "Vector reinterpret cast operation"]
48573#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"]
48574#[inline]
48575#[cfg(target_endian = "little")]
48576#[target_feature(enable = "neon")]
48577#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48578#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48579#[cfg_attr(
48580    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48581    assert_instr(nop)
48582)]
48583#[cfg_attr(
48584    not(target_arch = "arm"),
48585    stable(feature = "neon_intrinsics", since = "1.59.0")
48586)]
48587#[cfg_attr(
48588    target_arch = "arm",
48589    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48590)]
48591pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
48592    unsafe { transmute(a) }
48593}
48594#[doc = "Vector reinterpret cast operation"]
48595#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"]
48596#[inline]
48597#[cfg(target_endian = "big")]
48598#[target_feature(enable = "neon")]
48599#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48600#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48601#[cfg_attr(
48602    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48603    assert_instr(nop)
48604)]
48605#[cfg_attr(
48606    not(target_arch = "arm"),
48607    stable(feature = "neon_intrinsics", since = "1.59.0")
48608)]
48609#[cfg_attr(
48610    target_arch = "arm",
48611    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48612)]
48613pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
48614    unsafe {
48615        let ret_val: poly8x8_t = transmute(a);
48616        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48617    }
48618}
48619#[doc = "Vector reinterpret cast operation"]
48620#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"]
48621#[inline]
48622#[cfg(target_endian = "little")]
48623#[target_feature(enable = "neon")]
48624#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48625#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48626#[cfg_attr(
48627    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48628    assert_instr(nop)
48629)]
48630#[cfg_attr(
48631    not(target_arch = "arm"),
48632    stable(feature = "neon_intrinsics", since = "1.59.0")
48633)]
48634#[cfg_attr(
48635    target_arch = "arm",
48636    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48637)]
48638pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
48639    unsafe { transmute(a) }
48640}
48641#[doc = "Vector reinterpret cast operation"]
48642#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"]
48643#[inline]
48644#[cfg(target_endian = "big")]
48645#[target_feature(enable = "neon")]
48646#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48647#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48648#[cfg_attr(
48649    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48650    assert_instr(nop)
48651)]
48652#[cfg_attr(
48653    not(target_arch = "arm"),
48654    stable(feature = "neon_intrinsics", since = "1.59.0")
48655)]
48656#[cfg_attr(
48657    target_arch = "arm",
48658    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48659)]
48660pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
48661    unsafe {
48662        let ret_val: poly16x4_t = transmute(a);
48663        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48664    }
48665}
48666#[doc = "Vector reinterpret cast operation"]
48667#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"]
48668#[inline]
48669#[cfg(target_endian = "little")]
48670#[target_feature(enable = "neon")]
48671#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48672#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48673#[cfg_attr(
48674    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48675    assert_instr(nop)
48676)]
48677#[cfg_attr(
48678    not(target_arch = "arm"),
48679    stable(feature = "neon_intrinsics", since = "1.59.0")
48680)]
48681#[cfg_attr(
48682    target_arch = "arm",
48683    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48684)]
48685pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
48686    unsafe { transmute(a) }
48687}
48688#[doc = "Vector reinterpret cast operation"]
48689#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"]
48690#[inline]
48691#[cfg(target_endian = "big")]
48692#[target_feature(enable = "neon")]
48693#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48694#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48695#[cfg_attr(
48696    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48697    assert_instr(nop)
48698)]
48699#[cfg_attr(
48700    not(target_arch = "arm"),
48701    stable(feature = "neon_intrinsics", since = "1.59.0")
48702)]
48703#[cfg_attr(
48704    target_arch = "arm",
48705    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48706)]
48707pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
48708    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48709    unsafe {
48710        let ret_val: float32x4_t = transmute(a);
48711        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48712    }
48713}
48714#[doc = "Vector reinterpret cast operation"]
48715#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"]
48716#[inline]
48717#[cfg(target_endian = "little")]
48718#[target_feature(enable = "neon")]
48719#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48720#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48721#[cfg_attr(
48722    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48723    assert_instr(nop)
48724)]
48725#[cfg_attr(
48726    not(target_arch = "arm"),
48727    stable(feature = "neon_intrinsics", since = "1.59.0")
48728)]
48729#[cfg_attr(
48730    target_arch = "arm",
48731    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48732)]
48733pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
48734    unsafe { transmute(a) }
48735}
48736#[doc = "Vector reinterpret cast operation"]
48737#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"]
48738#[inline]
48739#[cfg(target_endian = "big")]
48740#[target_feature(enable = "neon")]
48741#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48742#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48743#[cfg_attr(
48744    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48745    assert_instr(nop)
48746)]
48747#[cfg_attr(
48748    not(target_arch = "arm"),
48749    stable(feature = "neon_intrinsics", since = "1.59.0")
48750)]
48751#[cfg_attr(
48752    target_arch = "arm",
48753    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48754)]
48755pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
48756    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48757    unsafe {
48758        let ret_val: int8x16_t = transmute(a);
48759        simd_shuffle!(
48760            ret_val,
48761            ret_val,
48762            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
48763        )
48764    }
48765}
48766#[doc = "Vector reinterpret cast operation"]
48767#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"]
48768#[inline]
48769#[cfg(target_endian = "little")]
48770#[target_feature(enable = "neon")]
48771#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48772#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48773#[cfg_attr(
48774    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48775    assert_instr(nop)
48776)]
48777#[cfg_attr(
48778    not(target_arch = "arm"),
48779    stable(feature = "neon_intrinsics", since = "1.59.0")
48780)]
48781#[cfg_attr(
48782    target_arch = "arm",
48783    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48784)]
48785pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
48786    unsafe { transmute(a) }
48787}
48788#[doc = "Vector reinterpret cast operation"]
48789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"]
48790#[inline]
48791#[cfg(target_endian = "big")]
48792#[target_feature(enable = "neon")]
48793#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48794#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48795#[cfg_attr(
48796    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48797    assert_instr(nop)
48798)]
48799#[cfg_attr(
48800    not(target_arch = "arm"),
48801    stable(feature = "neon_intrinsics", since = "1.59.0")
48802)]
48803#[cfg_attr(
48804    target_arch = "arm",
48805    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48806)]
48807pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
48808    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48809    unsafe {
48810        let ret_val: int16x8_t = transmute(a);
48811        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48812    }
48813}
48814#[doc = "Vector reinterpret cast operation"]
48815#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"]
48816#[inline]
48817#[cfg(target_endian = "little")]
48818#[target_feature(enable = "neon")]
48819#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48820#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48821#[cfg_attr(
48822    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48823    assert_instr(nop)
48824)]
48825#[cfg_attr(
48826    not(target_arch = "arm"),
48827    stable(feature = "neon_intrinsics", since = "1.59.0")
48828)]
48829#[cfg_attr(
48830    target_arch = "arm",
48831    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48832)]
48833pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
48834    unsafe { transmute(a) }
48835}
48836#[doc = "Vector reinterpret cast operation"]
48837#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"]
48838#[inline]
48839#[cfg(target_endian = "big")]
48840#[target_feature(enable = "neon")]
48841#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48842#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48843#[cfg_attr(
48844    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48845    assert_instr(nop)
48846)]
48847#[cfg_attr(
48848    not(target_arch = "arm"),
48849    stable(feature = "neon_intrinsics", since = "1.59.0")
48850)]
48851#[cfg_attr(
48852    target_arch = "arm",
48853    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48854)]
48855pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
48856    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48857    unsafe {
48858        let ret_val: int32x4_t = transmute(a);
48859        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48860    }
48861}
48862#[doc = "Vector reinterpret cast operation"]
48863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"]
48864#[inline]
48865#[cfg(target_endian = "little")]
48866#[target_feature(enable = "neon")]
48867#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48868#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48869#[cfg_attr(
48870    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48871    assert_instr(nop)
48872)]
48873#[cfg_attr(
48874    not(target_arch = "arm"),
48875    stable(feature = "neon_intrinsics", since = "1.59.0")
48876)]
48877#[cfg_attr(
48878    target_arch = "arm",
48879    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48880)]
48881pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
48882    unsafe { transmute(a) }
48883}
48884#[doc = "Vector reinterpret cast operation"]
48885#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"]
48886#[inline]
48887#[cfg(target_endian = "big")]
48888#[target_feature(enable = "neon")]
48889#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48890#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48891#[cfg_attr(
48892    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48893    assert_instr(nop)
48894)]
48895#[cfg_attr(
48896    not(target_arch = "arm"),
48897    stable(feature = "neon_intrinsics", since = "1.59.0")
48898)]
48899#[cfg_attr(
48900    target_arch = "arm",
48901    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48902)]
48903pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
48904    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48905    unsafe {
48906        let ret_val: uint8x16_t = transmute(a);
48907        simd_shuffle!(
48908            ret_val,
48909            ret_val,
48910            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
48911        )
48912    }
48913}
48914#[doc = "Vector reinterpret cast operation"]
48915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"]
48916#[inline]
48917#[cfg(target_endian = "little")]
48918#[target_feature(enable = "neon")]
48919#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48920#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48921#[cfg_attr(
48922    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48923    assert_instr(nop)
48924)]
48925#[cfg_attr(
48926    not(target_arch = "arm"),
48927    stable(feature = "neon_intrinsics", since = "1.59.0")
48928)]
48929#[cfg_attr(
48930    target_arch = "arm",
48931    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48932)]
48933pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
48934    unsafe { transmute(a) }
48935}
48936#[doc = "Vector reinterpret cast operation"]
48937#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"]
48938#[inline]
48939#[cfg(target_endian = "big")]
48940#[target_feature(enable = "neon")]
48941#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48942#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48943#[cfg_attr(
48944    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48945    assert_instr(nop)
48946)]
48947#[cfg_attr(
48948    not(target_arch = "arm"),
48949    stable(feature = "neon_intrinsics", since = "1.59.0")
48950)]
48951#[cfg_attr(
48952    target_arch = "arm",
48953    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48954)]
48955pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
48956    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48957    unsafe {
48958        let ret_val: uint16x8_t = transmute(a);
48959        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48960    }
48961}
48962#[doc = "Vector reinterpret cast operation"]
48963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"]
48964#[inline]
48965#[cfg(target_endian = "little")]
48966#[target_feature(enable = "neon")]
48967#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48968#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48969#[cfg_attr(
48970    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48971    assert_instr(nop)
48972)]
48973#[cfg_attr(
48974    not(target_arch = "arm"),
48975    stable(feature = "neon_intrinsics", since = "1.59.0")
48976)]
48977#[cfg_attr(
48978    target_arch = "arm",
48979    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48980)]
48981pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
48982    unsafe { transmute(a) }
48983}
48984#[doc = "Vector reinterpret cast operation"]
48985#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"]
48986#[inline]
48987#[cfg(target_endian = "big")]
48988#[target_feature(enable = "neon")]
48989#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48990#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48991#[cfg_attr(
48992    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48993    assert_instr(nop)
48994)]
48995#[cfg_attr(
48996    not(target_arch = "arm"),
48997    stable(feature = "neon_intrinsics", since = "1.59.0")
48998)]
48999#[cfg_attr(
49000    target_arch = "arm",
49001    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49002)]
49003pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
49004    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
49005    unsafe {
49006        let ret_val: uint32x4_t = transmute(a);
49007        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49008    }
49009}
49010#[doc = "Vector reinterpret cast operation"]
49011#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"]
49012#[inline]
49013#[cfg(target_endian = "little")]
49014#[target_feature(enable = "neon")]
49015#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49016#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49017#[cfg_attr(
49018    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49019    assert_instr(nop)
49020)]
49021#[cfg_attr(
49022    not(target_arch = "arm"),
49023    stable(feature = "neon_intrinsics", since = "1.59.0")
49024)]
49025#[cfg_attr(
49026    target_arch = "arm",
49027    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49028)]
49029pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
49030    unsafe { transmute(a) }
49031}
49032#[doc = "Vector reinterpret cast operation"]
49033#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"]
49034#[inline]
49035#[cfg(target_endian = "big")]
49036#[target_feature(enable = "neon")]
49037#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49038#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49039#[cfg_attr(
49040    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49041    assert_instr(nop)
49042)]
49043#[cfg_attr(
49044    not(target_arch = "arm"),
49045    stable(feature = "neon_intrinsics", since = "1.59.0")
49046)]
49047#[cfg_attr(
49048    target_arch = "arm",
49049    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49050)]
49051pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
49052    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
49053    unsafe {
49054        let ret_val: uint64x2_t = transmute(a);
49055        simd_shuffle!(ret_val, ret_val, [1, 0])
49056    }
49057}
49058#[doc = "Vector reinterpret cast operation"]
49059#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"]
49060#[inline]
49061#[cfg(target_endian = "little")]
49062#[target_feature(enable = "neon")]
49063#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49064#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49065#[cfg_attr(
49066    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49067    assert_instr(nop)
49068)]
49069#[cfg_attr(
49070    not(target_arch = "arm"),
49071    stable(feature = "neon_intrinsics", since = "1.59.0")
49072)]
49073#[cfg_attr(
49074    target_arch = "arm",
49075    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49076)]
49077pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
49078    unsafe { transmute(a) }
49079}
49080#[doc = "Vector reinterpret cast operation"]
49081#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"]
49082#[inline]
49083#[cfg(target_endian = "big")]
49084#[target_feature(enable = "neon")]
49085#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49086#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49087#[cfg_attr(
49088    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49089    assert_instr(nop)
49090)]
49091#[cfg_attr(
49092    not(target_arch = "arm"),
49093    stable(feature = "neon_intrinsics", since = "1.59.0")
49094)]
49095#[cfg_attr(
49096    target_arch = "arm",
49097    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49098)]
49099pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
49100    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
49101    unsafe {
49102        let ret_val: poly8x16_t = transmute(a);
49103        simd_shuffle!(
49104            ret_val,
49105            ret_val,
49106            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
49107        )
49108    }
49109}
49110#[doc = "Vector reinterpret cast operation"]
49111#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"]
49112#[inline]
49113#[cfg(target_endian = "little")]
49114#[target_feature(enable = "neon")]
49115#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49116#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49117#[cfg_attr(
49118    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49119    assert_instr(nop)
49120)]
49121#[cfg_attr(
49122    not(target_arch = "arm"),
49123    stable(feature = "neon_intrinsics", since = "1.59.0")
49124)]
49125#[cfg_attr(
49126    target_arch = "arm",
49127    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49128)]
49129pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
49130    unsafe { transmute(a) }
49131}
49132#[doc = "Vector reinterpret cast operation"]
49133#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"]
49134#[inline]
49135#[cfg(target_endian = "big")]
49136#[target_feature(enable = "neon")]
49137#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49138#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49139#[cfg_attr(
49140    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49141    assert_instr(nop)
49142)]
49143#[cfg_attr(
49144    not(target_arch = "arm"),
49145    stable(feature = "neon_intrinsics", since = "1.59.0")
49146)]
49147#[cfg_attr(
49148    target_arch = "arm",
49149    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49150)]
49151pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
49152    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
49153    unsafe {
49154        let ret_val: poly16x8_t = transmute(a);
49155        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
49156    }
49157}
49158#[doc = "Vector reinterpret cast operation"]
49159#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"]
49160#[inline]
49161#[cfg(target_endian = "little")]
49162#[target_feature(enable = "neon")]
49163#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49164#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49165#[cfg_attr(
49166    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49167    assert_instr(nop)
49168)]
49169#[cfg_attr(
49170    not(target_arch = "arm"),
49171    stable(feature = "neon_intrinsics", since = "1.59.0")
49172)]
49173#[cfg_attr(
49174    target_arch = "arm",
49175    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49176)]
49177pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
49178    unsafe { transmute(a) }
49179}
49180#[doc = "Vector reinterpret cast operation"]
49181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"]
49182#[inline]
49183#[cfg(target_endian = "big")]
49184#[target_feature(enable = "neon")]
49185#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49186#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49187#[cfg_attr(
49188    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49189    assert_instr(nop)
49190)]
49191#[cfg_attr(
49192    not(target_arch = "arm"),
49193    stable(feature = "neon_intrinsics", since = "1.59.0")
49194)]
49195#[cfg_attr(
49196    target_arch = "arm",
49197    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49198)]
49199pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
49200    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49201    unsafe {
49202        let ret_val: float32x2_t = transmute(a);
49203        simd_shuffle!(ret_val, ret_val, [1, 0])
49204    }
49205}
49206#[doc = "Vector reinterpret cast operation"]
49207#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"]
49208#[inline]
49209#[cfg(target_endian = "little")]
49210#[target_feature(enable = "neon")]
49211#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49212#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49213#[cfg_attr(
49214    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49215    assert_instr(nop)
49216)]
49217#[cfg_attr(
49218    not(target_arch = "arm"),
49219    stable(feature = "neon_intrinsics", since = "1.59.0")
49220)]
49221#[cfg_attr(
49222    target_arch = "arm",
49223    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49224)]
49225pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
49226    unsafe { transmute(a) }
49227}
49228#[doc = "Vector reinterpret cast operation"]
49229#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"]
49230#[inline]
49231#[cfg(target_endian = "big")]
49232#[target_feature(enable = "neon")]
49233#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49234#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49235#[cfg_attr(
49236    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49237    assert_instr(nop)
49238)]
49239#[cfg_attr(
49240    not(target_arch = "arm"),
49241    stable(feature = "neon_intrinsics", since = "1.59.0")
49242)]
49243#[cfg_attr(
49244    target_arch = "arm",
49245    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49246)]
49247pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
49248    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49249    unsafe {
49250        let ret_val: int8x8_t = transmute(a);
49251        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
49252    }
49253}
49254#[doc = "Vector reinterpret cast operation"]
49255#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"]
49256#[inline]
49257#[cfg(target_endian = "little")]
49258#[target_feature(enable = "neon")]
49259#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49260#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49261#[cfg_attr(
49262    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49263    assert_instr(nop)
49264)]
49265#[cfg_attr(
49266    not(target_arch = "arm"),
49267    stable(feature = "neon_intrinsics", since = "1.59.0")
49268)]
49269#[cfg_attr(
49270    target_arch = "arm",
49271    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49272)]
49273pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
49274    unsafe { transmute(a) }
49275}
49276#[doc = "Vector reinterpret cast operation"]
49277#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"]
49278#[inline]
49279#[cfg(target_endian = "big")]
49280#[target_feature(enable = "neon")]
49281#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49282#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49283#[cfg_attr(
49284    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49285    assert_instr(nop)
49286)]
49287#[cfg_attr(
49288    not(target_arch = "arm"),
49289    stable(feature = "neon_intrinsics", since = "1.59.0")
49290)]
49291#[cfg_attr(
49292    target_arch = "arm",
49293    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49294)]
49295pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
49296    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49297    unsafe {
49298        let ret_val: int16x4_t = transmute(a);
49299        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49300    }
49301}
49302#[doc = "Vector reinterpret cast operation"]
49303#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"]
49304#[inline]
49305#[cfg(target_endian = "little")]
49306#[target_feature(enable = "neon")]
49307#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49308#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49309#[cfg_attr(
49310    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49311    assert_instr(nop)
49312)]
49313#[cfg_attr(
49314    not(target_arch = "arm"),
49315    stable(feature = "neon_intrinsics", since = "1.59.0")
49316)]
49317#[cfg_attr(
49318    target_arch = "arm",
49319    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49320)]
49321pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
49322    unsafe { transmute(a) }
49323}
49324#[doc = "Vector reinterpret cast operation"]
49325#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"]
49326#[inline]
49327#[cfg(target_endian = "big")]
49328#[target_feature(enable = "neon")]
49329#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49330#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49331#[cfg_attr(
49332    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49333    assert_instr(nop)
49334)]
49335#[cfg_attr(
49336    not(target_arch = "arm"),
49337    stable(feature = "neon_intrinsics", since = "1.59.0")
49338)]
49339#[cfg_attr(
49340    target_arch = "arm",
49341    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49342)]
49343pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
49344    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49345    unsafe {
49346        let ret_val: int32x2_t = transmute(a);
49347        simd_shuffle!(ret_val, ret_val, [1, 0])
49348    }
49349}
49350#[doc = "Vector reinterpret cast operation"]
49351#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"]
49352#[inline]
49353#[cfg(target_endian = "little")]
49354#[target_feature(enable = "neon")]
49355#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49356#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49357#[cfg_attr(
49358    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49359    assert_instr(nop)
49360)]
49361#[cfg_attr(
49362    not(target_arch = "arm"),
49363    stable(feature = "neon_intrinsics", since = "1.59.0")
49364)]
49365#[cfg_attr(
49366    target_arch = "arm",
49367    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49368)]
49369pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
49370    unsafe { transmute(a) }
49371}
49372#[doc = "Vector reinterpret cast operation"]
49373#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"]
49374#[inline]
49375#[cfg(target_endian = "big")]
49376#[target_feature(enable = "neon")]
49377#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49378#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49379#[cfg_attr(
49380    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49381    assert_instr(nop)
49382)]
49383#[cfg_attr(
49384    not(target_arch = "arm"),
49385    stable(feature = "neon_intrinsics", since = "1.59.0")
49386)]
49387#[cfg_attr(
49388    target_arch = "arm",
49389    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49390)]
49391pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
49392    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49393    unsafe { transmute(a) }
49394}
49395#[doc = "Vector reinterpret cast operation"]
49396#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"]
49397#[inline]
49398#[cfg(target_endian = "little")]
49399#[target_feature(enable = "neon")]
49400#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49401#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49402#[cfg_attr(
49403    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49404    assert_instr(nop)
49405)]
49406#[cfg_attr(
49407    not(target_arch = "arm"),
49408    stable(feature = "neon_intrinsics", since = "1.59.0")
49409)]
49410#[cfg_attr(
49411    target_arch = "arm",
49412    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49413)]
49414pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
49415    unsafe { transmute(a) }
49416}
49417#[doc = "Vector reinterpret cast operation"]
49418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"]
49419#[inline]
49420#[cfg(target_endian = "big")]
49421#[target_feature(enable = "neon")]
49422#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49423#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49424#[cfg_attr(
49425    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49426    assert_instr(nop)
49427)]
49428#[cfg_attr(
49429    not(target_arch = "arm"),
49430    stable(feature = "neon_intrinsics", since = "1.59.0")
49431)]
49432#[cfg_attr(
49433    target_arch = "arm",
49434    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49435)]
49436pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
49437    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49438    unsafe {
49439        let ret_val: uint16x4_t = transmute(a);
49440        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49441    }
49442}
49443#[doc = "Vector reinterpret cast operation"]
49444#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"]
49445#[inline]
49446#[cfg(target_endian = "little")]
49447#[target_feature(enable = "neon")]
49448#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49449#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49450#[cfg_attr(
49451    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49452    assert_instr(nop)
49453)]
49454#[cfg_attr(
49455    not(target_arch = "arm"),
49456    stable(feature = "neon_intrinsics", since = "1.59.0")
49457)]
49458#[cfg_attr(
49459    target_arch = "arm",
49460    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49461)]
49462pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
49463    unsafe { transmute(a) }
49464}
49465#[doc = "Vector reinterpret cast operation"]
49466#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"]
49467#[inline]
49468#[cfg(target_endian = "big")]
49469#[target_feature(enable = "neon")]
49470#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49471#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49472#[cfg_attr(
49473    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49474    assert_instr(nop)
49475)]
49476#[cfg_attr(
49477    not(target_arch = "arm"),
49478    stable(feature = "neon_intrinsics", since = "1.59.0")
49479)]
49480#[cfg_attr(
49481    target_arch = "arm",
49482    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49483)]
49484pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
49485    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49486    unsafe {
49487        let ret_val: uint32x2_t = transmute(a);
49488        simd_shuffle!(ret_val, ret_val, [1, 0])
49489    }
49490}
49491#[doc = "Vector reinterpret cast operation"]
49492#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"]
49493#[inline]
49494#[cfg(target_endian = "little")]
49495#[target_feature(enable = "neon")]
49496#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49497#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49498#[cfg_attr(
49499    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49500    assert_instr(nop)
49501)]
49502#[cfg_attr(
49503    not(target_arch = "arm"),
49504    stable(feature = "neon_intrinsics", since = "1.59.0")
49505)]
49506#[cfg_attr(
49507    target_arch = "arm",
49508    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49509)]
49510pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
49511    unsafe { transmute(a) }
49512}
49513#[doc = "Vector reinterpret cast operation"]
49514#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"]
49515#[inline]
49516#[cfg(target_endian = "big")]
49517#[target_feature(enable = "neon")]
49518#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49519#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49520#[cfg_attr(
49521    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49522    assert_instr(nop)
49523)]
49524#[cfg_attr(
49525    not(target_arch = "arm"),
49526    stable(feature = "neon_intrinsics", since = "1.59.0")
49527)]
49528#[cfg_attr(
49529    target_arch = "arm",
49530    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49531)]
49532pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
49533    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49534    unsafe { transmute(a) }
49535}
49536#[doc = "Vector reinterpret cast operation"]
49537#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"]
49538#[inline]
49539#[cfg(target_endian = "little")]
49540#[target_feature(enable = "neon")]
49541#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49542#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49543#[cfg_attr(
49544    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49545    assert_instr(nop)
49546)]
49547#[cfg_attr(
49548    not(target_arch = "arm"),
49549    stable(feature = "neon_intrinsics", since = "1.59.0")
49550)]
49551#[cfg_attr(
49552    target_arch = "arm",
49553    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49554)]
49555pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
49556    unsafe { transmute(a) }
49557}
49558#[doc = "Vector reinterpret cast operation"]
49559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"]
49560#[inline]
49561#[cfg(target_endian = "big")]
49562#[target_feature(enable = "neon")]
49563#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49564#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49565#[cfg_attr(
49566    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49567    assert_instr(nop)
49568)]
49569#[cfg_attr(
49570    not(target_arch = "arm"),
49571    stable(feature = "neon_intrinsics", since = "1.59.0")
49572)]
49573#[cfg_attr(
49574    target_arch = "arm",
49575    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49576)]
49577pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
49578    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49579    unsafe {
49580        let ret_val: poly8x8_t = transmute(a);
49581        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
49582    }
49583}
49584#[doc = "Vector reinterpret cast operation"]
49585#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"]
49586#[inline]
49587#[cfg(target_endian = "little")]
49588#[target_feature(enable = "neon")]
49589#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49590#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49591#[cfg_attr(
49592    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49593    assert_instr(nop)
49594)]
49595#[cfg_attr(
49596    not(target_arch = "arm"),
49597    stable(feature = "neon_intrinsics", since = "1.59.0")
49598)]
49599#[cfg_attr(
49600    target_arch = "arm",
49601    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49602)]
49603pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
49604    unsafe { transmute(a) }
49605}
49606#[doc = "Vector reinterpret cast operation"]
49607#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"]
49608#[inline]
49609#[cfg(target_endian = "big")]
49610#[target_feature(enable = "neon")]
49611#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49612#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49613#[cfg_attr(
49614    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49615    assert_instr(nop)
49616)]
49617#[cfg_attr(
49618    not(target_arch = "arm"),
49619    stable(feature = "neon_intrinsics", since = "1.59.0")
49620)]
49621#[cfg_attr(
49622    target_arch = "arm",
49623    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49624)]
49625pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
49626    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49627    unsafe {
49628        let ret_val: poly16x4_t = transmute(a);
49629        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49630    }
49631}
49632#[doc = "Vector reinterpret cast operation"]
49633#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"]
49634#[inline]
49635#[cfg(target_endian = "little")]
49636#[target_feature(enable = "neon")]
49637#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49638#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49639#[cfg_attr(
49640    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49641    assert_instr(nop)
49642)]
49643#[cfg_attr(
49644    not(target_arch = "arm"),
49645    stable(feature = "neon_intrinsics", since = "1.59.0")
49646)]
49647#[cfg_attr(
49648    target_arch = "arm",
49649    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49650)]
49651pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
49652    unsafe { transmute(a) }
49653}
49654#[doc = "Vector reinterpret cast operation"]
49655#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"]
49656#[inline]
49657#[cfg(target_endian = "big")]
49658#[target_feature(enable = "neon")]
49659#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49660#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49661#[cfg_attr(
49662    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49663    assert_instr(nop)
49664)]
49665#[cfg_attr(
49666    not(target_arch = "arm"),
49667    stable(feature = "neon_intrinsics", since = "1.59.0")
49668)]
49669#[cfg_attr(
49670    target_arch = "arm",
49671    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49672)]
49673pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
49674    let a: uint8x16_t =
49675        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49676    unsafe {
49677        let ret_val: float32x4_t = transmute(a);
49678        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49679    }
49680}
49681#[doc = "Vector reinterpret cast operation"]
49682#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"]
49683#[inline]
49684#[cfg(target_endian = "little")]
49685#[target_feature(enable = "neon")]
49686#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49687#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49688#[cfg_attr(
49689    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49690    assert_instr(nop)
49691)]
49692#[cfg_attr(
49693    not(target_arch = "arm"),
49694    stable(feature = "neon_intrinsics", since = "1.59.0")
49695)]
49696#[cfg_attr(
49697    target_arch = "arm",
49698    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49699)]
49700pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
49701    unsafe { transmute(a) }
49702}
49703#[doc = "Vector reinterpret cast operation"]
49704#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"]
49705#[inline]
49706#[cfg(target_endian = "big")]
49707#[target_feature(enable = "neon")]
49708#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49709#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49710#[cfg_attr(
49711    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49712    assert_instr(nop)
49713)]
49714#[cfg_attr(
49715    not(target_arch = "arm"),
49716    stable(feature = "neon_intrinsics", since = "1.59.0")
49717)]
49718#[cfg_attr(
49719    target_arch = "arm",
49720    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49721)]
49722pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
49723    let a: uint8x16_t =
49724        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49725    unsafe {
49726        let ret_val: int8x16_t = transmute(a);
49727        simd_shuffle!(
49728            ret_val,
49729            ret_val,
49730            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
49731        )
49732    }
49733}
49734#[doc = "Vector reinterpret cast operation"]
49735#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"]
49736#[inline]
49737#[cfg(target_endian = "little")]
49738#[target_feature(enable = "neon")]
49739#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49740#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49741#[cfg_attr(
49742    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49743    assert_instr(nop)
49744)]
49745#[cfg_attr(
49746    not(target_arch = "arm"),
49747    stable(feature = "neon_intrinsics", since = "1.59.0")
49748)]
49749#[cfg_attr(
49750    target_arch = "arm",
49751    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49752)]
49753pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
49754    unsafe { transmute(a) }
49755}
49756#[doc = "Vector reinterpret cast operation"]
49757#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"]
49758#[inline]
49759#[cfg(target_endian = "big")]
49760#[target_feature(enable = "neon")]
49761#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49762#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49763#[cfg_attr(
49764    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49765    assert_instr(nop)
49766)]
49767#[cfg_attr(
49768    not(target_arch = "arm"),
49769    stable(feature = "neon_intrinsics", since = "1.59.0")
49770)]
49771#[cfg_attr(
49772    target_arch = "arm",
49773    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49774)]
49775pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
49776    let a: uint8x16_t =
49777        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49778    unsafe {
49779        let ret_val: int16x8_t = transmute(a);
49780        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
49781    }
49782}
49783#[doc = "Vector reinterpret cast operation"]
49784#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"]
49785#[inline]
49786#[cfg(target_endian = "little")]
49787#[target_feature(enable = "neon")]
49788#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49789#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49790#[cfg_attr(
49791    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49792    assert_instr(nop)
49793)]
49794#[cfg_attr(
49795    not(target_arch = "arm"),
49796    stable(feature = "neon_intrinsics", since = "1.59.0")
49797)]
49798#[cfg_attr(
49799    target_arch = "arm",
49800    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49801)]
49802pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
49803    unsafe { transmute(a) }
49804}
49805#[doc = "Vector reinterpret cast operation"]
49806#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"]
49807#[inline]
49808#[cfg(target_endian = "big")]
49809#[target_feature(enable = "neon")]
49810#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49811#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49812#[cfg_attr(
49813    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49814    assert_instr(nop)
49815)]
49816#[cfg_attr(
49817    not(target_arch = "arm"),
49818    stable(feature = "neon_intrinsics", since = "1.59.0")
49819)]
49820#[cfg_attr(
49821    target_arch = "arm",
49822    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49823)]
49824pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
49825    let a: uint8x16_t =
49826        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49827    unsafe {
49828        let ret_val: int32x4_t = transmute(a);
49829        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49830    }
49831}
49832#[doc = "Vector reinterpret cast operation"]
49833#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"]
49834#[inline]
49835#[cfg(target_endian = "little")]
49836#[target_feature(enable = "neon")]
49837#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49838#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49839#[cfg_attr(
49840    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49841    assert_instr(nop)
49842)]
49843#[cfg_attr(
49844    not(target_arch = "arm"),
49845    stable(feature = "neon_intrinsics", since = "1.59.0")
49846)]
49847#[cfg_attr(
49848    target_arch = "arm",
49849    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49850)]
49851pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
49852    unsafe { transmute(a) }
49853}
49854#[doc = "Vector reinterpret cast operation"]
49855#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"]
49856#[inline]
49857#[cfg(target_endian = "big")]
49858#[target_feature(enable = "neon")]
49859#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49860#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49861#[cfg_attr(
49862    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49863    assert_instr(nop)
49864)]
49865#[cfg_attr(
49866    not(target_arch = "arm"),
49867    stable(feature = "neon_intrinsics", since = "1.59.0")
49868)]
49869#[cfg_attr(
49870    target_arch = "arm",
49871    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49872)]
49873pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
49874    let a: uint8x16_t =
49875        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49876    unsafe {
49877        let ret_val: int64x2_t = transmute(a);
49878        simd_shuffle!(ret_val, ret_val, [1, 0])
49879    }
49880}
49881#[doc = "Vector reinterpret cast operation"]
49882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"]
49883#[inline]
49884#[cfg(target_endian = "little")]
49885#[target_feature(enable = "neon")]
49886#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49887#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49888#[cfg_attr(
49889    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49890    assert_instr(nop)
49891)]
49892#[cfg_attr(
49893    not(target_arch = "arm"),
49894    stable(feature = "neon_intrinsics", since = "1.59.0")
49895)]
49896#[cfg_attr(
49897    target_arch = "arm",
49898    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49899)]
49900pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
49901    unsafe { transmute(a) }
49902}
49903#[doc = "Vector reinterpret cast operation"]
49904#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"]
49905#[inline]
49906#[cfg(target_endian = "big")]
49907#[target_feature(enable = "neon")]
49908#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49909#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49910#[cfg_attr(
49911    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49912    assert_instr(nop)
49913)]
49914#[cfg_attr(
49915    not(target_arch = "arm"),
49916    stable(feature = "neon_intrinsics", since = "1.59.0")
49917)]
49918#[cfg_attr(
49919    target_arch = "arm",
49920    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49921)]
49922pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
49923    let a: uint8x16_t =
49924        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49925    unsafe {
49926        let ret_val: uint16x8_t = transmute(a);
49927        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
49928    }
49929}
49930#[doc = "Vector reinterpret cast operation"]
49931#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"]
49932#[inline]
49933#[cfg(target_endian = "little")]
49934#[target_feature(enable = "neon")]
49935#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49936#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49937#[cfg_attr(
49938    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49939    assert_instr(nop)
49940)]
49941#[cfg_attr(
49942    not(target_arch = "arm"),
49943    stable(feature = "neon_intrinsics", since = "1.59.0")
49944)]
49945#[cfg_attr(
49946    target_arch = "arm",
49947    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49948)]
49949pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
49950    unsafe { transmute(a) }
49951}
49952#[doc = "Vector reinterpret cast operation"]
49953#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"]
49954#[inline]
49955#[cfg(target_endian = "big")]
49956#[target_feature(enable = "neon")]
49957#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49958#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49959#[cfg_attr(
49960    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49961    assert_instr(nop)
49962)]
49963#[cfg_attr(
49964    not(target_arch = "arm"),
49965    stable(feature = "neon_intrinsics", since = "1.59.0")
49966)]
49967#[cfg_attr(
49968    target_arch = "arm",
49969    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49970)]
49971pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
49972    let a: uint8x16_t =
49973        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49974    unsafe {
49975        let ret_val: uint32x4_t = transmute(a);
49976        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49977    }
49978}
49979#[doc = "Vector reinterpret cast operation"]
49980#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"]
49981#[inline]
49982#[cfg(target_endian = "little")]
49983#[target_feature(enable = "neon")]
49984#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49985#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49986#[cfg_attr(
49987    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49988    assert_instr(nop)
49989)]
49990#[cfg_attr(
49991    not(target_arch = "arm"),
49992    stable(feature = "neon_intrinsics", since = "1.59.0")
49993)]
49994#[cfg_attr(
49995    target_arch = "arm",
49996    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49997)]
49998pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
49999    unsafe { transmute(a) }
50000}
50001#[doc = "Vector reinterpret cast operation"]
50002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"]
50003#[inline]
50004#[cfg(target_endian = "big")]
50005#[target_feature(enable = "neon")]
50006#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50007#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50008#[cfg_attr(
50009    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50010    assert_instr(nop)
50011)]
50012#[cfg_attr(
50013    not(target_arch = "arm"),
50014    stable(feature = "neon_intrinsics", since = "1.59.0")
50015)]
50016#[cfg_attr(
50017    target_arch = "arm",
50018    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50019)]
50020pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
50021    let a: uint8x16_t =
50022        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
50023    unsafe {
50024        let ret_val: uint64x2_t = transmute(a);
50025        simd_shuffle!(ret_val, ret_val, [1, 0])
50026    }
50027}
50028#[doc = "Vector reinterpret cast operation"]
50029#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"]
50030#[inline]
50031#[cfg(target_endian = "little")]
50032#[target_feature(enable = "neon")]
50033#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50034#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50035#[cfg_attr(
50036    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50037    assert_instr(nop)
50038)]
50039#[cfg_attr(
50040    not(target_arch = "arm"),
50041    stable(feature = "neon_intrinsics", since = "1.59.0")
50042)]
50043#[cfg_attr(
50044    target_arch = "arm",
50045    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50046)]
50047pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
50048    unsafe { transmute(a) }
50049}
50050#[doc = "Vector reinterpret cast operation"]
50051#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"]
50052#[inline]
50053#[cfg(target_endian = "big")]
50054#[target_feature(enable = "neon")]
50055#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50056#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50057#[cfg_attr(
50058    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50059    assert_instr(nop)
50060)]
50061#[cfg_attr(
50062    not(target_arch = "arm"),
50063    stable(feature = "neon_intrinsics", since = "1.59.0")
50064)]
50065#[cfg_attr(
50066    target_arch = "arm",
50067    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50068)]
50069pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
50070    let a: uint8x16_t =
50071        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
50072    unsafe {
50073        let ret_val: poly8x16_t = transmute(a);
50074        simd_shuffle!(
50075            ret_val,
50076            ret_val,
50077            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
50078        )
50079    }
50080}
50081#[doc = "Vector reinterpret cast operation"]
50082#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"]
50083#[inline]
50084#[cfg(target_endian = "little")]
50085#[target_feature(enable = "neon")]
50086#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50087#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50088#[cfg_attr(
50089    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50090    assert_instr(nop)
50091)]
50092#[cfg_attr(
50093    not(target_arch = "arm"),
50094    stable(feature = "neon_intrinsics", since = "1.59.0")
50095)]
50096#[cfg_attr(
50097    target_arch = "arm",
50098    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50099)]
50100pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
50101    unsafe { transmute(a) }
50102}
50103#[doc = "Vector reinterpret cast operation"]
50104#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"]
50105#[inline]
50106#[cfg(target_endian = "big")]
50107#[target_feature(enable = "neon")]
50108#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50109#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50110#[cfg_attr(
50111    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50112    assert_instr(nop)
50113)]
50114#[cfg_attr(
50115    not(target_arch = "arm"),
50116    stable(feature = "neon_intrinsics", since = "1.59.0")
50117)]
50118#[cfg_attr(
50119    target_arch = "arm",
50120    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50121)]
50122pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
50123    let a: uint8x16_t =
50124        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
50125    unsafe {
50126        let ret_val: poly16x8_t = transmute(a);
50127        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50128    }
50129}
50130#[doc = "Vector reinterpret cast operation"]
50131#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"]
50132#[inline]
50133#[cfg(target_endian = "little")]
50134#[target_feature(enable = "neon")]
50135#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50136#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50137#[cfg_attr(
50138    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50139    assert_instr(nop)
50140)]
50141#[cfg_attr(
50142    not(target_arch = "arm"),
50143    stable(feature = "neon_intrinsics", since = "1.59.0")
50144)]
50145#[cfg_attr(
50146    target_arch = "arm",
50147    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50148)]
50149pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
50150    unsafe { transmute(a) }
50151}
50152#[doc = "Vector reinterpret cast operation"]
50153#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"]
50154#[inline]
50155#[cfg(target_endian = "big")]
50156#[target_feature(enable = "neon")]
50157#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50158#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50159#[cfg_attr(
50160    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50161    assert_instr(nop)
50162)]
50163#[cfg_attr(
50164    not(target_arch = "arm"),
50165    stable(feature = "neon_intrinsics", since = "1.59.0")
50166)]
50167#[cfg_attr(
50168    target_arch = "arm",
50169    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50170)]
50171pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
50172    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50173    unsafe {
50174        let ret_val: float32x2_t = transmute(a);
50175        simd_shuffle!(ret_val, ret_val, [1, 0])
50176    }
50177}
50178#[doc = "Vector reinterpret cast operation"]
50179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"]
50180#[inline]
50181#[cfg(target_endian = "little")]
50182#[target_feature(enable = "neon")]
50183#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50184#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50185#[cfg_attr(
50186    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50187    assert_instr(nop)
50188)]
50189#[cfg_attr(
50190    not(target_arch = "arm"),
50191    stable(feature = "neon_intrinsics", since = "1.59.0")
50192)]
50193#[cfg_attr(
50194    target_arch = "arm",
50195    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50196)]
50197pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
50198    unsafe { transmute(a) }
50199}
50200#[doc = "Vector reinterpret cast operation"]
50201#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"]
50202#[inline]
50203#[cfg(target_endian = "big")]
50204#[target_feature(enable = "neon")]
50205#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50206#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50207#[cfg_attr(
50208    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50209    assert_instr(nop)
50210)]
50211#[cfg_attr(
50212    not(target_arch = "arm"),
50213    stable(feature = "neon_intrinsics", since = "1.59.0")
50214)]
50215#[cfg_attr(
50216    target_arch = "arm",
50217    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50218)]
50219pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
50220    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50221    unsafe {
50222        let ret_val: int8x8_t = transmute(a);
50223        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50224    }
50225}
50226#[doc = "Vector reinterpret cast operation"]
50227#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"]
50228#[inline]
50229#[cfg(target_endian = "little")]
50230#[target_feature(enable = "neon")]
50231#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50232#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50233#[cfg_attr(
50234    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50235    assert_instr(nop)
50236)]
50237#[cfg_attr(
50238    not(target_arch = "arm"),
50239    stable(feature = "neon_intrinsics", since = "1.59.0")
50240)]
50241#[cfg_attr(
50242    target_arch = "arm",
50243    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50244)]
50245pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
50246    unsafe { transmute(a) }
50247}
50248#[doc = "Vector reinterpret cast operation"]
50249#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"]
50250#[inline]
50251#[cfg(target_endian = "big")]
50252#[target_feature(enable = "neon")]
50253#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50254#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50255#[cfg_attr(
50256    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50257    assert_instr(nop)
50258)]
50259#[cfg_attr(
50260    not(target_arch = "arm"),
50261    stable(feature = "neon_intrinsics", since = "1.59.0")
50262)]
50263#[cfg_attr(
50264    target_arch = "arm",
50265    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50266)]
50267pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
50268    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50269    unsafe {
50270        let ret_val: int16x4_t = transmute(a);
50271        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50272    }
50273}
50274#[doc = "Vector reinterpret cast operation"]
50275#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"]
50276#[inline]
50277#[cfg(target_endian = "little")]
50278#[target_feature(enable = "neon")]
50279#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50280#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50281#[cfg_attr(
50282    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50283    assert_instr(nop)
50284)]
50285#[cfg_attr(
50286    not(target_arch = "arm"),
50287    stable(feature = "neon_intrinsics", since = "1.59.0")
50288)]
50289#[cfg_attr(
50290    target_arch = "arm",
50291    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50292)]
50293pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
50294    unsafe { transmute(a) }
50295}
50296#[doc = "Vector reinterpret cast operation"]
50297#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"]
50298#[inline]
50299#[cfg(target_endian = "big")]
50300#[target_feature(enable = "neon")]
50301#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50302#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50303#[cfg_attr(
50304    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50305    assert_instr(nop)
50306)]
50307#[cfg_attr(
50308    not(target_arch = "arm"),
50309    stable(feature = "neon_intrinsics", since = "1.59.0")
50310)]
50311#[cfg_attr(
50312    target_arch = "arm",
50313    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50314)]
50315pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
50316    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50317    unsafe {
50318        let ret_val: int32x2_t = transmute(a);
50319        simd_shuffle!(ret_val, ret_val, [1, 0])
50320    }
50321}
50322#[doc = "Vector reinterpret cast operation"]
50323#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"]
50324#[inline]
50325#[cfg(target_endian = "little")]
50326#[target_feature(enable = "neon")]
50327#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50328#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50329#[cfg_attr(
50330    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50331    assert_instr(nop)
50332)]
50333#[cfg_attr(
50334    not(target_arch = "arm"),
50335    stable(feature = "neon_intrinsics", since = "1.59.0")
50336)]
50337#[cfg_attr(
50338    target_arch = "arm",
50339    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50340)]
50341pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
50342    unsafe { transmute(a) }
50343}
50344#[doc = "Vector reinterpret cast operation"]
50345#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"]
50346#[inline]
50347#[cfg(target_endian = "big")]
50348#[target_feature(enable = "neon")]
50349#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50350#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50351#[cfg_attr(
50352    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50353    assert_instr(nop)
50354)]
50355#[cfg_attr(
50356    not(target_arch = "arm"),
50357    stable(feature = "neon_intrinsics", since = "1.59.0")
50358)]
50359#[cfg_attr(
50360    target_arch = "arm",
50361    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50362)]
50363pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
50364    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50365    unsafe { transmute(a) }
50366}
50367#[doc = "Vector reinterpret cast operation"]
50368#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"]
50369#[inline]
50370#[cfg(target_endian = "little")]
50371#[target_feature(enable = "neon")]
50372#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50373#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50374#[cfg_attr(
50375    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50376    assert_instr(nop)
50377)]
50378#[cfg_attr(
50379    not(target_arch = "arm"),
50380    stable(feature = "neon_intrinsics", since = "1.59.0")
50381)]
50382#[cfg_attr(
50383    target_arch = "arm",
50384    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50385)]
50386pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
50387    unsafe { transmute(a) }
50388}
50389#[doc = "Vector reinterpret cast operation"]
50390#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"]
50391#[inline]
50392#[cfg(target_endian = "big")]
50393#[target_feature(enable = "neon")]
50394#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50395#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50396#[cfg_attr(
50397    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50398    assert_instr(nop)
50399)]
50400#[cfg_attr(
50401    not(target_arch = "arm"),
50402    stable(feature = "neon_intrinsics", since = "1.59.0")
50403)]
50404#[cfg_attr(
50405    target_arch = "arm",
50406    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50407)]
50408pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
50409    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50410    unsafe {
50411        let ret_val: uint8x8_t = transmute(a);
50412        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50413    }
50414}
50415#[doc = "Vector reinterpret cast operation"]
50416#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"]
50417#[inline]
50418#[cfg(target_endian = "little")]
50419#[target_feature(enable = "neon")]
50420#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50421#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50422#[cfg_attr(
50423    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50424    assert_instr(nop)
50425)]
50426#[cfg_attr(
50427    not(target_arch = "arm"),
50428    stable(feature = "neon_intrinsics", since = "1.59.0")
50429)]
50430#[cfg_attr(
50431    target_arch = "arm",
50432    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50433)]
50434pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
50435    unsafe { transmute(a) }
50436}
50437#[doc = "Vector reinterpret cast operation"]
50438#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"]
50439#[inline]
50440#[cfg(target_endian = "big")]
50441#[target_feature(enable = "neon")]
50442#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50443#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50444#[cfg_attr(
50445    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50446    assert_instr(nop)
50447)]
50448#[cfg_attr(
50449    not(target_arch = "arm"),
50450    stable(feature = "neon_intrinsics", since = "1.59.0")
50451)]
50452#[cfg_attr(
50453    target_arch = "arm",
50454    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50455)]
50456pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
50457    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50458    unsafe {
50459        let ret_val: uint32x2_t = transmute(a);
50460        simd_shuffle!(ret_val, ret_val, [1, 0])
50461    }
50462}
50463#[doc = "Vector reinterpret cast operation"]
50464#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"]
50465#[inline]
50466#[cfg(target_endian = "little")]
50467#[target_feature(enable = "neon")]
50468#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50469#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50470#[cfg_attr(
50471    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50472    assert_instr(nop)
50473)]
50474#[cfg_attr(
50475    not(target_arch = "arm"),
50476    stable(feature = "neon_intrinsics", since = "1.59.0")
50477)]
50478#[cfg_attr(
50479    target_arch = "arm",
50480    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50481)]
50482pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
50483    unsafe { transmute(a) }
50484}
50485#[doc = "Vector reinterpret cast operation"]
50486#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"]
50487#[inline]
50488#[cfg(target_endian = "big")]
50489#[target_feature(enable = "neon")]
50490#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50491#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50492#[cfg_attr(
50493    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50494    assert_instr(nop)
50495)]
50496#[cfg_attr(
50497    not(target_arch = "arm"),
50498    stable(feature = "neon_intrinsics", since = "1.59.0")
50499)]
50500#[cfg_attr(
50501    target_arch = "arm",
50502    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50503)]
50504pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
50505    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50506    unsafe { transmute(a) }
50507}
50508#[doc = "Vector reinterpret cast operation"]
50509#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"]
50510#[inline]
50511#[cfg(target_endian = "little")]
50512#[target_feature(enable = "neon")]
50513#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50514#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50515#[cfg_attr(
50516    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50517    assert_instr(nop)
50518)]
50519#[cfg_attr(
50520    not(target_arch = "arm"),
50521    stable(feature = "neon_intrinsics", since = "1.59.0")
50522)]
50523#[cfg_attr(
50524    target_arch = "arm",
50525    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50526)]
50527pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
50528    unsafe { transmute(a) }
50529}
50530#[doc = "Vector reinterpret cast operation"]
50531#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"]
50532#[inline]
50533#[cfg(target_endian = "big")]
50534#[target_feature(enable = "neon")]
50535#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50536#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50537#[cfg_attr(
50538    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50539    assert_instr(nop)
50540)]
50541#[cfg_attr(
50542    not(target_arch = "arm"),
50543    stable(feature = "neon_intrinsics", since = "1.59.0")
50544)]
50545#[cfg_attr(
50546    target_arch = "arm",
50547    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50548)]
50549pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
50550    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50551    unsafe {
50552        let ret_val: poly8x8_t = transmute(a);
50553        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50554    }
50555}
50556#[doc = "Vector reinterpret cast operation"]
50557#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"]
50558#[inline]
50559#[cfg(target_endian = "little")]
50560#[target_feature(enable = "neon")]
50561#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50562#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50563#[cfg_attr(
50564    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50565    assert_instr(nop)
50566)]
50567#[cfg_attr(
50568    not(target_arch = "arm"),
50569    stable(feature = "neon_intrinsics", since = "1.59.0")
50570)]
50571#[cfg_attr(
50572    target_arch = "arm",
50573    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50574)]
50575pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
50576    unsafe { transmute(a) }
50577}
50578#[doc = "Vector reinterpret cast operation"]
50579#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"]
50580#[inline]
50581#[cfg(target_endian = "big")]
50582#[target_feature(enable = "neon")]
50583#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50584#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50585#[cfg_attr(
50586    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50587    assert_instr(nop)
50588)]
50589#[cfg_attr(
50590    not(target_arch = "arm"),
50591    stable(feature = "neon_intrinsics", since = "1.59.0")
50592)]
50593#[cfg_attr(
50594    target_arch = "arm",
50595    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50596)]
50597pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
50598    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50599    unsafe {
50600        let ret_val: poly16x4_t = transmute(a);
50601        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50602    }
50603}
50604#[doc = "Vector reinterpret cast operation"]
50605#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"]
50606#[inline]
50607#[cfg(target_endian = "little")]
50608#[target_feature(enable = "neon")]
50609#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50610#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50611#[cfg_attr(
50612    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50613    assert_instr(nop)
50614)]
50615#[cfg_attr(
50616    not(target_arch = "arm"),
50617    stable(feature = "neon_intrinsics", since = "1.59.0")
50618)]
50619#[cfg_attr(
50620    target_arch = "arm",
50621    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50622)]
50623pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
50624    unsafe { transmute(a) }
50625}
50626#[doc = "Vector reinterpret cast operation"]
50627#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"]
50628#[inline]
50629#[cfg(target_endian = "big")]
50630#[target_feature(enable = "neon")]
50631#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50632#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50633#[cfg_attr(
50634    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50635    assert_instr(nop)
50636)]
50637#[cfg_attr(
50638    not(target_arch = "arm"),
50639    stable(feature = "neon_intrinsics", since = "1.59.0")
50640)]
50641#[cfg_attr(
50642    target_arch = "arm",
50643    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50644)]
50645pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
50646    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50647    unsafe {
50648        let ret_val: float32x4_t = transmute(a);
50649        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50650    }
50651}
50652#[doc = "Vector reinterpret cast operation"]
50653#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"]
50654#[inline]
50655#[cfg(target_endian = "little")]
50656#[target_feature(enable = "neon")]
50657#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50658#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50659#[cfg_attr(
50660    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50661    assert_instr(nop)
50662)]
50663#[cfg_attr(
50664    not(target_arch = "arm"),
50665    stable(feature = "neon_intrinsics", since = "1.59.0")
50666)]
50667#[cfg_attr(
50668    target_arch = "arm",
50669    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50670)]
50671pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
50672    unsafe { transmute(a) }
50673}
50674#[doc = "Vector reinterpret cast operation"]
50675#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"]
50676#[inline]
50677#[cfg(target_endian = "big")]
50678#[target_feature(enable = "neon")]
50679#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50680#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50681#[cfg_attr(
50682    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50683    assert_instr(nop)
50684)]
50685#[cfg_attr(
50686    not(target_arch = "arm"),
50687    stable(feature = "neon_intrinsics", since = "1.59.0")
50688)]
50689#[cfg_attr(
50690    target_arch = "arm",
50691    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50692)]
50693pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
50694    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50695    unsafe {
50696        let ret_val: int8x16_t = transmute(a);
50697        simd_shuffle!(
50698            ret_val,
50699            ret_val,
50700            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
50701        )
50702    }
50703}
50704#[doc = "Vector reinterpret cast operation"]
50705#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"]
50706#[inline]
50707#[cfg(target_endian = "little")]
50708#[target_feature(enable = "neon")]
50709#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50710#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50711#[cfg_attr(
50712    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50713    assert_instr(nop)
50714)]
50715#[cfg_attr(
50716    not(target_arch = "arm"),
50717    stable(feature = "neon_intrinsics", since = "1.59.0")
50718)]
50719#[cfg_attr(
50720    target_arch = "arm",
50721    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50722)]
50723pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
50724    unsafe { transmute(a) }
50725}
50726#[doc = "Vector reinterpret cast operation"]
50727#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"]
50728#[inline]
50729#[cfg(target_endian = "big")]
50730#[target_feature(enable = "neon")]
50731#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50732#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50733#[cfg_attr(
50734    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50735    assert_instr(nop)
50736)]
50737#[cfg_attr(
50738    not(target_arch = "arm"),
50739    stable(feature = "neon_intrinsics", since = "1.59.0")
50740)]
50741#[cfg_attr(
50742    target_arch = "arm",
50743    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50744)]
50745pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
50746    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50747    unsafe {
50748        let ret_val: int16x8_t = transmute(a);
50749        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50750    }
50751}
50752#[doc = "Vector reinterpret cast operation"]
50753#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"]
50754#[inline]
50755#[cfg(target_endian = "little")]
50756#[target_feature(enable = "neon")]
50757#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50758#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50759#[cfg_attr(
50760    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50761    assert_instr(nop)
50762)]
50763#[cfg_attr(
50764    not(target_arch = "arm"),
50765    stable(feature = "neon_intrinsics", since = "1.59.0")
50766)]
50767#[cfg_attr(
50768    target_arch = "arm",
50769    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50770)]
50771pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
50772    unsafe { transmute(a) }
50773}
50774#[doc = "Vector reinterpret cast operation"]
50775#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"]
50776#[inline]
50777#[cfg(target_endian = "big")]
50778#[target_feature(enable = "neon")]
50779#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50780#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50781#[cfg_attr(
50782    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50783    assert_instr(nop)
50784)]
50785#[cfg_attr(
50786    not(target_arch = "arm"),
50787    stable(feature = "neon_intrinsics", since = "1.59.0")
50788)]
50789#[cfg_attr(
50790    target_arch = "arm",
50791    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50792)]
50793pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
50794    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50795    unsafe {
50796        let ret_val: int32x4_t = transmute(a);
50797        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50798    }
50799}
50800#[doc = "Vector reinterpret cast operation"]
50801#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"]
50802#[inline]
50803#[cfg(target_endian = "little")]
50804#[target_feature(enable = "neon")]
50805#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50806#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50807#[cfg_attr(
50808    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50809    assert_instr(nop)
50810)]
50811#[cfg_attr(
50812    not(target_arch = "arm"),
50813    stable(feature = "neon_intrinsics", since = "1.59.0")
50814)]
50815#[cfg_attr(
50816    target_arch = "arm",
50817    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50818)]
50819pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
50820    unsafe { transmute(a) }
50821}
50822#[doc = "Vector reinterpret cast operation"]
50823#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"]
50824#[inline]
50825#[cfg(target_endian = "big")]
50826#[target_feature(enable = "neon")]
50827#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50828#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50829#[cfg_attr(
50830    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50831    assert_instr(nop)
50832)]
50833#[cfg_attr(
50834    not(target_arch = "arm"),
50835    stable(feature = "neon_intrinsics", since = "1.59.0")
50836)]
50837#[cfg_attr(
50838    target_arch = "arm",
50839    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50840)]
50841pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
50842    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50843    unsafe {
50844        let ret_val: int64x2_t = transmute(a);
50845        simd_shuffle!(ret_val, ret_val, [1, 0])
50846    }
50847}
50848#[doc = "Vector reinterpret cast operation"]
50849#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"]
50850#[inline]
50851#[cfg(target_endian = "little")]
50852#[target_feature(enable = "neon")]
50853#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50854#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50855#[cfg_attr(
50856    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50857    assert_instr(nop)
50858)]
50859#[cfg_attr(
50860    not(target_arch = "arm"),
50861    stable(feature = "neon_intrinsics", since = "1.59.0")
50862)]
50863#[cfg_attr(
50864    target_arch = "arm",
50865    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50866)]
50867pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
50868    unsafe { transmute(a) }
50869}
50870#[doc = "Vector reinterpret cast operation"]
50871#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"]
50872#[inline]
50873#[cfg(target_endian = "big")]
50874#[target_feature(enable = "neon")]
50875#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50876#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50877#[cfg_attr(
50878    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50879    assert_instr(nop)
50880)]
50881#[cfg_attr(
50882    not(target_arch = "arm"),
50883    stable(feature = "neon_intrinsics", since = "1.59.0")
50884)]
50885#[cfg_attr(
50886    target_arch = "arm",
50887    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50888)]
50889pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
50890    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50891    unsafe {
50892        let ret_val: uint8x16_t = transmute(a);
50893        simd_shuffle!(
50894            ret_val,
50895            ret_val,
50896            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
50897        )
50898    }
50899}
50900#[doc = "Vector reinterpret cast operation"]
50901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"]
50902#[inline]
50903#[cfg(target_endian = "little")]
50904#[target_feature(enable = "neon")]
50905#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50906#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50907#[cfg_attr(
50908    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50909    assert_instr(nop)
50910)]
50911#[cfg_attr(
50912    not(target_arch = "arm"),
50913    stable(feature = "neon_intrinsics", since = "1.59.0")
50914)]
50915#[cfg_attr(
50916    target_arch = "arm",
50917    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50918)]
50919pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
50920    unsafe { transmute(a) }
50921}
50922#[doc = "Vector reinterpret cast operation"]
50923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"]
50924#[inline]
50925#[cfg(target_endian = "big")]
50926#[target_feature(enable = "neon")]
50927#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50928#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50929#[cfg_attr(
50930    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50931    assert_instr(nop)
50932)]
50933#[cfg_attr(
50934    not(target_arch = "arm"),
50935    stable(feature = "neon_intrinsics", since = "1.59.0")
50936)]
50937#[cfg_attr(
50938    target_arch = "arm",
50939    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50940)]
50941pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
50942    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50943    unsafe {
50944        let ret_val: uint32x4_t = transmute(a);
50945        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50946    }
50947}
50948#[doc = "Vector reinterpret cast operation"]
50949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"]
50950#[inline]
50951#[cfg(target_endian = "little")]
50952#[target_feature(enable = "neon")]
50953#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50954#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50955#[cfg_attr(
50956    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50957    assert_instr(nop)
50958)]
50959#[cfg_attr(
50960    not(target_arch = "arm"),
50961    stable(feature = "neon_intrinsics", since = "1.59.0")
50962)]
50963#[cfg_attr(
50964    target_arch = "arm",
50965    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50966)]
50967pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
50968    unsafe { transmute(a) }
50969}
50970#[doc = "Vector reinterpret cast operation"]
50971#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"]
50972#[inline]
50973#[cfg(target_endian = "big")]
50974#[target_feature(enable = "neon")]
50975#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50976#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50977#[cfg_attr(
50978    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50979    assert_instr(nop)
50980)]
50981#[cfg_attr(
50982    not(target_arch = "arm"),
50983    stable(feature = "neon_intrinsics", since = "1.59.0")
50984)]
50985#[cfg_attr(
50986    target_arch = "arm",
50987    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50988)]
50989pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
50990    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50991    unsafe {
50992        let ret_val: uint64x2_t = transmute(a);
50993        simd_shuffle!(ret_val, ret_val, [1, 0])
50994    }
50995}
50996#[doc = "Vector reinterpret cast operation"]
50997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"]
50998#[inline]
50999#[cfg(target_endian = "little")]
51000#[target_feature(enable = "neon")]
51001#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51002#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51003#[cfg_attr(
51004    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51005    assert_instr(nop)
51006)]
51007#[cfg_attr(
51008    not(target_arch = "arm"),
51009    stable(feature = "neon_intrinsics", since = "1.59.0")
51010)]
51011#[cfg_attr(
51012    target_arch = "arm",
51013    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51014)]
51015pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
51016    unsafe { transmute(a) }
51017}
51018#[doc = "Vector reinterpret cast operation"]
51019#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"]
51020#[inline]
51021#[cfg(target_endian = "big")]
51022#[target_feature(enable = "neon")]
51023#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51024#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51025#[cfg_attr(
51026    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51027    assert_instr(nop)
51028)]
51029#[cfg_attr(
51030    not(target_arch = "arm"),
51031    stable(feature = "neon_intrinsics", since = "1.59.0")
51032)]
51033#[cfg_attr(
51034    target_arch = "arm",
51035    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51036)]
51037pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
51038    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
51039    unsafe {
51040        let ret_val: poly8x16_t = transmute(a);
51041        simd_shuffle!(
51042            ret_val,
51043            ret_val,
51044            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
51045        )
51046    }
51047}
51048#[doc = "Vector reinterpret cast operation"]
51049#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"]
51050#[inline]
51051#[cfg(target_endian = "little")]
51052#[target_feature(enable = "neon")]
51053#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51054#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51055#[cfg_attr(
51056    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51057    assert_instr(nop)
51058)]
51059#[cfg_attr(
51060    not(target_arch = "arm"),
51061    stable(feature = "neon_intrinsics", since = "1.59.0")
51062)]
51063#[cfg_attr(
51064    target_arch = "arm",
51065    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51066)]
51067pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
51068    unsafe { transmute(a) }
51069}
51070#[doc = "Vector reinterpret cast operation"]
51071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"]
51072#[inline]
51073#[cfg(target_endian = "big")]
51074#[target_feature(enable = "neon")]
51075#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51076#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51077#[cfg_attr(
51078    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51079    assert_instr(nop)
51080)]
51081#[cfg_attr(
51082    not(target_arch = "arm"),
51083    stable(feature = "neon_intrinsics", since = "1.59.0")
51084)]
51085#[cfg_attr(
51086    target_arch = "arm",
51087    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51088)]
51089pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
51090    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
51091    unsafe {
51092        let ret_val: poly16x8_t = transmute(a);
51093        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51094    }
51095}
51096#[doc = "Vector reinterpret cast operation"]
51097#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"]
51098#[inline]
51099#[cfg(target_endian = "little")]
51100#[target_feature(enable = "neon")]
51101#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51102#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51103#[cfg_attr(
51104    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51105    assert_instr(nop)
51106)]
51107#[cfg_attr(
51108    not(target_arch = "arm"),
51109    stable(feature = "neon_intrinsics", since = "1.59.0")
51110)]
51111#[cfg_attr(
51112    target_arch = "arm",
51113    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51114)]
51115pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
51116    unsafe { transmute(a) }
51117}
51118#[doc = "Vector reinterpret cast operation"]
51119#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"]
51120#[inline]
51121#[cfg(target_endian = "big")]
51122#[target_feature(enable = "neon")]
51123#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51124#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51125#[cfg_attr(
51126    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51127    assert_instr(nop)
51128)]
51129#[cfg_attr(
51130    not(target_arch = "arm"),
51131    stable(feature = "neon_intrinsics", since = "1.59.0")
51132)]
51133#[cfg_attr(
51134    target_arch = "arm",
51135    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51136)]
51137pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
51138    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51139    unsafe {
51140        let ret_val: float32x2_t = transmute(a);
51141        simd_shuffle!(ret_val, ret_val, [1, 0])
51142    }
51143}
51144#[doc = "Vector reinterpret cast operation"]
51145#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"]
51146#[inline]
51147#[cfg(target_endian = "little")]
51148#[target_feature(enable = "neon")]
51149#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51150#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51151#[cfg_attr(
51152    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51153    assert_instr(nop)
51154)]
51155#[cfg_attr(
51156    not(target_arch = "arm"),
51157    stable(feature = "neon_intrinsics", since = "1.59.0")
51158)]
51159#[cfg_attr(
51160    target_arch = "arm",
51161    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51162)]
51163pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
51164    unsafe { transmute(a) }
51165}
51166#[doc = "Vector reinterpret cast operation"]
51167#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"]
51168#[inline]
51169#[cfg(target_endian = "big")]
51170#[target_feature(enable = "neon")]
51171#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51172#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51173#[cfg_attr(
51174    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51175    assert_instr(nop)
51176)]
51177#[cfg_attr(
51178    not(target_arch = "arm"),
51179    stable(feature = "neon_intrinsics", since = "1.59.0")
51180)]
51181#[cfg_attr(
51182    target_arch = "arm",
51183    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51184)]
51185pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
51186    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51187    unsafe {
51188        let ret_val: int8x8_t = transmute(a);
51189        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51190    }
51191}
51192#[doc = "Vector reinterpret cast operation"]
51193#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"]
51194#[inline]
51195#[cfg(target_endian = "little")]
51196#[target_feature(enable = "neon")]
51197#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51198#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51199#[cfg_attr(
51200    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51201    assert_instr(nop)
51202)]
51203#[cfg_attr(
51204    not(target_arch = "arm"),
51205    stable(feature = "neon_intrinsics", since = "1.59.0")
51206)]
51207#[cfg_attr(
51208    target_arch = "arm",
51209    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51210)]
51211pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
51212    unsafe { transmute(a) }
51213}
51214#[doc = "Vector reinterpret cast operation"]
51215#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"]
51216#[inline]
51217#[cfg(target_endian = "big")]
51218#[target_feature(enable = "neon")]
51219#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51220#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51221#[cfg_attr(
51222    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51223    assert_instr(nop)
51224)]
51225#[cfg_attr(
51226    not(target_arch = "arm"),
51227    stable(feature = "neon_intrinsics", since = "1.59.0")
51228)]
51229#[cfg_attr(
51230    target_arch = "arm",
51231    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51232)]
51233pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
51234    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51235    unsafe {
51236        let ret_val: int16x4_t = transmute(a);
51237        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
51238    }
51239}
51240#[doc = "Vector reinterpret cast operation"]
51241#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"]
51242#[inline]
51243#[cfg(target_endian = "little")]
51244#[target_feature(enable = "neon")]
51245#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51246#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51247#[cfg_attr(
51248    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51249    assert_instr(nop)
51250)]
51251#[cfg_attr(
51252    not(target_arch = "arm"),
51253    stable(feature = "neon_intrinsics", since = "1.59.0")
51254)]
51255#[cfg_attr(
51256    target_arch = "arm",
51257    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51258)]
51259pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
51260    unsafe { transmute(a) }
51261}
51262#[doc = "Vector reinterpret cast operation"]
51263#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"]
51264#[inline]
51265#[cfg(target_endian = "big")]
51266#[target_feature(enable = "neon")]
51267#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51268#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51269#[cfg_attr(
51270    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51271    assert_instr(nop)
51272)]
51273#[cfg_attr(
51274    not(target_arch = "arm"),
51275    stable(feature = "neon_intrinsics", since = "1.59.0")
51276)]
51277#[cfg_attr(
51278    target_arch = "arm",
51279    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51280)]
51281pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
51282    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51283    unsafe {
51284        let ret_val: int32x2_t = transmute(a);
51285        simd_shuffle!(ret_val, ret_val, [1, 0])
51286    }
51287}
51288#[doc = "Vector reinterpret cast operation"]
51289#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"]
51290#[inline]
51291#[cfg(target_endian = "little")]
51292#[target_feature(enable = "neon")]
51293#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51294#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51295#[cfg_attr(
51296    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51297    assert_instr(nop)
51298)]
51299#[cfg_attr(
51300    not(target_arch = "arm"),
51301    stable(feature = "neon_intrinsics", since = "1.59.0")
51302)]
51303#[cfg_attr(
51304    target_arch = "arm",
51305    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51306)]
51307pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
51308    unsafe { transmute(a) }
51309}
51310#[doc = "Vector reinterpret cast operation"]
51311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"]
51312#[inline]
51313#[cfg(target_endian = "big")]
51314#[target_feature(enable = "neon")]
51315#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51316#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51317#[cfg_attr(
51318    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51319    assert_instr(nop)
51320)]
51321#[cfg_attr(
51322    not(target_arch = "arm"),
51323    stable(feature = "neon_intrinsics", since = "1.59.0")
51324)]
51325#[cfg_attr(
51326    target_arch = "arm",
51327    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51328)]
51329pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
51330    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51331    unsafe { transmute(a) }
51332}
51333#[doc = "Vector reinterpret cast operation"]
51334#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"]
51335#[inline]
51336#[cfg(target_endian = "little")]
51337#[target_feature(enable = "neon")]
51338#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51339#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51340#[cfg_attr(
51341    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51342    assert_instr(nop)
51343)]
51344#[cfg_attr(
51345    not(target_arch = "arm"),
51346    stable(feature = "neon_intrinsics", since = "1.59.0")
51347)]
51348#[cfg_attr(
51349    target_arch = "arm",
51350    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51351)]
51352pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
51353    unsafe { transmute(a) }
51354}
51355#[doc = "Vector reinterpret cast operation"]
51356#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"]
51357#[inline]
51358#[cfg(target_endian = "big")]
51359#[target_feature(enable = "neon")]
51360#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51361#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51362#[cfg_attr(
51363    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51364    assert_instr(nop)
51365)]
51366#[cfg_attr(
51367    not(target_arch = "arm"),
51368    stable(feature = "neon_intrinsics", since = "1.59.0")
51369)]
51370#[cfg_attr(
51371    target_arch = "arm",
51372    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51373)]
51374pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
51375    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51376    unsafe {
51377        let ret_val: uint8x8_t = transmute(a);
51378        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51379    }
51380}
51381#[doc = "Vector reinterpret cast operation"]
51382#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"]
51383#[inline]
51384#[cfg(target_endian = "little")]
51385#[target_feature(enable = "neon")]
51386#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51387#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51388#[cfg_attr(
51389    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51390    assert_instr(nop)
51391)]
51392#[cfg_attr(
51393    not(target_arch = "arm"),
51394    stable(feature = "neon_intrinsics", since = "1.59.0")
51395)]
51396#[cfg_attr(
51397    target_arch = "arm",
51398    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51399)]
51400pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
51401    unsafe { transmute(a) }
51402}
51403#[doc = "Vector reinterpret cast operation"]
51404#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"]
51405#[inline]
51406#[cfg(target_endian = "big")]
51407#[target_feature(enable = "neon")]
51408#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51409#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51410#[cfg_attr(
51411    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51412    assert_instr(nop)
51413)]
51414#[cfg_attr(
51415    not(target_arch = "arm"),
51416    stable(feature = "neon_intrinsics", since = "1.59.0")
51417)]
51418#[cfg_attr(
51419    target_arch = "arm",
51420    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51421)]
51422pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
51423    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51424    unsafe {
51425        let ret_val: uint16x4_t = transmute(a);
51426        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
51427    }
51428}
51429#[doc = "Vector reinterpret cast operation"]
51430#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"]
51431#[inline]
51432#[cfg(target_endian = "little")]
51433#[target_feature(enable = "neon")]
51434#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51435#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51436#[cfg_attr(
51437    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51438    assert_instr(nop)
51439)]
51440#[cfg_attr(
51441    not(target_arch = "arm"),
51442    stable(feature = "neon_intrinsics", since = "1.59.0")
51443)]
51444#[cfg_attr(
51445    target_arch = "arm",
51446    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51447)]
51448pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
51449    unsafe { transmute(a) }
51450}
51451#[doc = "Vector reinterpret cast operation"]
51452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"]
51453#[inline]
51454#[cfg(target_endian = "big")]
51455#[target_feature(enable = "neon")]
51456#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51457#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51458#[cfg_attr(
51459    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51460    assert_instr(nop)
51461)]
51462#[cfg_attr(
51463    not(target_arch = "arm"),
51464    stable(feature = "neon_intrinsics", since = "1.59.0")
51465)]
51466#[cfg_attr(
51467    target_arch = "arm",
51468    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51469)]
51470pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
51471    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51472    unsafe { transmute(a) }
51473}
51474#[doc = "Vector reinterpret cast operation"]
51475#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"]
51476#[inline]
51477#[cfg(target_endian = "little")]
51478#[target_feature(enable = "neon")]
51479#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51480#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51481#[cfg_attr(
51482    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51483    assert_instr(nop)
51484)]
51485#[cfg_attr(
51486    not(target_arch = "arm"),
51487    stable(feature = "neon_intrinsics", since = "1.59.0")
51488)]
51489#[cfg_attr(
51490    target_arch = "arm",
51491    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51492)]
51493pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
51494    unsafe { transmute(a) }
51495}
51496#[doc = "Vector reinterpret cast operation"]
51497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"]
51498#[inline]
51499#[cfg(target_endian = "big")]
51500#[target_feature(enable = "neon")]
51501#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51502#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51503#[cfg_attr(
51504    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51505    assert_instr(nop)
51506)]
51507#[cfg_attr(
51508    not(target_arch = "arm"),
51509    stable(feature = "neon_intrinsics", since = "1.59.0")
51510)]
51511#[cfg_attr(
51512    target_arch = "arm",
51513    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51514)]
51515pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
51516    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51517    unsafe {
51518        let ret_val: poly8x8_t = transmute(a);
51519        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51520    }
51521}
51522#[doc = "Vector reinterpret cast operation"]
51523#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"]
51524#[inline]
51525#[cfg(target_endian = "little")]
51526#[target_feature(enable = "neon")]
51527#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51528#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51529#[cfg_attr(
51530    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51531    assert_instr(nop)
51532)]
51533#[cfg_attr(
51534    not(target_arch = "arm"),
51535    stable(feature = "neon_intrinsics", since = "1.59.0")
51536)]
51537#[cfg_attr(
51538    target_arch = "arm",
51539    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51540)]
51541pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
51542    unsafe { transmute(a) }
51543}
51544#[doc = "Vector reinterpret cast operation"]
51545#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"]
51546#[inline]
51547#[cfg(target_endian = "big")]
51548#[target_feature(enable = "neon")]
51549#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51550#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51551#[cfg_attr(
51552    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51553    assert_instr(nop)
51554)]
51555#[cfg_attr(
51556    not(target_arch = "arm"),
51557    stable(feature = "neon_intrinsics", since = "1.59.0")
51558)]
51559#[cfg_attr(
51560    target_arch = "arm",
51561    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51562)]
51563pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
51564    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51565    unsafe {
51566        let ret_val: poly16x4_t = transmute(a);
51567        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
51568    }
51569}
51570#[doc = "Vector reinterpret cast operation"]
51571#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"]
51572#[inline]
51573#[cfg(target_endian = "little")]
51574#[target_feature(enable = "neon")]
51575#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51576#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51577#[cfg_attr(
51578    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51579    assert_instr(nop)
51580)]
51581#[cfg_attr(
51582    not(target_arch = "arm"),
51583    stable(feature = "neon_intrinsics", since = "1.59.0")
51584)]
51585#[cfg_attr(
51586    target_arch = "arm",
51587    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51588)]
51589pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
51590    unsafe { transmute(a) }
51591}
51592#[doc = "Vector reinterpret cast operation"]
51593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"]
51594#[inline]
51595#[cfg(target_endian = "big")]
51596#[target_feature(enable = "neon")]
51597#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51598#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51599#[cfg_attr(
51600    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51601    assert_instr(nop)
51602)]
51603#[cfg_attr(
51604    not(target_arch = "arm"),
51605    stable(feature = "neon_intrinsics", since = "1.59.0")
51606)]
51607#[cfg_attr(
51608    target_arch = "arm",
51609    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51610)]
51611pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
51612    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51613    unsafe {
51614        let ret_val: float32x4_t = transmute(a);
51615        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
51616    }
51617}
51618#[doc = "Vector reinterpret cast operation"]
51619#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"]
51620#[inline]
51621#[cfg(target_endian = "little")]
51622#[target_feature(enable = "neon")]
51623#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51624#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51625#[cfg_attr(
51626    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51627    assert_instr(nop)
51628)]
51629#[cfg_attr(
51630    not(target_arch = "arm"),
51631    stable(feature = "neon_intrinsics", since = "1.59.0")
51632)]
51633#[cfg_attr(
51634    target_arch = "arm",
51635    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51636)]
51637pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
51638    unsafe { transmute(a) }
51639}
51640#[doc = "Vector reinterpret cast operation"]
51641#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"]
51642#[inline]
51643#[cfg(target_endian = "big")]
51644#[target_feature(enable = "neon")]
51645#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51646#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51647#[cfg_attr(
51648    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51649    assert_instr(nop)
51650)]
51651#[cfg_attr(
51652    not(target_arch = "arm"),
51653    stable(feature = "neon_intrinsics", since = "1.59.0")
51654)]
51655#[cfg_attr(
51656    target_arch = "arm",
51657    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51658)]
51659pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
51660    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51661    unsafe {
51662        let ret_val: int8x16_t = transmute(a);
51663        simd_shuffle!(
51664            ret_val,
51665            ret_val,
51666            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
51667        )
51668    }
51669}
51670#[doc = "Vector reinterpret cast operation"]
51671#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"]
51672#[inline]
51673#[cfg(target_endian = "little")]
51674#[target_feature(enable = "neon")]
51675#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51676#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51677#[cfg_attr(
51678    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51679    assert_instr(nop)
51680)]
51681#[cfg_attr(
51682    not(target_arch = "arm"),
51683    stable(feature = "neon_intrinsics", since = "1.59.0")
51684)]
51685#[cfg_attr(
51686    target_arch = "arm",
51687    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51688)]
51689pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
51690    unsafe { transmute(a) }
51691}
51692#[doc = "Vector reinterpret cast operation"]
51693#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"]
51694#[inline]
51695#[cfg(target_endian = "big")]
51696#[target_feature(enable = "neon")]
51697#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51698#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51699#[cfg_attr(
51700    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51701    assert_instr(nop)
51702)]
51703#[cfg_attr(
51704    not(target_arch = "arm"),
51705    stable(feature = "neon_intrinsics", since = "1.59.0")
51706)]
51707#[cfg_attr(
51708    target_arch = "arm",
51709    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51710)]
51711pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
51712    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51713    unsafe {
51714        let ret_val: int16x8_t = transmute(a);
51715        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51716    }
51717}
51718#[doc = "Vector reinterpret cast operation"]
51719#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"]
51720#[inline]
51721#[cfg(target_endian = "little")]
51722#[target_feature(enable = "neon")]
51723#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51724#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51725#[cfg_attr(
51726    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51727    assert_instr(nop)
51728)]
51729#[cfg_attr(
51730    not(target_arch = "arm"),
51731    stable(feature = "neon_intrinsics", since = "1.59.0")
51732)]
51733#[cfg_attr(
51734    target_arch = "arm",
51735    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51736)]
51737pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
51738    unsafe { transmute(a) }
51739}
51740#[doc = "Vector reinterpret cast operation"]
51741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"]
51742#[inline]
51743#[cfg(target_endian = "big")]
51744#[target_feature(enable = "neon")]
51745#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51746#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51747#[cfg_attr(
51748    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51749    assert_instr(nop)
51750)]
51751#[cfg_attr(
51752    not(target_arch = "arm"),
51753    stable(feature = "neon_intrinsics", since = "1.59.0")
51754)]
51755#[cfg_attr(
51756    target_arch = "arm",
51757    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51758)]
51759pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
51760    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51761    unsafe {
51762        let ret_val: int32x4_t = transmute(a);
51763        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
51764    }
51765}
51766#[doc = "Vector reinterpret cast operation"]
51767#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"]
51768#[inline]
51769#[cfg(target_endian = "little")]
51770#[target_feature(enable = "neon")]
51771#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51772#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51773#[cfg_attr(
51774    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51775    assert_instr(nop)
51776)]
51777#[cfg_attr(
51778    not(target_arch = "arm"),
51779    stable(feature = "neon_intrinsics", since = "1.59.0")
51780)]
51781#[cfg_attr(
51782    target_arch = "arm",
51783    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51784)]
51785pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
51786    unsafe { transmute(a) }
51787}
51788#[doc = "Vector reinterpret cast operation"]
51789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"]
51790#[inline]
51791#[cfg(target_endian = "big")]
51792#[target_feature(enable = "neon")]
51793#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51794#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51795#[cfg_attr(
51796    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51797    assert_instr(nop)
51798)]
51799#[cfg_attr(
51800    not(target_arch = "arm"),
51801    stable(feature = "neon_intrinsics", since = "1.59.0")
51802)]
51803#[cfg_attr(
51804    target_arch = "arm",
51805    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51806)]
51807pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
51808    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51809    unsafe {
51810        let ret_val: int64x2_t = transmute(a);
51811        simd_shuffle!(ret_val, ret_val, [1, 0])
51812    }
51813}
51814#[doc = "Vector reinterpret cast operation"]
51815#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"]
51816#[inline]
51817#[cfg(target_endian = "little")]
51818#[target_feature(enable = "neon")]
51819#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51820#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51821#[cfg_attr(
51822    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51823    assert_instr(nop)
51824)]
51825#[cfg_attr(
51826    not(target_arch = "arm"),
51827    stable(feature = "neon_intrinsics", since = "1.59.0")
51828)]
51829#[cfg_attr(
51830    target_arch = "arm",
51831    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51832)]
51833pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
51834    unsafe { transmute(a) }
51835}
51836#[doc = "Vector reinterpret cast operation"]
51837#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"]
51838#[inline]
51839#[cfg(target_endian = "big")]
51840#[target_feature(enable = "neon")]
51841#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51842#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51843#[cfg_attr(
51844    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51845    assert_instr(nop)
51846)]
51847#[cfg_attr(
51848    not(target_arch = "arm"),
51849    stable(feature = "neon_intrinsics", since = "1.59.0")
51850)]
51851#[cfg_attr(
51852    target_arch = "arm",
51853    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51854)]
51855pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
51856    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51857    unsafe {
51858        let ret_val: uint8x16_t = transmute(a);
51859        simd_shuffle!(
51860            ret_val,
51861            ret_val,
51862            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
51863        )
51864    }
51865}
51866#[doc = "Vector reinterpret cast operation"]
51867#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"]
51868#[inline]
51869#[cfg(target_endian = "little")]
51870#[target_feature(enable = "neon")]
51871#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51872#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51873#[cfg_attr(
51874    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51875    assert_instr(nop)
51876)]
51877#[cfg_attr(
51878    not(target_arch = "arm"),
51879    stable(feature = "neon_intrinsics", since = "1.59.0")
51880)]
51881#[cfg_attr(
51882    target_arch = "arm",
51883    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51884)]
51885pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
51886    unsafe { transmute(a) }
51887}
51888#[doc = "Vector reinterpret cast operation"]
51889#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"]
51890#[inline]
51891#[cfg(target_endian = "big")]
51892#[target_feature(enable = "neon")]
51893#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51894#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51895#[cfg_attr(
51896    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51897    assert_instr(nop)
51898)]
51899#[cfg_attr(
51900    not(target_arch = "arm"),
51901    stable(feature = "neon_intrinsics", since = "1.59.0")
51902)]
51903#[cfg_attr(
51904    target_arch = "arm",
51905    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51906)]
51907pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
51908    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51909    unsafe {
51910        let ret_val: uint16x8_t = transmute(a);
51911        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51912    }
51913}
51914#[doc = "Vector reinterpret cast operation"]
51915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"]
51916#[inline]
51917#[cfg(target_endian = "little")]
51918#[target_feature(enable = "neon")]
51919#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51920#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51921#[cfg_attr(
51922    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51923    assert_instr(nop)
51924)]
51925#[cfg_attr(
51926    not(target_arch = "arm"),
51927    stable(feature = "neon_intrinsics", since = "1.59.0")
51928)]
51929#[cfg_attr(
51930    target_arch = "arm",
51931    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51932)]
51933pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
51934    unsafe { transmute(a) }
51935}
51936#[doc = "Vector reinterpret cast operation"]
51937#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"]
51938#[inline]
51939#[cfg(target_endian = "big")]
51940#[target_feature(enable = "neon")]
51941#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51942#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51943#[cfg_attr(
51944    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51945    assert_instr(nop)
51946)]
51947#[cfg_attr(
51948    not(target_arch = "arm"),
51949    stable(feature = "neon_intrinsics", since = "1.59.0")
51950)]
51951#[cfg_attr(
51952    target_arch = "arm",
51953    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51954)]
51955pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
51956    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51957    unsafe {
51958        let ret_val: uint64x2_t = transmute(a);
51959        simd_shuffle!(ret_val, ret_val, [1, 0])
51960    }
51961}
51962#[doc = "Vector reinterpret cast operation"]
51963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"]
51964#[inline]
51965#[cfg(target_endian = "little")]
51966#[target_feature(enable = "neon")]
51967#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51968#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51969#[cfg_attr(
51970    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51971    assert_instr(nop)
51972)]
51973#[cfg_attr(
51974    not(target_arch = "arm"),
51975    stable(feature = "neon_intrinsics", since = "1.59.0")
51976)]
51977#[cfg_attr(
51978    target_arch = "arm",
51979    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51980)]
51981pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
51982    unsafe { transmute(a) }
51983}
51984#[doc = "Vector reinterpret cast operation"]
51985#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"]
51986#[inline]
51987#[cfg(target_endian = "big")]
51988#[target_feature(enable = "neon")]
51989#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51990#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51991#[cfg_attr(
51992    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51993    assert_instr(nop)
51994)]
51995#[cfg_attr(
51996    not(target_arch = "arm"),
51997    stable(feature = "neon_intrinsics", since = "1.59.0")
51998)]
51999#[cfg_attr(
52000    target_arch = "arm",
52001    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52002)]
52003pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
52004    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
52005    unsafe {
52006        let ret_val: poly8x16_t = transmute(a);
52007        simd_shuffle!(
52008            ret_val,
52009            ret_val,
52010            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
52011        )
52012    }
52013}
52014#[doc = "Vector reinterpret cast operation"]
52015#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"]
52016#[inline]
52017#[cfg(target_endian = "little")]
52018#[target_feature(enable = "neon")]
52019#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52020#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52021#[cfg_attr(
52022    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52023    assert_instr(nop)
52024)]
52025#[cfg_attr(
52026    not(target_arch = "arm"),
52027    stable(feature = "neon_intrinsics", since = "1.59.0")
52028)]
52029#[cfg_attr(
52030    target_arch = "arm",
52031    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52032)]
52033pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
52034    unsafe { transmute(a) }
52035}
52036#[doc = "Vector reinterpret cast operation"]
52037#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"]
52038#[inline]
52039#[cfg(target_endian = "big")]
52040#[target_feature(enable = "neon")]
52041#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52042#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52043#[cfg_attr(
52044    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52045    assert_instr(nop)
52046)]
52047#[cfg_attr(
52048    not(target_arch = "arm"),
52049    stable(feature = "neon_intrinsics", since = "1.59.0")
52050)]
52051#[cfg_attr(
52052    target_arch = "arm",
52053    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52054)]
52055pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
52056    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
52057    unsafe {
52058        let ret_val: poly16x8_t = transmute(a);
52059        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52060    }
52061}
52062#[doc = "Vector reinterpret cast operation"]
52063#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"]
52064#[inline]
52065#[cfg(target_endian = "little")]
52066#[target_feature(enable = "neon")]
52067#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52068#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52069#[cfg_attr(
52070    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52071    assert_instr(nop)
52072)]
52073#[cfg_attr(
52074    not(target_arch = "arm"),
52075    stable(feature = "neon_intrinsics", since = "1.59.0")
52076)]
52077#[cfg_attr(
52078    target_arch = "arm",
52079    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52080)]
52081pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
52082    unsafe { transmute(a) }
52083}
52084#[doc = "Vector reinterpret cast operation"]
52085#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"]
52086#[inline]
52087#[cfg(target_endian = "big")]
52088#[target_feature(enable = "neon")]
52089#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52090#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52091#[cfg_attr(
52092    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52093    assert_instr(nop)
52094)]
52095#[cfg_attr(
52096    not(target_arch = "arm"),
52097    stable(feature = "neon_intrinsics", since = "1.59.0")
52098)]
52099#[cfg_attr(
52100    target_arch = "arm",
52101    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52102)]
52103pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
52104    unsafe {
52105        let ret_val: float32x2_t = transmute(a);
52106        simd_shuffle!(ret_val, ret_val, [1, 0])
52107    }
52108}
52109#[doc = "Vector reinterpret cast operation"]
52110#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"]
52111#[inline]
52112#[cfg(target_endian = "little")]
52113#[target_feature(enable = "neon")]
52114#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52115#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52116#[cfg_attr(
52117    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52118    assert_instr(nop)
52119)]
52120#[cfg_attr(
52121    not(target_arch = "arm"),
52122    stable(feature = "neon_intrinsics", since = "1.59.0")
52123)]
52124#[cfg_attr(
52125    target_arch = "arm",
52126    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52127)]
52128pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
52129    unsafe { transmute(a) }
52130}
52131#[doc = "Vector reinterpret cast operation"]
52132#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"]
52133#[inline]
52134#[cfg(target_endian = "big")]
52135#[target_feature(enable = "neon")]
52136#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52137#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52138#[cfg_attr(
52139    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52140    assert_instr(nop)
52141)]
52142#[cfg_attr(
52143    not(target_arch = "arm"),
52144    stable(feature = "neon_intrinsics", since = "1.59.0")
52145)]
52146#[cfg_attr(
52147    target_arch = "arm",
52148    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52149)]
52150pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
52151    unsafe {
52152        let ret_val: int8x8_t = transmute(a);
52153        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52154    }
52155}
52156#[doc = "Vector reinterpret cast operation"]
52157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"]
52158#[inline]
52159#[cfg(target_endian = "little")]
52160#[target_feature(enable = "neon")]
52161#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52162#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52163#[cfg_attr(
52164    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52165    assert_instr(nop)
52166)]
52167#[cfg_attr(
52168    not(target_arch = "arm"),
52169    stable(feature = "neon_intrinsics", since = "1.59.0")
52170)]
52171#[cfg_attr(
52172    target_arch = "arm",
52173    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52174)]
52175pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
52176    unsafe { transmute(a) }
52177}
52178#[doc = "Vector reinterpret cast operation"]
52179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"]
52180#[inline]
52181#[cfg(target_endian = "big")]
52182#[target_feature(enable = "neon")]
52183#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52184#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52185#[cfg_attr(
52186    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52187    assert_instr(nop)
52188)]
52189#[cfg_attr(
52190    not(target_arch = "arm"),
52191    stable(feature = "neon_intrinsics", since = "1.59.0")
52192)]
52193#[cfg_attr(
52194    target_arch = "arm",
52195    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52196)]
52197pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
52198    unsafe {
52199        let ret_val: int16x4_t = transmute(a);
52200        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52201    }
52202}
52203#[doc = "Vector reinterpret cast operation"]
52204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"]
52205#[inline]
52206#[cfg(target_endian = "little")]
52207#[target_feature(enable = "neon")]
52208#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52209#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52210#[cfg_attr(
52211    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52212    assert_instr(nop)
52213)]
52214#[cfg_attr(
52215    not(target_arch = "arm"),
52216    stable(feature = "neon_intrinsics", since = "1.59.0")
52217)]
52218#[cfg_attr(
52219    target_arch = "arm",
52220    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52221)]
52222pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
52223    unsafe { transmute(a) }
52224}
52225#[doc = "Vector reinterpret cast operation"]
52226#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"]
52227#[inline]
52228#[cfg(target_endian = "big")]
52229#[target_feature(enable = "neon")]
52230#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52231#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52232#[cfg_attr(
52233    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52234    assert_instr(nop)
52235)]
52236#[cfg_attr(
52237    not(target_arch = "arm"),
52238    stable(feature = "neon_intrinsics", since = "1.59.0")
52239)]
52240#[cfg_attr(
52241    target_arch = "arm",
52242    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52243)]
52244pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
52245    unsafe {
52246        let ret_val: int32x2_t = transmute(a);
52247        simd_shuffle!(ret_val, ret_val, [1, 0])
52248    }
52249}
52250#[doc = "Vector reinterpret cast operation"]
52251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u64)"]
52252#[inline]
52253#[target_feature(enable = "neon")]
52254#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52255#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52256#[cfg_attr(
52257    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52258    assert_instr(nop)
52259)]
52260#[cfg_attr(
52261    not(target_arch = "arm"),
52262    stable(feature = "neon_intrinsics", since = "1.59.0")
52263)]
52264#[cfg_attr(
52265    target_arch = "arm",
52266    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52267)]
52268pub fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t {
52269    unsafe { transmute(a) }
52270}
52271#[doc = "Vector reinterpret cast operation"]
52272#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"]
52273#[inline]
52274#[cfg(target_endian = "little")]
52275#[target_feature(enable = "neon")]
52276#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52277#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52278#[cfg_attr(
52279    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52280    assert_instr(nop)
52281)]
52282#[cfg_attr(
52283    not(target_arch = "arm"),
52284    stable(feature = "neon_intrinsics", since = "1.59.0")
52285)]
52286#[cfg_attr(
52287    target_arch = "arm",
52288    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52289)]
52290pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
52291    unsafe { transmute(a) }
52292}
52293#[doc = "Vector reinterpret cast operation"]
52294#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"]
52295#[inline]
52296#[cfg(target_endian = "big")]
52297#[target_feature(enable = "neon")]
52298#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52299#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52300#[cfg_attr(
52301    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52302    assert_instr(nop)
52303)]
52304#[cfg_attr(
52305    not(target_arch = "arm"),
52306    stable(feature = "neon_intrinsics", since = "1.59.0")
52307)]
52308#[cfg_attr(
52309    target_arch = "arm",
52310    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52311)]
52312pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
52313    unsafe {
52314        let ret_val: uint8x8_t = transmute(a);
52315        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52316    }
52317}
52318#[doc = "Vector reinterpret cast operation"]
52319#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"]
52320#[inline]
52321#[cfg(target_endian = "little")]
52322#[target_feature(enable = "neon")]
52323#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52324#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52325#[cfg_attr(
52326    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52327    assert_instr(nop)
52328)]
52329#[cfg_attr(
52330    not(target_arch = "arm"),
52331    stable(feature = "neon_intrinsics", since = "1.59.0")
52332)]
52333#[cfg_attr(
52334    target_arch = "arm",
52335    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52336)]
52337pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
52338    unsafe { transmute(a) }
52339}
52340#[doc = "Vector reinterpret cast operation"]
52341#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"]
52342#[inline]
52343#[cfg(target_endian = "big")]
52344#[target_feature(enable = "neon")]
52345#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52346#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52347#[cfg_attr(
52348    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52349    assert_instr(nop)
52350)]
52351#[cfg_attr(
52352    not(target_arch = "arm"),
52353    stable(feature = "neon_intrinsics", since = "1.59.0")
52354)]
52355#[cfg_attr(
52356    target_arch = "arm",
52357    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52358)]
52359pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
52360    unsafe {
52361        let ret_val: uint16x4_t = transmute(a);
52362        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52363    }
52364}
52365#[doc = "Vector reinterpret cast operation"]
52366#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"]
52367#[inline]
52368#[cfg(target_endian = "little")]
52369#[target_feature(enable = "neon")]
52370#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52371#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52372#[cfg_attr(
52373    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52374    assert_instr(nop)
52375)]
52376#[cfg_attr(
52377    not(target_arch = "arm"),
52378    stable(feature = "neon_intrinsics", since = "1.59.0")
52379)]
52380#[cfg_attr(
52381    target_arch = "arm",
52382    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52383)]
52384pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
52385    unsafe { transmute(a) }
52386}
52387#[doc = "Vector reinterpret cast operation"]
52388#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"]
52389#[inline]
52390#[cfg(target_endian = "big")]
52391#[target_feature(enable = "neon")]
52392#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52393#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52394#[cfg_attr(
52395    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52396    assert_instr(nop)
52397)]
52398#[cfg_attr(
52399    not(target_arch = "arm"),
52400    stable(feature = "neon_intrinsics", since = "1.59.0")
52401)]
52402#[cfg_attr(
52403    target_arch = "arm",
52404    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52405)]
52406pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
52407    unsafe {
52408        let ret_val: uint32x2_t = transmute(a);
52409        simd_shuffle!(ret_val, ret_val, [1, 0])
52410    }
52411}
52412#[doc = "Vector reinterpret cast operation"]
52413#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"]
52414#[inline]
52415#[cfg(target_endian = "little")]
52416#[target_feature(enable = "neon")]
52417#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52418#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52419#[cfg_attr(
52420    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52421    assert_instr(nop)
52422)]
52423#[cfg_attr(
52424    not(target_arch = "arm"),
52425    stable(feature = "neon_intrinsics", since = "1.59.0")
52426)]
52427#[cfg_attr(
52428    target_arch = "arm",
52429    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52430)]
52431pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
52432    unsafe { transmute(a) }
52433}
52434#[doc = "Vector reinterpret cast operation"]
52435#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"]
52436#[inline]
52437#[cfg(target_endian = "big")]
52438#[target_feature(enable = "neon")]
52439#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52440#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52441#[cfg_attr(
52442    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52443    assert_instr(nop)
52444)]
52445#[cfg_attr(
52446    not(target_arch = "arm"),
52447    stable(feature = "neon_intrinsics", since = "1.59.0")
52448)]
52449#[cfg_attr(
52450    target_arch = "arm",
52451    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52452)]
52453pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
52454    unsafe {
52455        let ret_val: poly8x8_t = transmute(a);
52456        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52457    }
52458}
52459#[doc = "Vector reinterpret cast operation"]
52460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"]
52461#[inline]
52462#[cfg(target_endian = "little")]
52463#[target_feature(enable = "neon")]
52464#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52465#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52466#[cfg_attr(
52467    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52468    assert_instr(nop)
52469)]
52470#[cfg_attr(
52471    not(target_arch = "arm"),
52472    stable(feature = "neon_intrinsics", since = "1.59.0")
52473)]
52474#[cfg_attr(
52475    target_arch = "arm",
52476    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52477)]
52478pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
52479    unsafe { transmute(a) }
52480}
52481#[doc = "Vector reinterpret cast operation"]
52482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"]
52483#[inline]
52484#[cfg(target_endian = "big")]
52485#[target_feature(enable = "neon")]
52486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52487#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52488#[cfg_attr(
52489    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52490    assert_instr(nop)
52491)]
52492#[cfg_attr(
52493    not(target_arch = "arm"),
52494    stable(feature = "neon_intrinsics", since = "1.59.0")
52495)]
52496#[cfg_attr(
52497    target_arch = "arm",
52498    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52499)]
52500pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
52501    unsafe {
52502        let ret_val: poly16x4_t = transmute(a);
52503        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52504    }
52505}
52506#[doc = "Vector reinterpret cast operation"]
52507#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"]
52508#[inline]
52509#[cfg(target_endian = "little")]
52510#[target_feature(enable = "neon")]
52511#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52512#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52513#[cfg_attr(
52514    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52515    assert_instr(nop)
52516)]
52517#[cfg_attr(
52518    not(target_arch = "arm"),
52519    stable(feature = "neon_intrinsics", since = "1.59.0")
52520)]
52521#[cfg_attr(
52522    target_arch = "arm",
52523    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52524)]
52525pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
52526    unsafe { transmute(a) }
52527}
52528#[doc = "Vector reinterpret cast operation"]
52529#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"]
52530#[inline]
52531#[cfg(target_endian = "big")]
52532#[target_feature(enable = "neon")]
52533#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52534#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52535#[cfg_attr(
52536    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52537    assert_instr(nop)
52538)]
52539#[cfg_attr(
52540    not(target_arch = "arm"),
52541    stable(feature = "neon_intrinsics", since = "1.59.0")
52542)]
52543#[cfg_attr(
52544    target_arch = "arm",
52545    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52546)]
52547pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
52548    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52549    unsafe {
52550        let ret_val: float32x4_t = transmute(a);
52551        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52552    }
52553}
52554#[doc = "Vector reinterpret cast operation"]
52555#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"]
52556#[inline]
52557#[cfg(target_endian = "little")]
52558#[target_feature(enable = "neon")]
52559#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52560#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52561#[cfg_attr(
52562    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52563    assert_instr(nop)
52564)]
52565#[cfg_attr(
52566    not(target_arch = "arm"),
52567    stable(feature = "neon_intrinsics", since = "1.59.0")
52568)]
52569#[cfg_attr(
52570    target_arch = "arm",
52571    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52572)]
52573pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
52574    unsafe { transmute(a) }
52575}
52576#[doc = "Vector reinterpret cast operation"]
52577#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"]
52578#[inline]
52579#[cfg(target_endian = "big")]
52580#[target_feature(enable = "neon")]
52581#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52582#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52583#[cfg_attr(
52584    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52585    assert_instr(nop)
52586)]
52587#[cfg_attr(
52588    not(target_arch = "arm"),
52589    stable(feature = "neon_intrinsics", since = "1.59.0")
52590)]
52591#[cfg_attr(
52592    target_arch = "arm",
52593    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52594)]
52595pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
52596    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52597    unsafe {
52598        let ret_val: int8x16_t = transmute(a);
52599        simd_shuffle!(
52600            ret_val,
52601            ret_val,
52602            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
52603        )
52604    }
52605}
52606#[doc = "Vector reinterpret cast operation"]
52607#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"]
52608#[inline]
52609#[cfg(target_endian = "little")]
52610#[target_feature(enable = "neon")]
52611#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52612#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52613#[cfg_attr(
52614    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52615    assert_instr(nop)
52616)]
52617#[cfg_attr(
52618    not(target_arch = "arm"),
52619    stable(feature = "neon_intrinsics", since = "1.59.0")
52620)]
52621#[cfg_attr(
52622    target_arch = "arm",
52623    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52624)]
52625pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
52626    unsafe { transmute(a) }
52627}
52628#[doc = "Vector reinterpret cast operation"]
52629#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"]
52630#[inline]
52631#[cfg(target_endian = "big")]
52632#[target_feature(enable = "neon")]
52633#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52634#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52635#[cfg_attr(
52636    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52637    assert_instr(nop)
52638)]
52639#[cfg_attr(
52640    not(target_arch = "arm"),
52641    stable(feature = "neon_intrinsics", since = "1.59.0")
52642)]
52643#[cfg_attr(
52644    target_arch = "arm",
52645    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52646)]
52647pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
52648    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52649    unsafe {
52650        let ret_val: int16x8_t = transmute(a);
52651        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52652    }
52653}
52654#[doc = "Vector reinterpret cast operation"]
52655#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"]
52656#[inline]
52657#[cfg(target_endian = "little")]
52658#[target_feature(enable = "neon")]
52659#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52660#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52661#[cfg_attr(
52662    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52663    assert_instr(nop)
52664)]
52665#[cfg_attr(
52666    not(target_arch = "arm"),
52667    stable(feature = "neon_intrinsics", since = "1.59.0")
52668)]
52669#[cfg_attr(
52670    target_arch = "arm",
52671    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52672)]
52673pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
52674    unsafe { transmute(a) }
52675}
52676#[doc = "Vector reinterpret cast operation"]
52677#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"]
52678#[inline]
52679#[cfg(target_endian = "big")]
52680#[target_feature(enable = "neon")]
52681#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52682#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52683#[cfg_attr(
52684    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52685    assert_instr(nop)
52686)]
52687#[cfg_attr(
52688    not(target_arch = "arm"),
52689    stable(feature = "neon_intrinsics", since = "1.59.0")
52690)]
52691#[cfg_attr(
52692    target_arch = "arm",
52693    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52694)]
52695pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
52696    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52697    unsafe {
52698        let ret_val: int32x4_t = transmute(a);
52699        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52700    }
52701}
52702#[doc = "Vector reinterpret cast operation"]
52703#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"]
52704#[inline]
52705#[cfg(target_endian = "little")]
52706#[target_feature(enable = "neon")]
52707#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52708#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52709#[cfg_attr(
52710    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52711    assert_instr(nop)
52712)]
52713#[cfg_attr(
52714    not(target_arch = "arm"),
52715    stable(feature = "neon_intrinsics", since = "1.59.0")
52716)]
52717#[cfg_attr(
52718    target_arch = "arm",
52719    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52720)]
52721pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
52722    unsafe { transmute(a) }
52723}
52724#[doc = "Vector reinterpret cast operation"]
52725#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"]
52726#[inline]
52727#[cfg(target_endian = "big")]
52728#[target_feature(enable = "neon")]
52729#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52730#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52731#[cfg_attr(
52732    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52733    assert_instr(nop)
52734)]
52735#[cfg_attr(
52736    not(target_arch = "arm"),
52737    stable(feature = "neon_intrinsics", since = "1.59.0")
52738)]
52739#[cfg_attr(
52740    target_arch = "arm",
52741    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52742)]
52743pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
52744    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52745    unsafe {
52746        let ret_val: int64x2_t = transmute(a);
52747        simd_shuffle!(ret_val, ret_val, [1, 0])
52748    }
52749}
52750#[doc = "Vector reinterpret cast operation"]
52751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"]
52752#[inline]
52753#[cfg(target_endian = "little")]
52754#[target_feature(enable = "neon")]
52755#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52756#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52757#[cfg_attr(
52758    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52759    assert_instr(nop)
52760)]
52761#[cfg_attr(
52762    not(target_arch = "arm"),
52763    stable(feature = "neon_intrinsics", since = "1.59.0")
52764)]
52765#[cfg_attr(
52766    target_arch = "arm",
52767    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52768)]
52769pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
52770    unsafe { transmute(a) }
52771}
52772#[doc = "Vector reinterpret cast operation"]
52773#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"]
52774#[inline]
52775#[cfg(target_endian = "big")]
52776#[target_feature(enable = "neon")]
52777#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52778#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52779#[cfg_attr(
52780    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52781    assert_instr(nop)
52782)]
52783#[cfg_attr(
52784    not(target_arch = "arm"),
52785    stable(feature = "neon_intrinsics", since = "1.59.0")
52786)]
52787#[cfg_attr(
52788    target_arch = "arm",
52789    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52790)]
52791pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
52792    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52793    unsafe {
52794        let ret_val: uint8x16_t = transmute(a);
52795        simd_shuffle!(
52796            ret_val,
52797            ret_val,
52798            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
52799        )
52800    }
52801}
52802#[doc = "Vector reinterpret cast operation"]
52803#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"]
52804#[inline]
52805#[cfg(target_endian = "little")]
52806#[target_feature(enable = "neon")]
52807#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52808#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52809#[cfg_attr(
52810    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52811    assert_instr(nop)
52812)]
52813#[cfg_attr(
52814    not(target_arch = "arm"),
52815    stable(feature = "neon_intrinsics", since = "1.59.0")
52816)]
52817#[cfg_attr(
52818    target_arch = "arm",
52819    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52820)]
52821pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
52822    unsafe { transmute(a) }
52823}
52824#[doc = "Vector reinterpret cast operation"]
52825#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"]
52826#[inline]
52827#[cfg(target_endian = "big")]
52828#[target_feature(enable = "neon")]
52829#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52830#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52831#[cfg_attr(
52832    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52833    assert_instr(nop)
52834)]
52835#[cfg_attr(
52836    not(target_arch = "arm"),
52837    stable(feature = "neon_intrinsics", since = "1.59.0")
52838)]
52839#[cfg_attr(
52840    target_arch = "arm",
52841    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52842)]
52843pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
52844    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52845    unsafe {
52846        let ret_val: uint16x8_t = transmute(a);
52847        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52848    }
52849}
52850#[doc = "Vector reinterpret cast operation"]
52851#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"]
52852#[inline]
52853#[cfg(target_endian = "little")]
52854#[target_feature(enable = "neon")]
52855#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52856#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52857#[cfg_attr(
52858    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52859    assert_instr(nop)
52860)]
52861#[cfg_attr(
52862    not(target_arch = "arm"),
52863    stable(feature = "neon_intrinsics", since = "1.59.0")
52864)]
52865#[cfg_attr(
52866    target_arch = "arm",
52867    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52868)]
52869pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
52870    unsafe { transmute(a) }
52871}
52872#[doc = "Vector reinterpret cast operation"]
52873#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"]
52874#[inline]
52875#[cfg(target_endian = "big")]
52876#[target_feature(enable = "neon")]
52877#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52878#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52879#[cfg_attr(
52880    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52881    assert_instr(nop)
52882)]
52883#[cfg_attr(
52884    not(target_arch = "arm"),
52885    stable(feature = "neon_intrinsics", since = "1.59.0")
52886)]
52887#[cfg_attr(
52888    target_arch = "arm",
52889    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52890)]
52891pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
52892    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52893    unsafe {
52894        let ret_val: uint32x4_t = transmute(a);
52895        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52896    }
52897}
52898#[doc = "Vector reinterpret cast operation"]
52899#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"]
52900#[inline]
52901#[cfg(target_endian = "little")]
52902#[target_feature(enable = "neon")]
52903#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52904#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52905#[cfg_attr(
52906    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52907    assert_instr(nop)
52908)]
52909#[cfg_attr(
52910    not(target_arch = "arm"),
52911    stable(feature = "neon_intrinsics", since = "1.59.0")
52912)]
52913#[cfg_attr(
52914    target_arch = "arm",
52915    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52916)]
52917pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
52918    unsafe { transmute(a) }
52919}
52920#[doc = "Vector reinterpret cast operation"]
52921#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"]
52922#[inline]
52923#[cfg(target_endian = "big")]
52924#[target_feature(enable = "neon")]
52925#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52926#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52927#[cfg_attr(
52928    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52929    assert_instr(nop)
52930)]
52931#[cfg_attr(
52932    not(target_arch = "arm"),
52933    stable(feature = "neon_intrinsics", since = "1.59.0")
52934)]
52935#[cfg_attr(
52936    target_arch = "arm",
52937    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52938)]
52939pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
52940    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52941    unsafe {
52942        let ret_val: poly8x16_t = transmute(a);
52943        simd_shuffle!(
52944            ret_val,
52945            ret_val,
52946            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
52947        )
52948    }
52949}
52950#[doc = "Vector reinterpret cast operation"]
52951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"]
52952#[inline]
52953#[cfg(target_endian = "little")]
52954#[target_feature(enable = "neon")]
52955#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52956#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52957#[cfg_attr(
52958    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52959    assert_instr(nop)
52960)]
52961#[cfg_attr(
52962    not(target_arch = "arm"),
52963    stable(feature = "neon_intrinsics", since = "1.59.0")
52964)]
52965#[cfg_attr(
52966    target_arch = "arm",
52967    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52968)]
52969pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
52970    unsafe { transmute(a) }
52971}
52972#[doc = "Vector reinterpret cast operation"]
52973#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"]
52974#[inline]
52975#[cfg(target_endian = "big")]
52976#[target_feature(enable = "neon")]
52977#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52978#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52979#[cfg_attr(
52980    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52981    assert_instr(nop)
52982)]
52983#[cfg_attr(
52984    not(target_arch = "arm"),
52985    stable(feature = "neon_intrinsics", since = "1.59.0")
52986)]
52987#[cfg_attr(
52988    target_arch = "arm",
52989    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52990)]
52991pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
52992    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52993    unsafe {
52994        let ret_val: poly16x8_t = transmute(a);
52995        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52996    }
52997}
52998#[doc = "Vector reinterpret cast operation"]
52999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"]
53000#[inline]
53001#[cfg(target_endian = "little")]
53002#[target_feature(enable = "neon")]
53003#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53004#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53005#[cfg_attr(
53006    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53007    assert_instr(nop)
53008)]
53009#[cfg_attr(
53010    not(target_arch = "arm"),
53011    stable(feature = "neon_intrinsics", since = "1.59.0")
53012)]
53013#[cfg_attr(
53014    target_arch = "arm",
53015    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53016)]
53017pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
53018    unsafe { transmute(a) }
53019}
53020#[doc = "Vector reinterpret cast operation"]
53021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"]
53022#[inline]
53023#[cfg(target_endian = "big")]
53024#[target_feature(enable = "neon")]
53025#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53026#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53027#[cfg_attr(
53028    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53029    assert_instr(nop)
53030)]
53031#[cfg_attr(
53032    not(target_arch = "arm"),
53033    stable(feature = "neon_intrinsics", since = "1.59.0")
53034)]
53035#[cfg_attr(
53036    target_arch = "arm",
53037    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53038)]
53039pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
53040    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53041    unsafe {
53042        let ret_val: float32x2_t = transmute(a);
53043        simd_shuffle!(ret_val, ret_val, [1, 0])
53044    }
53045}
53046#[doc = "Vector reinterpret cast operation"]
53047#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"]
53048#[inline]
53049#[cfg(target_endian = "little")]
53050#[target_feature(enable = "neon")]
53051#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53052#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53053#[cfg_attr(
53054    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53055    assert_instr(nop)
53056)]
53057#[cfg_attr(
53058    not(target_arch = "arm"),
53059    stable(feature = "neon_intrinsics", since = "1.59.0")
53060)]
53061#[cfg_attr(
53062    target_arch = "arm",
53063    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53064)]
53065pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
53066    unsafe { transmute(a) }
53067}
53068#[doc = "Vector reinterpret cast operation"]
53069#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"]
53070#[inline]
53071#[cfg(target_endian = "big")]
53072#[target_feature(enable = "neon")]
53073#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53074#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53075#[cfg_attr(
53076    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53077    assert_instr(nop)
53078)]
53079#[cfg_attr(
53080    not(target_arch = "arm"),
53081    stable(feature = "neon_intrinsics", since = "1.59.0")
53082)]
53083#[cfg_attr(
53084    target_arch = "arm",
53085    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53086)]
53087pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
53088    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53089    unsafe {
53090        let ret_val: int8x8_t = transmute(a);
53091        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
53092    }
53093}
53094#[doc = "Vector reinterpret cast operation"]
53095#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"]
53096#[inline]
53097#[cfg(target_endian = "little")]
53098#[target_feature(enable = "neon")]
53099#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53100#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53101#[cfg_attr(
53102    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53103    assert_instr(nop)
53104)]
53105#[cfg_attr(
53106    not(target_arch = "arm"),
53107    stable(feature = "neon_intrinsics", since = "1.59.0")
53108)]
53109#[cfg_attr(
53110    target_arch = "arm",
53111    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53112)]
53113pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
53114    unsafe { transmute(a) }
53115}
53116#[doc = "Vector reinterpret cast operation"]
53117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"]
53118#[inline]
53119#[cfg(target_endian = "big")]
53120#[target_feature(enable = "neon")]
53121#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53122#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53123#[cfg_attr(
53124    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53125    assert_instr(nop)
53126)]
53127#[cfg_attr(
53128    not(target_arch = "arm"),
53129    stable(feature = "neon_intrinsics", since = "1.59.0")
53130)]
53131#[cfg_attr(
53132    target_arch = "arm",
53133    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53134)]
53135pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
53136    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53137    unsafe {
53138        let ret_val: int16x4_t = transmute(a);
53139        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53140    }
53141}
53142#[doc = "Vector reinterpret cast operation"]
53143#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"]
53144#[inline]
53145#[cfg(target_endian = "little")]
53146#[target_feature(enable = "neon")]
53147#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53148#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53149#[cfg_attr(
53150    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53151    assert_instr(nop)
53152)]
53153#[cfg_attr(
53154    not(target_arch = "arm"),
53155    stable(feature = "neon_intrinsics", since = "1.59.0")
53156)]
53157#[cfg_attr(
53158    target_arch = "arm",
53159    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53160)]
53161pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
53162    unsafe { transmute(a) }
53163}
53164#[doc = "Vector reinterpret cast operation"]
53165#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"]
53166#[inline]
53167#[cfg(target_endian = "big")]
53168#[target_feature(enable = "neon")]
53169#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53170#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53171#[cfg_attr(
53172    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53173    assert_instr(nop)
53174)]
53175#[cfg_attr(
53176    not(target_arch = "arm"),
53177    stable(feature = "neon_intrinsics", since = "1.59.0")
53178)]
53179#[cfg_attr(
53180    target_arch = "arm",
53181    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53182)]
53183pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
53184    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53185    unsafe {
53186        let ret_val: int32x2_t = transmute(a);
53187        simd_shuffle!(ret_val, ret_val, [1, 0])
53188    }
53189}
53190#[doc = "Vector reinterpret cast operation"]
53191#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"]
53192#[inline]
53193#[cfg(target_endian = "little")]
53194#[target_feature(enable = "neon")]
53195#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53196#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53197#[cfg_attr(
53198    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53199    assert_instr(nop)
53200)]
53201#[cfg_attr(
53202    not(target_arch = "arm"),
53203    stable(feature = "neon_intrinsics", since = "1.59.0")
53204)]
53205#[cfg_attr(
53206    target_arch = "arm",
53207    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53208)]
53209pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
53210    unsafe { transmute(a) }
53211}
53212#[doc = "Vector reinterpret cast operation"]
53213#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"]
53214#[inline]
53215#[cfg(target_endian = "big")]
53216#[target_feature(enable = "neon")]
53217#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53218#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53219#[cfg_attr(
53220    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53221    assert_instr(nop)
53222)]
53223#[cfg_attr(
53224    not(target_arch = "arm"),
53225    stable(feature = "neon_intrinsics", since = "1.59.0")
53226)]
53227#[cfg_attr(
53228    target_arch = "arm",
53229    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53230)]
53231pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
53232    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53233    unsafe { transmute(a) }
53234}
53235#[doc = "Vector reinterpret cast operation"]
53236#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"]
53237#[inline]
53238#[cfg(target_endian = "little")]
53239#[target_feature(enable = "neon")]
53240#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53241#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53242#[cfg_attr(
53243    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53244    assert_instr(nop)
53245)]
53246#[cfg_attr(
53247    not(target_arch = "arm"),
53248    stable(feature = "neon_intrinsics", since = "1.59.0")
53249)]
53250#[cfg_attr(
53251    target_arch = "arm",
53252    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53253)]
53254pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
53255    unsafe { transmute(a) }
53256}
53257#[doc = "Vector reinterpret cast operation"]
53258#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"]
53259#[inline]
53260#[cfg(target_endian = "big")]
53261#[target_feature(enable = "neon")]
53262#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53263#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53264#[cfg_attr(
53265    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53266    assert_instr(nop)
53267)]
53268#[cfg_attr(
53269    not(target_arch = "arm"),
53270    stable(feature = "neon_intrinsics", since = "1.59.0")
53271)]
53272#[cfg_attr(
53273    target_arch = "arm",
53274    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53275)]
53276pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
53277    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53278    unsafe {
53279        let ret_val: uint8x8_t = transmute(a);
53280        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
53281    }
53282}
53283#[doc = "Vector reinterpret cast operation"]
53284#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"]
53285#[inline]
53286#[cfg(target_endian = "little")]
53287#[target_feature(enable = "neon")]
53288#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53289#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53290#[cfg_attr(
53291    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53292    assert_instr(nop)
53293)]
53294#[cfg_attr(
53295    not(target_arch = "arm"),
53296    stable(feature = "neon_intrinsics", since = "1.59.0")
53297)]
53298#[cfg_attr(
53299    target_arch = "arm",
53300    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53301)]
53302pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
53303    unsafe { transmute(a) }
53304}
53305#[doc = "Vector reinterpret cast operation"]
53306#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"]
53307#[inline]
53308#[cfg(target_endian = "big")]
53309#[target_feature(enable = "neon")]
53310#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53311#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53312#[cfg_attr(
53313    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53314    assert_instr(nop)
53315)]
53316#[cfg_attr(
53317    not(target_arch = "arm"),
53318    stable(feature = "neon_intrinsics", since = "1.59.0")
53319)]
53320#[cfg_attr(
53321    target_arch = "arm",
53322    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53323)]
53324pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
53325    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53326    unsafe {
53327        let ret_val: uint16x4_t = transmute(a);
53328        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53329    }
53330}
53331#[doc = "Vector reinterpret cast operation"]
53332#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"]
53333#[inline]
53334#[cfg(target_endian = "little")]
53335#[target_feature(enable = "neon")]
53336#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53337#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53338#[cfg_attr(
53339    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53340    assert_instr(nop)
53341)]
53342#[cfg_attr(
53343    not(target_arch = "arm"),
53344    stable(feature = "neon_intrinsics", since = "1.59.0")
53345)]
53346#[cfg_attr(
53347    target_arch = "arm",
53348    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53349)]
53350pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
53351    unsafe { transmute(a) }
53352}
53353#[doc = "Vector reinterpret cast operation"]
53354#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"]
53355#[inline]
53356#[cfg(target_endian = "big")]
53357#[target_feature(enable = "neon")]
53358#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53359#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53360#[cfg_attr(
53361    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53362    assert_instr(nop)
53363)]
53364#[cfg_attr(
53365    not(target_arch = "arm"),
53366    stable(feature = "neon_intrinsics", since = "1.59.0")
53367)]
53368#[cfg_attr(
53369    target_arch = "arm",
53370    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53371)]
53372pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
53373    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53374    unsafe {
53375        let ret_val: uint32x2_t = transmute(a);
53376        simd_shuffle!(ret_val, ret_val, [1, 0])
53377    }
53378}
53379#[doc = "Vector reinterpret cast operation"]
53380#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"]
53381#[inline]
53382#[cfg(target_endian = "little")]
53383#[target_feature(enable = "neon")]
53384#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53385#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53386#[cfg_attr(
53387    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53388    assert_instr(nop)
53389)]
53390#[cfg_attr(
53391    not(target_arch = "arm"),
53392    stable(feature = "neon_intrinsics", since = "1.59.0")
53393)]
53394#[cfg_attr(
53395    target_arch = "arm",
53396    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53397)]
53398pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
53399    unsafe { transmute(a) }
53400}
53401#[doc = "Vector reinterpret cast operation"]
53402#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"]
53403#[inline]
53404#[cfg(target_endian = "big")]
53405#[target_feature(enable = "neon")]
53406#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53407#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53408#[cfg_attr(
53409    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53410    assert_instr(nop)
53411)]
53412#[cfg_attr(
53413    not(target_arch = "arm"),
53414    stable(feature = "neon_intrinsics", since = "1.59.0")
53415)]
53416#[cfg_attr(
53417    target_arch = "arm",
53418    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53419)]
53420pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
53421    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53422    unsafe { transmute(a) }
53423}
53424#[doc = "Vector reinterpret cast operation"]
53425#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"]
53426#[inline]
53427#[cfg(target_endian = "little")]
53428#[target_feature(enable = "neon")]
53429#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53430#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53431#[cfg_attr(
53432    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53433    assert_instr(nop)
53434)]
53435#[cfg_attr(
53436    not(target_arch = "arm"),
53437    stable(feature = "neon_intrinsics", since = "1.59.0")
53438)]
53439#[cfg_attr(
53440    target_arch = "arm",
53441    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53442)]
53443pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
53444    unsafe { transmute(a) }
53445}
53446#[doc = "Vector reinterpret cast operation"]
53447#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"]
53448#[inline]
53449#[cfg(target_endian = "big")]
53450#[target_feature(enable = "neon")]
53451#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53452#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53453#[cfg_attr(
53454    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53455    assert_instr(nop)
53456)]
53457#[cfg_attr(
53458    not(target_arch = "arm"),
53459    stable(feature = "neon_intrinsics", since = "1.59.0")
53460)]
53461#[cfg_attr(
53462    target_arch = "arm",
53463    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53464)]
53465pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
53466    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53467    unsafe {
53468        let ret_val: poly16x4_t = transmute(a);
53469        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53470    }
53471}
53472#[doc = "Vector reinterpret cast operation"]
53473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"]
53474#[inline]
53475#[cfg(target_endian = "little")]
53476#[target_feature(enable = "neon")]
53477#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53478#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53479#[cfg_attr(
53480    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53481    assert_instr(nop)
53482)]
53483#[cfg_attr(
53484    not(target_arch = "arm"),
53485    stable(feature = "neon_intrinsics", since = "1.59.0")
53486)]
53487#[cfg_attr(
53488    target_arch = "arm",
53489    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53490)]
53491pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
53492    unsafe { transmute(a) }
53493}
53494#[doc = "Vector reinterpret cast operation"]
53495#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"]
53496#[inline]
53497#[cfg(target_endian = "big")]
53498#[target_feature(enable = "neon")]
53499#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53500#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53501#[cfg_attr(
53502    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53503    assert_instr(nop)
53504)]
53505#[cfg_attr(
53506    not(target_arch = "arm"),
53507    stable(feature = "neon_intrinsics", since = "1.59.0")
53508)]
53509#[cfg_attr(
53510    target_arch = "arm",
53511    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53512)]
53513pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
53514    let a: poly8x16_t =
53515        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53516    unsafe {
53517        let ret_val: float32x4_t = transmute(a);
53518        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53519    }
53520}
53521#[doc = "Vector reinterpret cast operation"]
53522#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"]
53523#[inline]
53524#[cfg(target_endian = "little")]
53525#[target_feature(enable = "neon")]
53526#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53527#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53528#[cfg_attr(
53529    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53530    assert_instr(nop)
53531)]
53532#[cfg_attr(
53533    not(target_arch = "arm"),
53534    stable(feature = "neon_intrinsics", since = "1.59.0")
53535)]
53536#[cfg_attr(
53537    target_arch = "arm",
53538    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53539)]
53540pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
53541    unsafe { transmute(a) }
53542}
53543#[doc = "Vector reinterpret cast operation"]
53544#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"]
53545#[inline]
53546#[cfg(target_endian = "big")]
53547#[target_feature(enable = "neon")]
53548#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53549#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53550#[cfg_attr(
53551    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53552    assert_instr(nop)
53553)]
53554#[cfg_attr(
53555    not(target_arch = "arm"),
53556    stable(feature = "neon_intrinsics", since = "1.59.0")
53557)]
53558#[cfg_attr(
53559    target_arch = "arm",
53560    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53561)]
53562pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
53563    let a: poly8x16_t =
53564        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53565    unsafe {
53566        let ret_val: int8x16_t = transmute(a);
53567        simd_shuffle!(
53568            ret_val,
53569            ret_val,
53570            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
53571        )
53572    }
53573}
53574#[doc = "Vector reinterpret cast operation"]
53575#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"]
53576#[inline]
53577#[cfg(target_endian = "little")]
53578#[target_feature(enable = "neon")]
53579#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53580#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53581#[cfg_attr(
53582    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53583    assert_instr(nop)
53584)]
53585#[cfg_attr(
53586    not(target_arch = "arm"),
53587    stable(feature = "neon_intrinsics", since = "1.59.0")
53588)]
53589#[cfg_attr(
53590    target_arch = "arm",
53591    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53592)]
53593pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
53594    unsafe { transmute(a) }
53595}
53596#[doc = "Vector reinterpret cast operation"]
53597#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"]
53598#[inline]
53599#[cfg(target_endian = "big")]
53600#[target_feature(enable = "neon")]
53601#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53602#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53603#[cfg_attr(
53604    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53605    assert_instr(nop)
53606)]
53607#[cfg_attr(
53608    not(target_arch = "arm"),
53609    stable(feature = "neon_intrinsics", since = "1.59.0")
53610)]
53611#[cfg_attr(
53612    target_arch = "arm",
53613    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53614)]
53615pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
53616    let a: poly8x16_t =
53617        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53618    unsafe {
53619        let ret_val: int16x8_t = transmute(a);
53620        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
53621    }
53622}
53623#[doc = "Vector reinterpret cast operation"]
53624#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"]
53625#[inline]
53626#[cfg(target_endian = "little")]
53627#[target_feature(enable = "neon")]
53628#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53629#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53630#[cfg_attr(
53631    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53632    assert_instr(nop)
53633)]
53634#[cfg_attr(
53635    not(target_arch = "arm"),
53636    stable(feature = "neon_intrinsics", since = "1.59.0")
53637)]
53638#[cfg_attr(
53639    target_arch = "arm",
53640    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53641)]
53642pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
53643    unsafe { transmute(a) }
53644}
53645#[doc = "Vector reinterpret cast operation"]
53646#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"]
53647#[inline]
53648#[cfg(target_endian = "big")]
53649#[target_feature(enable = "neon")]
53650#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53651#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53652#[cfg_attr(
53653    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53654    assert_instr(nop)
53655)]
53656#[cfg_attr(
53657    not(target_arch = "arm"),
53658    stable(feature = "neon_intrinsics", since = "1.59.0")
53659)]
53660#[cfg_attr(
53661    target_arch = "arm",
53662    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53663)]
53664pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
53665    let a: poly8x16_t =
53666        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53667    unsafe {
53668        let ret_val: int32x4_t = transmute(a);
53669        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53670    }
53671}
53672#[doc = "Vector reinterpret cast operation"]
53673#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"]
53674#[inline]
53675#[cfg(target_endian = "little")]
53676#[target_feature(enable = "neon")]
53677#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53678#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53679#[cfg_attr(
53680    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53681    assert_instr(nop)
53682)]
53683#[cfg_attr(
53684    not(target_arch = "arm"),
53685    stable(feature = "neon_intrinsics", since = "1.59.0")
53686)]
53687#[cfg_attr(
53688    target_arch = "arm",
53689    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53690)]
53691pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
53692    unsafe { transmute(a) }
53693}
53694#[doc = "Vector reinterpret cast operation"]
53695#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"]
53696#[inline]
53697#[cfg(target_endian = "big")]
53698#[target_feature(enable = "neon")]
53699#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53700#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53701#[cfg_attr(
53702    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53703    assert_instr(nop)
53704)]
53705#[cfg_attr(
53706    not(target_arch = "arm"),
53707    stable(feature = "neon_intrinsics", since = "1.59.0")
53708)]
53709#[cfg_attr(
53710    target_arch = "arm",
53711    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53712)]
53713pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
53714    let a: poly8x16_t =
53715        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53716    unsafe {
53717        let ret_val: int64x2_t = transmute(a);
53718        simd_shuffle!(ret_val, ret_val, [1, 0])
53719    }
53720}
53721#[doc = "Vector reinterpret cast operation"]
53722#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"]
53723#[inline]
53724#[cfg(target_endian = "little")]
53725#[target_feature(enable = "neon")]
53726#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53727#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53728#[cfg_attr(
53729    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53730    assert_instr(nop)
53731)]
53732#[cfg_attr(
53733    not(target_arch = "arm"),
53734    stable(feature = "neon_intrinsics", since = "1.59.0")
53735)]
53736#[cfg_attr(
53737    target_arch = "arm",
53738    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53739)]
53740pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
53741    unsafe { transmute(a) }
53742}
53743#[doc = "Vector reinterpret cast operation"]
53744#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"]
53745#[inline]
53746#[cfg(target_endian = "big")]
53747#[target_feature(enable = "neon")]
53748#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53749#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53750#[cfg_attr(
53751    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53752    assert_instr(nop)
53753)]
53754#[cfg_attr(
53755    not(target_arch = "arm"),
53756    stable(feature = "neon_intrinsics", since = "1.59.0")
53757)]
53758#[cfg_attr(
53759    target_arch = "arm",
53760    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53761)]
53762pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
53763    let a: poly8x16_t =
53764        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53765    unsafe {
53766        let ret_val: uint8x16_t = transmute(a);
53767        simd_shuffle!(
53768            ret_val,
53769            ret_val,
53770            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
53771        )
53772    }
53773}
53774#[doc = "Vector reinterpret cast operation"]
53775#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"]
53776#[inline]
53777#[cfg(target_endian = "little")]
53778#[target_feature(enable = "neon")]
53779#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53780#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53781#[cfg_attr(
53782    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53783    assert_instr(nop)
53784)]
53785#[cfg_attr(
53786    not(target_arch = "arm"),
53787    stable(feature = "neon_intrinsics", since = "1.59.0")
53788)]
53789#[cfg_attr(
53790    target_arch = "arm",
53791    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53792)]
53793pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
53794    unsafe { transmute(a) }
53795}
53796#[doc = "Vector reinterpret cast operation"]
53797#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"]
53798#[inline]
53799#[cfg(target_endian = "big")]
53800#[target_feature(enable = "neon")]
53801#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53802#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53803#[cfg_attr(
53804    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53805    assert_instr(nop)
53806)]
53807#[cfg_attr(
53808    not(target_arch = "arm"),
53809    stable(feature = "neon_intrinsics", since = "1.59.0")
53810)]
53811#[cfg_attr(
53812    target_arch = "arm",
53813    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53814)]
53815pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
53816    let a: poly8x16_t =
53817        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53818    unsafe {
53819        let ret_val: uint16x8_t = transmute(a);
53820        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
53821    }
53822}
53823#[doc = "Vector reinterpret cast operation"]
53824#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"]
53825#[inline]
53826#[cfg(target_endian = "little")]
53827#[target_feature(enable = "neon")]
53828#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53829#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53830#[cfg_attr(
53831    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53832    assert_instr(nop)
53833)]
53834#[cfg_attr(
53835    not(target_arch = "arm"),
53836    stable(feature = "neon_intrinsics", since = "1.59.0")
53837)]
53838#[cfg_attr(
53839    target_arch = "arm",
53840    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53841)]
53842pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
53843    unsafe { transmute(a) }
53844}
53845#[doc = "Vector reinterpret cast operation"]
53846#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"]
53847#[inline]
53848#[cfg(target_endian = "big")]
53849#[target_feature(enable = "neon")]
53850#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53851#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53852#[cfg_attr(
53853    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53854    assert_instr(nop)
53855)]
53856#[cfg_attr(
53857    not(target_arch = "arm"),
53858    stable(feature = "neon_intrinsics", since = "1.59.0")
53859)]
53860#[cfg_attr(
53861    target_arch = "arm",
53862    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53863)]
53864pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
53865    let a: poly8x16_t =
53866        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53867    unsafe {
53868        let ret_val: uint32x4_t = transmute(a);
53869        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53870    }
53871}
53872#[doc = "Vector reinterpret cast operation"]
53873#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"]
53874#[inline]
53875#[cfg(target_endian = "little")]
53876#[target_feature(enable = "neon")]
53877#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53878#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53879#[cfg_attr(
53880    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53881    assert_instr(nop)
53882)]
53883#[cfg_attr(
53884    not(target_arch = "arm"),
53885    stable(feature = "neon_intrinsics", since = "1.59.0")
53886)]
53887#[cfg_attr(
53888    target_arch = "arm",
53889    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53890)]
53891pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
53892    unsafe { transmute(a) }
53893}
53894#[doc = "Vector reinterpret cast operation"]
53895#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"]
53896#[inline]
53897#[cfg(target_endian = "big")]
53898#[target_feature(enable = "neon")]
53899#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53900#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53901#[cfg_attr(
53902    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53903    assert_instr(nop)
53904)]
53905#[cfg_attr(
53906    not(target_arch = "arm"),
53907    stable(feature = "neon_intrinsics", since = "1.59.0")
53908)]
53909#[cfg_attr(
53910    target_arch = "arm",
53911    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53912)]
53913pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
53914    let a: poly8x16_t =
53915        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53916    unsafe {
53917        let ret_val: uint64x2_t = transmute(a);
53918        simd_shuffle!(ret_val, ret_val, [1, 0])
53919    }
53920}
53921#[doc = "Vector reinterpret cast operation"]
53922#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"]
53923#[inline]
53924#[cfg(target_endian = "little")]
53925#[target_feature(enable = "neon")]
53926#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53927#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53928#[cfg_attr(
53929    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53930    assert_instr(nop)
53931)]
53932#[cfg_attr(
53933    not(target_arch = "arm"),
53934    stable(feature = "neon_intrinsics", since = "1.59.0")
53935)]
53936#[cfg_attr(
53937    target_arch = "arm",
53938    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53939)]
53940pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
53941    unsafe { transmute(a) }
53942}
53943#[doc = "Vector reinterpret cast operation"]
53944#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"]
53945#[inline]
53946#[cfg(target_endian = "big")]
53947#[target_feature(enable = "neon")]
53948#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53949#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53950#[cfg_attr(
53951    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53952    assert_instr(nop)
53953)]
53954#[cfg_attr(
53955    not(target_arch = "arm"),
53956    stable(feature = "neon_intrinsics", since = "1.59.0")
53957)]
53958#[cfg_attr(
53959    target_arch = "arm",
53960    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53961)]
53962pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
53963    let a: poly8x16_t =
53964        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53965    unsafe {
53966        let ret_val: poly16x8_t = transmute(a);
53967        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
53968    }
53969}
53970#[doc = "Vector reinterpret cast operation"]
53971#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"]
53972#[inline]
53973#[cfg(target_endian = "little")]
53974#[target_feature(enable = "neon")]
53975#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53976#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53977#[cfg_attr(
53978    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53979    assert_instr(nop)
53980)]
53981#[cfg_attr(
53982    not(target_arch = "arm"),
53983    stable(feature = "neon_intrinsics", since = "1.59.0")
53984)]
53985#[cfg_attr(
53986    target_arch = "arm",
53987    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53988)]
53989pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
53990    unsafe { transmute(a) }
53991}
53992#[doc = "Vector reinterpret cast operation"]
53993#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"]
53994#[inline]
53995#[cfg(target_endian = "big")]
53996#[target_feature(enable = "neon")]
53997#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53998#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53999#[cfg_attr(
54000    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54001    assert_instr(nop)
54002)]
54003#[cfg_attr(
54004    not(target_arch = "arm"),
54005    stable(feature = "neon_intrinsics", since = "1.59.0")
54006)]
54007#[cfg_attr(
54008    target_arch = "arm",
54009    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54010)]
54011pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
54012    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54013    unsafe {
54014        let ret_val: float32x2_t = transmute(a);
54015        simd_shuffle!(ret_val, ret_val, [1, 0])
54016    }
54017}
54018#[doc = "Vector reinterpret cast operation"]
54019#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"]
54020#[inline]
54021#[cfg(target_endian = "little")]
54022#[target_feature(enable = "neon")]
54023#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54024#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54025#[cfg_attr(
54026    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54027    assert_instr(nop)
54028)]
54029#[cfg_attr(
54030    not(target_arch = "arm"),
54031    stable(feature = "neon_intrinsics", since = "1.59.0")
54032)]
54033#[cfg_attr(
54034    target_arch = "arm",
54035    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54036)]
54037pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
54038    unsafe { transmute(a) }
54039}
54040#[doc = "Vector reinterpret cast operation"]
54041#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"]
54042#[inline]
54043#[cfg(target_endian = "big")]
54044#[target_feature(enable = "neon")]
54045#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54046#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54047#[cfg_attr(
54048    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54049    assert_instr(nop)
54050)]
54051#[cfg_attr(
54052    not(target_arch = "arm"),
54053    stable(feature = "neon_intrinsics", since = "1.59.0")
54054)]
54055#[cfg_attr(
54056    target_arch = "arm",
54057    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54058)]
54059pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
54060    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54061    unsafe {
54062        let ret_val: int8x8_t = transmute(a);
54063        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
54064    }
54065}
54066#[doc = "Vector reinterpret cast operation"]
54067#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"]
54068#[inline]
54069#[cfg(target_endian = "little")]
54070#[target_feature(enable = "neon")]
54071#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54072#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54073#[cfg_attr(
54074    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54075    assert_instr(nop)
54076)]
54077#[cfg_attr(
54078    not(target_arch = "arm"),
54079    stable(feature = "neon_intrinsics", since = "1.59.0")
54080)]
54081#[cfg_attr(
54082    target_arch = "arm",
54083    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54084)]
54085pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
54086    unsafe { transmute(a) }
54087}
54088#[doc = "Vector reinterpret cast operation"]
54089#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"]
54090#[inline]
54091#[cfg(target_endian = "big")]
54092#[target_feature(enable = "neon")]
54093#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54094#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54095#[cfg_attr(
54096    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54097    assert_instr(nop)
54098)]
54099#[cfg_attr(
54100    not(target_arch = "arm"),
54101    stable(feature = "neon_intrinsics", since = "1.59.0")
54102)]
54103#[cfg_attr(
54104    target_arch = "arm",
54105    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54106)]
54107pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
54108    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54109    unsafe {
54110        let ret_val: int16x4_t = transmute(a);
54111        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
54112    }
54113}
54114#[doc = "Vector reinterpret cast operation"]
54115#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"]
54116#[inline]
54117#[cfg(target_endian = "little")]
54118#[target_feature(enable = "neon")]
54119#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54120#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54121#[cfg_attr(
54122    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54123    assert_instr(nop)
54124)]
54125#[cfg_attr(
54126    not(target_arch = "arm"),
54127    stable(feature = "neon_intrinsics", since = "1.59.0")
54128)]
54129#[cfg_attr(
54130    target_arch = "arm",
54131    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54132)]
54133pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
54134    unsafe { transmute(a) }
54135}
54136#[doc = "Vector reinterpret cast operation"]
54137#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"]
54138#[inline]
54139#[cfg(target_endian = "big")]
54140#[target_feature(enable = "neon")]
54141#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54142#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54143#[cfg_attr(
54144    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54145    assert_instr(nop)
54146)]
54147#[cfg_attr(
54148    not(target_arch = "arm"),
54149    stable(feature = "neon_intrinsics", since = "1.59.0")
54150)]
54151#[cfg_attr(
54152    target_arch = "arm",
54153    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54154)]
54155pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
54156    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54157    unsafe {
54158        let ret_val: int32x2_t = transmute(a);
54159        simd_shuffle!(ret_val, ret_val, [1, 0])
54160    }
54161}
54162#[doc = "Vector reinterpret cast operation"]
54163#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"]
54164#[inline]
54165#[cfg(target_endian = "little")]
54166#[target_feature(enable = "neon")]
54167#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54168#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54169#[cfg_attr(
54170    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54171    assert_instr(nop)
54172)]
54173#[cfg_attr(
54174    not(target_arch = "arm"),
54175    stable(feature = "neon_intrinsics", since = "1.59.0")
54176)]
54177#[cfg_attr(
54178    target_arch = "arm",
54179    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54180)]
54181pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
54182    unsafe { transmute(a) }
54183}
54184#[doc = "Vector reinterpret cast operation"]
54185#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"]
54186#[inline]
54187#[cfg(target_endian = "big")]
54188#[target_feature(enable = "neon")]
54189#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54190#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54191#[cfg_attr(
54192    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54193    assert_instr(nop)
54194)]
54195#[cfg_attr(
54196    not(target_arch = "arm"),
54197    stable(feature = "neon_intrinsics", since = "1.59.0")
54198)]
54199#[cfg_attr(
54200    target_arch = "arm",
54201    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54202)]
54203pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
54204    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54205    unsafe { transmute(a) }
54206}
54207#[doc = "Vector reinterpret cast operation"]
54208#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"]
54209#[inline]
54210#[cfg(target_endian = "little")]
54211#[target_feature(enable = "neon")]
54212#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54213#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54214#[cfg_attr(
54215    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54216    assert_instr(nop)
54217)]
54218#[cfg_attr(
54219    not(target_arch = "arm"),
54220    stable(feature = "neon_intrinsics", since = "1.59.0")
54221)]
54222#[cfg_attr(
54223    target_arch = "arm",
54224    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54225)]
54226pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
54227    unsafe { transmute(a) }
54228}
54229#[doc = "Vector reinterpret cast operation"]
54230#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"]
54231#[inline]
54232#[cfg(target_endian = "big")]
54233#[target_feature(enable = "neon")]
54234#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54235#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54236#[cfg_attr(
54237    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54238    assert_instr(nop)
54239)]
54240#[cfg_attr(
54241    not(target_arch = "arm"),
54242    stable(feature = "neon_intrinsics", since = "1.59.0")
54243)]
54244#[cfg_attr(
54245    target_arch = "arm",
54246    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54247)]
54248pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
54249    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54250    unsafe {
54251        let ret_val: uint8x8_t = transmute(a);
54252        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
54253    }
54254}
54255#[doc = "Vector reinterpret cast operation"]
54256#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"]
54257#[inline]
54258#[cfg(target_endian = "little")]
54259#[target_feature(enable = "neon")]
54260#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54261#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54262#[cfg_attr(
54263    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54264    assert_instr(nop)
54265)]
54266#[cfg_attr(
54267    not(target_arch = "arm"),
54268    stable(feature = "neon_intrinsics", since = "1.59.0")
54269)]
54270#[cfg_attr(
54271    target_arch = "arm",
54272    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54273)]
54274pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
54275    unsafe { transmute(a) }
54276}
54277#[doc = "Vector reinterpret cast operation"]
54278#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"]
54279#[inline]
54280#[cfg(target_endian = "big")]
54281#[target_feature(enable = "neon")]
54282#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54283#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54284#[cfg_attr(
54285    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54286    assert_instr(nop)
54287)]
54288#[cfg_attr(
54289    not(target_arch = "arm"),
54290    stable(feature = "neon_intrinsics", since = "1.59.0")
54291)]
54292#[cfg_attr(
54293    target_arch = "arm",
54294    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54295)]
54296pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
54297    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54298    unsafe {
54299        let ret_val: uint16x4_t = transmute(a);
54300        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
54301    }
54302}
54303#[doc = "Vector reinterpret cast operation"]
54304#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"]
54305#[inline]
54306#[cfg(target_endian = "little")]
54307#[target_feature(enable = "neon")]
54308#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54309#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54310#[cfg_attr(
54311    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54312    assert_instr(nop)
54313)]
54314#[cfg_attr(
54315    not(target_arch = "arm"),
54316    stable(feature = "neon_intrinsics", since = "1.59.0")
54317)]
54318#[cfg_attr(
54319    target_arch = "arm",
54320    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54321)]
54322pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
54323    unsafe { transmute(a) }
54324}
54325#[doc = "Vector reinterpret cast operation"]
54326#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"]
54327#[inline]
54328#[cfg(target_endian = "big")]
54329#[target_feature(enable = "neon")]
54330#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54331#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54332#[cfg_attr(
54333    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54334    assert_instr(nop)
54335)]
54336#[cfg_attr(
54337    not(target_arch = "arm"),
54338    stable(feature = "neon_intrinsics", since = "1.59.0")
54339)]
54340#[cfg_attr(
54341    target_arch = "arm",
54342    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54343)]
54344pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
54345    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54346    unsafe {
54347        let ret_val: uint32x2_t = transmute(a);
54348        simd_shuffle!(ret_val, ret_val, [1, 0])
54349    }
54350}
54351#[doc = "Vector reinterpret cast operation"]
54352#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"]
54353#[inline]
54354#[cfg(target_endian = "little")]
54355#[target_feature(enable = "neon")]
54356#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54357#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54358#[cfg_attr(
54359    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54360    assert_instr(nop)
54361)]
54362#[cfg_attr(
54363    not(target_arch = "arm"),
54364    stable(feature = "neon_intrinsics", since = "1.59.0")
54365)]
54366#[cfg_attr(
54367    target_arch = "arm",
54368    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54369)]
54370pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
54371    unsafe { transmute(a) }
54372}
54373#[doc = "Vector reinterpret cast operation"]
54374#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"]
54375#[inline]
54376#[cfg(target_endian = "big")]
54377#[target_feature(enable = "neon")]
54378#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54379#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54380#[cfg_attr(
54381    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54382    assert_instr(nop)
54383)]
54384#[cfg_attr(
54385    not(target_arch = "arm"),
54386    stable(feature = "neon_intrinsics", since = "1.59.0")
54387)]
54388#[cfg_attr(
54389    target_arch = "arm",
54390    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54391)]
54392pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
54393    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54394    unsafe { transmute(a) }
54395}
54396#[doc = "Vector reinterpret cast operation"]
54397#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"]
54398#[inline]
54399#[cfg(target_endian = "little")]
54400#[target_feature(enable = "neon")]
54401#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54402#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54403#[cfg_attr(
54404    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54405    assert_instr(nop)
54406)]
54407#[cfg_attr(
54408    not(target_arch = "arm"),
54409    stable(feature = "neon_intrinsics", since = "1.59.0")
54410)]
54411#[cfg_attr(
54412    target_arch = "arm",
54413    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54414)]
54415pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
54416    unsafe { transmute(a) }
54417}
54418#[doc = "Vector reinterpret cast operation"]
54419#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"]
54420#[inline]
54421#[cfg(target_endian = "big")]
54422#[target_feature(enable = "neon")]
54423#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54424#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54425#[cfg_attr(
54426    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54427    assert_instr(nop)
54428)]
54429#[cfg_attr(
54430    not(target_arch = "arm"),
54431    stable(feature = "neon_intrinsics", since = "1.59.0")
54432)]
54433#[cfg_attr(
54434    target_arch = "arm",
54435    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54436)]
54437pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
54438    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54439    unsafe {
54440        let ret_val: poly8x8_t = transmute(a);
54441        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
54442    }
54443}
54444#[doc = "Vector reinterpret cast operation"]
54445#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"]
54446#[inline]
54447#[cfg(target_endian = "little")]
54448#[target_feature(enable = "neon")]
54449#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54450#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54451#[cfg_attr(
54452    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54453    assert_instr(nop)
54454)]
54455#[cfg_attr(
54456    not(target_arch = "arm"),
54457    stable(feature = "neon_intrinsics", since = "1.59.0")
54458)]
54459#[cfg_attr(
54460    target_arch = "arm",
54461    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54462)]
54463pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
54464    unsafe { transmute(a) }
54465}
54466#[doc = "Vector reinterpret cast operation"]
54467#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"]
54468#[inline]
54469#[cfg(target_endian = "big")]
54470#[target_feature(enable = "neon")]
54471#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54472#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54473#[cfg_attr(
54474    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54475    assert_instr(nop)
54476)]
54477#[cfg_attr(
54478    not(target_arch = "arm"),
54479    stable(feature = "neon_intrinsics", since = "1.59.0")
54480)]
54481#[cfg_attr(
54482    target_arch = "arm",
54483    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54484)]
54485pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
54486    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54487    unsafe {
54488        let ret_val: float32x4_t = transmute(a);
54489        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
54490    }
54491}
54492#[doc = "Vector reinterpret cast operation"]
54493#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"]
54494#[inline]
54495#[cfg(target_endian = "little")]
54496#[target_feature(enable = "neon")]
54497#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54498#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54499#[cfg_attr(
54500    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54501    assert_instr(nop)
54502)]
54503#[cfg_attr(
54504    not(target_arch = "arm"),
54505    stable(feature = "neon_intrinsics", since = "1.59.0")
54506)]
54507#[cfg_attr(
54508    target_arch = "arm",
54509    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54510)]
54511pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
54512    unsafe { transmute(a) }
54513}
54514#[doc = "Vector reinterpret cast operation"]
54515#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"]
54516#[inline]
54517#[cfg(target_endian = "big")]
54518#[target_feature(enable = "neon")]
54519#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54520#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54521#[cfg_attr(
54522    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54523    assert_instr(nop)
54524)]
54525#[cfg_attr(
54526    not(target_arch = "arm"),
54527    stable(feature = "neon_intrinsics", since = "1.59.0")
54528)]
54529#[cfg_attr(
54530    target_arch = "arm",
54531    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54532)]
54533pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
54534    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54535    unsafe {
54536        let ret_val: int8x16_t = transmute(a);
54537        simd_shuffle!(
54538            ret_val,
54539            ret_val,
54540            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
54541        )
54542    }
54543}
54544#[doc = "Vector reinterpret cast operation"]
54545#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"]
54546#[inline]
54547#[cfg(target_endian = "little")]
54548#[target_feature(enable = "neon")]
54549#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54550#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54551#[cfg_attr(
54552    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54553    assert_instr(nop)
54554)]
54555#[cfg_attr(
54556    not(target_arch = "arm"),
54557    stable(feature = "neon_intrinsics", since = "1.59.0")
54558)]
54559#[cfg_attr(
54560    target_arch = "arm",
54561    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54562)]
54563pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
54564    unsafe { transmute(a) }
54565}
54566#[doc = "Vector reinterpret cast operation"]
54567#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"]
54568#[inline]
54569#[cfg(target_endian = "big")]
54570#[target_feature(enable = "neon")]
54571#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54572#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54573#[cfg_attr(
54574    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54575    assert_instr(nop)
54576)]
54577#[cfg_attr(
54578    not(target_arch = "arm"),
54579    stable(feature = "neon_intrinsics", since = "1.59.0")
54580)]
54581#[cfg_attr(
54582    target_arch = "arm",
54583    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54584)]
54585pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
54586    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54587    unsafe {
54588        let ret_val: int16x8_t = transmute(a);
54589        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
54590    }
54591}
54592#[doc = "Vector reinterpret cast operation"]
54593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"]
54594#[inline]
54595#[cfg(target_endian = "little")]
54596#[target_feature(enable = "neon")]
54597#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54598#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54599#[cfg_attr(
54600    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54601    assert_instr(nop)
54602)]
54603#[cfg_attr(
54604    not(target_arch = "arm"),
54605    stable(feature = "neon_intrinsics", since = "1.59.0")
54606)]
54607#[cfg_attr(
54608    target_arch = "arm",
54609    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54610)]
54611pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
54612    unsafe { transmute(a) }
54613}
54614#[doc = "Vector reinterpret cast operation"]
54615#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"]
54616#[inline]
54617#[cfg(target_endian = "big")]
54618#[target_feature(enable = "neon")]
54619#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54620#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54621#[cfg_attr(
54622    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54623    assert_instr(nop)
54624)]
54625#[cfg_attr(
54626    not(target_arch = "arm"),
54627    stable(feature = "neon_intrinsics", since = "1.59.0")
54628)]
54629#[cfg_attr(
54630    target_arch = "arm",
54631    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54632)]
54633pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
54634    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54635    unsafe {
54636        let ret_val: int32x4_t = transmute(a);
54637        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
54638    }
54639}
54640#[doc = "Vector reinterpret cast operation"]
54641#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"]
54642#[inline]
54643#[cfg(target_endian = "little")]
54644#[target_feature(enable = "neon")]
54645#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54646#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54647#[cfg_attr(
54648    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54649    assert_instr(nop)
54650)]
54651#[cfg_attr(
54652    not(target_arch = "arm"),
54653    stable(feature = "neon_intrinsics", since = "1.59.0")
54654)]
54655#[cfg_attr(
54656    target_arch = "arm",
54657    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54658)]
54659pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
54660    unsafe { transmute(a) }
54661}
54662#[doc = "Vector reinterpret cast operation"]
54663#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"]
54664#[inline]
54665#[cfg(target_endian = "big")]
54666#[target_feature(enable = "neon")]
54667#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54668#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54669#[cfg_attr(
54670    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54671    assert_instr(nop)
54672)]
54673#[cfg_attr(
54674    not(target_arch = "arm"),
54675    stable(feature = "neon_intrinsics", since = "1.59.0")
54676)]
54677#[cfg_attr(
54678    target_arch = "arm",
54679    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54680)]
54681pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
54682    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54683    unsafe {
54684        let ret_val: int64x2_t = transmute(a);
54685        simd_shuffle!(ret_val, ret_val, [1, 0])
54686    }
54687}
54688#[doc = "Vector reinterpret cast operation"]
54689#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"]
54690#[inline]
54691#[cfg(target_endian = "little")]
54692#[target_feature(enable = "neon")]
54693#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54694#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54695#[cfg_attr(
54696    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54697    assert_instr(nop)
54698)]
54699#[cfg_attr(
54700    not(target_arch = "arm"),
54701    stable(feature = "neon_intrinsics", since = "1.59.0")
54702)]
54703#[cfg_attr(
54704    target_arch = "arm",
54705    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54706)]
54707pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
54708    unsafe { transmute(a) }
54709}
54710#[doc = "Vector reinterpret cast operation"]
54711#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"]
54712#[inline]
54713#[cfg(target_endian = "big")]
54714#[target_feature(enable = "neon")]
54715#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54716#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54717#[cfg_attr(
54718    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54719    assert_instr(nop)
54720)]
54721#[cfg_attr(
54722    not(target_arch = "arm"),
54723    stable(feature = "neon_intrinsics", since = "1.59.0")
54724)]
54725#[cfg_attr(
54726    target_arch = "arm",
54727    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54728)]
54729pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
54730    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54731    unsafe {
54732        let ret_val: uint8x16_t = transmute(a);
54733        simd_shuffle!(
54734            ret_val,
54735            ret_val,
54736            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
54737        )
54738    }
54739}
54740#[doc = "Vector reinterpret cast operation"]
54741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"]
54742#[inline]
54743#[cfg(target_endian = "little")]
54744#[target_feature(enable = "neon")]
54745#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54746#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54747#[cfg_attr(
54748    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54749    assert_instr(nop)
54750)]
54751#[cfg_attr(
54752    not(target_arch = "arm"),
54753    stable(feature = "neon_intrinsics", since = "1.59.0")
54754)]
54755#[cfg_attr(
54756    target_arch = "arm",
54757    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54758)]
54759pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
54760    unsafe { transmute(a) }
54761}
54762#[doc = "Vector reinterpret cast operation"]
54763#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"]
54764#[inline]
54765#[cfg(target_endian = "big")]
54766#[target_feature(enable = "neon")]
54767#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54768#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54769#[cfg_attr(
54770    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54771    assert_instr(nop)
54772)]
54773#[cfg_attr(
54774    not(target_arch = "arm"),
54775    stable(feature = "neon_intrinsics", since = "1.59.0")
54776)]
54777#[cfg_attr(
54778    target_arch = "arm",
54779    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54780)]
54781pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
54782    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54783    unsafe {
54784        let ret_val: uint16x8_t = transmute(a);
54785        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
54786    }
54787}
54788#[doc = "Vector reinterpret cast operation"]
54789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"]
54790#[inline]
54791#[cfg(target_endian = "little")]
54792#[target_feature(enable = "neon")]
54793#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54794#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54795#[cfg_attr(
54796    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54797    assert_instr(nop)
54798)]
54799#[cfg_attr(
54800    not(target_arch = "arm"),
54801    stable(feature = "neon_intrinsics", since = "1.59.0")
54802)]
54803#[cfg_attr(
54804    target_arch = "arm",
54805    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54806)]
54807pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
54808    unsafe { transmute(a) }
54809}
54810#[doc = "Vector reinterpret cast operation"]
54811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"]
54812#[inline]
54813#[cfg(target_endian = "big")]
54814#[target_feature(enable = "neon")]
54815#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54816#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54817#[cfg_attr(
54818    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54819    assert_instr(nop)
54820)]
54821#[cfg_attr(
54822    not(target_arch = "arm"),
54823    stable(feature = "neon_intrinsics", since = "1.59.0")
54824)]
54825#[cfg_attr(
54826    target_arch = "arm",
54827    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54828)]
54829pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
54830    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54831    unsafe {
54832        let ret_val: uint32x4_t = transmute(a);
54833        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
54834    }
54835}
54836#[doc = "Vector reinterpret cast operation"]
54837#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"]
54838#[inline]
54839#[cfg(target_endian = "little")]
54840#[target_feature(enable = "neon")]
54841#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54842#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54843#[cfg_attr(
54844    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54845    assert_instr(nop)
54846)]
54847#[cfg_attr(
54848    not(target_arch = "arm"),
54849    stable(feature = "neon_intrinsics", since = "1.59.0")
54850)]
54851#[cfg_attr(
54852    target_arch = "arm",
54853    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54854)]
54855pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
54856    unsafe { transmute(a) }
54857}
54858#[doc = "Vector reinterpret cast operation"]
54859#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"]
54860#[inline]
54861#[cfg(target_endian = "big")]
54862#[target_feature(enable = "neon")]
54863#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54864#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54865#[cfg_attr(
54866    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54867    assert_instr(nop)
54868)]
54869#[cfg_attr(
54870    not(target_arch = "arm"),
54871    stable(feature = "neon_intrinsics", since = "1.59.0")
54872)]
54873#[cfg_attr(
54874    target_arch = "arm",
54875    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54876)]
54877pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
54878    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54879    unsafe {
54880        let ret_val: uint64x2_t = transmute(a);
54881        simd_shuffle!(ret_val, ret_val, [1, 0])
54882    }
54883}
54884#[doc = "Vector reinterpret cast operation"]
54885#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"]
54886#[inline]
54887#[cfg(target_endian = "little")]
54888#[target_feature(enable = "neon")]
54889#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54890#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54891#[cfg_attr(
54892    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54893    assert_instr(nop)
54894)]
54895#[cfg_attr(
54896    not(target_arch = "arm"),
54897    stable(feature = "neon_intrinsics", since = "1.59.0")
54898)]
54899#[cfg_attr(
54900    target_arch = "arm",
54901    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54902)]
54903pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
54904    unsafe { transmute(a) }
54905}
54906#[doc = "Vector reinterpret cast operation"]
54907#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"]
54908#[inline]
54909#[cfg(target_endian = "big")]
54910#[target_feature(enable = "neon")]
54911#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54912#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54913#[cfg_attr(
54914    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54915    assert_instr(nop)
54916)]
54917#[cfg_attr(
54918    not(target_arch = "arm"),
54919    stable(feature = "neon_intrinsics", since = "1.59.0")
54920)]
54921#[cfg_attr(
54922    target_arch = "arm",
54923    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54924)]
54925pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
54926    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54927    unsafe {
54928        let ret_val: poly8x16_t = transmute(a);
54929        simd_shuffle!(
54930            ret_val,
54931            ret_val,
54932            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
54933        )
54934    }
54935}
54936#[doc = "Vector reinterpret cast operation"]
54937#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"]
54938#[inline]
54939#[cfg(target_endian = "little")]
54940#[target_feature(enable = "neon,aes")]
54941#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54942#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54943#[cfg_attr(
54944    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54945    assert_instr(nop)
54946)]
54947#[cfg_attr(
54948    not(target_arch = "arm"),
54949    stable(feature = "neon_intrinsics", since = "1.59.0")
54950)]
54951#[cfg_attr(
54952    target_arch = "arm",
54953    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54954)]
54955pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t {
54956    unsafe { transmute(a) }
54957}
54958#[doc = "Vector reinterpret cast operation"]
54959#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"]
54960#[inline]
54961#[cfg(target_endian = "big")]
54962#[target_feature(enable = "neon,aes")]
54963#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54964#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54965#[cfg_attr(
54966    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54967    assert_instr(nop)
54968)]
54969#[cfg_attr(
54970    not(target_arch = "arm"),
54971    stable(feature = "neon_intrinsics", since = "1.59.0")
54972)]
54973#[cfg_attr(
54974    target_arch = "arm",
54975    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54976)]
54977pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t {
54978    unsafe {
54979        let ret_val: int8x16_t = transmute(a);
54980        simd_shuffle!(
54981            ret_val,
54982            ret_val,
54983            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
54984        )
54985    }
54986}
54987#[doc = "Vector reinterpret cast operation"]
54988#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"]
54989#[inline]
54990#[cfg(target_endian = "little")]
54991#[target_feature(enable = "neon,aes")]
54992#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54993#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54994#[cfg_attr(
54995    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54996    assert_instr(nop)
54997)]
54998#[cfg_attr(
54999    not(target_arch = "arm"),
55000    stable(feature = "neon_intrinsics", since = "1.59.0")
55001)]
55002#[cfg_attr(
55003    target_arch = "arm",
55004    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55005)]
55006pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t {
55007    unsafe { transmute(a) }
55008}
55009#[doc = "Vector reinterpret cast operation"]
55010#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"]
55011#[inline]
55012#[cfg(target_endian = "big")]
55013#[target_feature(enable = "neon,aes")]
55014#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55015#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55016#[cfg_attr(
55017    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55018    assert_instr(nop)
55019)]
55020#[cfg_attr(
55021    not(target_arch = "arm"),
55022    stable(feature = "neon_intrinsics", since = "1.59.0")
55023)]
55024#[cfg_attr(
55025    target_arch = "arm",
55026    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55027)]
55028pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t {
55029    unsafe {
55030        let ret_val: int16x8_t = transmute(a);
55031        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
55032    }
55033}
55034#[doc = "Vector reinterpret cast operation"]
55035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"]
55036#[inline]
55037#[cfg(target_endian = "little")]
55038#[target_feature(enable = "neon,aes")]
55039#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55040#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55041#[cfg_attr(
55042    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55043    assert_instr(nop)
55044)]
55045#[cfg_attr(
55046    not(target_arch = "arm"),
55047    stable(feature = "neon_intrinsics", since = "1.59.0")
55048)]
55049#[cfg_attr(
55050    target_arch = "arm",
55051    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55052)]
55053pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t {
55054    unsafe { transmute(a) }
55055}
55056#[doc = "Vector reinterpret cast operation"]
55057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"]
55058#[inline]
55059#[cfg(target_endian = "big")]
55060#[target_feature(enable = "neon,aes")]
55061#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55062#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55063#[cfg_attr(
55064    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55065    assert_instr(nop)
55066)]
55067#[cfg_attr(
55068    not(target_arch = "arm"),
55069    stable(feature = "neon_intrinsics", since = "1.59.0")
55070)]
55071#[cfg_attr(
55072    target_arch = "arm",
55073    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55074)]
55075pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t {
55076    unsafe {
55077        let ret_val: int32x4_t = transmute(a);
55078        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
55079    }
55080}
55081#[doc = "Vector reinterpret cast operation"]
55082#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"]
55083#[inline]
55084#[cfg(target_endian = "little")]
55085#[target_feature(enable = "neon,aes")]
55086#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55087#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55088#[cfg_attr(
55089    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55090    assert_instr(nop)
55091)]
55092#[cfg_attr(
55093    not(target_arch = "arm"),
55094    stable(feature = "neon_intrinsics", since = "1.59.0")
55095)]
55096#[cfg_attr(
55097    target_arch = "arm",
55098    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55099)]
55100pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t {
55101    unsafe { transmute(a) }
55102}
55103#[doc = "Vector reinterpret cast operation"]
55104#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"]
55105#[inline]
55106#[cfg(target_endian = "big")]
55107#[target_feature(enable = "neon,aes")]
55108#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55109#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55110#[cfg_attr(
55111    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55112    assert_instr(nop)
55113)]
55114#[cfg_attr(
55115    not(target_arch = "arm"),
55116    stable(feature = "neon_intrinsics", since = "1.59.0")
55117)]
55118#[cfg_attr(
55119    target_arch = "arm",
55120    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55121)]
55122pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t {
55123    unsafe {
55124        let ret_val: int64x2_t = transmute(a);
55125        simd_shuffle!(ret_val, ret_val, [1, 0])
55126    }
55127}
55128#[doc = "Vector reinterpret cast operation"]
55129#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"]
55130#[inline]
55131#[cfg(target_endian = "little")]
55132#[target_feature(enable = "neon,aes")]
55133#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55134#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55135#[cfg_attr(
55136    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55137    assert_instr(nop)
55138)]
55139#[cfg_attr(
55140    not(target_arch = "arm"),
55141    stable(feature = "neon_intrinsics", since = "1.59.0")
55142)]
55143#[cfg_attr(
55144    target_arch = "arm",
55145    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55146)]
55147pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t {
55148    unsafe { transmute(a) }
55149}
55150#[doc = "Vector reinterpret cast operation"]
55151#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"]
55152#[inline]
55153#[cfg(target_endian = "big")]
55154#[target_feature(enable = "neon,aes")]
55155#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55156#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55157#[cfg_attr(
55158    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55159    assert_instr(nop)
55160)]
55161#[cfg_attr(
55162    not(target_arch = "arm"),
55163    stable(feature = "neon_intrinsics", since = "1.59.0")
55164)]
55165#[cfg_attr(
55166    target_arch = "arm",
55167    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55168)]
55169pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t {
55170    unsafe {
55171        let ret_val: uint8x16_t = transmute(a);
55172        simd_shuffle!(
55173            ret_val,
55174            ret_val,
55175            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
55176        )
55177    }
55178}
55179#[doc = "Vector reinterpret cast operation"]
55180#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"]
55181#[inline]
55182#[cfg(target_endian = "little")]
55183#[target_feature(enable = "neon,aes")]
55184#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55185#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55186#[cfg_attr(
55187    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55188    assert_instr(nop)
55189)]
55190#[cfg_attr(
55191    not(target_arch = "arm"),
55192    stable(feature = "neon_intrinsics", since = "1.59.0")
55193)]
55194#[cfg_attr(
55195    target_arch = "arm",
55196    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55197)]
55198pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t {
55199    unsafe { transmute(a) }
55200}
55201#[doc = "Vector reinterpret cast operation"]
55202#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"]
55203#[inline]
55204#[cfg(target_endian = "big")]
55205#[target_feature(enable = "neon,aes")]
55206#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55207#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55208#[cfg_attr(
55209    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55210    assert_instr(nop)
55211)]
55212#[cfg_attr(
55213    not(target_arch = "arm"),
55214    stable(feature = "neon_intrinsics", since = "1.59.0")
55215)]
55216#[cfg_attr(
55217    target_arch = "arm",
55218    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55219)]
55220pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t {
55221    unsafe {
55222        let ret_val: uint16x8_t = transmute(a);
55223        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
55224    }
55225}
55226#[doc = "Vector reinterpret cast operation"]
55227#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"]
55228#[inline]
55229#[cfg(target_endian = "little")]
55230#[target_feature(enable = "neon,aes")]
55231#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55232#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55233#[cfg_attr(
55234    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55235    assert_instr(nop)
55236)]
55237#[cfg_attr(
55238    not(target_arch = "arm"),
55239    stable(feature = "neon_intrinsics", since = "1.59.0")
55240)]
55241#[cfg_attr(
55242    target_arch = "arm",
55243    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55244)]
55245pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t {
55246    unsafe { transmute(a) }
55247}
55248#[doc = "Vector reinterpret cast operation"]
55249#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"]
55250#[inline]
55251#[cfg(target_endian = "big")]
55252#[target_feature(enable = "neon,aes")]
55253#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55254#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55255#[cfg_attr(
55256    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55257    assert_instr(nop)
55258)]
55259#[cfg_attr(
55260    not(target_arch = "arm"),
55261    stable(feature = "neon_intrinsics", since = "1.59.0")
55262)]
55263#[cfg_attr(
55264    target_arch = "arm",
55265    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55266)]
55267pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t {
55268    unsafe {
55269        let ret_val: uint32x4_t = transmute(a);
55270        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
55271    }
55272}
55273#[doc = "Vector reinterpret cast operation"]
55274#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"]
55275#[inline]
55276#[cfg(target_endian = "little")]
55277#[target_feature(enable = "neon,aes")]
55278#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55279#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55280#[cfg_attr(
55281    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55282    assert_instr(nop)
55283)]
55284#[cfg_attr(
55285    not(target_arch = "arm"),
55286    stable(feature = "neon_intrinsics", since = "1.59.0")
55287)]
55288#[cfg_attr(
55289    target_arch = "arm",
55290    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55291)]
55292pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t {
55293    unsafe { transmute(a) }
55294}
55295#[doc = "Vector reinterpret cast operation"]
55296#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"]
55297#[inline]
55298#[cfg(target_endian = "big")]
55299#[target_feature(enable = "neon,aes")]
55300#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55301#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55302#[cfg_attr(
55303    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55304    assert_instr(nop)
55305)]
55306#[cfg_attr(
55307    not(target_arch = "arm"),
55308    stable(feature = "neon_intrinsics", since = "1.59.0")
55309)]
55310#[cfg_attr(
55311    target_arch = "arm",
55312    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55313)]
55314pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t {
55315    unsafe {
55316        let ret_val: uint64x2_t = transmute(a);
55317        simd_shuffle!(ret_val, ret_val, [1, 0])
55318    }
55319}
55320#[doc = "Vector reinterpret cast operation"]
55321#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"]
55322#[inline]
55323#[cfg(target_endian = "little")]
55324#[target_feature(enable = "neon,aes")]
55325#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55326#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55327#[cfg_attr(
55328    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55329    assert_instr(nop)
55330)]
55331#[cfg_attr(
55332    not(target_arch = "arm"),
55333    stable(feature = "neon_intrinsics", since = "1.59.0")
55334)]
55335#[cfg_attr(
55336    target_arch = "arm",
55337    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55338)]
55339pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t {
55340    unsafe { transmute(a) }
55341}
55342#[doc = "Vector reinterpret cast operation"]
55343#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"]
55344#[inline]
55345#[cfg(target_endian = "big")]
55346#[target_feature(enable = "neon,aes")]
55347#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55348#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55349#[cfg_attr(
55350    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55351    assert_instr(nop)
55352)]
55353#[cfg_attr(
55354    not(target_arch = "arm"),
55355    stable(feature = "neon_intrinsics", since = "1.59.0")
55356)]
55357#[cfg_attr(
55358    target_arch = "arm",
55359    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55360)]
55361pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t {
55362    unsafe {
55363        let ret_val: poly8x16_t = transmute(a);
55364        simd_shuffle!(
55365            ret_val,
55366            ret_val,
55367            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
55368        )
55369    }
55370}
55371#[doc = "Vector reinterpret cast operation"]
55372#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"]
55373#[inline]
55374#[cfg(target_endian = "little")]
55375#[target_feature(enable = "neon,aes")]
55376#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55377#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55378#[cfg_attr(
55379    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55380    assert_instr(nop)
55381)]
55382#[cfg_attr(
55383    not(target_arch = "arm"),
55384    stable(feature = "neon_intrinsics", since = "1.59.0")
55385)]
55386#[cfg_attr(
55387    target_arch = "arm",
55388    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55389)]
55390pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t {
55391    unsafe { transmute(a) }
55392}
55393#[doc = "Vector reinterpret cast operation"]
55394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"]
55395#[inline]
55396#[cfg(target_endian = "big")]
55397#[target_feature(enable = "neon,aes")]
55398#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55399#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55400#[cfg_attr(
55401    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55402    assert_instr(nop)
55403)]
55404#[cfg_attr(
55405    not(target_arch = "arm"),
55406    stable(feature = "neon_intrinsics", since = "1.59.0")
55407)]
55408#[cfg_attr(
55409    target_arch = "arm",
55410    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55411)]
55412pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t {
55413    unsafe {
55414        let ret_val: poly16x8_t = transmute(a);
55415        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
55416    }
55417}
55418#[doc = "Vector reinterpret cast operation"]
55419#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"]
55420#[inline]
55421#[cfg(target_endian = "little")]
55422#[target_feature(enable = "neon,aes")]
55423#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55424#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55425#[cfg_attr(
55426    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55427    assert_instr(nop)
55428)]
55429#[cfg_attr(
55430    not(target_arch = "arm"),
55431    stable(feature = "neon_intrinsics", since = "1.59.0")
55432)]
55433#[cfg_attr(
55434    target_arch = "arm",
55435    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55436)]
55437pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t {
55438    unsafe { transmute(a) }
55439}
55440#[doc = "Vector reinterpret cast operation"]
55441#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"]
55442#[inline]
55443#[cfg(target_endian = "big")]
55444#[target_feature(enable = "neon,aes")]
55445#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55446#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55447#[cfg_attr(
55448    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55449    assert_instr(nop)
55450)]
55451#[cfg_attr(
55452    not(target_arch = "arm"),
55453    stable(feature = "neon_intrinsics", since = "1.59.0")
55454)]
55455#[cfg_attr(
55456    target_arch = "arm",
55457    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55458)]
55459pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t {
55460    unsafe {
55461        let ret_val: poly64x2_t = transmute(a);
55462        simd_shuffle!(ret_val, ret_val, [1, 0])
55463    }
55464}
55465#[doc = "Vector reinterpret cast operation"]
55466#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"]
55467#[inline]
55468#[cfg(target_endian = "little")]
55469#[target_feature(enable = "neon,aes")]
55470#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55471#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55472#[cfg_attr(
55473    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55474    assert_instr(nop)
55475)]
55476#[cfg_attr(
55477    not(target_arch = "arm"),
55478    stable(feature = "neon_intrinsics", since = "1.59.0")
55479)]
55480#[cfg_attr(
55481    target_arch = "arm",
55482    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55483)]
55484pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
55485    unsafe { transmute(a) }
55486}
55487#[doc = "Vector reinterpret cast operation"]
55488#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"]
55489#[inline]
55490#[cfg(target_endian = "big")]
55491#[target_feature(enable = "neon,aes")]
55492#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55493#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55494#[cfg_attr(
55495    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55496    assert_instr(nop)
55497)]
55498#[cfg_attr(
55499    not(target_arch = "arm"),
55500    stable(feature = "neon_intrinsics", since = "1.59.0")
55501)]
55502#[cfg_attr(
55503    target_arch = "arm",
55504    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55505)]
55506pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
55507    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
55508    unsafe { transmute(a) }
55509}
55510#[doc = "Vector reinterpret cast operation"]
55511#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"]
55512#[inline]
55513#[cfg(target_endian = "little")]
55514#[target_feature(enable = "neon,aes")]
55515#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55516#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55517#[cfg_attr(
55518    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55519    assert_instr(nop)
55520)]
55521#[cfg_attr(
55522    not(target_arch = "arm"),
55523    stable(feature = "neon_intrinsics", since = "1.59.0")
55524)]
55525#[cfg_attr(
55526    target_arch = "arm",
55527    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55528)]
55529pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
55530    unsafe { transmute(a) }
55531}
55532#[doc = "Vector reinterpret cast operation"]
55533#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"]
55534#[inline]
55535#[cfg(target_endian = "big")]
55536#[target_feature(enable = "neon,aes")]
55537#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55538#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55539#[cfg_attr(
55540    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55541    assert_instr(nop)
55542)]
55543#[cfg_attr(
55544    not(target_arch = "arm"),
55545    stable(feature = "neon_intrinsics", since = "1.59.0")
55546)]
55547#[cfg_attr(
55548    target_arch = "arm",
55549    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55550)]
55551pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
55552    let a: int8x16_t =
55553        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
55554    unsafe { transmute(a) }
55555}
55556#[doc = "Vector reinterpret cast operation"]
55557#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"]
55558#[inline]
55559#[cfg(target_endian = "little")]
55560#[target_feature(enable = "neon,aes")]
55561#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55562#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55563#[cfg_attr(
55564    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55565    assert_instr(nop)
55566)]
55567#[cfg_attr(
55568    not(target_arch = "arm"),
55569    stable(feature = "neon_intrinsics", since = "1.59.0")
55570)]
55571#[cfg_attr(
55572    target_arch = "arm",
55573    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55574)]
55575pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
55576    unsafe { transmute(a) }
55577}
55578#[doc = "Vector reinterpret cast operation"]
55579#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"]
55580#[inline]
55581#[cfg(target_endian = "big")]
55582#[target_feature(enable = "neon,aes")]
55583#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55584#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55585#[cfg_attr(
55586    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55587    assert_instr(nop)
55588)]
55589#[cfg_attr(
55590    not(target_arch = "arm"),
55591    stable(feature = "neon_intrinsics", since = "1.59.0")
55592)]
55593#[cfg_attr(
55594    target_arch = "arm",
55595    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55596)]
55597pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
55598    let a: int8x16_t =
55599        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
55600    unsafe {
55601        let ret_val: poly64x2_t = transmute(a);
55602        simd_shuffle!(ret_val, ret_val, [1, 0])
55603    }
55604}
55605#[doc = "Vector reinterpret cast operation"]
55606#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"]
55607#[inline]
55608#[cfg(target_endian = "little")]
55609#[target_feature(enable = "neon,aes")]
55610#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55611#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55612#[cfg_attr(
55613    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55614    assert_instr(nop)
55615)]
55616#[cfg_attr(
55617    not(target_arch = "arm"),
55618    stable(feature = "neon_intrinsics", since = "1.59.0")
55619)]
55620#[cfg_attr(
55621    target_arch = "arm",
55622    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55623)]
55624pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
55625    unsafe { transmute(a) }
55626}
55627#[doc = "Vector reinterpret cast operation"]
55628#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"]
55629#[inline]
55630#[cfg(target_endian = "big")]
55631#[target_feature(enable = "neon,aes")]
55632#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55633#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55634#[cfg_attr(
55635    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55636    assert_instr(nop)
55637)]
55638#[cfg_attr(
55639    not(target_arch = "arm"),
55640    stable(feature = "neon_intrinsics", since = "1.59.0")
55641)]
55642#[cfg_attr(
55643    target_arch = "arm",
55644    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55645)]
55646pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
55647    let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
55648    unsafe { transmute(a) }
55649}
55650#[doc = "Vector reinterpret cast operation"]
55651#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"]
55652#[inline]
55653#[cfg(target_endian = "little")]
55654#[target_feature(enable = "neon,aes")]
55655#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55656#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55657#[cfg_attr(
55658    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55659    assert_instr(nop)
55660)]
55661#[cfg_attr(
55662    not(target_arch = "arm"),
55663    stable(feature = "neon_intrinsics", since = "1.59.0")
55664)]
55665#[cfg_attr(
55666    target_arch = "arm",
55667    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55668)]
55669pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
55670    unsafe { transmute(a) }
55671}
55672#[doc = "Vector reinterpret cast operation"]
55673#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"]
55674#[inline]
55675#[cfg(target_endian = "big")]
55676#[target_feature(enable = "neon,aes")]
55677#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55678#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55679#[cfg_attr(
55680    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55681    assert_instr(nop)
55682)]
55683#[cfg_attr(
55684    not(target_arch = "arm"),
55685    stable(feature = "neon_intrinsics", since = "1.59.0")
55686)]
55687#[cfg_attr(
55688    target_arch = "arm",
55689    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55690)]
55691pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
55692    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
55693    unsafe { transmute(a) }
55694}
55695#[doc = "Vector reinterpret cast operation"]
55696#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"]
55697#[inline]
55698#[cfg(target_endian = "little")]
55699#[target_feature(enable = "neon,aes")]
55700#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55701#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55702#[cfg_attr(
55703    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55704    assert_instr(nop)
55705)]
55706#[cfg_attr(
55707    not(target_arch = "arm"),
55708    stable(feature = "neon_intrinsics", since = "1.59.0")
55709)]
55710#[cfg_attr(
55711    target_arch = "arm",
55712    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55713)]
55714pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
55715    unsafe { transmute(a) }
55716}
55717#[doc = "Vector reinterpret cast operation"]
55718#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"]
55719#[inline]
55720#[cfg(target_endian = "big")]
55721#[target_feature(enable = "neon,aes")]
55722#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55723#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55724#[cfg_attr(
55725    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55726    assert_instr(nop)
55727)]
55728#[cfg_attr(
55729    not(target_arch = "arm"),
55730    stable(feature = "neon_intrinsics", since = "1.59.0")
55731)]
55732#[cfg_attr(
55733    target_arch = "arm",
55734    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55735)]
55736pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
55737    let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
55738    unsafe {
55739        let ret_val: poly64x2_t = transmute(a);
55740        simd_shuffle!(ret_val, ret_val, [1, 0])
55741    }
55742}
55743#[doc = "Vector reinterpret cast operation"]
55744#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"]
55745#[inline]
55746#[cfg(target_endian = "little")]
55747#[target_feature(enable = "neon,aes")]
55748#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55749#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55750#[cfg_attr(
55751    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55752    assert_instr(nop)
55753)]
55754#[cfg_attr(
55755    not(target_arch = "arm"),
55756    stable(feature = "neon_intrinsics", since = "1.59.0")
55757)]
55758#[cfg_attr(
55759    target_arch = "arm",
55760    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55761)]
55762pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
55763    unsafe { transmute(a) }
55764}
55765#[doc = "Vector reinterpret cast operation"]
55766#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"]
55767#[inline]
55768#[cfg(target_endian = "big")]
55769#[target_feature(enable = "neon,aes")]
55770#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55771#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55772#[cfg_attr(
55773    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55774    assert_instr(nop)
55775)]
55776#[cfg_attr(
55777    not(target_arch = "arm"),
55778    stable(feature = "neon_intrinsics", since = "1.59.0")
55779)]
55780#[cfg_attr(
55781    target_arch = "arm",
55782    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55783)]
55784pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
55785    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
55786    unsafe { transmute(a) }
55787}
55788#[doc = "Vector reinterpret cast operation"]
55789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"]
55790#[inline]
55791#[cfg(target_endian = "little")]
55792#[target_feature(enable = "neon,aes")]
55793#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55794#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55795#[cfg_attr(
55796    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55797    assert_instr(nop)
55798)]
55799#[cfg_attr(
55800    not(target_arch = "arm"),
55801    stable(feature = "neon_intrinsics", since = "1.59.0")
55802)]
55803#[cfg_attr(
55804    target_arch = "arm",
55805    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55806)]
55807pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
55808    unsafe { transmute(a) }
55809}
55810#[doc = "Vector reinterpret cast operation"]
55811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"]
55812#[inline]
55813#[cfg(target_endian = "big")]
55814#[target_feature(enable = "neon,aes")]
55815#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55816#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55817#[cfg_attr(
55818    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55819    assert_instr(nop)
55820)]
55821#[cfg_attr(
55822    not(target_arch = "arm"),
55823    stable(feature = "neon_intrinsics", since = "1.59.0")
55824)]
55825#[cfg_attr(
55826    target_arch = "arm",
55827    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55828)]
55829pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
55830    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
55831    unsafe { transmute(a) }
55832}
55833#[doc = "Vector reinterpret cast operation"]
55834#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"]
55835#[inline]
55836#[cfg(target_endian = "little")]
55837#[target_feature(enable = "neon,aes")]
55838#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55839#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55840#[cfg_attr(
55841    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55842    assert_instr(nop)
55843)]
55844#[cfg_attr(
55845    not(target_arch = "arm"),
55846    stable(feature = "neon_intrinsics", since = "1.59.0")
55847)]
55848#[cfg_attr(
55849    target_arch = "arm",
55850    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55851)]
55852pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
55853    unsafe { transmute(a) }
55854}
55855#[doc = "Vector reinterpret cast operation"]
55856#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"]
55857#[inline]
55858#[cfg(target_endian = "big")]
55859#[target_feature(enable = "neon,aes")]
55860#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55861#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55862#[cfg_attr(
55863    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55864    assert_instr(nop)
55865)]
55866#[cfg_attr(
55867    not(target_arch = "arm"),
55868    stable(feature = "neon_intrinsics", since = "1.59.0")
55869)]
55870#[cfg_attr(
55871    target_arch = "arm",
55872    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55873)]
55874pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
55875    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
55876    unsafe {
55877        let ret_val: poly64x2_t = transmute(a);
55878        simd_shuffle!(ret_val, ret_val, [1, 0])
55879    }
55880}
55881#[doc = "Vector reinterpret cast operation"]
55882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"]
55883#[inline]
55884#[cfg(target_endian = "little")]
55885#[target_feature(enable = "neon,aes")]
55886#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55887#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55888#[cfg_attr(
55889    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55890    assert_instr(nop)
55891)]
55892#[cfg_attr(
55893    not(target_arch = "arm"),
55894    stable(feature = "neon_intrinsics", since = "1.59.0")
55895)]
55896#[cfg_attr(
55897    target_arch = "arm",
55898    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55899)]
55900pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
55901    unsafe { transmute(a) }
55902}
55903#[doc = "Vector reinterpret cast operation"]
55904#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"]
55905#[inline]
55906#[cfg(target_endian = "big")]
55907#[target_feature(enable = "neon,aes")]
55908#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55909#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55910#[cfg_attr(
55911    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55912    assert_instr(nop)
55913)]
55914#[cfg_attr(
55915    not(target_arch = "arm"),
55916    stable(feature = "neon_intrinsics", since = "1.59.0")
55917)]
55918#[cfg_attr(
55919    target_arch = "arm",
55920    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55921)]
55922pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
55923    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
55924    unsafe { transmute(a) }
55925}
55926#[doc = "Vector reinterpret cast operation"]
55927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"]
55928#[inline]
55929#[cfg(target_endian = "little")]
55930#[target_feature(enable = "neon,aes")]
55931#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55932#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55933#[cfg_attr(
55934    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55935    assert_instr(nop)
55936)]
55937#[cfg_attr(
55938    not(target_arch = "arm"),
55939    stable(feature = "neon_intrinsics", since = "1.59.0")
55940)]
55941#[cfg_attr(
55942    target_arch = "arm",
55943    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55944)]
55945pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
55946    unsafe { transmute(a) }
55947}
55948#[doc = "Vector reinterpret cast operation"]
55949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"]
55950#[inline]
55951#[cfg(target_endian = "big")]
55952#[target_feature(enable = "neon,aes")]
55953#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55954#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55955#[cfg_attr(
55956    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55957    assert_instr(nop)
55958)]
55959#[cfg_attr(
55960    not(target_arch = "arm"),
55961    stable(feature = "neon_intrinsics", since = "1.59.0")
55962)]
55963#[cfg_attr(
55964    target_arch = "arm",
55965    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55966)]
55967pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
55968    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
55969    unsafe { transmute(a) }
55970}
55971#[doc = "Vector reinterpret cast operation"]
55972#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"]
55973#[inline]
55974#[cfg(target_endian = "little")]
55975#[target_feature(enable = "neon,aes")]
55976#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55977#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55978#[cfg_attr(
55979    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55980    assert_instr(nop)
55981)]
55982#[cfg_attr(
55983    not(target_arch = "arm"),
55984    stable(feature = "neon_intrinsics", since = "1.59.0")
55985)]
55986#[cfg_attr(
55987    target_arch = "arm",
55988    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55989)]
55990pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
55991    unsafe { transmute(a) }
55992}
55993#[doc = "Vector reinterpret cast operation"]
55994#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"]
55995#[inline]
55996#[cfg(target_endian = "big")]
55997#[target_feature(enable = "neon,aes")]
55998#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55999#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56000#[cfg_attr(
56001    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56002    assert_instr(nop)
56003)]
56004#[cfg_attr(
56005    not(target_arch = "arm"),
56006    stable(feature = "neon_intrinsics", since = "1.59.0")
56007)]
56008#[cfg_attr(
56009    target_arch = "arm",
56010    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56011)]
56012pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
56013    let a: uint8x16_t =
56014        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
56015    unsafe { transmute(a) }
56016}
56017#[doc = "Vector reinterpret cast operation"]
56018#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"]
56019#[inline]
56020#[cfg(target_endian = "little")]
56021#[target_feature(enable = "neon,aes")]
56022#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56023#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56024#[cfg_attr(
56025    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56026    assert_instr(nop)
56027)]
56028#[cfg_attr(
56029    not(target_arch = "arm"),
56030    stable(feature = "neon_intrinsics", since = "1.59.0")
56031)]
56032#[cfg_attr(
56033    target_arch = "arm",
56034    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56035)]
56036pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
56037    unsafe { transmute(a) }
56038}
56039#[doc = "Vector reinterpret cast operation"]
56040#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"]
56041#[inline]
56042#[cfg(target_endian = "big")]
56043#[target_feature(enable = "neon,aes")]
56044#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56045#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56046#[cfg_attr(
56047    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56048    assert_instr(nop)
56049)]
56050#[cfg_attr(
56051    not(target_arch = "arm"),
56052    stable(feature = "neon_intrinsics", since = "1.59.0")
56053)]
56054#[cfg_attr(
56055    target_arch = "arm",
56056    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56057)]
56058pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
56059    let a: uint8x16_t =
56060        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
56061    unsafe {
56062        let ret_val: poly64x2_t = transmute(a);
56063        simd_shuffle!(ret_val, ret_val, [1, 0])
56064    }
56065}
56066#[doc = "Vector reinterpret cast operation"]
56067#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"]
56068#[inline]
56069#[cfg(target_endian = "little")]
56070#[target_feature(enable = "neon,aes")]
56071#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56072#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56073#[cfg_attr(
56074    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56075    assert_instr(nop)
56076)]
56077#[cfg_attr(
56078    not(target_arch = "arm"),
56079    stable(feature = "neon_intrinsics", since = "1.59.0")
56080)]
56081#[cfg_attr(
56082    target_arch = "arm",
56083    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56084)]
56085pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
56086    unsafe { transmute(a) }
56087}
56088#[doc = "Vector reinterpret cast operation"]
56089#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"]
56090#[inline]
56091#[cfg(target_endian = "big")]
56092#[target_feature(enable = "neon,aes")]
56093#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56094#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56095#[cfg_attr(
56096    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56097    assert_instr(nop)
56098)]
56099#[cfg_attr(
56100    not(target_arch = "arm"),
56101    stable(feature = "neon_intrinsics", since = "1.59.0")
56102)]
56103#[cfg_attr(
56104    target_arch = "arm",
56105    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56106)]
56107pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
56108    let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
56109    unsafe { transmute(a) }
56110}
56111#[doc = "Vector reinterpret cast operation"]
56112#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"]
56113#[inline]
56114#[cfg(target_endian = "little")]
56115#[target_feature(enable = "neon,aes")]
56116#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56117#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56118#[cfg_attr(
56119    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56120    assert_instr(nop)
56121)]
56122#[cfg_attr(
56123    not(target_arch = "arm"),
56124    stable(feature = "neon_intrinsics", since = "1.59.0")
56125)]
56126#[cfg_attr(
56127    target_arch = "arm",
56128    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56129)]
56130pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
56131    unsafe { transmute(a) }
56132}
56133#[doc = "Vector reinterpret cast operation"]
56134#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"]
56135#[inline]
56136#[cfg(target_endian = "big")]
56137#[target_feature(enable = "neon,aes")]
56138#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56139#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56140#[cfg_attr(
56141    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56142    assert_instr(nop)
56143)]
56144#[cfg_attr(
56145    not(target_arch = "arm"),
56146    stable(feature = "neon_intrinsics", since = "1.59.0")
56147)]
56148#[cfg_attr(
56149    target_arch = "arm",
56150    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56151)]
56152pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
56153    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
56154    unsafe { transmute(a) }
56155}
56156#[doc = "Vector reinterpret cast operation"]
56157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"]
56158#[inline]
56159#[cfg(target_endian = "little")]
56160#[target_feature(enable = "neon,aes")]
56161#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56162#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56163#[cfg_attr(
56164    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56165    assert_instr(nop)
56166)]
56167#[cfg_attr(
56168    not(target_arch = "arm"),
56169    stable(feature = "neon_intrinsics", since = "1.59.0")
56170)]
56171#[cfg_attr(
56172    target_arch = "arm",
56173    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56174)]
56175pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
56176    unsafe { transmute(a) }
56177}
56178#[doc = "Vector reinterpret cast operation"]
56179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"]
56180#[inline]
56181#[cfg(target_endian = "big")]
56182#[target_feature(enable = "neon,aes")]
56183#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56184#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56185#[cfg_attr(
56186    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56187    assert_instr(nop)
56188)]
56189#[cfg_attr(
56190    not(target_arch = "arm"),
56191    stable(feature = "neon_intrinsics", since = "1.59.0")
56192)]
56193#[cfg_attr(
56194    target_arch = "arm",
56195    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56196)]
56197pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
56198    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
56199    unsafe {
56200        let ret_val: poly64x2_t = transmute(a);
56201        simd_shuffle!(ret_val, ret_val, [1, 0])
56202    }
56203}
56204#[doc = "Vector reinterpret cast operation"]
56205#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"]
56206#[inline]
56207#[cfg(target_endian = "little")]
56208#[target_feature(enable = "neon,aes")]
56209#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56210#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56211#[cfg_attr(
56212    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56213    assert_instr(nop)
56214)]
56215#[cfg_attr(
56216    not(target_arch = "arm"),
56217    stable(feature = "neon_intrinsics", since = "1.59.0")
56218)]
56219#[cfg_attr(
56220    target_arch = "arm",
56221    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56222)]
56223pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
56224    unsafe { transmute(a) }
56225}
56226#[doc = "Vector reinterpret cast operation"]
56227#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"]
56228#[inline]
56229#[cfg(target_endian = "big")]
56230#[target_feature(enable = "neon,aes")]
56231#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56232#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56233#[cfg_attr(
56234    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56235    assert_instr(nop)
56236)]
56237#[cfg_attr(
56238    not(target_arch = "arm"),
56239    stable(feature = "neon_intrinsics", since = "1.59.0")
56240)]
56241#[cfg_attr(
56242    target_arch = "arm",
56243    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56244)]
56245pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
56246    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
56247    unsafe { transmute(a) }
56248}
56249#[doc = "Vector reinterpret cast operation"]
56250#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"]
56251#[inline]
56252#[cfg(target_endian = "little")]
56253#[target_feature(enable = "neon,aes")]
56254#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56255#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56256#[cfg_attr(
56257    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56258    assert_instr(nop)
56259)]
56260#[cfg_attr(
56261    not(target_arch = "arm"),
56262    stable(feature = "neon_intrinsics", since = "1.59.0")
56263)]
56264#[cfg_attr(
56265    target_arch = "arm",
56266    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56267)]
56268pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
56269    unsafe { transmute(a) }
56270}
56271#[doc = "Vector reinterpret cast operation"]
56272#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"]
56273#[inline]
56274#[cfg(target_endian = "big")]
56275#[target_feature(enable = "neon,aes")]
56276#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56277#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56278#[cfg_attr(
56279    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56280    assert_instr(nop)
56281)]
56282#[cfg_attr(
56283    not(target_arch = "arm"),
56284    stable(feature = "neon_intrinsics", since = "1.59.0")
56285)]
56286#[cfg_attr(
56287    target_arch = "arm",
56288    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56289)]
56290pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
56291    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
56292    unsafe { transmute(a) }
56293}
56294#[doc = "Vector reinterpret cast operation"]
56295#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"]
56296#[inline]
56297#[cfg(target_endian = "little")]
56298#[target_feature(enable = "neon,aes")]
56299#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56300#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56301#[cfg_attr(
56302    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56303    assert_instr(nop)
56304)]
56305#[cfg_attr(
56306    not(target_arch = "arm"),
56307    stable(feature = "neon_intrinsics", since = "1.59.0")
56308)]
56309#[cfg_attr(
56310    target_arch = "arm",
56311    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56312)]
56313pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
56314    unsafe { transmute(a) }
56315}
56316#[doc = "Vector reinterpret cast operation"]
56317#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"]
56318#[inline]
56319#[cfg(target_endian = "big")]
56320#[target_feature(enable = "neon,aes")]
56321#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56322#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56323#[cfg_attr(
56324    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56325    assert_instr(nop)
56326)]
56327#[cfg_attr(
56328    not(target_arch = "arm"),
56329    stable(feature = "neon_intrinsics", since = "1.59.0")
56330)]
56331#[cfg_attr(
56332    target_arch = "arm",
56333    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56334)]
56335pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
56336    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
56337    unsafe {
56338        let ret_val: poly64x2_t = transmute(a);
56339        simd_shuffle!(ret_val, ret_val, [1, 0])
56340    }
56341}
56342#[doc = "Vector reinterpret cast operation"]
56343#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"]
56344#[inline]
56345#[cfg(target_endian = "little")]
56346#[target_feature(enable = "neon,aes")]
56347#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56348#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56349#[cfg_attr(
56350    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56351    assert_instr(nop)
56352)]
56353#[cfg_attr(
56354    not(target_arch = "arm"),
56355    stable(feature = "neon_intrinsics", since = "1.59.0")
56356)]
56357#[cfg_attr(
56358    target_arch = "arm",
56359    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56360)]
56361pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
56362    unsafe { transmute(a) }
56363}
56364#[doc = "Vector reinterpret cast operation"]
56365#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"]
56366#[inline]
56367#[cfg(target_endian = "big")]
56368#[target_feature(enable = "neon,aes")]
56369#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56370#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56371#[cfg_attr(
56372    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56373    assert_instr(nop)
56374)]
56375#[cfg_attr(
56376    not(target_arch = "arm"),
56377    stable(feature = "neon_intrinsics", since = "1.59.0")
56378)]
56379#[cfg_attr(
56380    target_arch = "arm",
56381    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56382)]
56383pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
56384    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
56385    unsafe { transmute(a) }
56386}
56387#[doc = "Vector reinterpret cast operation"]
56388#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"]
56389#[inline]
56390#[cfg(target_endian = "little")]
56391#[target_feature(enable = "neon,aes")]
56392#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56393#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56394#[cfg_attr(
56395    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56396    assert_instr(nop)
56397)]
56398#[cfg_attr(
56399    not(target_arch = "arm"),
56400    stable(feature = "neon_intrinsics", since = "1.59.0")
56401)]
56402#[cfg_attr(
56403    target_arch = "arm",
56404    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56405)]
56406pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
56407    unsafe { transmute(a) }
56408}
56409#[doc = "Vector reinterpret cast operation"]
56410#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"]
56411#[inline]
56412#[cfg(target_endian = "big")]
56413#[target_feature(enable = "neon,aes")]
56414#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56415#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56416#[cfg_attr(
56417    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56418    assert_instr(nop)
56419)]
56420#[cfg_attr(
56421    not(target_arch = "arm"),
56422    stable(feature = "neon_intrinsics", since = "1.59.0")
56423)]
56424#[cfg_attr(
56425    target_arch = "arm",
56426    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56427)]
56428pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
56429    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
56430    unsafe { transmute(a) }
56431}
56432#[doc = "Vector reinterpret cast operation"]
56433#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"]
56434#[inline]
56435#[cfg(target_endian = "little")]
56436#[target_feature(enable = "neon,aes")]
56437#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56438#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56439#[cfg_attr(
56440    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56441    assert_instr(nop)
56442)]
56443#[cfg_attr(
56444    not(target_arch = "arm"),
56445    stable(feature = "neon_intrinsics", since = "1.59.0")
56446)]
56447#[cfg_attr(
56448    target_arch = "arm",
56449    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56450)]
56451pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
56452    unsafe { transmute(a) }
56453}
56454#[doc = "Vector reinterpret cast operation"]
56455#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"]
56456#[inline]
56457#[cfg(target_endian = "big")]
56458#[target_feature(enable = "neon,aes")]
56459#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56460#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56461#[cfg_attr(
56462    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56463    assert_instr(nop)
56464)]
56465#[cfg_attr(
56466    not(target_arch = "arm"),
56467    stable(feature = "neon_intrinsics", since = "1.59.0")
56468)]
56469#[cfg_attr(
56470    target_arch = "arm",
56471    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56472)]
56473pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
56474    let a: poly8x16_t =
56475        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
56476    unsafe { transmute(a) }
56477}
56478#[doc = "Vector reinterpret cast operation"]
56479#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"]
56480#[inline]
56481#[cfg(target_endian = "little")]
56482#[target_feature(enable = "neon,aes")]
56483#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56484#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56485#[cfg_attr(
56486    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56487    assert_instr(nop)
56488)]
56489#[cfg_attr(
56490    not(target_arch = "arm"),
56491    stable(feature = "neon_intrinsics", since = "1.59.0")
56492)]
56493#[cfg_attr(
56494    target_arch = "arm",
56495    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56496)]
56497pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
56498    unsafe { transmute(a) }
56499}
56500#[doc = "Vector reinterpret cast operation"]
56501#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"]
56502#[inline]
56503#[cfg(target_endian = "big")]
56504#[target_feature(enable = "neon,aes")]
56505#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56506#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56507#[cfg_attr(
56508    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56509    assert_instr(nop)
56510)]
56511#[cfg_attr(
56512    not(target_arch = "arm"),
56513    stable(feature = "neon_intrinsics", since = "1.59.0")
56514)]
56515#[cfg_attr(
56516    target_arch = "arm",
56517    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56518)]
56519pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
56520    let a: poly8x16_t =
56521        unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
56522    unsafe {
56523        let ret_val: poly64x2_t = transmute(a);
56524        simd_shuffle!(ret_val, ret_val, [1, 0])
56525    }
56526}
56527#[doc = "Vector reinterpret cast operation"]
56528#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"]
56529#[inline]
56530#[cfg(target_endian = "little")]
56531#[target_feature(enable = "neon,aes")]
56532#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56533#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56534#[cfg_attr(
56535    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56536    assert_instr(nop)
56537)]
56538#[cfg_attr(
56539    not(target_arch = "arm"),
56540    stable(feature = "neon_intrinsics", since = "1.59.0")
56541)]
56542#[cfg_attr(
56543    target_arch = "arm",
56544    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56545)]
56546pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
56547    unsafe { transmute(a) }
56548}
56549#[doc = "Vector reinterpret cast operation"]
56550#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"]
56551#[inline]
56552#[cfg(target_endian = "big")]
56553#[target_feature(enable = "neon,aes")]
56554#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56555#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56556#[cfg_attr(
56557    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56558    assert_instr(nop)
56559)]
56560#[cfg_attr(
56561    not(target_arch = "arm"),
56562    stable(feature = "neon_intrinsics", since = "1.59.0")
56563)]
56564#[cfg_attr(
56565    target_arch = "arm",
56566    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56567)]
56568pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
56569    let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
56570    unsafe { transmute(a) }
56571}
56572#[doc = "Vector reinterpret cast operation"]
56573#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"]
56574#[inline]
56575#[cfg(target_endian = "little")]
56576#[target_feature(enable = "neon,aes")]
56577#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56578#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56579#[cfg_attr(
56580    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56581    assert_instr(nop)
56582)]
56583#[cfg_attr(
56584    not(target_arch = "arm"),
56585    stable(feature = "neon_intrinsics", since = "1.59.0")
56586)]
56587#[cfg_attr(
56588    target_arch = "arm",
56589    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56590)]
56591pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
56592    unsafe { transmute(a) }
56593}
56594#[doc = "Vector reinterpret cast operation"]
56595#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"]
56596#[inline]
56597#[cfg(target_endian = "big")]
56598#[target_feature(enable = "neon,aes")]
56599#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56600#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56601#[cfg_attr(
56602    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56603    assert_instr(nop)
56604)]
56605#[cfg_attr(
56606    not(target_arch = "arm"),
56607    stable(feature = "neon_intrinsics", since = "1.59.0")
56608)]
56609#[cfg_attr(
56610    target_arch = "arm",
56611    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56612)]
56613pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
56614    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
56615    unsafe { transmute(a) }
56616}
56617#[doc = "Vector reinterpret cast operation"]
56618#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"]
56619#[inline]
56620#[cfg(target_endian = "little")]
56621#[target_feature(enable = "neon,aes")]
56622#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56623#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56624#[cfg_attr(
56625    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56626    assert_instr(nop)
56627)]
56628#[cfg_attr(
56629    not(target_arch = "arm"),
56630    stable(feature = "neon_intrinsics", since = "1.59.0")
56631)]
56632#[cfg_attr(
56633    target_arch = "arm",
56634    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56635)]
56636pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
56637    unsafe { transmute(a) }
56638}
56639#[doc = "Vector reinterpret cast operation"]
56640#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"]
56641#[inline]
56642#[cfg(target_endian = "big")]
56643#[target_feature(enable = "neon,aes")]
56644#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56645#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56646#[cfg_attr(
56647    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56648    assert_instr(nop)
56649)]
56650#[cfg_attr(
56651    not(target_arch = "arm"),
56652    stable(feature = "neon_intrinsics", since = "1.59.0")
56653)]
56654#[cfg_attr(
56655    target_arch = "arm",
56656    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56657)]
56658pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
56659    let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
56660    unsafe {
56661        let ret_val: poly64x2_t = transmute(a);
56662        simd_shuffle!(ret_val, ret_val, [1, 0])
56663    }
56664}
56665#[doc = "Vector reinterpret cast operation"]
56666#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"]
56667#[inline]
56668#[cfg(target_endian = "little")]
56669#[target_feature(enable = "neon,aes")]
56670#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56671#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56672#[cfg_attr(
56673    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56674    assert_instr(nop)
56675)]
56676#[cfg_attr(
56677    not(target_arch = "arm"),
56678    stable(feature = "neon_intrinsics", since = "1.59.0")
56679)]
56680#[cfg_attr(
56681    target_arch = "arm",
56682    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56683)]
56684pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
56685    unsafe { transmute(a) }
56686}
56687#[doc = "Vector reinterpret cast operation"]
56688#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"]
56689#[inline]
56690#[cfg(target_endian = "big")]
56691#[target_feature(enable = "neon,aes")]
56692#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56693#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56694#[cfg_attr(
56695    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56696    assert_instr(nop)
56697)]
56698#[cfg_attr(
56699    not(target_arch = "arm"),
56700    stable(feature = "neon_intrinsics", since = "1.59.0")
56701)]
56702#[cfg_attr(
56703    target_arch = "arm",
56704    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56705)]
56706pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
56707    unsafe {
56708        let ret_val: int8x8_t = transmute(a);
56709        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
56710    }
56711}
56712#[doc = "Vector reinterpret cast operation"]
56713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"]
56714#[inline]
56715#[cfg(target_endian = "little")]
56716#[target_feature(enable = "neon,aes")]
56717#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56718#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56719#[cfg_attr(
56720    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56721    assert_instr(nop)
56722)]
56723#[cfg_attr(
56724    not(target_arch = "arm"),
56725    stable(feature = "neon_intrinsics", since = "1.59.0")
56726)]
56727#[cfg_attr(
56728    target_arch = "arm",
56729    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56730)]
56731pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
56732    unsafe { transmute(a) }
56733}
56734#[doc = "Vector reinterpret cast operation"]
56735#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"]
56736#[inline]
56737#[cfg(target_endian = "big")]
56738#[target_feature(enable = "neon,aes")]
56739#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56740#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56741#[cfg_attr(
56742    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56743    assert_instr(nop)
56744)]
56745#[cfg_attr(
56746    not(target_arch = "arm"),
56747    stable(feature = "neon_intrinsics", since = "1.59.0")
56748)]
56749#[cfg_attr(
56750    target_arch = "arm",
56751    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56752)]
56753pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
56754    unsafe {
56755        let ret_val: int16x4_t = transmute(a);
56756        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
56757    }
56758}
56759#[doc = "Vector reinterpret cast operation"]
56760#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"]
56761#[inline]
56762#[cfg(target_endian = "little")]
56763#[target_feature(enable = "neon,aes")]
56764#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56765#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56766#[cfg_attr(
56767    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56768    assert_instr(nop)
56769)]
56770#[cfg_attr(
56771    not(target_arch = "arm"),
56772    stable(feature = "neon_intrinsics", since = "1.59.0")
56773)]
56774#[cfg_attr(
56775    target_arch = "arm",
56776    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56777)]
56778pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
56779    unsafe { transmute(a) }
56780}
56781#[doc = "Vector reinterpret cast operation"]
56782#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"]
56783#[inline]
56784#[cfg(target_endian = "big")]
56785#[target_feature(enable = "neon,aes")]
56786#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56787#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56788#[cfg_attr(
56789    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56790    assert_instr(nop)
56791)]
56792#[cfg_attr(
56793    not(target_arch = "arm"),
56794    stable(feature = "neon_intrinsics", since = "1.59.0")
56795)]
56796#[cfg_attr(
56797    target_arch = "arm",
56798    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56799)]
56800pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
56801    unsafe {
56802        let ret_val: int32x2_t = transmute(a);
56803        simd_shuffle!(ret_val, ret_val, [1, 0])
56804    }
56805}
56806#[doc = "Vector reinterpret cast operation"]
56807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"]
56808#[inline]
56809#[cfg(target_endian = "little")]
56810#[target_feature(enable = "neon,aes")]
56811#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56812#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56813#[cfg_attr(
56814    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56815    assert_instr(nop)
56816)]
56817#[cfg_attr(
56818    not(target_arch = "arm"),
56819    stable(feature = "neon_intrinsics", since = "1.59.0")
56820)]
56821#[cfg_attr(
56822    target_arch = "arm",
56823    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56824)]
56825pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
56826    unsafe { transmute(a) }
56827}
56828#[doc = "Vector reinterpret cast operation"]
56829#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"]
56830#[inline]
56831#[cfg(target_endian = "big")]
56832#[target_feature(enable = "neon,aes")]
56833#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56834#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56835#[cfg_attr(
56836    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56837    assert_instr(nop)
56838)]
56839#[cfg_attr(
56840    not(target_arch = "arm"),
56841    stable(feature = "neon_intrinsics", since = "1.59.0")
56842)]
56843#[cfg_attr(
56844    target_arch = "arm",
56845    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56846)]
56847pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
56848    unsafe {
56849        let ret_val: uint8x8_t = transmute(a);
56850        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
56851    }
56852}
56853#[doc = "Vector reinterpret cast operation"]
56854#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"]
56855#[inline]
56856#[cfg(target_endian = "little")]
56857#[target_feature(enable = "neon,aes")]
56858#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56859#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56860#[cfg_attr(
56861    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56862    assert_instr(nop)
56863)]
56864#[cfg_attr(
56865    not(target_arch = "arm"),
56866    stable(feature = "neon_intrinsics", since = "1.59.0")
56867)]
56868#[cfg_attr(
56869    target_arch = "arm",
56870    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56871)]
56872pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
56873    unsafe { transmute(a) }
56874}
56875#[doc = "Vector reinterpret cast operation"]
56876#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"]
56877#[inline]
56878#[cfg(target_endian = "big")]
56879#[target_feature(enable = "neon,aes")]
56880#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56881#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56882#[cfg_attr(
56883    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56884    assert_instr(nop)
56885)]
56886#[cfg_attr(
56887    not(target_arch = "arm"),
56888    stable(feature = "neon_intrinsics", since = "1.59.0")
56889)]
56890#[cfg_attr(
56891    target_arch = "arm",
56892    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56893)]
56894pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
56895    unsafe {
56896        let ret_val: uint16x4_t = transmute(a);
56897        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
56898    }
56899}
56900#[doc = "Vector reinterpret cast operation"]
56901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"]
56902#[inline]
56903#[cfg(target_endian = "little")]
56904#[target_feature(enable = "neon,aes")]
56905#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56906#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56907#[cfg_attr(
56908    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56909    assert_instr(nop)
56910)]
56911#[cfg_attr(
56912    not(target_arch = "arm"),
56913    stable(feature = "neon_intrinsics", since = "1.59.0")
56914)]
56915#[cfg_attr(
56916    target_arch = "arm",
56917    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56918)]
56919pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
56920    unsafe { transmute(a) }
56921}
56922#[doc = "Vector reinterpret cast operation"]
56923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"]
56924#[inline]
56925#[cfg(target_endian = "big")]
56926#[target_feature(enable = "neon,aes")]
56927#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56928#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56929#[cfg_attr(
56930    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56931    assert_instr(nop)
56932)]
56933#[cfg_attr(
56934    not(target_arch = "arm"),
56935    stable(feature = "neon_intrinsics", since = "1.59.0")
56936)]
56937#[cfg_attr(
56938    target_arch = "arm",
56939    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56940)]
56941pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
56942    unsafe {
56943        let ret_val: uint32x2_t = transmute(a);
56944        simd_shuffle!(ret_val, ret_val, [1, 0])
56945    }
56946}
56947#[doc = "Vector reinterpret cast operation"]
56948#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"]
56949#[inline]
56950#[cfg(target_endian = "little")]
56951#[target_feature(enable = "neon,aes")]
56952#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56953#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56954#[cfg_attr(
56955    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56956    assert_instr(nop)
56957)]
56958#[cfg_attr(
56959    not(target_arch = "arm"),
56960    stable(feature = "neon_intrinsics", since = "1.59.0")
56961)]
56962#[cfg_attr(
56963    target_arch = "arm",
56964    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56965)]
56966pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
56967    unsafe { transmute(a) }
56968}
56969#[doc = "Vector reinterpret cast operation"]
56970#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"]
56971#[inline]
56972#[cfg(target_endian = "big")]
56973#[target_feature(enable = "neon,aes")]
56974#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56975#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56976#[cfg_attr(
56977    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56978    assert_instr(nop)
56979)]
56980#[cfg_attr(
56981    not(target_arch = "arm"),
56982    stable(feature = "neon_intrinsics", since = "1.59.0")
56983)]
56984#[cfg_attr(
56985    target_arch = "arm",
56986    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56987)]
56988pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
56989    unsafe {
56990        let ret_val: poly8x8_t = transmute(a);
56991        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
56992    }
56993}
56994#[doc = "Vector reinterpret cast operation"]
56995#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"]
56996#[inline]
56997#[cfg(target_endian = "little")]
56998#[target_feature(enable = "neon,aes")]
56999#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57000#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57001#[cfg_attr(
57002    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57003    assert_instr(nop)
57004)]
57005#[cfg_attr(
57006    not(target_arch = "arm"),
57007    stable(feature = "neon_intrinsics", since = "1.59.0")
57008)]
57009#[cfg_attr(
57010    target_arch = "arm",
57011    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57012)]
57013pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
57014    unsafe { transmute(a) }
57015}
57016#[doc = "Vector reinterpret cast operation"]
57017#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"]
57018#[inline]
57019#[cfg(target_endian = "big")]
57020#[target_feature(enable = "neon,aes")]
57021#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57022#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57023#[cfg_attr(
57024    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57025    assert_instr(nop)
57026)]
57027#[cfg_attr(
57028    not(target_arch = "arm"),
57029    stable(feature = "neon_intrinsics", since = "1.59.0")
57030)]
57031#[cfg_attr(
57032    target_arch = "arm",
57033    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57034)]
57035pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
57036    unsafe {
57037        let ret_val: poly16x4_t = transmute(a);
57038        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
57039    }
57040}
57041#[doc = "Vector reinterpret cast operation"]
57042#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"]
57043#[inline]
57044#[cfg(target_endian = "little")]
57045#[target_feature(enable = "neon,aes")]
57046#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57047#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57048#[cfg_attr(
57049    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57050    assert_instr(nop)
57051)]
57052#[cfg_attr(
57053    not(target_arch = "arm"),
57054    stable(feature = "neon_intrinsics", since = "1.59.0")
57055)]
57056#[cfg_attr(
57057    target_arch = "arm",
57058    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57059)]
57060pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
57061    unsafe { transmute(a) }
57062}
57063#[doc = "Vector reinterpret cast operation"]
57064#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"]
57065#[inline]
57066#[cfg(target_endian = "big")]
57067#[target_feature(enable = "neon,aes")]
57068#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57069#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57070#[cfg_attr(
57071    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57072    assert_instr(nop)
57073)]
57074#[cfg_attr(
57075    not(target_arch = "arm"),
57076    stable(feature = "neon_intrinsics", since = "1.59.0")
57077)]
57078#[cfg_attr(
57079    target_arch = "arm",
57080    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57081)]
57082pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
57083    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57084    unsafe { transmute(a) }
57085}
57086#[doc = "Vector reinterpret cast operation"]
57087#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"]
57088#[inline]
57089#[cfg(target_endian = "little")]
57090#[target_feature(enable = "neon,aes")]
57091#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57092#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57093#[cfg_attr(
57094    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57095    assert_instr(nop)
57096)]
57097#[cfg_attr(
57098    not(target_arch = "arm"),
57099    stable(feature = "neon_intrinsics", since = "1.59.0")
57100)]
57101#[cfg_attr(
57102    target_arch = "arm",
57103    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57104)]
57105pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
57106    unsafe { transmute(a) }
57107}
57108#[doc = "Vector reinterpret cast operation"]
57109#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"]
57110#[inline]
57111#[cfg(target_endian = "big")]
57112#[target_feature(enable = "neon,aes")]
57113#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57114#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57115#[cfg_attr(
57116    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57117    assert_instr(nop)
57118)]
57119#[cfg_attr(
57120    not(target_arch = "arm"),
57121    stable(feature = "neon_intrinsics", since = "1.59.0")
57122)]
57123#[cfg_attr(
57124    target_arch = "arm",
57125    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57126)]
57127pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
57128    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57129    unsafe {
57130        let ret_val: int8x16_t = transmute(a);
57131        simd_shuffle!(
57132            ret_val,
57133            ret_val,
57134            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
57135        )
57136    }
57137}
57138#[doc = "Vector reinterpret cast operation"]
57139#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"]
57140#[inline]
57141#[cfg(target_endian = "little")]
57142#[target_feature(enable = "neon,aes")]
57143#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57144#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57145#[cfg_attr(
57146    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57147    assert_instr(nop)
57148)]
57149#[cfg_attr(
57150    not(target_arch = "arm"),
57151    stable(feature = "neon_intrinsics", since = "1.59.0")
57152)]
57153#[cfg_attr(
57154    target_arch = "arm",
57155    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57156)]
57157pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
57158    unsafe { transmute(a) }
57159}
57160#[doc = "Vector reinterpret cast operation"]
57161#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"]
57162#[inline]
57163#[cfg(target_endian = "big")]
57164#[target_feature(enable = "neon,aes")]
57165#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57166#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57167#[cfg_attr(
57168    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57169    assert_instr(nop)
57170)]
57171#[cfg_attr(
57172    not(target_arch = "arm"),
57173    stable(feature = "neon_intrinsics", since = "1.59.0")
57174)]
57175#[cfg_attr(
57176    target_arch = "arm",
57177    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57178)]
57179pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
57180    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57181    unsafe {
57182        let ret_val: int16x8_t = transmute(a);
57183        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
57184    }
57185}
57186#[doc = "Vector reinterpret cast operation"]
57187#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"]
57188#[inline]
57189#[cfg(target_endian = "little")]
57190#[target_feature(enable = "neon,aes")]
57191#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57192#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57193#[cfg_attr(
57194    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57195    assert_instr(nop)
57196)]
57197#[cfg_attr(
57198    not(target_arch = "arm"),
57199    stable(feature = "neon_intrinsics", since = "1.59.0")
57200)]
57201#[cfg_attr(
57202    target_arch = "arm",
57203    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57204)]
57205pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
57206    unsafe { transmute(a) }
57207}
57208#[doc = "Vector reinterpret cast operation"]
57209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"]
57210#[inline]
57211#[cfg(target_endian = "big")]
57212#[target_feature(enable = "neon,aes")]
57213#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57214#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57215#[cfg_attr(
57216    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57217    assert_instr(nop)
57218)]
57219#[cfg_attr(
57220    not(target_arch = "arm"),
57221    stable(feature = "neon_intrinsics", since = "1.59.0")
57222)]
57223#[cfg_attr(
57224    target_arch = "arm",
57225    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57226)]
57227pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
57228    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57229    unsafe {
57230        let ret_val: int32x4_t = transmute(a);
57231        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
57232    }
57233}
57234#[doc = "Vector reinterpret cast operation"]
57235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"]
57236#[inline]
57237#[cfg(target_endian = "little")]
57238#[target_feature(enable = "neon,aes")]
57239#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57240#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57241#[cfg_attr(
57242    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57243    assert_instr(nop)
57244)]
57245#[cfg_attr(
57246    not(target_arch = "arm"),
57247    stable(feature = "neon_intrinsics", since = "1.59.0")
57248)]
57249#[cfg_attr(
57250    target_arch = "arm",
57251    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57252)]
57253pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
57254    unsafe { transmute(a) }
57255}
57256#[doc = "Vector reinterpret cast operation"]
57257#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"]
57258#[inline]
57259#[cfg(target_endian = "big")]
57260#[target_feature(enable = "neon,aes")]
57261#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57262#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57263#[cfg_attr(
57264    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57265    assert_instr(nop)
57266)]
57267#[cfg_attr(
57268    not(target_arch = "arm"),
57269    stable(feature = "neon_intrinsics", since = "1.59.0")
57270)]
57271#[cfg_attr(
57272    target_arch = "arm",
57273    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57274)]
57275pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
57276    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57277    unsafe {
57278        let ret_val: uint8x16_t = transmute(a);
57279        simd_shuffle!(
57280            ret_val,
57281            ret_val,
57282            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
57283        )
57284    }
57285}
57286#[doc = "Vector reinterpret cast operation"]
57287#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"]
57288#[inline]
57289#[cfg(target_endian = "little")]
57290#[target_feature(enable = "neon,aes")]
57291#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57292#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57293#[cfg_attr(
57294    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57295    assert_instr(nop)
57296)]
57297#[cfg_attr(
57298    not(target_arch = "arm"),
57299    stable(feature = "neon_intrinsics", since = "1.59.0")
57300)]
57301#[cfg_attr(
57302    target_arch = "arm",
57303    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57304)]
57305pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
57306    unsafe { transmute(a) }
57307}
57308#[doc = "Vector reinterpret cast operation"]
57309#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"]
57310#[inline]
57311#[cfg(target_endian = "big")]
57312#[target_feature(enable = "neon,aes")]
57313#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57314#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57315#[cfg_attr(
57316    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57317    assert_instr(nop)
57318)]
57319#[cfg_attr(
57320    not(target_arch = "arm"),
57321    stable(feature = "neon_intrinsics", since = "1.59.0")
57322)]
57323#[cfg_attr(
57324    target_arch = "arm",
57325    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57326)]
57327pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
57328    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57329    unsafe {
57330        let ret_val: uint16x8_t = transmute(a);
57331        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
57332    }
57333}
57334#[doc = "Vector reinterpret cast operation"]
57335#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"]
57336#[inline]
57337#[cfg(target_endian = "little")]
57338#[target_feature(enable = "neon,aes")]
57339#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57340#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57341#[cfg_attr(
57342    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57343    assert_instr(nop)
57344)]
57345#[cfg_attr(
57346    not(target_arch = "arm"),
57347    stable(feature = "neon_intrinsics", since = "1.59.0")
57348)]
57349#[cfg_attr(
57350    target_arch = "arm",
57351    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57352)]
57353pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
57354    unsafe { transmute(a) }
57355}
57356#[doc = "Vector reinterpret cast operation"]
57357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"]
57358#[inline]
57359#[cfg(target_endian = "big")]
57360#[target_feature(enable = "neon,aes")]
57361#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57362#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57363#[cfg_attr(
57364    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57365    assert_instr(nop)
57366)]
57367#[cfg_attr(
57368    not(target_arch = "arm"),
57369    stable(feature = "neon_intrinsics", since = "1.59.0")
57370)]
57371#[cfg_attr(
57372    target_arch = "arm",
57373    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57374)]
57375pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
57376    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57377    unsafe {
57378        let ret_val: uint32x4_t = transmute(a);
57379        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
57380    }
57381}
57382#[doc = "Vector reinterpret cast operation"]
57383#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"]
57384#[inline]
57385#[cfg(target_endian = "little")]
57386#[target_feature(enable = "neon,aes")]
57387#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57388#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57389#[cfg_attr(
57390    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57391    assert_instr(nop)
57392)]
57393#[cfg_attr(
57394    not(target_arch = "arm"),
57395    stable(feature = "neon_intrinsics", since = "1.59.0")
57396)]
57397#[cfg_attr(
57398    target_arch = "arm",
57399    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57400)]
57401pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
57402    unsafe { transmute(a) }
57403}
57404#[doc = "Vector reinterpret cast operation"]
57405#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"]
57406#[inline]
57407#[cfg(target_endian = "big")]
57408#[target_feature(enable = "neon,aes")]
57409#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57410#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57411#[cfg_attr(
57412    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57413    assert_instr(nop)
57414)]
57415#[cfg_attr(
57416    not(target_arch = "arm"),
57417    stable(feature = "neon_intrinsics", since = "1.59.0")
57418)]
57419#[cfg_attr(
57420    target_arch = "arm",
57421    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57422)]
57423pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
57424    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57425    unsafe {
57426        let ret_val: poly8x16_t = transmute(a);
57427        simd_shuffle!(
57428            ret_val,
57429            ret_val,
57430            [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
57431        )
57432    }
57433}
57434#[doc = "Vector reinterpret cast operation"]
57435#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"]
57436#[inline]
57437#[cfg(target_endian = "little")]
57438#[target_feature(enable = "neon,aes")]
57439#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57440#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57441#[cfg_attr(
57442    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57443    assert_instr(nop)
57444)]
57445#[cfg_attr(
57446    not(target_arch = "arm"),
57447    stable(feature = "neon_intrinsics", since = "1.59.0")
57448)]
57449#[cfg_attr(
57450    target_arch = "arm",
57451    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57452)]
57453pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
57454    unsafe { transmute(a) }
57455}
57456#[doc = "Vector reinterpret cast operation"]
57457#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"]
57458#[inline]
57459#[cfg(target_endian = "big")]
57460#[target_feature(enable = "neon,aes")]
57461#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57462#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57463#[cfg_attr(
57464    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57465    assert_instr(nop)
57466)]
57467#[cfg_attr(
57468    not(target_arch = "arm"),
57469    stable(feature = "neon_intrinsics", since = "1.59.0")
57470)]
57471#[cfg_attr(
57472    target_arch = "arm",
57473    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57474)]
57475pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
57476    let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57477    unsafe {
57478        let ret_val: poly16x8_t = transmute(a);
57479        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
57480    }
57481}
57482#[doc = "Reversing vector elements (swap endianness)"]
57483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_p8)"]
57484#[inline]
57485#[target_feature(enable = "neon")]
57486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57487#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57488#[cfg_attr(
57489    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57490    assert_instr(rev16)
57491)]
57492#[cfg_attr(
57493    not(target_arch = "arm"),
57494    stable(feature = "neon_intrinsics", since = "1.59.0")
57495)]
57496#[cfg_attr(
57497    target_arch = "arm",
57498    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57499)]
57500pub fn vrev16_p8(a: poly8x8_t) -> poly8x8_t {
57501    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57502}
57503#[doc = "Reversing vector elements (swap endianness)"]
57504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_s8)"]
57505#[inline]
57506#[target_feature(enable = "neon")]
57507#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57508#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57509#[cfg_attr(
57510    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57511    assert_instr(rev16)
57512)]
57513#[cfg_attr(
57514    not(target_arch = "arm"),
57515    stable(feature = "neon_intrinsics", since = "1.59.0")
57516)]
57517#[cfg_attr(
57518    target_arch = "arm",
57519    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57520)]
57521pub fn vrev16_s8(a: int8x8_t) -> int8x8_t {
57522    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57523}
57524#[doc = "Reversing vector elements (swap endianness)"]
57525#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_u8)"]
57526#[inline]
57527#[target_feature(enable = "neon")]
57528#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57529#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57530#[cfg_attr(
57531    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57532    assert_instr(rev16)
57533)]
57534#[cfg_attr(
57535    not(target_arch = "arm"),
57536    stable(feature = "neon_intrinsics", since = "1.59.0")
57537)]
57538#[cfg_attr(
57539    target_arch = "arm",
57540    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57541)]
57542pub fn vrev16_u8(a: uint8x8_t) -> uint8x8_t {
57543    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57544}
57545#[doc = "Reversing vector elements (swap endianness)"]
57546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_p8)"]
57547#[inline]
57548#[target_feature(enable = "neon")]
57549#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57550#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57551#[cfg_attr(
57552    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57553    assert_instr(rev16)
57554)]
57555#[cfg_attr(
57556    not(target_arch = "arm"),
57557    stable(feature = "neon_intrinsics", since = "1.59.0")
57558)]
57559#[cfg_attr(
57560    target_arch = "arm",
57561    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57562)]
57563pub fn vrev16q_p8(a: poly8x16_t) -> poly8x16_t {
57564    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) }
57565}
57566#[doc = "Reversing vector elements (swap endianness)"]
57567#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_s8)"]
57568#[inline]
57569#[target_feature(enable = "neon")]
57570#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57571#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57572#[cfg_attr(
57573    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57574    assert_instr(rev16)
57575)]
57576#[cfg_attr(
57577    not(target_arch = "arm"),
57578    stable(feature = "neon_intrinsics", since = "1.59.0")
57579)]
57580#[cfg_attr(
57581    target_arch = "arm",
57582    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57583)]
57584pub fn vrev16q_s8(a: int8x16_t) -> int8x16_t {
57585    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) }
57586}
57587#[doc = "Reversing vector elements (swap endianness)"]
57588#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_u8)"]
57589#[inline]
57590#[target_feature(enable = "neon")]
57591#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57592#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57593#[cfg_attr(
57594    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57595    assert_instr(rev16)
57596)]
57597#[cfg_attr(
57598    not(target_arch = "arm"),
57599    stable(feature = "neon_intrinsics", since = "1.59.0")
57600)]
57601#[cfg_attr(
57602    target_arch = "arm",
57603    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57604)]
57605pub fn vrev16q_u8(a: uint8x16_t) -> uint8x16_t {
57606    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) }
57607}
57608#[doc = "Reversing vector elements (swap endianness)"]
57609#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p16)"]
57610#[inline]
57611#[target_feature(enable = "neon")]
57612#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57613#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57614#[cfg_attr(
57615    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57616    assert_instr(rev32)
57617)]
57618#[cfg_attr(
57619    not(target_arch = "arm"),
57620    stable(feature = "neon_intrinsics", since = "1.59.0")
57621)]
57622#[cfg_attr(
57623    target_arch = "arm",
57624    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57625)]
57626pub fn vrev32_p16(a: poly16x4_t) -> poly16x4_t {
57627    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
57628}
57629#[doc = "Reversing vector elements (swap endianness)"]
57630#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p8)"]
57631#[inline]
57632#[target_feature(enable = "neon")]
57633#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57634#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57635#[cfg_attr(
57636    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57637    assert_instr(rev32)
57638)]
57639#[cfg_attr(
57640    not(target_arch = "arm"),
57641    stable(feature = "neon_intrinsics", since = "1.59.0")
57642)]
57643#[cfg_attr(
57644    target_arch = "arm",
57645    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57646)]
57647pub fn vrev32_p8(a: poly8x8_t) -> poly8x8_t {
57648    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
57649}
57650#[doc = "Reversing vector elements (swap endianness)"]
57651#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s16)"]
57652#[inline]
57653#[target_feature(enable = "neon")]
57654#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57655#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57656#[cfg_attr(
57657    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57658    assert_instr(rev32)
57659)]
57660#[cfg_attr(
57661    not(target_arch = "arm"),
57662    stable(feature = "neon_intrinsics", since = "1.59.0")
57663)]
57664#[cfg_attr(
57665    target_arch = "arm",
57666    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57667)]
57668pub fn vrev32_s16(a: int16x4_t) -> int16x4_t {
57669    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
57670}
57671#[doc = "Reversing vector elements (swap endianness)"]
57672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s8)"]
57673#[inline]
57674#[target_feature(enable = "neon")]
57675#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57676#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57677#[cfg_attr(
57678    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57679    assert_instr(rev32)
57680)]
57681#[cfg_attr(
57682    not(target_arch = "arm"),
57683    stable(feature = "neon_intrinsics", since = "1.59.0")
57684)]
57685#[cfg_attr(
57686    target_arch = "arm",
57687    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57688)]
57689pub fn vrev32_s8(a: int8x8_t) -> int8x8_t {
57690    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
57691}
57692#[doc = "Reversing vector elements (swap endianness)"]
57693#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u16)"]
57694#[inline]
57695#[target_feature(enable = "neon")]
57696#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57697#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57698#[cfg_attr(
57699    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57700    assert_instr(rev32)
57701)]
57702#[cfg_attr(
57703    not(target_arch = "arm"),
57704    stable(feature = "neon_intrinsics", since = "1.59.0")
57705)]
57706#[cfg_attr(
57707    target_arch = "arm",
57708    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57709)]
57710pub fn vrev32_u16(a: uint16x4_t) -> uint16x4_t {
57711    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
57712}
57713#[doc = "Reversing vector elements (swap endianness)"]
57714#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u8)"]
57715#[inline]
57716#[target_feature(enable = "neon")]
57717#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57718#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57719#[cfg_attr(
57720    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57721    assert_instr(rev32)
57722)]
57723#[cfg_attr(
57724    not(target_arch = "arm"),
57725    stable(feature = "neon_intrinsics", since = "1.59.0")
57726)]
57727#[cfg_attr(
57728    target_arch = "arm",
57729    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57730)]
57731pub fn vrev32_u8(a: uint8x8_t) -> uint8x8_t {
57732    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
57733}
57734#[doc = "Reversing vector elements (swap endianness)"]
57735#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p16)"]
57736#[inline]
57737#[target_feature(enable = "neon")]
57738#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57739#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57740#[cfg_attr(
57741    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57742    assert_instr(rev32)
57743)]
57744#[cfg_attr(
57745    not(target_arch = "arm"),
57746    stable(feature = "neon_intrinsics", since = "1.59.0")
57747)]
57748#[cfg_attr(
57749    target_arch = "arm",
57750    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57751)]
57752pub fn vrev32q_p16(a: poly16x8_t) -> poly16x8_t {
57753    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57754}
57755#[doc = "Reversing vector elements (swap endianness)"]
57756#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p8)"]
57757#[inline]
57758#[target_feature(enable = "neon")]
57759#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57760#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57761#[cfg_attr(
57762    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57763    assert_instr(rev32)
57764)]
57765#[cfg_attr(
57766    not(target_arch = "arm"),
57767    stable(feature = "neon_intrinsics", since = "1.59.0")
57768)]
57769#[cfg_attr(
57770    target_arch = "arm",
57771    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57772)]
57773pub fn vrev32q_p8(a: poly8x16_t) -> poly8x16_t {
57774    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) }
57775}
57776#[doc = "Reversing vector elements (swap endianness)"]
57777#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s16)"]
57778#[inline]
57779#[target_feature(enable = "neon")]
57780#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57781#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57782#[cfg_attr(
57783    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57784    assert_instr(rev32)
57785)]
57786#[cfg_attr(
57787    not(target_arch = "arm"),
57788    stable(feature = "neon_intrinsics", since = "1.59.0")
57789)]
57790#[cfg_attr(
57791    target_arch = "arm",
57792    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57793)]
57794pub fn vrev32q_s16(a: int16x8_t) -> int16x8_t {
57795    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57796}
57797#[doc = "Reversing vector elements (swap endianness)"]
57798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s8)"]
57799#[inline]
57800#[target_feature(enable = "neon")]
57801#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57802#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57803#[cfg_attr(
57804    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57805    assert_instr(rev32)
57806)]
57807#[cfg_attr(
57808    not(target_arch = "arm"),
57809    stable(feature = "neon_intrinsics", since = "1.59.0")
57810)]
57811#[cfg_attr(
57812    target_arch = "arm",
57813    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57814)]
57815pub fn vrev32q_s8(a: int8x16_t) -> int8x16_t {
57816    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) }
57817}
57818#[doc = "Reversing vector elements (swap endianness)"]
57819#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u16)"]
57820#[inline]
57821#[target_feature(enable = "neon")]
57822#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57823#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57824#[cfg_attr(
57825    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57826    assert_instr(rev32)
57827)]
57828#[cfg_attr(
57829    not(target_arch = "arm"),
57830    stable(feature = "neon_intrinsics", since = "1.59.0")
57831)]
57832#[cfg_attr(
57833    target_arch = "arm",
57834    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57835)]
57836pub fn vrev32q_u16(a: uint16x8_t) -> uint16x8_t {
57837    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57838}
57839#[doc = "Reversing vector elements (swap endianness)"]
57840#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u8)"]
57841#[inline]
57842#[target_feature(enable = "neon")]
57843#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57844#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57845#[cfg_attr(
57846    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57847    assert_instr(rev32)
57848)]
57849#[cfg_attr(
57850    not(target_arch = "arm"),
57851    stable(feature = "neon_intrinsics", since = "1.59.0")
57852)]
57853#[cfg_attr(
57854    target_arch = "arm",
57855    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57856)]
57857pub fn vrev32q_u8(a: uint8x16_t) -> uint8x16_t {
57858    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) }
57859}
57860#[doc = "Reversing vector elements (swap endianness)"]
57861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f32)"]
57862#[inline]
57863#[target_feature(enable = "neon")]
57864#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57865#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
57866#[cfg_attr(
57867    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57868    assert_instr(rev64)
57869)]
57870#[cfg_attr(
57871    not(target_arch = "arm"),
57872    stable(feature = "neon_intrinsics", since = "1.59.0")
57873)]
57874#[cfg_attr(
57875    target_arch = "arm",
57876    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57877)]
57878pub fn vrev64_f32(a: float32x2_t) -> float32x2_t {
57879    unsafe { simd_shuffle!(a, a, [1, 0]) }
57880}
57881#[doc = "Reversing vector elements (swap endianness)"]
57882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p16)"]
57883#[inline]
57884#[target_feature(enable = "neon")]
57885#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57886#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
57887#[cfg_attr(
57888    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57889    assert_instr(rev64)
57890)]
57891#[cfg_attr(
57892    not(target_arch = "arm"),
57893    stable(feature = "neon_intrinsics", since = "1.59.0")
57894)]
57895#[cfg_attr(
57896    target_arch = "arm",
57897    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57898)]
57899pub fn vrev64_p16(a: poly16x4_t) -> poly16x4_t {
57900    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }
57901}
57902#[doc = "Reversing vector elements (swap endianness)"]
57903#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p8)"]
57904#[inline]
57905#[target_feature(enable = "neon")]
57906#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57907#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
57908#[cfg_attr(
57909    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57910    assert_instr(rev64)
57911)]
57912#[cfg_attr(
57913    not(target_arch = "arm"),
57914    stable(feature = "neon_intrinsics", since = "1.59.0")
57915)]
57916#[cfg_attr(
57917    target_arch = "arm",
57918    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57919)]
57920pub fn vrev64_p8(a: poly8x8_t) -> poly8x8_t {
57921    unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }
57922}
57923#[doc = "Reversing vector elements (swap endianness)"]
57924#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s16)"]
57925#[inline]
57926#[target_feature(enable = "neon")]
57927#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57928#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
57929#[cfg_attr(
57930    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57931    assert_instr(rev64)
57932)]
57933#[cfg_attr(
57934    not(target_arch = "arm"),
57935    stable(feature = "neon_intrinsics", since = "1.59.0")
57936)]
57937#[cfg_attr(
57938    target_arch = "arm",
57939    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57940)]
57941pub fn vrev64_s16(a: int16x4_t) -> int16x4_t {
57942    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }
57943}
57944#[doc = "Reversing vector elements (swap endianness)"]
57945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s32)"]
57946#[inline]
57947#[target_feature(enable = "neon")]
57948#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57949#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
57950#[cfg_attr(
57951    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57952    assert_instr(rev64)
57953)]
57954#[cfg_attr(
57955    not(target_arch = "arm"),
57956    stable(feature = "neon_intrinsics", since = "1.59.0")
57957)]
57958#[cfg_attr(
57959    target_arch = "arm",
57960    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57961)]
57962pub fn vrev64_s32(a: int32x2_t) -> int32x2_t {
57963    unsafe { simd_shuffle!(a, a, [1, 0]) }
57964}
57965#[doc = "Reversing vector elements (swap endianness)"]
57966#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s8)"]
57967#[inline]
57968#[target_feature(enable = "neon")]
57969#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57970#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
57971#[cfg_attr(
57972    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57973    assert_instr(rev64)
57974)]
57975#[cfg_attr(
57976    not(target_arch = "arm"),
57977    stable(feature = "neon_intrinsics", since = "1.59.0")
57978)]
57979#[cfg_attr(
57980    target_arch = "arm",
57981    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57982)]
57983pub fn vrev64_s8(a: int8x8_t) -> int8x8_t {
57984    unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }
57985}
57986#[doc = "Reversing vector elements (swap endianness)"]
57987#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u16)"]
57988#[inline]
57989#[target_feature(enable = "neon")]
57990#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57991#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
57992#[cfg_attr(
57993    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57994    assert_instr(rev64)
57995)]
57996#[cfg_attr(
57997    not(target_arch = "arm"),
57998    stable(feature = "neon_intrinsics", since = "1.59.0")
57999)]
58000#[cfg_attr(
58001    target_arch = "arm",
58002    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58003)]
58004pub fn vrev64_u16(a: uint16x4_t) -> uint16x4_t {
58005    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }
58006}
58007#[doc = "Reversing vector elements (swap endianness)"]
58008#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u32)"]
58009#[inline]
58010#[target_feature(enable = "neon")]
58011#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58012#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
58013#[cfg_attr(
58014    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58015    assert_instr(rev64)
58016)]
58017#[cfg_attr(
58018    not(target_arch = "arm"),
58019    stable(feature = "neon_intrinsics", since = "1.59.0")
58020)]
58021#[cfg_attr(
58022    target_arch = "arm",
58023    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58024)]
58025pub fn vrev64_u32(a: uint32x2_t) -> uint32x2_t {
58026    unsafe { simd_shuffle!(a, a, [1, 0]) }
58027}
58028#[doc = "Reversing vector elements (swap endianness)"]
58029#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u8)"]
58030#[inline]
58031#[target_feature(enable = "neon")]
58032#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58033#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
58034#[cfg_attr(
58035    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58036    assert_instr(rev64)
58037)]
58038#[cfg_attr(
58039    not(target_arch = "arm"),
58040    stable(feature = "neon_intrinsics", since = "1.59.0")
58041)]
58042#[cfg_attr(
58043    target_arch = "arm",
58044    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58045)]
58046pub fn vrev64_u8(a: uint8x8_t) -> uint8x8_t {
58047    unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }
58048}
58049#[doc = "Reversing vector elements (swap endianness)"]
58050#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f32)"]
58051#[inline]
58052#[target_feature(enable = "neon")]
58053#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58054#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
58055#[cfg_attr(
58056    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58057    assert_instr(rev64)
58058)]
58059#[cfg_attr(
58060    not(target_arch = "arm"),
58061    stable(feature = "neon_intrinsics", since = "1.59.0")
58062)]
58063#[cfg_attr(
58064    target_arch = "arm",
58065    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58066)]
58067pub fn vrev64q_f32(a: float32x4_t) -> float32x4_t {
58068    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
58069}
58070#[doc = "Reversing vector elements (swap endianness)"]
58071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p16)"]
58072#[inline]
58073#[target_feature(enable = "neon")]
58074#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58075#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
58076#[cfg_attr(
58077    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58078    assert_instr(rev64)
58079)]
58080#[cfg_attr(
58081    not(target_arch = "arm"),
58082    stable(feature = "neon_intrinsics", since = "1.59.0")
58083)]
58084#[cfg_attr(
58085    target_arch = "arm",
58086    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58087)]
58088pub fn vrev64q_p16(a: poly16x8_t) -> poly16x8_t {
58089    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
58090}
58091#[doc = "Reversing vector elements (swap endianness)"]
58092#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p8)"]
58093#[inline]
58094#[target_feature(enable = "neon")]
58095#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58096#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
58097#[cfg_attr(
58098    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58099    assert_instr(rev64)
58100)]
58101#[cfg_attr(
58102    not(target_arch = "arm"),
58103    stable(feature = "neon_intrinsics", since = "1.59.0")
58104)]
58105#[cfg_attr(
58106    target_arch = "arm",
58107    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58108)]
58109pub fn vrev64q_p8(a: poly8x16_t) -> poly8x16_t {
58110    unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) }
58111}
58112#[doc = "Reversing vector elements (swap endianness)"]
58113#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s16)"]
58114#[inline]
58115#[target_feature(enable = "neon")]
58116#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58117#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
58118#[cfg_attr(
58119    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58120    assert_instr(rev64)
58121)]
58122#[cfg_attr(
58123    not(target_arch = "arm"),
58124    stable(feature = "neon_intrinsics", since = "1.59.0")
58125)]
58126#[cfg_attr(
58127    target_arch = "arm",
58128    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58129)]
58130pub fn vrev64q_s16(a: int16x8_t) -> int16x8_t {
58131    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
58132}
58133#[doc = "Reversing vector elements (swap endianness)"]
58134#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s32)"]
58135#[inline]
58136#[target_feature(enable = "neon")]
58137#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58138#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
58139#[cfg_attr(
58140    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58141    assert_instr(rev64)
58142)]
58143#[cfg_attr(
58144    not(target_arch = "arm"),
58145    stable(feature = "neon_intrinsics", since = "1.59.0")
58146)]
58147#[cfg_attr(
58148    target_arch = "arm",
58149    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58150)]
58151pub fn vrev64q_s32(a: int32x4_t) -> int32x4_t {
58152    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
58153}
58154#[doc = "Reversing vector elements (swap endianness)"]
58155#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s8)"]
58156#[inline]
58157#[target_feature(enable = "neon")]
58158#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58159#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
58160#[cfg_attr(
58161    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58162    assert_instr(rev64)
58163)]
58164#[cfg_attr(
58165    not(target_arch = "arm"),
58166    stable(feature = "neon_intrinsics", since = "1.59.0")
58167)]
58168#[cfg_attr(
58169    target_arch = "arm",
58170    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58171)]
58172pub fn vrev64q_s8(a: int8x16_t) -> int8x16_t {
58173    unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) }
58174}
58175#[doc = "Reversing vector elements (swap endianness)"]
58176#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u16)"]
58177#[inline]
58178#[target_feature(enable = "neon")]
58179#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58180#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
58181#[cfg_attr(
58182    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58183    assert_instr(rev64)
58184)]
58185#[cfg_attr(
58186    not(target_arch = "arm"),
58187    stable(feature = "neon_intrinsics", since = "1.59.0")
58188)]
58189#[cfg_attr(
58190    target_arch = "arm",
58191    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58192)]
58193pub fn vrev64q_u16(a: uint16x8_t) -> uint16x8_t {
58194    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
58195}
58196#[doc = "Reversing vector elements (swap endianness)"]
58197#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u32)"]
58198#[inline]
58199#[target_feature(enable = "neon")]
58200#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58201#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
58202#[cfg_attr(
58203    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58204    assert_instr(rev64)
58205)]
58206#[cfg_attr(
58207    not(target_arch = "arm"),
58208    stable(feature = "neon_intrinsics", since = "1.59.0")
58209)]
58210#[cfg_attr(
58211    target_arch = "arm",
58212    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58213)]
58214pub fn vrev64q_u32(a: uint32x4_t) -> uint32x4_t {
58215    unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
58216}
58217#[doc = "Reversing vector elements (swap endianness)"]
58218#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u8)"]
58219#[inline]
58220#[target_feature(enable = "neon")]
58221#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58222#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
58223#[cfg_attr(
58224    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58225    assert_instr(rev64)
58226)]
58227#[cfg_attr(
58228    not(target_arch = "arm"),
58229    stable(feature = "neon_intrinsics", since = "1.59.0")
58230)]
58231#[cfg_attr(
58232    target_arch = "arm",
58233    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58234)]
58235pub fn vrev64q_u8(a: uint8x16_t) -> uint8x16_t {
58236    unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) }
58237}
58238#[doc = "Reverse elements in 64-bit doublewords"]
58239#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f16)"]
58240#[inline]
58241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58242#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))]
58243#[cfg_attr(
58244    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58245    assert_instr(rev64)
58246)]
58247#[target_feature(enable = "neon,fp16")]
58248#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
58249pub fn vrev64_f16(a: float16x4_t) -> float16x4_t {
58250    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }
58251}
58252#[doc = "Reverse elements in 64-bit doublewords"]
58253#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f16)"]
58254#[inline]
58255#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58256#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))]
58257#[cfg_attr(
58258    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58259    assert_instr(rev64)
58260)]
58261#[target_feature(enable = "neon,fp16")]
58262#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
58263pub fn vrev64q_f16(a: float16x8_t) -> float16x8_t {
58264    unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
58265}
58266#[doc = "Rounding halving add"]
58267#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s8)"]
58268#[inline]
58269#[target_feature(enable = "neon")]
58270#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58271#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))]
58272#[cfg_attr(
58273    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58274    assert_instr(srhadd)
58275)]
58276#[cfg_attr(
58277    not(target_arch = "arm"),
58278    stable(feature = "neon_intrinsics", since = "1.59.0")
58279)]
58280#[cfg_attr(
58281    target_arch = "arm",
58282    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58283)]
58284pub fn vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
58285    unsafe extern "unadjusted" {
58286        #[cfg_attr(
58287            any(target_arch = "aarch64", target_arch = "arm64ec"),
58288            link_name = "llvm.aarch64.neon.srhadd.v8i8"
58289        )]
58290        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v8i8")]
58291        fn _vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
58292    }
58293    unsafe { _vrhadd_s8(a, b) }
58294}
58295#[doc = "Rounding halving add"]
58296#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s8)"]
58297#[inline]
58298#[target_feature(enable = "neon")]
58299#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58300#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))]
58301#[cfg_attr(
58302    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58303    assert_instr(srhadd)
58304)]
58305#[cfg_attr(
58306    not(target_arch = "arm"),
58307    stable(feature = "neon_intrinsics", since = "1.59.0")
58308)]
58309#[cfg_attr(
58310    target_arch = "arm",
58311    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58312)]
58313pub fn vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
58314    unsafe extern "unadjusted" {
58315        #[cfg_attr(
58316            any(target_arch = "aarch64", target_arch = "arm64ec"),
58317            link_name = "llvm.aarch64.neon.srhadd.v16i8"
58318        )]
58319        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v16i8")]
58320        fn _vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
58321    }
58322    unsafe { _vrhaddq_s8(a, b) }
58323}
58324#[doc = "Rounding halving add"]
58325#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s16)"]
58326#[inline]
58327#[target_feature(enable = "neon")]
58328#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58329#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))]
58330#[cfg_attr(
58331    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58332    assert_instr(srhadd)
58333)]
58334#[cfg_attr(
58335    not(target_arch = "arm"),
58336    stable(feature = "neon_intrinsics", since = "1.59.0")
58337)]
58338#[cfg_attr(
58339    target_arch = "arm",
58340    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58341)]
58342pub fn vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
58343    unsafe extern "unadjusted" {
58344        #[cfg_attr(
58345            any(target_arch = "aarch64", target_arch = "arm64ec"),
58346            link_name = "llvm.aarch64.neon.srhadd.v4i16"
58347        )]
58348        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v4i16")]
58349        fn _vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
58350    }
58351    unsafe { _vrhadd_s16(a, b) }
58352}
58353#[doc = "Rounding halving add"]
58354#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s16)"]
58355#[inline]
58356#[target_feature(enable = "neon")]
58357#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58358#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))]
58359#[cfg_attr(
58360    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58361    assert_instr(srhadd)
58362)]
58363#[cfg_attr(
58364    not(target_arch = "arm"),
58365    stable(feature = "neon_intrinsics", since = "1.59.0")
58366)]
58367#[cfg_attr(
58368    target_arch = "arm",
58369    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58370)]
58371pub fn vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
58372    unsafe extern "unadjusted" {
58373        #[cfg_attr(
58374            any(target_arch = "aarch64", target_arch = "arm64ec"),
58375            link_name = "llvm.aarch64.neon.srhadd.v8i16"
58376        )]
58377        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v8i16")]
58378        fn _vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
58379    }
58380    unsafe { _vrhaddq_s16(a, b) }
58381}
58382#[doc = "Rounding halving add"]
58383#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s32)"]
58384#[inline]
58385#[target_feature(enable = "neon")]
58386#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58387#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))]
58388#[cfg_attr(
58389    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58390    assert_instr(srhadd)
58391)]
58392#[cfg_attr(
58393    not(target_arch = "arm"),
58394    stable(feature = "neon_intrinsics", since = "1.59.0")
58395)]
58396#[cfg_attr(
58397    target_arch = "arm",
58398    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58399)]
58400pub fn vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
58401    unsafe extern "unadjusted" {
58402        #[cfg_attr(
58403            any(target_arch = "aarch64", target_arch = "arm64ec"),
58404            link_name = "llvm.aarch64.neon.srhadd.v2i32"
58405        )]
58406        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v2i32")]
58407        fn _vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
58408    }
58409    unsafe { _vrhadd_s32(a, b) }
58410}
58411#[doc = "Rounding halving add"]
58412#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s32)"]
58413#[inline]
58414#[target_feature(enable = "neon")]
58415#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58416#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))]
58417#[cfg_attr(
58418    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58419    assert_instr(srhadd)
58420)]
58421#[cfg_attr(
58422    not(target_arch = "arm"),
58423    stable(feature = "neon_intrinsics", since = "1.59.0")
58424)]
58425#[cfg_attr(
58426    target_arch = "arm",
58427    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58428)]
58429pub fn vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
58430    unsafe extern "unadjusted" {
58431        #[cfg_attr(
58432            any(target_arch = "aarch64", target_arch = "arm64ec"),
58433            link_name = "llvm.aarch64.neon.srhadd.v4i32"
58434        )]
58435        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v4i32")]
58436        fn _vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
58437    }
58438    unsafe { _vrhaddq_s32(a, b) }
58439}
58440#[doc = "Rounding halving add"]
58441#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u8)"]
58442#[inline]
58443#[target_feature(enable = "neon")]
58444#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58445#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))]
58446#[cfg_attr(
58447    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58448    assert_instr(urhadd)
58449)]
58450#[cfg_attr(
58451    not(target_arch = "arm"),
58452    stable(feature = "neon_intrinsics", since = "1.59.0")
58453)]
58454#[cfg_attr(
58455    target_arch = "arm",
58456    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58457)]
58458pub fn vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
58459    unsafe extern "unadjusted" {
58460        #[cfg_attr(
58461            any(target_arch = "aarch64", target_arch = "arm64ec"),
58462            link_name = "llvm.aarch64.neon.urhadd.v8i8"
58463        )]
58464        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v8i8")]
58465        fn _vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
58466    }
58467    unsafe { _vrhadd_u8(a, b) }
58468}
58469#[doc = "Rounding halving add"]
58470#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u8)"]
58471#[inline]
58472#[target_feature(enable = "neon")]
58473#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58474#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))]
58475#[cfg_attr(
58476    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58477    assert_instr(urhadd)
58478)]
58479#[cfg_attr(
58480    not(target_arch = "arm"),
58481    stable(feature = "neon_intrinsics", since = "1.59.0")
58482)]
58483#[cfg_attr(
58484    target_arch = "arm",
58485    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58486)]
58487pub fn vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
58488    unsafe extern "unadjusted" {
58489        #[cfg_attr(
58490            any(target_arch = "aarch64", target_arch = "arm64ec"),
58491            link_name = "llvm.aarch64.neon.urhadd.v16i8"
58492        )]
58493        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v16i8")]
58494        fn _vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
58495    }
58496    unsafe { _vrhaddq_u8(a, b) }
58497}
58498#[doc = "Rounding halving add"]
58499#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u16)"]
58500#[inline]
58501#[target_feature(enable = "neon")]
58502#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58503#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))]
58504#[cfg_attr(
58505    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58506    assert_instr(urhadd)
58507)]
58508#[cfg_attr(
58509    not(target_arch = "arm"),
58510    stable(feature = "neon_intrinsics", since = "1.59.0")
58511)]
58512#[cfg_attr(
58513    target_arch = "arm",
58514    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58515)]
58516pub fn vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
58517    unsafe extern "unadjusted" {
58518        #[cfg_attr(
58519            any(target_arch = "aarch64", target_arch = "arm64ec"),
58520            link_name = "llvm.aarch64.neon.urhadd.v4i16"
58521        )]
58522        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v4i16")]
58523        fn _vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
58524    }
58525    unsafe { _vrhadd_u16(a, b) }
58526}
58527#[doc = "Rounding halving add"]
58528#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u16)"]
58529#[inline]
58530#[target_feature(enable = "neon")]
58531#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58532#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))]
58533#[cfg_attr(
58534    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58535    assert_instr(urhadd)
58536)]
58537#[cfg_attr(
58538    not(target_arch = "arm"),
58539    stable(feature = "neon_intrinsics", since = "1.59.0")
58540)]
58541#[cfg_attr(
58542    target_arch = "arm",
58543    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58544)]
58545pub fn vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
58546    unsafe extern "unadjusted" {
58547        #[cfg_attr(
58548            any(target_arch = "aarch64", target_arch = "arm64ec"),
58549            link_name = "llvm.aarch64.neon.urhadd.v8i16"
58550        )]
58551        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v8i16")]
58552        fn _vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
58553    }
58554    unsafe { _vrhaddq_u16(a, b) }
58555}
58556#[doc = "Rounding halving add"]
58557#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u32)"]
58558#[inline]
58559#[target_feature(enable = "neon")]
58560#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58561#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))]
58562#[cfg_attr(
58563    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58564    assert_instr(urhadd)
58565)]
58566#[cfg_attr(
58567    not(target_arch = "arm"),
58568    stable(feature = "neon_intrinsics", since = "1.59.0")
58569)]
58570#[cfg_attr(
58571    target_arch = "arm",
58572    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58573)]
58574pub fn vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
58575    unsafe extern "unadjusted" {
58576        #[cfg_attr(
58577            any(target_arch = "aarch64", target_arch = "arm64ec"),
58578            link_name = "llvm.aarch64.neon.urhadd.v2i32"
58579        )]
58580        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v2i32")]
58581        fn _vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
58582    }
58583    unsafe { _vrhadd_u32(a, b) }
58584}
58585#[doc = "Rounding halving add"]
58586#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u32)"]
58587#[inline]
58588#[target_feature(enable = "neon")]
58589#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58590#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))]
58591#[cfg_attr(
58592    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58593    assert_instr(urhadd)
58594)]
58595#[cfg_attr(
58596    not(target_arch = "arm"),
58597    stable(feature = "neon_intrinsics", since = "1.59.0")
58598)]
58599#[cfg_attr(
58600    target_arch = "arm",
58601    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58602)]
58603pub fn vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
58604    unsafe extern "unadjusted" {
58605        #[cfg_attr(
58606            any(target_arch = "aarch64", target_arch = "arm64ec"),
58607            link_name = "llvm.aarch64.neon.urhadd.v4i32"
58608        )]
58609        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v4i32")]
58610        fn _vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
58611    }
58612    unsafe { _vrhaddq_u32(a, b) }
58613}
58614#[doc = "Floating-point round to integral, to nearest with ties to even"]
58615#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f16)"]
58616#[inline]
58617#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
58618#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
58619#[cfg_attr(
58620    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58621    assert_instr(frintn)
58622)]
58623#[target_feature(enable = "neon,fp16")]
58624#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
58625pub fn vrndn_f16(a: float16x4_t) -> float16x4_t {
58626    unsafe extern "unadjusted" {
58627        #[cfg_attr(
58628            any(target_arch = "aarch64", target_arch = "arm64ec"),
58629            link_name = "llvm.roundeven.v4f16"
58630        )]
58631        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v4f16")]
58632        fn _vrndn_f16(a: float16x4_t) -> float16x4_t;
58633    }
58634    unsafe { _vrndn_f16(a) }
58635}
58636#[doc = "Floating-point round to integral, to nearest with ties to even"]
58637#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f16)"]
58638#[inline]
58639#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
58640#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
58641#[cfg_attr(
58642    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58643    assert_instr(frintn)
58644)]
58645#[target_feature(enable = "neon,fp16")]
58646#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
58647pub fn vrndnq_f16(a: float16x8_t) -> float16x8_t {
58648    unsafe extern "unadjusted" {
58649        #[cfg_attr(
58650            any(target_arch = "aarch64", target_arch = "arm64ec"),
58651            link_name = "llvm.roundeven.v8f16"
58652        )]
58653        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v8f16")]
58654        fn _vrndnq_f16(a: float16x8_t) -> float16x8_t;
58655    }
58656    unsafe { _vrndnq_f16(a) }
58657}
58658#[doc = "Floating-point round to integral, to nearest with ties to even"]
58659#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f32)"]
58660#[inline]
58661#[target_feature(enable = "neon")]
58662#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
58663#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
58664#[cfg_attr(
58665    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58666    assert_instr(frintn)
58667)]
58668#[cfg_attr(
58669    not(target_arch = "arm"),
58670    stable(feature = "neon_intrinsics", since = "1.59.0")
58671)]
58672#[cfg_attr(
58673    target_arch = "arm",
58674    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58675)]
58676pub fn vrndn_f32(a: float32x2_t) -> float32x2_t {
58677    unsafe extern "unadjusted" {
58678        #[cfg_attr(
58679            any(target_arch = "aarch64", target_arch = "arm64ec"),
58680            link_name = "llvm.roundeven.v2f32"
58681        )]
58682        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v2f32")]
58683        fn _vrndn_f32(a: float32x2_t) -> float32x2_t;
58684    }
58685    unsafe { _vrndn_f32(a) }
58686}
58687#[doc = "Floating-point round to integral, to nearest with ties to even"]
58688#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f32)"]
58689#[inline]
58690#[target_feature(enable = "neon")]
58691#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
58692#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
58693#[cfg_attr(
58694    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58695    assert_instr(frintn)
58696)]
58697#[cfg_attr(
58698    not(target_arch = "arm"),
58699    stable(feature = "neon_intrinsics", since = "1.59.0")
58700)]
58701#[cfg_attr(
58702    target_arch = "arm",
58703    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58704)]
58705pub fn vrndnq_f32(a: float32x4_t) -> float32x4_t {
58706    unsafe extern "unadjusted" {
58707        #[cfg_attr(
58708            any(target_arch = "aarch64", target_arch = "arm64ec"),
58709            link_name = "llvm.roundeven.v4f32"
58710        )]
58711        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v4f32")]
58712        fn _vrndnq_f32(a: float32x4_t) -> float32x4_t;
58713    }
58714    unsafe { _vrndnq_f32(a) }
58715}
58716#[doc = "Signed rounding shift left"]
58717#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s8)"]
58718#[inline]
58719#[target_feature(enable = "neon")]
58720#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58721#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58722#[cfg_attr(
58723    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58724    assert_instr(srshl)
58725)]
58726#[cfg_attr(
58727    not(target_arch = "arm"),
58728    stable(feature = "neon_intrinsics", since = "1.59.0")
58729)]
58730#[cfg_attr(
58731    target_arch = "arm",
58732    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58733)]
58734pub fn vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
58735    unsafe extern "unadjusted" {
58736        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v8i8")]
58737        #[cfg_attr(
58738            any(target_arch = "aarch64", target_arch = "arm64ec"),
58739            link_name = "llvm.aarch64.neon.srshl.v8i8"
58740        )]
58741        fn _vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
58742    }
58743    unsafe { _vrshl_s8(a, b) }
58744}
58745#[doc = "Signed rounding shift left"]
58746#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s8)"]
58747#[inline]
58748#[target_feature(enable = "neon")]
58749#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58750#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58751#[cfg_attr(
58752    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58753    assert_instr(srshl)
58754)]
58755#[cfg_attr(
58756    not(target_arch = "arm"),
58757    stable(feature = "neon_intrinsics", since = "1.59.0")
58758)]
58759#[cfg_attr(
58760    target_arch = "arm",
58761    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58762)]
58763pub fn vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
58764    unsafe extern "unadjusted" {
58765        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v16i8")]
58766        #[cfg_attr(
58767            any(target_arch = "aarch64", target_arch = "arm64ec"),
58768            link_name = "llvm.aarch64.neon.srshl.v16i8"
58769        )]
58770        fn _vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
58771    }
58772    unsafe { _vrshlq_s8(a, b) }
58773}
58774#[doc = "Signed rounding shift left"]
58775#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s16)"]
58776#[inline]
58777#[target_feature(enable = "neon")]
58778#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58779#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58780#[cfg_attr(
58781    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58782    assert_instr(srshl)
58783)]
58784#[cfg_attr(
58785    not(target_arch = "arm"),
58786    stable(feature = "neon_intrinsics", since = "1.59.0")
58787)]
58788#[cfg_attr(
58789    target_arch = "arm",
58790    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58791)]
58792pub fn vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
58793    unsafe extern "unadjusted" {
58794        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v4i16")]
58795        #[cfg_attr(
58796            any(target_arch = "aarch64", target_arch = "arm64ec"),
58797            link_name = "llvm.aarch64.neon.srshl.v4i16"
58798        )]
58799        fn _vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
58800    }
58801    unsafe { _vrshl_s16(a, b) }
58802}
58803#[doc = "Signed rounding shift left"]
58804#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s16)"]
58805#[inline]
58806#[target_feature(enable = "neon")]
58807#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58808#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58809#[cfg_attr(
58810    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58811    assert_instr(srshl)
58812)]
58813#[cfg_attr(
58814    not(target_arch = "arm"),
58815    stable(feature = "neon_intrinsics", since = "1.59.0")
58816)]
58817#[cfg_attr(
58818    target_arch = "arm",
58819    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58820)]
58821pub fn vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
58822    unsafe extern "unadjusted" {
58823        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v8i16")]
58824        #[cfg_attr(
58825            any(target_arch = "aarch64", target_arch = "arm64ec"),
58826            link_name = "llvm.aarch64.neon.srshl.v8i16"
58827        )]
58828        fn _vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
58829    }
58830    unsafe { _vrshlq_s16(a, b) }
58831}
58832#[doc = "Signed rounding shift left"]
58833#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s32)"]
58834#[inline]
58835#[target_feature(enable = "neon")]
58836#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58837#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58838#[cfg_attr(
58839    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58840    assert_instr(srshl)
58841)]
58842#[cfg_attr(
58843    not(target_arch = "arm"),
58844    stable(feature = "neon_intrinsics", since = "1.59.0")
58845)]
58846#[cfg_attr(
58847    target_arch = "arm",
58848    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58849)]
58850pub fn vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
58851    unsafe extern "unadjusted" {
58852        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v2i32")]
58853        #[cfg_attr(
58854            any(target_arch = "aarch64", target_arch = "arm64ec"),
58855            link_name = "llvm.aarch64.neon.srshl.v2i32"
58856        )]
58857        fn _vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
58858    }
58859    unsafe { _vrshl_s32(a, b) }
58860}
58861#[doc = "Signed rounding shift left"]
58862#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s32)"]
58863#[inline]
58864#[target_feature(enable = "neon")]
58865#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58866#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58867#[cfg_attr(
58868    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58869    assert_instr(srshl)
58870)]
58871#[cfg_attr(
58872    not(target_arch = "arm"),
58873    stable(feature = "neon_intrinsics", since = "1.59.0")
58874)]
58875#[cfg_attr(
58876    target_arch = "arm",
58877    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58878)]
58879pub fn vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
58880    unsafe extern "unadjusted" {
58881        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v4i32")]
58882        #[cfg_attr(
58883            any(target_arch = "aarch64", target_arch = "arm64ec"),
58884            link_name = "llvm.aarch64.neon.srshl.v4i32"
58885        )]
58886        fn _vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
58887    }
58888    unsafe { _vrshlq_s32(a, b) }
58889}
58890#[doc = "Signed rounding shift left"]
58891#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s64)"]
58892#[inline]
58893#[target_feature(enable = "neon")]
58894#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58895#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58896#[cfg_attr(
58897    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58898    assert_instr(srshl)
58899)]
58900#[cfg_attr(
58901    not(target_arch = "arm"),
58902    stable(feature = "neon_intrinsics", since = "1.59.0")
58903)]
58904#[cfg_attr(
58905    target_arch = "arm",
58906    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58907)]
58908pub fn vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
58909    unsafe extern "unadjusted" {
58910        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v1i64")]
58911        #[cfg_attr(
58912            any(target_arch = "aarch64", target_arch = "arm64ec"),
58913            link_name = "llvm.aarch64.neon.srshl.v1i64"
58914        )]
58915        fn _vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
58916    }
58917    unsafe { _vrshl_s64(a, b) }
58918}
58919#[doc = "Signed rounding shift left"]
58920#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s64)"]
58921#[inline]
58922#[target_feature(enable = "neon")]
58923#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58924#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58925#[cfg_attr(
58926    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58927    assert_instr(srshl)
58928)]
58929#[cfg_attr(
58930    not(target_arch = "arm"),
58931    stable(feature = "neon_intrinsics", since = "1.59.0")
58932)]
58933#[cfg_attr(
58934    target_arch = "arm",
58935    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58936)]
58937pub fn vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
58938    unsafe extern "unadjusted" {
58939        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v2i64")]
58940        #[cfg_attr(
58941            any(target_arch = "aarch64", target_arch = "arm64ec"),
58942            link_name = "llvm.aarch64.neon.srshl.v2i64"
58943        )]
58944        fn _vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
58945    }
58946    unsafe { _vrshlq_s64(a, b) }
58947}
58948#[doc = "Unsigned rounding shift left"]
58949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u8)"]
58950#[inline]
58951#[target_feature(enable = "neon")]
58952#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58953#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58954#[cfg_attr(
58955    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58956    assert_instr(urshl)
58957)]
58958#[cfg_attr(
58959    not(target_arch = "arm"),
58960    stable(feature = "neon_intrinsics", since = "1.59.0")
58961)]
58962#[cfg_attr(
58963    target_arch = "arm",
58964    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58965)]
58966pub fn vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
58967    unsafe extern "unadjusted" {
58968        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v8i8")]
58969        #[cfg_attr(
58970            any(target_arch = "aarch64", target_arch = "arm64ec"),
58971            link_name = "llvm.aarch64.neon.urshl.v8i8"
58972        )]
58973        fn _vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t;
58974    }
58975    unsafe { _vrshl_u8(a, b) }
58976}
58977#[doc = "Unsigned rounding shift left"]
58978#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u8)"]
58979#[inline]
58980#[target_feature(enable = "neon")]
58981#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58982#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58983#[cfg_attr(
58984    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58985    assert_instr(urshl)
58986)]
58987#[cfg_attr(
58988    not(target_arch = "arm"),
58989    stable(feature = "neon_intrinsics", since = "1.59.0")
58990)]
58991#[cfg_attr(
58992    target_arch = "arm",
58993    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58994)]
58995pub fn vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
58996    unsafe extern "unadjusted" {
58997        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v16i8")]
58998        #[cfg_attr(
58999            any(target_arch = "aarch64", target_arch = "arm64ec"),
59000            link_name = "llvm.aarch64.neon.urshl.v16i8"
59001        )]
59002        fn _vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t;
59003    }
59004    unsafe { _vrshlq_u8(a, b) }
59005}
59006#[doc = "Unsigned rounding shift left"]
59007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u16)"]
59008#[inline]
59009#[target_feature(enable = "neon")]
59010#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59011#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
59012#[cfg_attr(
59013    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59014    assert_instr(urshl)
59015)]
59016#[cfg_attr(
59017    not(target_arch = "arm"),
59018    stable(feature = "neon_intrinsics", since = "1.59.0")
59019)]
59020#[cfg_attr(
59021    target_arch = "arm",
59022    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59023)]
59024pub fn vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
59025    unsafe extern "unadjusted" {
59026        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v4i16")]
59027        #[cfg_attr(
59028            any(target_arch = "aarch64", target_arch = "arm64ec"),
59029            link_name = "llvm.aarch64.neon.urshl.v4i16"
59030        )]
59031        fn _vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t;
59032    }
59033    unsafe { _vrshl_u16(a, b) }
59034}
59035#[doc = "Unsigned rounding shift left"]
59036#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u16)"]
59037#[inline]
59038#[target_feature(enable = "neon")]
59039#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59040#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
59041#[cfg_attr(
59042    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59043    assert_instr(urshl)
59044)]
59045#[cfg_attr(
59046    not(target_arch = "arm"),
59047    stable(feature = "neon_intrinsics", since = "1.59.0")
59048)]
59049#[cfg_attr(
59050    target_arch = "arm",
59051    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59052)]
59053pub fn vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
59054    unsafe extern "unadjusted" {
59055        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v8i16")]
59056        #[cfg_attr(
59057            any(target_arch = "aarch64", target_arch = "arm64ec"),
59058            link_name = "llvm.aarch64.neon.urshl.v8i16"
59059        )]
59060        fn _vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t;
59061    }
59062    unsafe { _vrshlq_u16(a, b) }
59063}
59064#[doc = "Unsigned rounding shift left"]
59065#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u32)"]
59066#[inline]
59067#[target_feature(enable = "neon")]
59068#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59069#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
59070#[cfg_attr(
59071    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59072    assert_instr(urshl)
59073)]
59074#[cfg_attr(
59075    not(target_arch = "arm"),
59076    stable(feature = "neon_intrinsics", since = "1.59.0")
59077)]
59078#[cfg_attr(
59079    target_arch = "arm",
59080    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59081)]
59082pub fn vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
59083    unsafe extern "unadjusted" {
59084        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v2i32")]
59085        #[cfg_attr(
59086            any(target_arch = "aarch64", target_arch = "arm64ec"),
59087            link_name = "llvm.aarch64.neon.urshl.v2i32"
59088        )]
59089        fn _vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t;
59090    }
59091    unsafe { _vrshl_u32(a, b) }
59092}
59093#[doc = "Unsigned rounding shift left"]
59094#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u32)"]
59095#[inline]
59096#[target_feature(enable = "neon")]
59097#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59098#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
59099#[cfg_attr(
59100    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59101    assert_instr(urshl)
59102)]
59103#[cfg_attr(
59104    not(target_arch = "arm"),
59105    stable(feature = "neon_intrinsics", since = "1.59.0")
59106)]
59107#[cfg_attr(
59108    target_arch = "arm",
59109    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59110)]
59111pub fn vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
59112    unsafe extern "unadjusted" {
59113        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v4i32")]
59114        #[cfg_attr(
59115            any(target_arch = "aarch64", target_arch = "arm64ec"),
59116            link_name = "llvm.aarch64.neon.urshl.v4i32"
59117        )]
59118        fn _vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t;
59119    }
59120    unsafe { _vrshlq_u32(a, b) }
59121}
59122#[doc = "Unsigned rounding shift left"]
59123#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u64)"]
59124#[inline]
59125#[target_feature(enable = "neon")]
59126#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59127#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
59128#[cfg_attr(
59129    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59130    assert_instr(urshl)
59131)]
59132#[cfg_attr(
59133    not(target_arch = "arm"),
59134    stable(feature = "neon_intrinsics", since = "1.59.0")
59135)]
59136#[cfg_attr(
59137    target_arch = "arm",
59138    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59139)]
59140pub fn vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
59141    unsafe extern "unadjusted" {
59142        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v1i64")]
59143        #[cfg_attr(
59144            any(target_arch = "aarch64", target_arch = "arm64ec"),
59145            link_name = "llvm.aarch64.neon.urshl.v1i64"
59146        )]
59147        fn _vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t;
59148    }
59149    unsafe { _vrshl_u64(a, b) }
59150}
59151#[doc = "Unsigned rounding shift left"]
59152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u64)"]
59153#[inline]
59154#[target_feature(enable = "neon")]
59155#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59156#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
59157#[cfg_attr(
59158    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59159    assert_instr(urshl)
59160)]
59161#[cfg_attr(
59162    not(target_arch = "arm"),
59163    stable(feature = "neon_intrinsics", since = "1.59.0")
59164)]
59165#[cfg_attr(
59166    target_arch = "arm",
59167    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59168)]
59169pub fn vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
59170    unsafe extern "unadjusted" {
59171        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v2i64")]
59172        #[cfg_attr(
59173            any(target_arch = "aarch64", target_arch = "arm64ec"),
59174            link_name = "llvm.aarch64.neon.urshl.v2i64"
59175        )]
59176        fn _vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t;
59177    }
59178    unsafe { _vrshlq_u64(a, b) }
59179}
59180#[doc = "Signed rounding shift right"]
59181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s8)"]
59182#[inline]
59183#[target_feature(enable = "neon")]
59184#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59185#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59186#[cfg_attr(
59187    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59188    assert_instr(srshr, N = 2)
59189)]
59190#[rustc_legacy_const_generics(1)]
59191#[cfg_attr(
59192    not(target_arch = "arm"),
59193    stable(feature = "neon_intrinsics", since = "1.59.0")
59194)]
59195#[cfg_attr(
59196    target_arch = "arm",
59197    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59198)]
59199pub fn vrshr_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
59200    static_assert!(N >= 1 && N <= 8);
59201    vrshl_s8(a, vdup_n_s8(-N as _))
59202}
59203#[doc = "Signed rounding shift right"]
59204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s8)"]
59205#[inline]
59206#[target_feature(enable = "neon")]
59207#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59208#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59209#[cfg_attr(
59210    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59211    assert_instr(srshr, N = 2)
59212)]
59213#[rustc_legacy_const_generics(1)]
59214#[cfg_attr(
59215    not(target_arch = "arm"),
59216    stable(feature = "neon_intrinsics", since = "1.59.0")
59217)]
59218#[cfg_attr(
59219    target_arch = "arm",
59220    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59221)]
59222pub fn vrshrq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
59223    static_assert!(N >= 1 && N <= 8);
59224    vrshlq_s8(a, vdupq_n_s8(-N as _))
59225}
59226#[doc = "Signed rounding shift right"]
59227#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s16)"]
59228#[inline]
59229#[target_feature(enable = "neon")]
59230#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59231#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59232#[cfg_attr(
59233    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59234    assert_instr(srshr, N = 2)
59235)]
59236#[rustc_legacy_const_generics(1)]
59237#[cfg_attr(
59238    not(target_arch = "arm"),
59239    stable(feature = "neon_intrinsics", since = "1.59.0")
59240)]
59241#[cfg_attr(
59242    target_arch = "arm",
59243    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59244)]
59245pub fn vrshr_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
59246    static_assert!(N >= 1 && N <= 16);
59247    vrshl_s16(a, vdup_n_s16(-N as _))
59248}
59249#[doc = "Signed rounding shift right"]
59250#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s16)"]
59251#[inline]
59252#[target_feature(enable = "neon")]
59253#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59254#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59255#[cfg_attr(
59256    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59257    assert_instr(srshr, N = 2)
59258)]
59259#[rustc_legacy_const_generics(1)]
59260#[cfg_attr(
59261    not(target_arch = "arm"),
59262    stable(feature = "neon_intrinsics", since = "1.59.0")
59263)]
59264#[cfg_attr(
59265    target_arch = "arm",
59266    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59267)]
59268pub fn vrshrq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
59269    static_assert!(N >= 1 && N <= 16);
59270    vrshlq_s16(a, vdupq_n_s16(-N as _))
59271}
59272#[doc = "Signed rounding shift right"]
59273#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s32)"]
59274#[inline]
59275#[target_feature(enable = "neon")]
59276#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59277#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59278#[cfg_attr(
59279    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59280    assert_instr(srshr, N = 2)
59281)]
59282#[rustc_legacy_const_generics(1)]
59283#[cfg_attr(
59284    not(target_arch = "arm"),
59285    stable(feature = "neon_intrinsics", since = "1.59.0")
59286)]
59287#[cfg_attr(
59288    target_arch = "arm",
59289    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59290)]
59291pub fn vrshr_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
59292    static_assert!(N >= 1 && N <= 32);
59293    vrshl_s32(a, vdup_n_s32(-N as _))
59294}
59295#[doc = "Signed rounding shift right"]
59296#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s32)"]
59297#[inline]
59298#[target_feature(enable = "neon")]
59299#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59300#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59301#[cfg_attr(
59302    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59303    assert_instr(srshr, N = 2)
59304)]
59305#[rustc_legacy_const_generics(1)]
59306#[cfg_attr(
59307    not(target_arch = "arm"),
59308    stable(feature = "neon_intrinsics", since = "1.59.0")
59309)]
59310#[cfg_attr(
59311    target_arch = "arm",
59312    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59313)]
59314pub fn vrshrq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
59315    static_assert!(N >= 1 && N <= 32);
59316    vrshlq_s32(a, vdupq_n_s32(-N as _))
59317}
59318#[doc = "Signed rounding shift right"]
59319#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s64)"]
59320#[inline]
59321#[target_feature(enable = "neon")]
59322#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59323#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59324#[cfg_attr(
59325    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59326    assert_instr(srshr, N = 2)
59327)]
59328#[rustc_legacy_const_generics(1)]
59329#[cfg_attr(
59330    not(target_arch = "arm"),
59331    stable(feature = "neon_intrinsics", since = "1.59.0")
59332)]
59333#[cfg_attr(
59334    target_arch = "arm",
59335    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59336)]
59337pub fn vrshr_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
59338    static_assert!(N >= 1 && N <= 64);
59339    vrshl_s64(a, vdup_n_s64(-N as _))
59340}
59341#[doc = "Signed rounding shift right"]
59342#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s64)"]
59343#[inline]
59344#[target_feature(enable = "neon")]
59345#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59346#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59347#[cfg_attr(
59348    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59349    assert_instr(srshr, N = 2)
59350)]
59351#[rustc_legacy_const_generics(1)]
59352#[cfg_attr(
59353    not(target_arch = "arm"),
59354    stable(feature = "neon_intrinsics", since = "1.59.0")
59355)]
59356#[cfg_attr(
59357    target_arch = "arm",
59358    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59359)]
59360pub fn vrshrq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
59361    static_assert!(N >= 1 && N <= 64);
59362    vrshlq_s64(a, vdupq_n_s64(-N as _))
59363}
59364#[doc = "Unsigned rounding shift right"]
59365#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u8)"]
59366#[inline]
59367#[target_feature(enable = "neon")]
59368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59369#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59370#[cfg_attr(
59371    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59372    assert_instr(urshr, N = 2)
59373)]
59374#[rustc_legacy_const_generics(1)]
59375#[cfg_attr(
59376    not(target_arch = "arm"),
59377    stable(feature = "neon_intrinsics", since = "1.59.0")
59378)]
59379#[cfg_attr(
59380    target_arch = "arm",
59381    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59382)]
59383pub fn vrshr_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
59384    static_assert!(N >= 1 && N <= 8);
59385    vrshl_u8(a, vdup_n_s8(-N as _))
59386}
59387#[doc = "Unsigned rounding shift right"]
59388#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u8)"]
59389#[inline]
59390#[target_feature(enable = "neon")]
59391#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59392#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59393#[cfg_attr(
59394    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59395    assert_instr(urshr, N = 2)
59396)]
59397#[rustc_legacy_const_generics(1)]
59398#[cfg_attr(
59399    not(target_arch = "arm"),
59400    stable(feature = "neon_intrinsics", since = "1.59.0")
59401)]
59402#[cfg_attr(
59403    target_arch = "arm",
59404    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59405)]
59406pub fn vrshrq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
59407    static_assert!(N >= 1 && N <= 8);
59408    vrshlq_u8(a, vdupq_n_s8(-N as _))
59409}
59410#[doc = "Unsigned rounding shift right"]
59411#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u16)"]
59412#[inline]
59413#[target_feature(enable = "neon")]
59414#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59415#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59416#[cfg_attr(
59417    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59418    assert_instr(urshr, N = 2)
59419)]
59420#[rustc_legacy_const_generics(1)]
59421#[cfg_attr(
59422    not(target_arch = "arm"),
59423    stable(feature = "neon_intrinsics", since = "1.59.0")
59424)]
59425#[cfg_attr(
59426    target_arch = "arm",
59427    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59428)]
59429pub fn vrshr_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
59430    static_assert!(N >= 1 && N <= 16);
59431    vrshl_u16(a, vdup_n_s16(-N as _))
59432}
59433#[doc = "Unsigned rounding shift right"]
59434#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u16)"]
59435#[inline]
59436#[target_feature(enable = "neon")]
59437#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59438#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59439#[cfg_attr(
59440    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59441    assert_instr(urshr, N = 2)
59442)]
59443#[rustc_legacy_const_generics(1)]
59444#[cfg_attr(
59445    not(target_arch = "arm"),
59446    stable(feature = "neon_intrinsics", since = "1.59.0")
59447)]
59448#[cfg_attr(
59449    target_arch = "arm",
59450    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59451)]
59452pub fn vrshrq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
59453    static_assert!(N >= 1 && N <= 16);
59454    vrshlq_u16(a, vdupq_n_s16(-N as _))
59455}
59456#[doc = "Unsigned rounding shift right"]
59457#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u32)"]
59458#[inline]
59459#[target_feature(enable = "neon")]
59460#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59461#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59462#[cfg_attr(
59463    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59464    assert_instr(urshr, N = 2)
59465)]
59466#[rustc_legacy_const_generics(1)]
59467#[cfg_attr(
59468    not(target_arch = "arm"),
59469    stable(feature = "neon_intrinsics", since = "1.59.0")
59470)]
59471#[cfg_attr(
59472    target_arch = "arm",
59473    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59474)]
59475pub fn vrshr_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
59476    static_assert!(N >= 1 && N <= 32);
59477    vrshl_u32(a, vdup_n_s32(-N as _))
59478}
59479#[doc = "Unsigned rounding shift right"]
59480#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u32)"]
59481#[inline]
59482#[target_feature(enable = "neon")]
59483#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59484#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59485#[cfg_attr(
59486    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59487    assert_instr(urshr, N = 2)
59488)]
59489#[rustc_legacy_const_generics(1)]
59490#[cfg_attr(
59491    not(target_arch = "arm"),
59492    stable(feature = "neon_intrinsics", since = "1.59.0")
59493)]
59494#[cfg_attr(
59495    target_arch = "arm",
59496    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59497)]
59498pub fn vrshrq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
59499    static_assert!(N >= 1 && N <= 32);
59500    vrshlq_u32(a, vdupq_n_s32(-N as _))
59501}
59502#[doc = "Unsigned rounding shift right"]
59503#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u64)"]
59504#[inline]
59505#[target_feature(enable = "neon")]
59506#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59507#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59508#[cfg_attr(
59509    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59510    assert_instr(urshr, N = 2)
59511)]
59512#[rustc_legacy_const_generics(1)]
59513#[cfg_attr(
59514    not(target_arch = "arm"),
59515    stable(feature = "neon_intrinsics", since = "1.59.0")
59516)]
59517#[cfg_attr(
59518    target_arch = "arm",
59519    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59520)]
59521pub fn vrshr_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
59522    static_assert!(N >= 1 && N <= 64);
59523    vrshl_u64(a, vdup_n_s64(-N as _))
59524}
59525#[doc = "Unsigned rounding shift right"]
59526#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u64)"]
59527#[inline]
59528#[target_feature(enable = "neon")]
59529#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59530#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59531#[cfg_attr(
59532    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59533    assert_instr(urshr, N = 2)
59534)]
59535#[rustc_legacy_const_generics(1)]
59536#[cfg_attr(
59537    not(target_arch = "arm"),
59538    stable(feature = "neon_intrinsics", since = "1.59.0")
59539)]
59540#[cfg_attr(
59541    target_arch = "arm",
59542    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59543)]
59544pub fn vrshrq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
59545    static_assert!(N >= 1 && N <= 64);
59546    vrshlq_u64(a, vdupq_n_s64(-N as _))
59547}
59548#[doc = "Rounding shift right narrow"]
59549#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"]
59550#[inline]
59551#[cfg(target_arch = "arm")]
59552#[target_feature(enable = "neon,v7")]
59553#[cfg_attr(test, assert_instr(vrshrn, N = 2))]
59554#[rustc_legacy_const_generics(1)]
59555#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59556pub fn vrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
59557    static_assert!(N >= 1 && N <= 8);
59558    unsafe extern "unadjusted" {
59559        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v8i8")]
59560        fn _vrshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t;
59561    }
59562    unsafe {
59563        _vrshrn_n_s16(
59564            a,
59565            const {
59566                int16x8_t([
59567                    -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
59568                    -N as i16,
59569                ])
59570            },
59571        )
59572    }
59573}
59574#[doc = "Rounding shift right narrow"]
59575#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"]
59576#[inline]
59577#[cfg(target_arch = "arm")]
59578#[target_feature(enable = "neon,v7")]
59579#[cfg_attr(test, assert_instr(vrshrn, N = 2))]
59580#[rustc_legacy_const_generics(1)]
59581#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59582pub fn vrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
59583    static_assert!(N >= 1 && N <= 16);
59584    unsafe extern "unadjusted" {
59585        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v4i16")]
59586        fn _vrshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t;
59587    }
59588    unsafe {
59589        _vrshrn_n_s32(
59590            a,
59591            const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
59592        )
59593    }
59594}
59595#[doc = "Rounding shift right narrow"]
59596#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"]
59597#[inline]
59598#[cfg(target_arch = "arm")]
59599#[target_feature(enable = "neon,v7")]
59600#[cfg_attr(test, assert_instr(vrshrn, N = 2))]
59601#[rustc_legacy_const_generics(1)]
59602#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59603pub fn vrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
59604    static_assert!(N >= 1 && N <= 32);
59605    unsafe extern "unadjusted" {
59606        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v2i32")]
59607        fn _vrshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t;
59608    }
59609    unsafe { _vrshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
59610}
59611#[doc = "Rounding shift right narrow"]
59612#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"]
59613#[inline]
59614#[target_feature(enable = "neon")]
59615#[cfg(not(target_arch = "arm"))]
59616#[cfg_attr(test, assert_instr(rshrn, N = 2))]
59617#[rustc_legacy_const_generics(1)]
59618#[stable(feature = "neon_intrinsics", since = "1.59.0")]
59619pub fn vrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
59620    static_assert!(N >= 1 && N <= 8);
59621    unsafe extern "unadjusted" {
59622        #[cfg_attr(
59623            any(target_arch = "aarch64", target_arch = "arm64ec"),
59624            link_name = "llvm.aarch64.neon.rshrn.v8i8"
59625        )]
59626        fn _vrshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t;
59627    }
59628    unsafe { _vrshrn_n_s16(a, N) }
59629}
59630#[doc = "Rounding shift right narrow"]
59631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"]
59632#[inline]
59633#[target_feature(enable = "neon")]
59634#[cfg(not(target_arch = "arm"))]
59635#[cfg_attr(test, assert_instr(rshrn, N = 2))]
59636#[rustc_legacy_const_generics(1)]
59637#[stable(feature = "neon_intrinsics", since = "1.59.0")]
59638pub fn vrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
59639    static_assert!(N >= 1 && N <= 16);
59640    unsafe extern "unadjusted" {
59641        #[cfg_attr(
59642            any(target_arch = "aarch64", target_arch = "arm64ec"),
59643            link_name = "llvm.aarch64.neon.rshrn.v4i16"
59644        )]
59645        fn _vrshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t;
59646    }
59647    unsafe { _vrshrn_n_s32(a, N) }
59648}
59649#[doc = "Rounding shift right narrow"]
59650#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"]
59651#[inline]
59652#[target_feature(enable = "neon")]
59653#[cfg(not(target_arch = "arm"))]
59654#[cfg_attr(test, assert_instr(rshrn, N = 2))]
59655#[rustc_legacy_const_generics(1)]
59656#[stable(feature = "neon_intrinsics", since = "1.59.0")]
59657pub fn vrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
59658    static_assert!(N >= 1 && N <= 32);
59659    unsafe extern "unadjusted" {
59660        #[cfg_attr(
59661            any(target_arch = "aarch64", target_arch = "arm64ec"),
59662            link_name = "llvm.aarch64.neon.rshrn.v2i32"
59663        )]
59664        fn _vrshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t;
59665    }
59666    unsafe { _vrshrn_n_s64(a, N) }
59667}
59668#[doc = "Rounding shift right narrow"]
59669#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u16)"]
59670#[inline]
59671#[target_feature(enable = "neon")]
59672#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59673#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
59674#[cfg_attr(
59675    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59676    assert_instr(rshrn, N = 2)
59677)]
59678#[rustc_legacy_const_generics(1)]
59679#[cfg_attr(
59680    not(target_arch = "arm"),
59681    stable(feature = "neon_intrinsics", since = "1.59.0")
59682)]
59683#[cfg_attr(
59684    target_arch = "arm",
59685    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59686)]
59687pub fn vrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
59688    static_assert!(N >= 1 && N <= 8);
59689    unsafe { transmute(vrshrn_n_s16::<N>(transmute(a))) }
59690}
59691#[doc = "Rounding shift right narrow"]
59692#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u32)"]
59693#[inline]
59694#[target_feature(enable = "neon")]
59695#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59696#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
59697#[cfg_attr(
59698    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59699    assert_instr(rshrn, N = 2)
59700)]
59701#[rustc_legacy_const_generics(1)]
59702#[cfg_attr(
59703    not(target_arch = "arm"),
59704    stable(feature = "neon_intrinsics", since = "1.59.0")
59705)]
59706#[cfg_attr(
59707    target_arch = "arm",
59708    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59709)]
59710pub fn vrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
59711    static_assert!(N >= 1 && N <= 16);
59712    unsafe { transmute(vrshrn_n_s32::<N>(transmute(a))) }
59713}
59714#[doc = "Rounding shift right narrow"]
59715#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u64)"]
59716#[inline]
59717#[target_feature(enable = "neon")]
59718#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59719#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
59720#[cfg_attr(
59721    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59722    assert_instr(rshrn, N = 2)
59723)]
59724#[rustc_legacy_const_generics(1)]
59725#[cfg_attr(
59726    not(target_arch = "arm"),
59727    stable(feature = "neon_intrinsics", since = "1.59.0")
59728)]
59729#[cfg_attr(
59730    target_arch = "arm",
59731    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59732)]
59733pub fn vrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
59734    static_assert!(N >= 1 && N <= 32);
59735    unsafe { transmute(vrshrn_n_s64::<N>(transmute(a))) }
59736}
59737#[doc = "Reciprocal square-root estimate."]
59738#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f16)"]
59739#[inline]
59740#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
59741#[target_feature(enable = "neon,fp16")]
59742#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59743#[cfg_attr(
59744    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59745    assert_instr(frsqrte)
59746)]
59747#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
59748pub fn vrsqrte_f16(a: float16x4_t) -> float16x4_t {
59749    unsafe extern "unadjusted" {
59750        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4f16")]
59751        #[cfg_attr(
59752            any(target_arch = "aarch64", target_arch = "arm64ec"),
59753            link_name = "llvm.aarch64.neon.frsqrte.v4f16"
59754        )]
59755        fn _vrsqrte_f16(a: float16x4_t) -> float16x4_t;
59756    }
59757    unsafe { _vrsqrte_f16(a) }
59758}
59759#[doc = "Reciprocal square-root estimate."]
59760#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f16)"]
59761#[inline]
59762#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
59763#[target_feature(enable = "neon,fp16")]
59764#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59765#[cfg_attr(
59766    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59767    assert_instr(frsqrte)
59768)]
59769#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
59770pub fn vrsqrteq_f16(a: float16x8_t) -> float16x8_t {
59771    unsafe extern "unadjusted" {
59772        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v8f16")]
59773        #[cfg_attr(
59774            any(target_arch = "aarch64", target_arch = "arm64ec"),
59775            link_name = "llvm.aarch64.neon.frsqrte.v8f16"
59776        )]
59777        fn _vrsqrteq_f16(a: float16x8_t) -> float16x8_t;
59778    }
59779    unsafe { _vrsqrteq_f16(a) }
59780}
59781#[doc = "Reciprocal square-root estimate."]
59782#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f32)"]
59783#[inline]
59784#[target_feature(enable = "neon")]
59785#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59786#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59787#[cfg_attr(
59788    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59789    assert_instr(frsqrte)
59790)]
59791#[cfg_attr(
59792    not(target_arch = "arm"),
59793    stable(feature = "neon_intrinsics", since = "1.59.0")
59794)]
59795#[cfg_attr(
59796    target_arch = "arm",
59797    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59798)]
59799pub fn vrsqrte_f32(a: float32x2_t) -> float32x2_t {
59800    unsafe extern "unadjusted" {
59801        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v2f32")]
59802        #[cfg_attr(
59803            any(target_arch = "aarch64", target_arch = "arm64ec"),
59804            link_name = "llvm.aarch64.neon.frsqrte.v2f32"
59805        )]
59806        fn _vrsqrte_f32(a: float32x2_t) -> float32x2_t;
59807    }
59808    unsafe { _vrsqrte_f32(a) }
59809}
59810#[doc = "Reciprocal square-root estimate."]
59811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f32)"]
59812#[inline]
59813#[target_feature(enable = "neon")]
59814#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59815#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59816#[cfg_attr(
59817    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59818    assert_instr(frsqrte)
59819)]
59820#[cfg_attr(
59821    not(target_arch = "arm"),
59822    stable(feature = "neon_intrinsics", since = "1.59.0")
59823)]
59824#[cfg_attr(
59825    target_arch = "arm",
59826    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59827)]
59828pub fn vrsqrteq_f32(a: float32x4_t) -> float32x4_t {
59829    unsafe extern "unadjusted" {
59830        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4f32")]
59831        #[cfg_attr(
59832            any(target_arch = "aarch64", target_arch = "arm64ec"),
59833            link_name = "llvm.aarch64.neon.frsqrte.v4f32"
59834        )]
59835        fn _vrsqrteq_f32(a: float32x4_t) -> float32x4_t;
59836    }
59837    unsafe { _vrsqrteq_f32(a) }
59838}
59839#[doc = "Unsigned reciprocal square root estimate"]
59840#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_u32)"]
59841#[inline]
59842#[target_feature(enable = "neon")]
59843#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59844#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59845#[cfg_attr(
59846    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59847    assert_instr(ursqrte)
59848)]
59849#[cfg_attr(
59850    not(target_arch = "arm"),
59851    stable(feature = "neon_intrinsics", since = "1.59.0")
59852)]
59853#[cfg_attr(
59854    target_arch = "arm",
59855    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59856)]
59857pub fn vrsqrte_u32(a: uint32x2_t) -> uint32x2_t {
59858    unsafe extern "unadjusted" {
59859        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v2i32")]
59860        #[cfg_attr(
59861            any(target_arch = "aarch64", target_arch = "arm64ec"),
59862            link_name = "llvm.aarch64.neon.ursqrte.v2i32"
59863        )]
59864        fn _vrsqrte_u32(a: uint32x2_t) -> uint32x2_t;
59865    }
59866    unsafe { _vrsqrte_u32(a) }
59867}
59868#[doc = "Unsigned reciprocal square root estimate"]
59869#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_u32)"]
59870#[inline]
59871#[target_feature(enable = "neon")]
59872#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59873#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59874#[cfg_attr(
59875    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59876    assert_instr(ursqrte)
59877)]
59878#[cfg_attr(
59879    not(target_arch = "arm"),
59880    stable(feature = "neon_intrinsics", since = "1.59.0")
59881)]
59882#[cfg_attr(
59883    target_arch = "arm",
59884    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59885)]
59886pub fn vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t {
59887    unsafe extern "unadjusted" {
59888        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4i32")]
59889        #[cfg_attr(
59890            any(target_arch = "aarch64", target_arch = "arm64ec"),
59891            link_name = "llvm.aarch64.neon.ursqrte.v4i32"
59892        )]
59893        fn _vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t;
59894    }
59895    unsafe { _vrsqrteq_u32(a) }
59896}
59897#[doc = "Floating-point reciprocal square root step"]
59898#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f16)"]
59899#[inline]
59900#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
59901#[target_feature(enable = "neon,fp16")]
59902#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
59903#[cfg_attr(
59904    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59905    assert_instr(frsqrts)
59906)]
59907#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
59908pub fn vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
59909    unsafe extern "unadjusted" {
59910        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v4f16")]
59911        #[cfg_attr(
59912            any(target_arch = "aarch64", target_arch = "arm64ec"),
59913            link_name = "llvm.aarch64.neon.frsqrts.v4f16"
59914        )]
59915        fn _vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
59916    }
59917    unsafe { _vrsqrts_f16(a, b) }
59918}
59919#[doc = "Floating-point reciprocal square root step"]
59920#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f16)"]
59921#[inline]
59922#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
59923#[target_feature(enable = "neon,fp16")]
59924#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
59925#[cfg_attr(
59926    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59927    assert_instr(frsqrts)
59928)]
59929#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
59930pub fn vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
59931    unsafe extern "unadjusted" {
59932        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v8f16")]
59933        #[cfg_attr(
59934            any(target_arch = "aarch64", target_arch = "arm64ec"),
59935            link_name = "llvm.aarch64.neon.frsqrts.v8f16"
59936        )]
59937        fn _vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
59938    }
59939    unsafe { _vrsqrtsq_f16(a, b) }
59940}
59941#[doc = "Floating-point reciprocal square root step"]
59942#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f32)"]
59943#[inline]
59944#[target_feature(enable = "neon")]
59945#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59946#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
59947#[cfg_attr(
59948    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59949    assert_instr(frsqrts)
59950)]
59951#[cfg_attr(
59952    not(target_arch = "arm"),
59953    stable(feature = "neon_intrinsics", since = "1.59.0")
59954)]
59955#[cfg_attr(
59956    target_arch = "arm",
59957    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59958)]
59959pub fn vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
59960    unsafe extern "unadjusted" {
59961        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v2f32")]
59962        #[cfg_attr(
59963            any(target_arch = "aarch64", target_arch = "arm64ec"),
59964            link_name = "llvm.aarch64.neon.frsqrts.v2f32"
59965        )]
59966        fn _vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
59967    }
59968    unsafe { _vrsqrts_f32(a, b) }
59969}
59970#[doc = "Floating-point reciprocal square root step"]
59971#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f32)"]
59972#[inline]
59973#[target_feature(enable = "neon")]
59974#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59975#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
59976#[cfg_attr(
59977    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59978    assert_instr(frsqrts)
59979)]
59980#[cfg_attr(
59981    not(target_arch = "arm"),
59982    stable(feature = "neon_intrinsics", since = "1.59.0")
59983)]
59984#[cfg_attr(
59985    target_arch = "arm",
59986    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59987)]
59988pub fn vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
59989    unsafe extern "unadjusted" {
59990        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v4f32")]
59991        #[cfg_attr(
59992            any(target_arch = "aarch64", target_arch = "arm64ec"),
59993            link_name = "llvm.aarch64.neon.frsqrts.v4f32"
59994        )]
59995        fn _vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
59996    }
59997    unsafe { _vrsqrtsq_f32(a, b) }
59998}
59999#[doc = "Signed rounding shift right and accumulate"]
60000#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s8)"]
60001#[inline]
60002#[target_feature(enable = "neon")]
60003#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60004#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60005#[cfg_attr(
60006    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60007    assert_instr(srsra, N = 2)
60008)]
60009#[rustc_legacy_const_generics(2)]
60010#[cfg_attr(
60011    not(target_arch = "arm"),
60012    stable(feature = "neon_intrinsics", since = "1.59.0")
60013)]
60014#[cfg_attr(
60015    target_arch = "arm",
60016    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60017)]
60018pub fn vrsra_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
60019    static_assert!(N >= 1 && N <= 8);
60020    unsafe { simd_add(a, vrshr_n_s8::<N>(b)) }
60021}
60022#[doc = "Signed rounding shift right and accumulate"]
60023#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s8)"]
60024#[inline]
60025#[target_feature(enable = "neon")]
60026#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60027#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60028#[cfg_attr(
60029    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60030    assert_instr(srsra, N = 2)
60031)]
60032#[rustc_legacy_const_generics(2)]
60033#[cfg_attr(
60034    not(target_arch = "arm"),
60035    stable(feature = "neon_intrinsics", since = "1.59.0")
60036)]
60037#[cfg_attr(
60038    target_arch = "arm",
60039    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60040)]
60041pub fn vrsraq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
60042    static_assert!(N >= 1 && N <= 8);
60043    unsafe { simd_add(a, vrshrq_n_s8::<N>(b)) }
60044}
60045#[doc = "Signed rounding shift right and accumulate"]
60046#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s16)"]
60047#[inline]
60048#[target_feature(enable = "neon")]
60049#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60050#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60051#[cfg_attr(
60052    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60053    assert_instr(srsra, N = 2)
60054)]
60055#[rustc_legacy_const_generics(2)]
60056#[cfg_attr(
60057    not(target_arch = "arm"),
60058    stable(feature = "neon_intrinsics", since = "1.59.0")
60059)]
60060#[cfg_attr(
60061    target_arch = "arm",
60062    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60063)]
60064pub fn vrsra_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
60065    static_assert!(N >= 1 && N <= 16);
60066    unsafe { simd_add(a, vrshr_n_s16::<N>(b)) }
60067}
60068#[doc = "Signed rounding shift right and accumulate"]
60069#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s16)"]
60070#[inline]
60071#[target_feature(enable = "neon")]
60072#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60073#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60074#[cfg_attr(
60075    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60076    assert_instr(srsra, N = 2)
60077)]
60078#[rustc_legacy_const_generics(2)]
60079#[cfg_attr(
60080    not(target_arch = "arm"),
60081    stable(feature = "neon_intrinsics", since = "1.59.0")
60082)]
60083#[cfg_attr(
60084    target_arch = "arm",
60085    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60086)]
60087pub fn vrsraq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
60088    static_assert!(N >= 1 && N <= 16);
60089    unsafe { simd_add(a, vrshrq_n_s16::<N>(b)) }
60090}
60091#[doc = "Signed rounding shift right and accumulate"]
60092#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s32)"]
60093#[inline]
60094#[target_feature(enable = "neon")]
60095#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60096#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60097#[cfg_attr(
60098    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60099    assert_instr(srsra, N = 2)
60100)]
60101#[rustc_legacy_const_generics(2)]
60102#[cfg_attr(
60103    not(target_arch = "arm"),
60104    stable(feature = "neon_intrinsics", since = "1.59.0")
60105)]
60106#[cfg_attr(
60107    target_arch = "arm",
60108    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60109)]
60110pub fn vrsra_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
60111    static_assert!(N >= 1 && N <= 32);
60112    unsafe { simd_add(a, vrshr_n_s32::<N>(b)) }
60113}
60114#[doc = "Signed rounding shift right and accumulate"]
60115#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s32)"]
60116#[inline]
60117#[target_feature(enable = "neon")]
60118#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60119#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60120#[cfg_attr(
60121    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60122    assert_instr(srsra, N = 2)
60123)]
60124#[rustc_legacy_const_generics(2)]
60125#[cfg_attr(
60126    not(target_arch = "arm"),
60127    stable(feature = "neon_intrinsics", since = "1.59.0")
60128)]
60129#[cfg_attr(
60130    target_arch = "arm",
60131    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60132)]
60133pub fn vrsraq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
60134    static_assert!(N >= 1 && N <= 32);
60135    unsafe { simd_add(a, vrshrq_n_s32::<N>(b)) }
60136}
60137#[doc = "Signed rounding shift right and accumulate"]
60138#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s64)"]
60139#[inline]
60140#[target_feature(enable = "neon")]
60141#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60142#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60143#[cfg_attr(
60144    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60145    assert_instr(srsra, N = 2)
60146)]
60147#[rustc_legacy_const_generics(2)]
60148#[cfg_attr(
60149    not(target_arch = "arm"),
60150    stable(feature = "neon_intrinsics", since = "1.59.0")
60151)]
60152#[cfg_attr(
60153    target_arch = "arm",
60154    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60155)]
60156pub fn vrsra_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
60157    static_assert!(N >= 1 && N <= 64);
60158    unsafe { simd_add(a, vrshr_n_s64::<N>(b)) }
60159}
60160#[doc = "Signed rounding shift right and accumulate"]
60161#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s64)"]
60162#[inline]
60163#[target_feature(enable = "neon")]
60164#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60165#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60166#[cfg_attr(
60167    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60168    assert_instr(srsra, N = 2)
60169)]
60170#[rustc_legacy_const_generics(2)]
60171#[cfg_attr(
60172    not(target_arch = "arm"),
60173    stable(feature = "neon_intrinsics", since = "1.59.0")
60174)]
60175#[cfg_attr(
60176    target_arch = "arm",
60177    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60178)]
60179pub fn vrsraq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
60180    static_assert!(N >= 1 && N <= 64);
60181    unsafe { simd_add(a, vrshrq_n_s64::<N>(b)) }
60182}
60183#[doc = "Unsigned rounding shift right and accumulate"]
60184#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u8)"]
60185#[inline]
60186#[target_feature(enable = "neon")]
60187#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60188#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60189#[cfg_attr(
60190    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60191    assert_instr(ursra, N = 2)
60192)]
60193#[rustc_legacy_const_generics(2)]
60194#[cfg_attr(
60195    not(target_arch = "arm"),
60196    stable(feature = "neon_intrinsics", since = "1.59.0")
60197)]
60198#[cfg_attr(
60199    target_arch = "arm",
60200    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60201)]
60202pub fn vrsra_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
60203    static_assert!(N >= 1 && N <= 8);
60204    unsafe { simd_add(a, vrshr_n_u8::<N>(b)) }
60205}
60206#[doc = "Unsigned rounding shift right and accumulate"]
60207#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u8)"]
60208#[inline]
60209#[target_feature(enable = "neon")]
60210#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60211#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60212#[cfg_attr(
60213    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60214    assert_instr(ursra, N = 2)
60215)]
60216#[rustc_legacy_const_generics(2)]
60217#[cfg_attr(
60218    not(target_arch = "arm"),
60219    stable(feature = "neon_intrinsics", since = "1.59.0")
60220)]
60221#[cfg_attr(
60222    target_arch = "arm",
60223    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60224)]
60225pub fn vrsraq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
60226    static_assert!(N >= 1 && N <= 8);
60227    unsafe { simd_add(a, vrshrq_n_u8::<N>(b)) }
60228}
60229#[doc = "Unsigned rounding shift right and accumulate"]
60230#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u16)"]
60231#[inline]
60232#[target_feature(enable = "neon")]
60233#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60234#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60235#[cfg_attr(
60236    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60237    assert_instr(ursra, N = 2)
60238)]
60239#[rustc_legacy_const_generics(2)]
60240#[cfg_attr(
60241    not(target_arch = "arm"),
60242    stable(feature = "neon_intrinsics", since = "1.59.0")
60243)]
60244#[cfg_attr(
60245    target_arch = "arm",
60246    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60247)]
60248pub fn vrsra_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
60249    static_assert!(N >= 1 && N <= 16);
60250    unsafe { simd_add(a, vrshr_n_u16::<N>(b)) }
60251}
60252#[doc = "Unsigned rounding shift right and accumulate"]
60253#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u16)"]
60254#[inline]
60255#[target_feature(enable = "neon")]
60256#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60257#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60258#[cfg_attr(
60259    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60260    assert_instr(ursra, N = 2)
60261)]
60262#[rustc_legacy_const_generics(2)]
60263#[cfg_attr(
60264    not(target_arch = "arm"),
60265    stable(feature = "neon_intrinsics", since = "1.59.0")
60266)]
60267#[cfg_attr(
60268    target_arch = "arm",
60269    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60270)]
60271pub fn vrsraq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
60272    static_assert!(N >= 1 && N <= 16);
60273    unsafe { simd_add(a, vrshrq_n_u16::<N>(b)) }
60274}
60275#[doc = "Unsigned rounding shift right and accumulate"]
60276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u32)"]
60277#[inline]
60278#[target_feature(enable = "neon")]
60279#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60280#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60281#[cfg_attr(
60282    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60283    assert_instr(ursra, N = 2)
60284)]
60285#[rustc_legacy_const_generics(2)]
60286#[cfg_attr(
60287    not(target_arch = "arm"),
60288    stable(feature = "neon_intrinsics", since = "1.59.0")
60289)]
60290#[cfg_attr(
60291    target_arch = "arm",
60292    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60293)]
60294pub fn vrsra_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
60295    static_assert!(N >= 1 && N <= 32);
60296    unsafe { simd_add(a, vrshr_n_u32::<N>(b)) }
60297}
60298#[doc = "Unsigned rounding shift right and accumulate"]
60299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u32)"]
60300#[inline]
60301#[target_feature(enable = "neon")]
60302#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60303#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60304#[cfg_attr(
60305    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60306    assert_instr(ursra, N = 2)
60307)]
60308#[rustc_legacy_const_generics(2)]
60309#[cfg_attr(
60310    not(target_arch = "arm"),
60311    stable(feature = "neon_intrinsics", since = "1.59.0")
60312)]
60313#[cfg_attr(
60314    target_arch = "arm",
60315    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60316)]
60317pub fn vrsraq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
60318    static_assert!(N >= 1 && N <= 32);
60319    unsafe { simd_add(a, vrshrq_n_u32::<N>(b)) }
60320}
60321#[doc = "Unsigned rounding shift right and accumulate"]
60322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u64)"]
60323#[inline]
60324#[target_feature(enable = "neon")]
60325#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60326#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60327#[cfg_attr(
60328    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60329    assert_instr(ursra, N = 2)
60330)]
60331#[rustc_legacy_const_generics(2)]
60332#[cfg_attr(
60333    not(target_arch = "arm"),
60334    stable(feature = "neon_intrinsics", since = "1.59.0")
60335)]
60336#[cfg_attr(
60337    target_arch = "arm",
60338    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60339)]
60340pub fn vrsra_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
60341    static_assert!(N >= 1 && N <= 64);
60342    unsafe { simd_add(a, vrshr_n_u64::<N>(b)) }
60343}
60344#[doc = "Unsigned rounding shift right and accumulate"]
60345#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u64)"]
60346#[inline]
60347#[target_feature(enable = "neon")]
60348#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60349#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60350#[cfg_attr(
60351    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60352    assert_instr(ursra, N = 2)
60353)]
60354#[rustc_legacy_const_generics(2)]
60355#[cfg_attr(
60356    not(target_arch = "arm"),
60357    stable(feature = "neon_intrinsics", since = "1.59.0")
60358)]
60359#[cfg_attr(
60360    target_arch = "arm",
60361    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60362)]
60363pub fn vrsraq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
60364    static_assert!(N >= 1 && N <= 64);
60365    unsafe { simd_add(a, vrshrq_n_u64::<N>(b)) }
60366}
60367#[doc = "Rounding subtract returning high narrow"]
60368#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s16)"]
60369#[inline]
60370#[target_feature(enable = "neon")]
60371#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60372#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60373#[cfg_attr(
60374    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60375    assert_instr(rsubhn)
60376)]
60377#[cfg_attr(
60378    not(target_arch = "arm"),
60379    stable(feature = "neon_intrinsics", since = "1.59.0")
60380)]
60381#[cfg_attr(
60382    target_arch = "arm",
60383    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60384)]
60385pub fn vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
60386    unsafe extern "unadjusted" {
60387        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v8i8")]
60388        #[cfg_attr(
60389            any(target_arch = "aarch64", target_arch = "arm64ec"),
60390            link_name = "llvm.aarch64.neon.rsubhn.v8i8"
60391        )]
60392        fn _vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t;
60393    }
60394    unsafe { _vrsubhn_s16(a, b) }
60395}
60396#[doc = "Rounding subtract returning high narrow"]
60397#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s32)"]
60398#[inline]
60399#[target_feature(enable = "neon")]
60400#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60401#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60402#[cfg_attr(
60403    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60404    assert_instr(rsubhn)
60405)]
60406#[cfg_attr(
60407    not(target_arch = "arm"),
60408    stable(feature = "neon_intrinsics", since = "1.59.0")
60409)]
60410#[cfg_attr(
60411    target_arch = "arm",
60412    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60413)]
60414pub fn vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
60415    unsafe extern "unadjusted" {
60416        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v4i16")]
60417        #[cfg_attr(
60418            any(target_arch = "aarch64", target_arch = "arm64ec"),
60419            link_name = "llvm.aarch64.neon.rsubhn.v4i16"
60420        )]
60421        fn _vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t;
60422    }
60423    unsafe { _vrsubhn_s32(a, b) }
60424}
60425#[doc = "Rounding subtract returning high narrow"]
60426#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s64)"]
60427#[inline]
60428#[target_feature(enable = "neon")]
60429#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60430#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60431#[cfg_attr(
60432    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60433    assert_instr(rsubhn)
60434)]
60435#[cfg_attr(
60436    not(target_arch = "arm"),
60437    stable(feature = "neon_intrinsics", since = "1.59.0")
60438)]
60439#[cfg_attr(
60440    target_arch = "arm",
60441    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60442)]
60443pub fn vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
60444    unsafe extern "unadjusted" {
60445        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v2i32")]
60446        #[cfg_attr(
60447            any(target_arch = "aarch64", target_arch = "arm64ec"),
60448            link_name = "llvm.aarch64.neon.rsubhn.v2i32"
60449        )]
60450        fn _vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t;
60451    }
60452    unsafe { _vrsubhn_s64(a, b) }
60453}
60454#[doc = "Rounding subtract returning high narrow"]
60455#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"]
60456#[inline]
60457#[cfg(target_endian = "little")]
60458#[target_feature(enable = "neon")]
60459#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60460#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60461#[cfg_attr(
60462    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60463    assert_instr(rsubhn)
60464)]
60465#[cfg_attr(
60466    not(target_arch = "arm"),
60467    stable(feature = "neon_intrinsics", since = "1.59.0")
60468)]
60469#[cfg_attr(
60470    target_arch = "arm",
60471    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60472)]
60473pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
60474    unsafe { transmute(vrsubhn_s16(transmute(a), transmute(b))) }
60475}
60476#[doc = "Rounding subtract returning high narrow"]
60477#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"]
60478#[inline]
60479#[cfg(target_endian = "big")]
60480#[target_feature(enable = "neon")]
60481#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60482#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60483#[cfg_attr(
60484    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60485    assert_instr(rsubhn)
60486)]
60487#[cfg_attr(
60488    not(target_arch = "arm"),
60489    stable(feature = "neon_intrinsics", since = "1.59.0")
60490)]
60491#[cfg_attr(
60492    target_arch = "arm",
60493    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60494)]
60495pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
60496    let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
60497    let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
60498    unsafe {
60499        let ret_val: uint8x8_t = transmute(vrsubhn_s16(transmute(a), transmute(b)));
60500        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
60501    }
60502}
60503#[doc = "Rounding subtract returning high narrow"]
60504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"]
60505#[inline]
60506#[cfg(target_endian = "little")]
60507#[target_feature(enable = "neon")]
60508#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60509#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60510#[cfg_attr(
60511    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60512    assert_instr(rsubhn)
60513)]
60514#[cfg_attr(
60515    not(target_arch = "arm"),
60516    stable(feature = "neon_intrinsics", since = "1.59.0")
60517)]
60518#[cfg_attr(
60519    target_arch = "arm",
60520    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60521)]
60522pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
60523    unsafe { transmute(vrsubhn_s32(transmute(a), transmute(b))) }
60524}
60525#[doc = "Rounding subtract returning high narrow"]
60526#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"]
60527#[inline]
60528#[cfg(target_endian = "big")]
60529#[target_feature(enable = "neon")]
60530#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60531#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60532#[cfg_attr(
60533    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60534    assert_instr(rsubhn)
60535)]
60536#[cfg_attr(
60537    not(target_arch = "arm"),
60538    stable(feature = "neon_intrinsics", since = "1.59.0")
60539)]
60540#[cfg_attr(
60541    target_arch = "arm",
60542    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60543)]
60544pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
60545    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
60546    let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) };
60547    unsafe {
60548        let ret_val: uint16x4_t = transmute(vrsubhn_s32(transmute(a), transmute(b)));
60549        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
60550    }
60551}
60552#[doc = "Rounding subtract returning high narrow"]
60553#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"]
60554#[inline]
60555#[cfg(target_endian = "little")]
60556#[target_feature(enable = "neon")]
60557#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60558#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60559#[cfg_attr(
60560    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60561    assert_instr(rsubhn)
60562)]
60563#[cfg_attr(
60564    not(target_arch = "arm"),
60565    stable(feature = "neon_intrinsics", since = "1.59.0")
60566)]
60567#[cfg_attr(
60568    target_arch = "arm",
60569    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60570)]
60571pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
60572    unsafe { transmute(vrsubhn_s64(transmute(a), transmute(b))) }
60573}
60574#[doc = "Rounding subtract returning high narrow"]
60575#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"]
60576#[inline]
60577#[cfg(target_endian = "big")]
60578#[target_feature(enable = "neon")]
60579#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60580#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60581#[cfg_attr(
60582    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60583    assert_instr(rsubhn)
60584)]
60585#[cfg_attr(
60586    not(target_arch = "arm"),
60587    stable(feature = "neon_intrinsics", since = "1.59.0")
60588)]
60589#[cfg_attr(
60590    target_arch = "arm",
60591    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60592)]
60593pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
60594    let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
60595    let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) };
60596    unsafe {
60597        let ret_val: uint32x2_t = transmute(vrsubhn_s64(transmute(a), transmute(b)));
60598        simd_shuffle!(ret_val, ret_val, [1, 0])
60599    }
60600}
60601#[doc = "Insert vector element from another vector element"]
60602#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f16)"]
60603#[inline]
60604#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
60605#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60606#[cfg_attr(
60607    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60608    assert_instr(nop, LANE = 0)
60609)]
60610#[rustc_legacy_const_generics(2)]
60611#[target_feature(enable = "neon,fp16")]
60612#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
60613pub fn vset_lane_f16<const LANE: i32>(a: f16, b: float16x4_t) -> float16x4_t {
60614    static_assert_uimm_bits!(LANE, 2);
60615    unsafe { simd_insert!(b, LANE as u32, a) }
60616}
60617#[doc = "Insert vector element from another vector element"]
60618#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f16)"]
60619#[inline]
60620#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
60621#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60622#[cfg_attr(
60623    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60624    assert_instr(nop, LANE = 0)
60625)]
60626#[rustc_legacy_const_generics(2)]
60627#[target_feature(enable = "neon,fp16")]
60628#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
60629pub fn vsetq_lane_f16<const LANE: i32>(a: f16, b: float16x8_t) -> float16x8_t {
60630    static_assert_uimm_bits!(LANE, 3);
60631    unsafe { simd_insert!(b, LANE as u32, a) }
60632}
60633#[doc = "Insert vector element from another vector element"]
60634#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f32)"]
60635#[inline]
60636#[target_feature(enable = "neon")]
60637#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60638#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60639#[cfg_attr(
60640    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60641    assert_instr(nop, LANE = 0)
60642)]
60643#[rustc_legacy_const_generics(2)]
60644#[cfg_attr(
60645    not(target_arch = "arm"),
60646    stable(feature = "neon_intrinsics", since = "1.59.0")
60647)]
60648#[cfg_attr(
60649    target_arch = "arm",
60650    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60651)]
60652pub fn vset_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> float32x2_t {
60653    static_assert_uimm_bits!(LANE, 1);
60654    unsafe { simd_insert!(b, LANE as u32, a) }
60655}
60656#[doc = "Insert vector element from another vector element"]
60657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f32)"]
60658#[inline]
60659#[target_feature(enable = "neon")]
60660#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60661#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60662#[cfg_attr(
60663    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60664    assert_instr(nop, LANE = 0)
60665)]
60666#[rustc_legacy_const_generics(2)]
60667#[cfg_attr(
60668    not(target_arch = "arm"),
60669    stable(feature = "neon_intrinsics", since = "1.59.0")
60670)]
60671#[cfg_attr(
60672    target_arch = "arm",
60673    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60674)]
60675pub fn vsetq_lane_f32<const LANE: i32>(a: f32, b: float32x4_t) -> float32x4_t {
60676    static_assert_uimm_bits!(LANE, 2);
60677    unsafe { simd_insert!(b, LANE as u32, a) }
60678}
60679#[doc = "Insert vector element from another vector element"]
60680#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s8)"]
60681#[inline]
60682#[target_feature(enable = "neon")]
60683#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60684#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60685#[cfg_attr(
60686    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60687    assert_instr(nop, LANE = 0)
60688)]
60689#[rustc_legacy_const_generics(2)]
60690#[cfg_attr(
60691    not(target_arch = "arm"),
60692    stable(feature = "neon_intrinsics", since = "1.59.0")
60693)]
60694#[cfg_attr(
60695    target_arch = "arm",
60696    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60697)]
60698pub fn vset_lane_s8<const LANE: i32>(a: i8, b: int8x8_t) -> int8x8_t {
60699    static_assert_uimm_bits!(LANE, 3);
60700    unsafe { simd_insert!(b, LANE as u32, a) }
60701}
60702#[doc = "Insert vector element from another vector element"]
60703#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s8)"]
60704#[inline]
60705#[target_feature(enable = "neon")]
60706#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60707#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60708#[cfg_attr(
60709    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60710    assert_instr(nop, LANE = 0)
60711)]
60712#[rustc_legacy_const_generics(2)]
60713#[cfg_attr(
60714    not(target_arch = "arm"),
60715    stable(feature = "neon_intrinsics", since = "1.59.0")
60716)]
60717#[cfg_attr(
60718    target_arch = "arm",
60719    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60720)]
60721pub fn vsetq_lane_s8<const LANE: i32>(a: i8, b: int8x16_t) -> int8x16_t {
60722    static_assert_uimm_bits!(LANE, 4);
60723    unsafe { simd_insert!(b, LANE as u32, a) }
60724}
60725#[doc = "Insert vector element from another vector element"]
60726#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s16)"]
60727#[inline]
60728#[target_feature(enable = "neon")]
60729#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60730#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60731#[cfg_attr(
60732    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60733    assert_instr(nop, LANE = 0)
60734)]
60735#[rustc_legacy_const_generics(2)]
60736#[cfg_attr(
60737    not(target_arch = "arm"),
60738    stable(feature = "neon_intrinsics", since = "1.59.0")
60739)]
60740#[cfg_attr(
60741    target_arch = "arm",
60742    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60743)]
60744pub fn vset_lane_s16<const LANE: i32>(a: i16, b: int16x4_t) -> int16x4_t {
60745    static_assert_uimm_bits!(LANE, 2);
60746    unsafe { simd_insert!(b, LANE as u32, a) }
60747}
60748#[doc = "Insert vector element from another vector element"]
60749#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s16)"]
60750#[inline]
60751#[target_feature(enable = "neon")]
60752#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60753#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60754#[cfg_attr(
60755    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60756    assert_instr(nop, LANE = 0)
60757)]
60758#[rustc_legacy_const_generics(2)]
60759#[cfg_attr(
60760    not(target_arch = "arm"),
60761    stable(feature = "neon_intrinsics", since = "1.59.0")
60762)]
60763#[cfg_attr(
60764    target_arch = "arm",
60765    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60766)]
60767pub fn vsetq_lane_s16<const LANE: i32>(a: i16, b: int16x8_t) -> int16x8_t {
60768    static_assert_uimm_bits!(LANE, 3);
60769    unsafe { simd_insert!(b, LANE as u32, a) }
60770}
60771#[doc = "Insert vector element from another vector element"]
60772#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s32)"]
60773#[inline]
60774#[target_feature(enable = "neon")]
60775#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60776#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60777#[cfg_attr(
60778    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60779    assert_instr(nop, LANE = 0)
60780)]
60781#[rustc_legacy_const_generics(2)]
60782#[cfg_attr(
60783    not(target_arch = "arm"),
60784    stable(feature = "neon_intrinsics", since = "1.59.0")
60785)]
60786#[cfg_attr(
60787    target_arch = "arm",
60788    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60789)]
60790pub fn vset_lane_s32<const LANE: i32>(a: i32, b: int32x2_t) -> int32x2_t {
60791    static_assert_uimm_bits!(LANE, 1);
60792    unsafe { simd_insert!(b, LANE as u32, a) }
60793}
60794#[doc = "Insert vector element from another vector element"]
60795#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s32)"]
60796#[inline]
60797#[target_feature(enable = "neon")]
60798#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60799#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60800#[cfg_attr(
60801    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60802    assert_instr(nop, LANE = 0)
60803)]
60804#[rustc_legacy_const_generics(2)]
60805#[cfg_attr(
60806    not(target_arch = "arm"),
60807    stable(feature = "neon_intrinsics", since = "1.59.0")
60808)]
60809#[cfg_attr(
60810    target_arch = "arm",
60811    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60812)]
60813pub fn vsetq_lane_s32<const LANE: i32>(a: i32, b: int32x4_t) -> int32x4_t {
60814    static_assert_uimm_bits!(LANE, 2);
60815    unsafe { simd_insert!(b, LANE as u32, a) }
60816}
60817#[doc = "Insert vector element from another vector element"]
60818#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s64)"]
60819#[inline]
60820#[target_feature(enable = "neon")]
60821#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60822#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60823#[cfg_attr(
60824    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60825    assert_instr(nop, LANE = 0)
60826)]
60827#[rustc_legacy_const_generics(2)]
60828#[cfg_attr(
60829    not(target_arch = "arm"),
60830    stable(feature = "neon_intrinsics", since = "1.59.0")
60831)]
60832#[cfg_attr(
60833    target_arch = "arm",
60834    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60835)]
60836pub fn vsetq_lane_s64<const LANE: i32>(a: i64, b: int64x2_t) -> int64x2_t {
60837    static_assert_uimm_bits!(LANE, 1);
60838    unsafe { simd_insert!(b, LANE as u32, a) }
60839}
60840#[doc = "Insert vector element from another vector element"]
60841#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u8)"]
60842#[inline]
60843#[target_feature(enable = "neon")]
60844#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60845#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60846#[cfg_attr(
60847    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60848    assert_instr(nop, LANE = 0)
60849)]
60850#[rustc_legacy_const_generics(2)]
60851#[cfg_attr(
60852    not(target_arch = "arm"),
60853    stable(feature = "neon_intrinsics", since = "1.59.0")
60854)]
60855#[cfg_attr(
60856    target_arch = "arm",
60857    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60858)]
60859pub fn vset_lane_u8<const LANE: i32>(a: u8, b: uint8x8_t) -> uint8x8_t {
60860    static_assert_uimm_bits!(LANE, 3);
60861    unsafe { simd_insert!(b, LANE as u32, a) }
60862}
60863#[doc = "Insert vector element from another vector element"]
60864#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u8)"]
60865#[inline]
60866#[target_feature(enable = "neon")]
60867#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60868#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60869#[cfg_attr(
60870    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60871    assert_instr(nop, LANE = 0)
60872)]
60873#[rustc_legacy_const_generics(2)]
60874#[cfg_attr(
60875    not(target_arch = "arm"),
60876    stable(feature = "neon_intrinsics", since = "1.59.0")
60877)]
60878#[cfg_attr(
60879    target_arch = "arm",
60880    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60881)]
60882pub fn vsetq_lane_u8<const LANE: i32>(a: u8, b: uint8x16_t) -> uint8x16_t {
60883    static_assert_uimm_bits!(LANE, 4);
60884    unsafe { simd_insert!(b, LANE as u32, a) }
60885}
60886#[doc = "Insert vector element from another vector element"]
60887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u16)"]
60888#[inline]
60889#[target_feature(enable = "neon")]
60890#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60891#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60892#[cfg_attr(
60893    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60894    assert_instr(nop, LANE = 0)
60895)]
60896#[rustc_legacy_const_generics(2)]
60897#[cfg_attr(
60898    not(target_arch = "arm"),
60899    stable(feature = "neon_intrinsics", since = "1.59.0")
60900)]
60901#[cfg_attr(
60902    target_arch = "arm",
60903    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60904)]
60905pub fn vset_lane_u16<const LANE: i32>(a: u16, b: uint16x4_t) -> uint16x4_t {
60906    static_assert_uimm_bits!(LANE, 2);
60907    unsafe { simd_insert!(b, LANE as u32, a) }
60908}
60909#[doc = "Insert vector element from another vector element"]
60910#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u16)"]
60911#[inline]
60912#[target_feature(enable = "neon")]
60913#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60914#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60915#[cfg_attr(
60916    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60917    assert_instr(nop, LANE = 0)
60918)]
60919#[rustc_legacy_const_generics(2)]
60920#[cfg_attr(
60921    not(target_arch = "arm"),
60922    stable(feature = "neon_intrinsics", since = "1.59.0")
60923)]
60924#[cfg_attr(
60925    target_arch = "arm",
60926    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60927)]
60928pub fn vsetq_lane_u16<const LANE: i32>(a: u16, b: uint16x8_t) -> uint16x8_t {
60929    static_assert_uimm_bits!(LANE, 3);
60930    unsafe { simd_insert!(b, LANE as u32, a) }
60931}
60932#[doc = "Insert vector element from another vector element"]
60933#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u32)"]
60934#[inline]
60935#[target_feature(enable = "neon")]
60936#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60937#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60938#[cfg_attr(
60939    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60940    assert_instr(nop, LANE = 0)
60941)]
60942#[rustc_legacy_const_generics(2)]
60943#[cfg_attr(
60944    not(target_arch = "arm"),
60945    stable(feature = "neon_intrinsics", since = "1.59.0")
60946)]
60947#[cfg_attr(
60948    target_arch = "arm",
60949    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60950)]
60951pub fn vset_lane_u32<const LANE: i32>(a: u32, b: uint32x2_t) -> uint32x2_t {
60952    static_assert_uimm_bits!(LANE, 1);
60953    unsafe { simd_insert!(b, LANE as u32, a) }
60954}
60955#[doc = "Insert vector element from another vector element"]
60956#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u32)"]
60957#[inline]
60958#[target_feature(enable = "neon")]
60959#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60960#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60961#[cfg_attr(
60962    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60963    assert_instr(nop, LANE = 0)
60964)]
60965#[rustc_legacy_const_generics(2)]
60966#[cfg_attr(
60967    not(target_arch = "arm"),
60968    stable(feature = "neon_intrinsics", since = "1.59.0")
60969)]
60970#[cfg_attr(
60971    target_arch = "arm",
60972    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60973)]
60974pub fn vsetq_lane_u32<const LANE: i32>(a: u32, b: uint32x4_t) -> uint32x4_t {
60975    static_assert_uimm_bits!(LANE, 2);
60976    unsafe { simd_insert!(b, LANE as u32, a) }
60977}
60978#[doc = "Insert vector element from another vector element"]
60979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u64)"]
60980#[inline]
60981#[target_feature(enable = "neon")]
60982#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60983#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60984#[cfg_attr(
60985    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60986    assert_instr(nop, LANE = 0)
60987)]
60988#[rustc_legacy_const_generics(2)]
60989#[cfg_attr(
60990    not(target_arch = "arm"),
60991    stable(feature = "neon_intrinsics", since = "1.59.0")
60992)]
60993#[cfg_attr(
60994    target_arch = "arm",
60995    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60996)]
60997pub fn vsetq_lane_u64<const LANE: i32>(a: u64, b: uint64x2_t) -> uint64x2_t {
60998    static_assert_uimm_bits!(LANE, 1);
60999    unsafe { simd_insert!(b, LANE as u32, a) }
61000}
61001#[doc = "Insert vector element from another vector element"]
61002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p8)"]
61003#[inline]
61004#[target_feature(enable = "neon")]
61005#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61006#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61007#[cfg_attr(
61008    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61009    assert_instr(nop, LANE = 0)
61010)]
61011#[rustc_legacy_const_generics(2)]
61012#[cfg_attr(
61013    not(target_arch = "arm"),
61014    stable(feature = "neon_intrinsics", since = "1.59.0")
61015)]
61016#[cfg_attr(
61017    target_arch = "arm",
61018    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61019)]
61020pub fn vset_lane_p8<const LANE: i32>(a: p8, b: poly8x8_t) -> poly8x8_t {
61021    static_assert_uimm_bits!(LANE, 3);
61022    unsafe { simd_insert!(b, LANE as u32, a) }
61023}
61024#[doc = "Insert vector element from another vector element"]
61025#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p8)"]
61026#[inline]
61027#[target_feature(enable = "neon")]
61028#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61029#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61030#[cfg_attr(
61031    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61032    assert_instr(nop, LANE = 0)
61033)]
61034#[rustc_legacy_const_generics(2)]
61035#[cfg_attr(
61036    not(target_arch = "arm"),
61037    stable(feature = "neon_intrinsics", since = "1.59.0")
61038)]
61039#[cfg_attr(
61040    target_arch = "arm",
61041    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61042)]
61043pub fn vsetq_lane_p8<const LANE: i32>(a: p8, b: poly8x16_t) -> poly8x16_t {
61044    static_assert_uimm_bits!(LANE, 4);
61045    unsafe { simd_insert!(b, LANE as u32, a) }
61046}
61047#[doc = "Insert vector element from another vector element"]
61048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p16)"]
61049#[inline]
61050#[target_feature(enable = "neon")]
61051#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61052#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61053#[cfg_attr(
61054    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61055    assert_instr(nop, LANE = 0)
61056)]
61057#[rustc_legacy_const_generics(2)]
61058#[cfg_attr(
61059    not(target_arch = "arm"),
61060    stable(feature = "neon_intrinsics", since = "1.59.0")
61061)]
61062#[cfg_attr(
61063    target_arch = "arm",
61064    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61065)]
61066pub fn vset_lane_p16<const LANE: i32>(a: p16, b: poly16x4_t) -> poly16x4_t {
61067    static_assert_uimm_bits!(LANE, 2);
61068    unsafe { simd_insert!(b, LANE as u32, a) }
61069}
61070#[doc = "Insert vector element from another vector element"]
61071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p16)"]
61072#[inline]
61073#[target_feature(enable = "neon")]
61074#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61075#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61076#[cfg_attr(
61077    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61078    assert_instr(nop, LANE = 0)
61079)]
61080#[rustc_legacy_const_generics(2)]
61081#[cfg_attr(
61082    not(target_arch = "arm"),
61083    stable(feature = "neon_intrinsics", since = "1.59.0")
61084)]
61085#[cfg_attr(
61086    target_arch = "arm",
61087    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61088)]
61089pub fn vsetq_lane_p16<const LANE: i32>(a: p16, b: poly16x8_t) -> poly16x8_t {
61090    static_assert_uimm_bits!(LANE, 3);
61091    unsafe { simd_insert!(b, LANE as u32, a) }
61092}
61093#[doc = "Insert vector element from another vector element"]
61094#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p64)"]
61095#[inline]
61096#[target_feature(enable = "neon,aes")]
61097#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61098#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61099#[cfg_attr(
61100    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61101    assert_instr(nop, LANE = 0)
61102)]
61103#[rustc_legacy_const_generics(2)]
61104#[cfg_attr(
61105    not(target_arch = "arm"),
61106    stable(feature = "neon_intrinsics", since = "1.59.0")
61107)]
61108#[cfg_attr(
61109    target_arch = "arm",
61110    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61111)]
61112pub fn vset_lane_p64<const LANE: i32>(a: p64, b: poly64x1_t) -> poly64x1_t {
61113    static_assert!(LANE == 0);
61114    unsafe { simd_insert!(b, LANE as u32, a) }
61115}
61116#[doc = "Insert vector element from another vector element"]
61117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s64)"]
61118#[inline]
61119#[target_feature(enable = "neon")]
61120#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61121#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61122#[cfg_attr(
61123    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61124    assert_instr(nop, LANE = 0)
61125)]
61126#[rustc_legacy_const_generics(2)]
61127#[cfg_attr(
61128    not(target_arch = "arm"),
61129    stable(feature = "neon_intrinsics", since = "1.59.0")
61130)]
61131#[cfg_attr(
61132    target_arch = "arm",
61133    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61134)]
61135pub fn vset_lane_s64<const LANE: i32>(a: i64, b: int64x1_t) -> int64x1_t {
61136    static_assert!(LANE == 0);
61137    unsafe { simd_insert!(b, LANE as u32, a) }
61138}
61139#[doc = "Insert vector element from another vector element"]
61140#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u64)"]
61141#[inline]
61142#[target_feature(enable = "neon")]
61143#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61144#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61145#[cfg_attr(
61146    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61147    assert_instr(nop, LANE = 0)
61148)]
61149#[rustc_legacy_const_generics(2)]
61150#[cfg_attr(
61151    not(target_arch = "arm"),
61152    stable(feature = "neon_intrinsics", since = "1.59.0")
61153)]
61154#[cfg_attr(
61155    target_arch = "arm",
61156    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61157)]
61158pub fn vset_lane_u64<const LANE: i32>(a: u64, b: uint64x1_t) -> uint64x1_t {
61159    static_assert!(LANE == 0);
61160    unsafe { simd_insert!(b, LANE as u32, a) }
61161}
61162#[doc = "Insert vector element from another vector element"]
61163#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p64)"]
61164#[inline]
61165#[target_feature(enable = "neon,aes")]
61166#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61167#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61168#[cfg_attr(
61169    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61170    assert_instr(nop, LANE = 0)
61171)]
61172#[rustc_legacy_const_generics(2)]
61173#[cfg_attr(
61174    not(target_arch = "arm"),
61175    stable(feature = "neon_intrinsics", since = "1.59.0")
61176)]
61177#[cfg_attr(
61178    target_arch = "arm",
61179    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61180)]
61181pub fn vsetq_lane_p64<const LANE: i32>(a: p64, b: poly64x2_t) -> poly64x2_t {
61182    static_assert_uimm_bits!(LANE, 1);
61183    unsafe { simd_insert!(b, LANE as u32, a) }
61184}
61185#[doc = "SHA1 hash update accelerator, choose."]
61186#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1cq_u32)"]
61187#[inline]
61188#[target_feature(enable = "sha2")]
61189#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61190#[cfg_attr(test, assert_instr(sha1c))]
61191#[cfg_attr(
61192    target_arch = "arm",
61193    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61194)]
61195#[cfg_attr(
61196    not(target_arch = "arm"),
61197    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61198)]
61199pub fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
61200    unsafe extern "unadjusted" {
61201        #[cfg_attr(
61202            any(target_arch = "aarch64", target_arch = "arm64ec"),
61203            link_name = "llvm.aarch64.crypto.sha1c"
61204        )]
61205        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1c")]
61206        fn _vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
61207    }
61208    unsafe { _vsha1cq_u32(hash_abcd, hash_e, wk) }
61209}
61210#[doc = "SHA1 fixed rotate."]
61211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1h_u32)"]
61212#[inline]
61213#[target_feature(enable = "sha2")]
61214#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61215#[cfg_attr(test, assert_instr(sha1h))]
61216#[cfg_attr(
61217    target_arch = "arm",
61218    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61219)]
61220#[cfg_attr(
61221    not(target_arch = "arm"),
61222    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61223)]
61224pub fn vsha1h_u32(hash_e: u32) -> u32 {
61225    unsafe extern "unadjusted" {
61226        #[cfg_attr(
61227            any(target_arch = "aarch64", target_arch = "arm64ec"),
61228            link_name = "llvm.aarch64.crypto.sha1h"
61229        )]
61230        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1h")]
61231        fn _vsha1h_u32(hash_e: u32) -> u32;
61232    }
61233    unsafe { _vsha1h_u32(hash_e) }
61234}
61235#[doc = "SHA1 hash update accelerator, majority"]
61236#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1mq_u32)"]
61237#[inline]
61238#[target_feature(enable = "sha2")]
61239#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61240#[cfg_attr(test, assert_instr(sha1m))]
61241#[cfg_attr(
61242    target_arch = "arm",
61243    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61244)]
61245#[cfg_attr(
61246    not(target_arch = "arm"),
61247    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61248)]
61249pub fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
61250    unsafe extern "unadjusted" {
61251        #[cfg_attr(
61252            any(target_arch = "aarch64", target_arch = "arm64ec"),
61253            link_name = "llvm.aarch64.crypto.sha1m"
61254        )]
61255        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1m")]
61256        fn _vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
61257    }
61258    unsafe { _vsha1mq_u32(hash_abcd, hash_e, wk) }
61259}
61260#[doc = "SHA1 hash update accelerator, parity"]
61261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1pq_u32)"]
61262#[inline]
61263#[target_feature(enable = "sha2")]
61264#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61265#[cfg_attr(test, assert_instr(sha1p))]
61266#[cfg_attr(
61267    target_arch = "arm",
61268    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61269)]
61270#[cfg_attr(
61271    not(target_arch = "arm"),
61272    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61273)]
61274pub fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
61275    unsafe extern "unadjusted" {
61276        #[cfg_attr(
61277            any(target_arch = "aarch64", target_arch = "arm64ec"),
61278            link_name = "llvm.aarch64.crypto.sha1p"
61279        )]
61280        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1p")]
61281        fn _vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
61282    }
61283    unsafe { _vsha1pq_u32(hash_abcd, hash_e, wk) }
61284}
61285#[doc = "SHA1 schedule update accelerator, first part."]
61286#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su0q_u32)"]
61287#[inline]
61288#[target_feature(enable = "sha2")]
61289#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61290#[cfg_attr(test, assert_instr(sha1su0))]
61291#[cfg_attr(
61292    target_arch = "arm",
61293    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61294)]
61295#[cfg_attr(
61296    not(target_arch = "arm"),
61297    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61298)]
61299pub fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t {
61300    unsafe extern "unadjusted" {
61301        #[cfg_attr(
61302            any(target_arch = "aarch64", target_arch = "arm64ec"),
61303            link_name = "llvm.aarch64.crypto.sha1su0"
61304        )]
61305        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su0")]
61306        fn _vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t;
61307    }
61308    unsafe { _vsha1su0q_u32(w0_3, w4_7, w8_11) }
61309}
61310#[doc = "SHA1 schedule update accelerator, second part."]
61311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su1q_u32)"]
61312#[inline]
61313#[target_feature(enable = "sha2")]
61314#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61315#[cfg_attr(test, assert_instr(sha1su1))]
61316#[cfg_attr(
61317    target_arch = "arm",
61318    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61319)]
61320#[cfg_attr(
61321    not(target_arch = "arm"),
61322    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61323)]
61324pub fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t {
61325    unsafe extern "unadjusted" {
61326        #[cfg_attr(
61327            any(target_arch = "aarch64", target_arch = "arm64ec"),
61328            link_name = "llvm.aarch64.crypto.sha1su1"
61329        )]
61330        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su1")]
61331        fn _vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t;
61332    }
61333    unsafe { _vsha1su1q_u32(tw0_3, w12_15) }
61334}
61335#[doc = "SHA1 schedule update accelerator, upper part."]
61336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256h2q_u32)"]
61337#[inline]
61338#[target_feature(enable = "sha2")]
61339#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61340#[cfg_attr(test, assert_instr(sha256h2))]
61341#[cfg_attr(
61342    target_arch = "arm",
61343    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61344)]
61345#[cfg_attr(
61346    not(target_arch = "arm"),
61347    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61348)]
61349pub fn vsha256h2q_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t {
61350    unsafe extern "unadjusted" {
61351        #[cfg_attr(
61352            any(target_arch = "aarch64", target_arch = "arm64ec"),
61353            link_name = "llvm.aarch64.crypto.sha256h2"
61354        )]
61355        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h2")]
61356        fn _vsha256h2q_u32(
61357            hash_abcd: uint32x4_t,
61358            hash_efgh: uint32x4_t,
61359            wk: uint32x4_t,
61360        ) -> uint32x4_t;
61361    }
61362    unsafe { _vsha256h2q_u32(hash_abcd, hash_efgh, wk) }
61363}
61364#[doc = "SHA1 schedule update accelerator, first part."]
61365#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256hq_u32)"]
61366#[inline]
61367#[target_feature(enable = "sha2")]
61368#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61369#[cfg_attr(test, assert_instr(sha256h))]
61370#[cfg_attr(
61371    target_arch = "arm",
61372    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61373)]
61374#[cfg_attr(
61375    not(target_arch = "arm"),
61376    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61377)]
61378pub fn vsha256hq_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t {
61379    unsafe extern "unadjusted" {
61380        #[cfg_attr(
61381            any(target_arch = "aarch64", target_arch = "arm64ec"),
61382            link_name = "llvm.aarch64.crypto.sha256h"
61383        )]
61384        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h")]
61385        fn _vsha256hq_u32(
61386            hash_abcd: uint32x4_t,
61387            hash_efgh: uint32x4_t,
61388            wk: uint32x4_t,
61389        ) -> uint32x4_t;
61390    }
61391    unsafe { _vsha256hq_u32(hash_abcd, hash_efgh, wk) }
61392}
61393#[doc = "SHA256 schedule update accelerator, first part."]
61394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su0q_u32)"]
61395#[inline]
61396#[target_feature(enable = "sha2")]
61397#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61398#[cfg_attr(test, assert_instr(sha256su0))]
61399#[cfg_attr(
61400    target_arch = "arm",
61401    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61402)]
61403#[cfg_attr(
61404    not(target_arch = "arm"),
61405    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61406)]
61407pub fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t {
61408    unsafe extern "unadjusted" {
61409        #[cfg_attr(
61410            any(target_arch = "aarch64", target_arch = "arm64ec"),
61411            link_name = "llvm.aarch64.crypto.sha256su0"
61412        )]
61413        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su0")]
61414        fn _vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t;
61415    }
61416    unsafe { _vsha256su0q_u32(w0_3, w4_7) }
61417}
61418#[doc = "SHA256 schedule update accelerator, second part."]
61419#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su1q_u32)"]
61420#[inline]
61421#[target_feature(enable = "sha2")]
61422#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61423#[cfg_attr(test, assert_instr(sha256su1))]
61424#[cfg_attr(
61425    target_arch = "arm",
61426    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61427)]
61428#[cfg_attr(
61429    not(target_arch = "arm"),
61430    stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61431)]
61432pub fn vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t {
61433    unsafe extern "unadjusted" {
61434        #[cfg_attr(
61435            any(target_arch = "aarch64", target_arch = "arm64ec"),
61436            link_name = "llvm.aarch64.crypto.sha256su1"
61437        )]
61438        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su1")]
61439        fn _vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t)
61440            -> uint32x4_t;
61441    }
61442    unsafe { _vsha256su1q_u32(tw0_3, w8_11, w12_15) }
61443}
61444#[doc = "Shift Right and Insert (immediate)"]
61445#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v16i8)"]
61446#[inline]
61447#[target_feature(enable = "neon")]
61448#[cfg(target_arch = "arm")]
61449#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61450#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61451fn vshiftins_v16i8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
61452    unsafe extern "unadjusted" {
61453        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v16i8")]
61454        fn _vshiftins_v16i8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t;
61455    }
61456    unsafe { _vshiftins_v16i8(a, b, c) }
61457}
61458#[doc = "Shift Right and Insert (immediate)"]
61459#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v1i64)"]
61460#[inline]
61461#[target_feature(enable = "neon")]
61462#[cfg(target_arch = "arm")]
61463#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61464#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61465fn vshiftins_v1i64(a: int64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t {
61466    unsafe extern "unadjusted" {
61467        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v1i64")]
61468        fn _vshiftins_v1i64(a: int64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t;
61469    }
61470    unsafe { _vshiftins_v1i64(a, b, c) }
61471}
61472#[doc = "Shift Right and Insert (immediate)"]
61473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v2i32)"]
61474#[inline]
61475#[target_feature(enable = "neon")]
61476#[cfg(target_arch = "arm")]
61477#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61478#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61479fn vshiftins_v2i32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
61480    unsafe extern "unadjusted" {
61481        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i32")]
61482        fn _vshiftins_v2i32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t;
61483    }
61484    unsafe { _vshiftins_v2i32(a, b, c) }
61485}
61486#[doc = "Shift Right and Insert (immediate)"]
61487#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v2i64)"]
61488#[inline]
61489#[target_feature(enable = "neon")]
61490#[cfg(target_arch = "arm")]
61491#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61492#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61493fn vshiftins_v2i64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
61494    unsafe extern "unadjusted" {
61495        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i64")]
61496        fn _vshiftins_v2i64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t;
61497    }
61498    unsafe { _vshiftins_v2i64(a, b, c) }
61499}
61500#[doc = "Shift Right and Insert (immediate)"]
61501#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v4i16)"]
61502#[inline]
61503#[target_feature(enable = "neon")]
61504#[cfg(target_arch = "arm")]
61505#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61506#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61507fn vshiftins_v4i16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
61508    unsafe extern "unadjusted" {
61509        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i16")]
61510        fn _vshiftins_v4i16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t;
61511    }
61512    unsafe { _vshiftins_v4i16(a, b, c) }
61513}
61514#[doc = "Shift Right and Insert (immediate)"]
61515#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v4i32)"]
61516#[inline]
61517#[target_feature(enable = "neon")]
61518#[cfg(target_arch = "arm")]
61519#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61520#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61521fn vshiftins_v4i32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
61522    unsafe extern "unadjusted" {
61523        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i32")]
61524        fn _vshiftins_v4i32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t;
61525    }
61526    unsafe { _vshiftins_v4i32(a, b, c) }
61527}
61528#[doc = "Shift Right and Insert (immediate)"]
61529#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v8i16)"]
61530#[inline]
61531#[target_feature(enable = "neon")]
61532#[cfg(target_arch = "arm")]
61533#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61534#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61535fn vshiftins_v8i16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
61536    unsafe extern "unadjusted" {
61537        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i16")]
61538        fn _vshiftins_v8i16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t;
61539    }
61540    unsafe { _vshiftins_v8i16(a, b, c) }
61541}
61542#[doc = "Shift Right and Insert (immediate)"]
61543#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v8i8)"]
61544#[inline]
61545#[target_feature(enable = "neon")]
61546#[cfg(target_arch = "arm")]
61547#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61548#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61549fn vshiftins_v8i8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
61550    unsafe extern "unadjusted" {
61551        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i8")]
61552        fn _vshiftins_v8i8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t;
61553    }
61554    unsafe { _vshiftins_v8i8(a, b, c) }
61555}
61556#[doc = "Shift left"]
61557#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s8)"]
61558#[inline]
61559#[target_feature(enable = "neon")]
61560#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61561#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61562#[cfg_attr(
61563    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61564    assert_instr(shl, N = 2)
61565)]
61566#[rustc_legacy_const_generics(1)]
61567#[cfg_attr(
61568    not(target_arch = "arm"),
61569    stable(feature = "neon_intrinsics", since = "1.59.0")
61570)]
61571#[cfg_attr(
61572    target_arch = "arm",
61573    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61574)]
61575pub fn vshl_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
61576    static_assert_uimm_bits!(N, 3);
61577    unsafe { simd_shl(a, vdup_n_s8(N as _)) }
61578}
61579#[doc = "Shift left"]
61580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s8)"]
61581#[inline]
61582#[target_feature(enable = "neon")]
61583#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61584#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61585#[cfg_attr(
61586    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61587    assert_instr(shl, N = 2)
61588)]
61589#[rustc_legacy_const_generics(1)]
61590#[cfg_attr(
61591    not(target_arch = "arm"),
61592    stable(feature = "neon_intrinsics", since = "1.59.0")
61593)]
61594#[cfg_attr(
61595    target_arch = "arm",
61596    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61597)]
61598pub fn vshlq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
61599    static_assert_uimm_bits!(N, 3);
61600    unsafe { simd_shl(a, vdupq_n_s8(N as _)) }
61601}
61602#[doc = "Shift left"]
61603#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s16)"]
61604#[inline]
61605#[target_feature(enable = "neon")]
61606#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61607#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61608#[cfg_attr(
61609    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61610    assert_instr(shl, N = 2)
61611)]
61612#[rustc_legacy_const_generics(1)]
61613#[cfg_attr(
61614    not(target_arch = "arm"),
61615    stable(feature = "neon_intrinsics", since = "1.59.0")
61616)]
61617#[cfg_attr(
61618    target_arch = "arm",
61619    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61620)]
61621pub fn vshl_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
61622    static_assert_uimm_bits!(N, 4);
61623    unsafe { simd_shl(a, vdup_n_s16(N as _)) }
61624}
61625#[doc = "Shift left"]
61626#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s16)"]
61627#[inline]
61628#[target_feature(enable = "neon")]
61629#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61630#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61631#[cfg_attr(
61632    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61633    assert_instr(shl, N = 2)
61634)]
61635#[rustc_legacy_const_generics(1)]
61636#[cfg_attr(
61637    not(target_arch = "arm"),
61638    stable(feature = "neon_intrinsics", since = "1.59.0")
61639)]
61640#[cfg_attr(
61641    target_arch = "arm",
61642    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61643)]
61644pub fn vshlq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
61645    static_assert_uimm_bits!(N, 4);
61646    unsafe { simd_shl(a, vdupq_n_s16(N as _)) }
61647}
61648#[doc = "Shift left"]
61649#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s32)"]
61650#[inline]
61651#[target_feature(enable = "neon")]
61652#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61653#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61654#[cfg_attr(
61655    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61656    assert_instr(shl, N = 2)
61657)]
61658#[rustc_legacy_const_generics(1)]
61659#[cfg_attr(
61660    not(target_arch = "arm"),
61661    stable(feature = "neon_intrinsics", since = "1.59.0")
61662)]
61663#[cfg_attr(
61664    target_arch = "arm",
61665    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61666)]
61667pub fn vshl_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
61668    static_assert_uimm_bits!(N, 5);
61669    unsafe { simd_shl(a, vdup_n_s32(N as _)) }
61670}
61671#[doc = "Shift left"]
61672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s32)"]
61673#[inline]
61674#[target_feature(enable = "neon")]
61675#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61676#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61677#[cfg_attr(
61678    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61679    assert_instr(shl, N = 2)
61680)]
61681#[rustc_legacy_const_generics(1)]
61682#[cfg_attr(
61683    not(target_arch = "arm"),
61684    stable(feature = "neon_intrinsics", since = "1.59.0")
61685)]
61686#[cfg_attr(
61687    target_arch = "arm",
61688    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61689)]
61690pub fn vshlq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
61691    static_assert_uimm_bits!(N, 5);
61692    unsafe { simd_shl(a, vdupq_n_s32(N as _)) }
61693}
61694#[doc = "Shift left"]
61695#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s64)"]
61696#[inline]
61697#[target_feature(enable = "neon")]
61698#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61699#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61700#[cfg_attr(
61701    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61702    assert_instr(shl, N = 2)
61703)]
61704#[rustc_legacy_const_generics(1)]
61705#[cfg_attr(
61706    not(target_arch = "arm"),
61707    stable(feature = "neon_intrinsics", since = "1.59.0")
61708)]
61709#[cfg_attr(
61710    target_arch = "arm",
61711    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61712)]
61713pub fn vshl_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
61714    static_assert_uimm_bits!(N, 6);
61715    unsafe { simd_shl(a, vdup_n_s64(N as _)) }
61716}
61717#[doc = "Shift left"]
61718#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s64)"]
61719#[inline]
61720#[target_feature(enable = "neon")]
61721#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61722#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61723#[cfg_attr(
61724    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61725    assert_instr(shl, N = 2)
61726)]
61727#[rustc_legacy_const_generics(1)]
61728#[cfg_attr(
61729    not(target_arch = "arm"),
61730    stable(feature = "neon_intrinsics", since = "1.59.0")
61731)]
61732#[cfg_attr(
61733    target_arch = "arm",
61734    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61735)]
61736pub fn vshlq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
61737    static_assert_uimm_bits!(N, 6);
61738    unsafe { simd_shl(a, vdupq_n_s64(N as _)) }
61739}
61740#[doc = "Shift left"]
61741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u8)"]
61742#[inline]
61743#[target_feature(enable = "neon")]
61744#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61745#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61746#[cfg_attr(
61747    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61748    assert_instr(shl, N = 2)
61749)]
61750#[rustc_legacy_const_generics(1)]
61751#[cfg_attr(
61752    not(target_arch = "arm"),
61753    stable(feature = "neon_intrinsics", since = "1.59.0")
61754)]
61755#[cfg_attr(
61756    target_arch = "arm",
61757    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61758)]
61759pub fn vshl_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
61760    static_assert_uimm_bits!(N, 3);
61761    unsafe { simd_shl(a, vdup_n_u8(N as _)) }
61762}
61763#[doc = "Shift left"]
61764#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u8)"]
61765#[inline]
61766#[target_feature(enable = "neon")]
61767#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61768#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61769#[cfg_attr(
61770    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61771    assert_instr(shl, N = 2)
61772)]
61773#[rustc_legacy_const_generics(1)]
61774#[cfg_attr(
61775    not(target_arch = "arm"),
61776    stable(feature = "neon_intrinsics", since = "1.59.0")
61777)]
61778#[cfg_attr(
61779    target_arch = "arm",
61780    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61781)]
61782pub fn vshlq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
61783    static_assert_uimm_bits!(N, 3);
61784    unsafe { simd_shl(a, vdupq_n_u8(N as _)) }
61785}
61786#[doc = "Shift left"]
61787#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u16)"]
61788#[inline]
61789#[target_feature(enable = "neon")]
61790#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61791#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61792#[cfg_attr(
61793    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61794    assert_instr(shl, N = 2)
61795)]
61796#[rustc_legacy_const_generics(1)]
61797#[cfg_attr(
61798    not(target_arch = "arm"),
61799    stable(feature = "neon_intrinsics", since = "1.59.0")
61800)]
61801#[cfg_attr(
61802    target_arch = "arm",
61803    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61804)]
61805pub fn vshl_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
61806    static_assert_uimm_bits!(N, 4);
61807    unsafe { simd_shl(a, vdup_n_u16(N as _)) }
61808}
61809#[doc = "Shift left"]
61810#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u16)"]
61811#[inline]
61812#[target_feature(enable = "neon")]
61813#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61814#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61815#[cfg_attr(
61816    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61817    assert_instr(shl, N = 2)
61818)]
61819#[rustc_legacy_const_generics(1)]
61820#[cfg_attr(
61821    not(target_arch = "arm"),
61822    stable(feature = "neon_intrinsics", since = "1.59.0")
61823)]
61824#[cfg_attr(
61825    target_arch = "arm",
61826    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61827)]
61828pub fn vshlq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
61829    static_assert_uimm_bits!(N, 4);
61830    unsafe { simd_shl(a, vdupq_n_u16(N as _)) }
61831}
61832#[doc = "Shift left"]
61833#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u32)"]
61834#[inline]
61835#[target_feature(enable = "neon")]
61836#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61837#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61838#[cfg_attr(
61839    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61840    assert_instr(shl, N = 2)
61841)]
61842#[rustc_legacy_const_generics(1)]
61843#[cfg_attr(
61844    not(target_arch = "arm"),
61845    stable(feature = "neon_intrinsics", since = "1.59.0")
61846)]
61847#[cfg_attr(
61848    target_arch = "arm",
61849    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61850)]
61851pub fn vshl_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
61852    static_assert_uimm_bits!(N, 5);
61853    unsafe { simd_shl(a, vdup_n_u32(N as _)) }
61854}
61855#[doc = "Shift left"]
61856#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u32)"]
61857#[inline]
61858#[target_feature(enable = "neon")]
61859#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61860#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61861#[cfg_attr(
61862    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61863    assert_instr(shl, N = 2)
61864)]
61865#[rustc_legacy_const_generics(1)]
61866#[cfg_attr(
61867    not(target_arch = "arm"),
61868    stable(feature = "neon_intrinsics", since = "1.59.0")
61869)]
61870#[cfg_attr(
61871    target_arch = "arm",
61872    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61873)]
61874pub fn vshlq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
61875    static_assert_uimm_bits!(N, 5);
61876    unsafe { simd_shl(a, vdupq_n_u32(N as _)) }
61877}
61878#[doc = "Shift left"]
61879#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u64)"]
61880#[inline]
61881#[target_feature(enable = "neon")]
61882#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61883#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61884#[cfg_attr(
61885    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61886    assert_instr(shl, N = 2)
61887)]
61888#[rustc_legacy_const_generics(1)]
61889#[cfg_attr(
61890    not(target_arch = "arm"),
61891    stable(feature = "neon_intrinsics", since = "1.59.0")
61892)]
61893#[cfg_attr(
61894    target_arch = "arm",
61895    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61896)]
61897pub fn vshl_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
61898    static_assert_uimm_bits!(N, 6);
61899    unsafe { simd_shl(a, vdup_n_u64(N as _)) }
61900}
61901#[doc = "Shift left"]
61902#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u64)"]
61903#[inline]
61904#[target_feature(enable = "neon")]
61905#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61906#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61907#[cfg_attr(
61908    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61909    assert_instr(shl, N = 2)
61910)]
61911#[rustc_legacy_const_generics(1)]
61912#[cfg_attr(
61913    not(target_arch = "arm"),
61914    stable(feature = "neon_intrinsics", since = "1.59.0")
61915)]
61916#[cfg_attr(
61917    target_arch = "arm",
61918    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61919)]
61920pub fn vshlq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
61921    static_assert_uimm_bits!(N, 6);
61922    unsafe { simd_shl(a, vdupq_n_u64(N as _)) }
61923}
61924#[doc = "Signed Shift left"]
61925#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s8)"]
61926#[inline]
61927#[target_feature(enable = "neon")]
61928#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61929#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
61930#[cfg_attr(
61931    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61932    assert_instr(sshl)
61933)]
61934#[cfg_attr(
61935    not(target_arch = "arm"),
61936    stable(feature = "neon_intrinsics", since = "1.59.0")
61937)]
61938#[cfg_attr(
61939    target_arch = "arm",
61940    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61941)]
61942pub fn vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
61943    unsafe extern "unadjusted" {
61944        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v8i8")]
61945        #[cfg_attr(
61946            any(target_arch = "aarch64", target_arch = "arm64ec"),
61947            link_name = "llvm.aarch64.neon.sshl.v8i8"
61948        )]
61949        fn _vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
61950    }
61951    unsafe { _vshl_s8(a, b) }
61952}
61953#[doc = "Signed Shift left"]
61954#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s8)"]
61955#[inline]
61956#[target_feature(enable = "neon")]
61957#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61958#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
61959#[cfg_attr(
61960    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61961    assert_instr(sshl)
61962)]
61963#[cfg_attr(
61964    not(target_arch = "arm"),
61965    stable(feature = "neon_intrinsics", since = "1.59.0")
61966)]
61967#[cfg_attr(
61968    target_arch = "arm",
61969    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61970)]
61971pub fn vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
61972    unsafe extern "unadjusted" {
61973        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v16i8")]
61974        #[cfg_attr(
61975            any(target_arch = "aarch64", target_arch = "arm64ec"),
61976            link_name = "llvm.aarch64.neon.sshl.v16i8"
61977        )]
61978        fn _vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
61979    }
61980    unsafe { _vshlq_s8(a, b) }
61981}
61982#[doc = "Signed Shift left"]
61983#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s16)"]
61984#[inline]
61985#[target_feature(enable = "neon")]
61986#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61987#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
61988#[cfg_attr(
61989    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61990    assert_instr(sshl)
61991)]
61992#[cfg_attr(
61993    not(target_arch = "arm"),
61994    stable(feature = "neon_intrinsics", since = "1.59.0")
61995)]
61996#[cfg_attr(
61997    target_arch = "arm",
61998    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61999)]
62000pub fn vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
62001    unsafe extern "unadjusted" {
62002        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v4i16")]
62003        #[cfg_attr(
62004            any(target_arch = "aarch64", target_arch = "arm64ec"),
62005            link_name = "llvm.aarch64.neon.sshl.v4i16"
62006        )]
62007        fn _vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
62008    }
62009    unsafe { _vshl_s16(a, b) }
62010}
62011#[doc = "Signed Shift left"]
62012#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s16)"]
62013#[inline]
62014#[target_feature(enable = "neon")]
62015#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62016#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62017#[cfg_attr(
62018    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62019    assert_instr(sshl)
62020)]
62021#[cfg_attr(
62022    not(target_arch = "arm"),
62023    stable(feature = "neon_intrinsics", since = "1.59.0")
62024)]
62025#[cfg_attr(
62026    target_arch = "arm",
62027    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62028)]
62029pub fn vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
62030    unsafe extern "unadjusted" {
62031        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v8i16")]
62032        #[cfg_attr(
62033            any(target_arch = "aarch64", target_arch = "arm64ec"),
62034            link_name = "llvm.aarch64.neon.sshl.v8i16"
62035        )]
62036        fn _vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
62037    }
62038    unsafe { _vshlq_s16(a, b) }
62039}
62040#[doc = "Signed Shift left"]
62041#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s32)"]
62042#[inline]
62043#[target_feature(enable = "neon")]
62044#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62045#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62046#[cfg_attr(
62047    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62048    assert_instr(sshl)
62049)]
62050#[cfg_attr(
62051    not(target_arch = "arm"),
62052    stable(feature = "neon_intrinsics", since = "1.59.0")
62053)]
62054#[cfg_attr(
62055    target_arch = "arm",
62056    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62057)]
62058pub fn vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
62059    unsafe extern "unadjusted" {
62060        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v2i32")]
62061        #[cfg_attr(
62062            any(target_arch = "aarch64", target_arch = "arm64ec"),
62063            link_name = "llvm.aarch64.neon.sshl.v2i32"
62064        )]
62065        fn _vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
62066    }
62067    unsafe { _vshl_s32(a, b) }
62068}
62069#[doc = "Signed Shift left"]
62070#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s32)"]
62071#[inline]
62072#[target_feature(enable = "neon")]
62073#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62074#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62075#[cfg_attr(
62076    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62077    assert_instr(sshl)
62078)]
62079#[cfg_attr(
62080    not(target_arch = "arm"),
62081    stable(feature = "neon_intrinsics", since = "1.59.0")
62082)]
62083#[cfg_attr(
62084    target_arch = "arm",
62085    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62086)]
62087pub fn vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
62088    unsafe extern "unadjusted" {
62089        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v4i32")]
62090        #[cfg_attr(
62091            any(target_arch = "aarch64", target_arch = "arm64ec"),
62092            link_name = "llvm.aarch64.neon.sshl.v4i32"
62093        )]
62094        fn _vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
62095    }
62096    unsafe { _vshlq_s32(a, b) }
62097}
62098#[doc = "Signed Shift left"]
62099#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s64)"]
62100#[inline]
62101#[target_feature(enable = "neon")]
62102#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62103#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62104#[cfg_attr(
62105    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62106    assert_instr(sshl)
62107)]
62108#[cfg_attr(
62109    not(target_arch = "arm"),
62110    stable(feature = "neon_intrinsics", since = "1.59.0")
62111)]
62112#[cfg_attr(
62113    target_arch = "arm",
62114    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62115)]
62116pub fn vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
62117    unsafe extern "unadjusted" {
62118        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v1i64")]
62119        #[cfg_attr(
62120            any(target_arch = "aarch64", target_arch = "arm64ec"),
62121            link_name = "llvm.aarch64.neon.sshl.v1i64"
62122        )]
62123        fn _vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
62124    }
62125    unsafe { _vshl_s64(a, b) }
62126}
62127#[doc = "Signed Shift left"]
62128#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s64)"]
62129#[inline]
62130#[target_feature(enable = "neon")]
62131#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62132#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62133#[cfg_attr(
62134    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62135    assert_instr(sshl)
62136)]
62137#[cfg_attr(
62138    not(target_arch = "arm"),
62139    stable(feature = "neon_intrinsics", since = "1.59.0")
62140)]
62141#[cfg_attr(
62142    target_arch = "arm",
62143    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62144)]
62145pub fn vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
62146    unsafe extern "unadjusted" {
62147        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v2i64")]
62148        #[cfg_attr(
62149            any(target_arch = "aarch64", target_arch = "arm64ec"),
62150            link_name = "llvm.aarch64.neon.sshl.v2i64"
62151        )]
62152        fn _vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
62153    }
62154    unsafe { _vshlq_s64(a, b) }
62155}
62156#[doc = "Unsigned Shift left"]
62157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u8)"]
62158#[inline]
62159#[target_feature(enable = "neon")]
62160#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62161#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62162#[cfg_attr(
62163    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62164    assert_instr(ushl)
62165)]
62166#[cfg_attr(
62167    not(target_arch = "arm"),
62168    stable(feature = "neon_intrinsics", since = "1.59.0")
62169)]
62170#[cfg_attr(
62171    target_arch = "arm",
62172    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62173)]
62174pub fn vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
62175    unsafe extern "unadjusted" {
62176        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v8i8")]
62177        #[cfg_attr(
62178            any(target_arch = "aarch64", target_arch = "arm64ec"),
62179            link_name = "llvm.aarch64.neon.ushl.v8i8"
62180        )]
62181        fn _vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t;
62182    }
62183    unsafe { _vshl_u8(a, b) }
62184}
62185#[doc = "Unsigned Shift left"]
62186#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u8)"]
62187#[inline]
62188#[target_feature(enable = "neon")]
62189#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62190#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62191#[cfg_attr(
62192    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62193    assert_instr(ushl)
62194)]
62195#[cfg_attr(
62196    not(target_arch = "arm"),
62197    stable(feature = "neon_intrinsics", since = "1.59.0")
62198)]
62199#[cfg_attr(
62200    target_arch = "arm",
62201    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62202)]
62203pub fn vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
62204    unsafe extern "unadjusted" {
62205        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v16i8")]
62206        #[cfg_attr(
62207            any(target_arch = "aarch64", target_arch = "arm64ec"),
62208            link_name = "llvm.aarch64.neon.ushl.v16i8"
62209        )]
62210        fn _vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t;
62211    }
62212    unsafe { _vshlq_u8(a, b) }
62213}
62214#[doc = "Unsigned Shift left"]
62215#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u16)"]
62216#[inline]
62217#[target_feature(enable = "neon")]
62218#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62219#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62220#[cfg_attr(
62221    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62222    assert_instr(ushl)
62223)]
62224#[cfg_attr(
62225    not(target_arch = "arm"),
62226    stable(feature = "neon_intrinsics", since = "1.59.0")
62227)]
62228#[cfg_attr(
62229    target_arch = "arm",
62230    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62231)]
62232pub fn vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
62233    unsafe extern "unadjusted" {
62234        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v4i16")]
62235        #[cfg_attr(
62236            any(target_arch = "aarch64", target_arch = "arm64ec"),
62237            link_name = "llvm.aarch64.neon.ushl.v4i16"
62238        )]
62239        fn _vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t;
62240    }
62241    unsafe { _vshl_u16(a, b) }
62242}
62243#[doc = "Unsigned Shift left"]
62244#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u16)"]
62245#[inline]
62246#[target_feature(enable = "neon")]
62247#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62248#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62249#[cfg_attr(
62250    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62251    assert_instr(ushl)
62252)]
62253#[cfg_attr(
62254    not(target_arch = "arm"),
62255    stable(feature = "neon_intrinsics", since = "1.59.0")
62256)]
62257#[cfg_attr(
62258    target_arch = "arm",
62259    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62260)]
62261pub fn vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
62262    unsafe extern "unadjusted" {
62263        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v8i16")]
62264        #[cfg_attr(
62265            any(target_arch = "aarch64", target_arch = "arm64ec"),
62266            link_name = "llvm.aarch64.neon.ushl.v8i16"
62267        )]
62268        fn _vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t;
62269    }
62270    unsafe { _vshlq_u16(a, b) }
62271}
62272#[doc = "Unsigned Shift left"]
62273#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u32)"]
62274#[inline]
62275#[target_feature(enable = "neon")]
62276#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62277#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62278#[cfg_attr(
62279    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62280    assert_instr(ushl)
62281)]
62282#[cfg_attr(
62283    not(target_arch = "arm"),
62284    stable(feature = "neon_intrinsics", since = "1.59.0")
62285)]
62286#[cfg_attr(
62287    target_arch = "arm",
62288    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62289)]
62290pub fn vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
62291    unsafe extern "unadjusted" {
62292        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v2i32")]
62293        #[cfg_attr(
62294            any(target_arch = "aarch64", target_arch = "arm64ec"),
62295            link_name = "llvm.aarch64.neon.ushl.v2i32"
62296        )]
62297        fn _vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t;
62298    }
62299    unsafe { _vshl_u32(a, b) }
62300}
62301#[doc = "Unsigned Shift left"]
62302#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u32)"]
62303#[inline]
62304#[target_feature(enable = "neon")]
62305#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62306#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62307#[cfg_attr(
62308    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62309    assert_instr(ushl)
62310)]
62311#[cfg_attr(
62312    not(target_arch = "arm"),
62313    stable(feature = "neon_intrinsics", since = "1.59.0")
62314)]
62315#[cfg_attr(
62316    target_arch = "arm",
62317    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62318)]
62319pub fn vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
62320    unsafe extern "unadjusted" {
62321        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v4i32")]
62322        #[cfg_attr(
62323            any(target_arch = "aarch64", target_arch = "arm64ec"),
62324            link_name = "llvm.aarch64.neon.ushl.v4i32"
62325        )]
62326        fn _vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t;
62327    }
62328    unsafe { _vshlq_u32(a, b) }
62329}
62330#[doc = "Unsigned Shift left"]
62331#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u64)"]
62332#[inline]
62333#[target_feature(enable = "neon")]
62334#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62335#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62336#[cfg_attr(
62337    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62338    assert_instr(ushl)
62339)]
62340#[cfg_attr(
62341    not(target_arch = "arm"),
62342    stable(feature = "neon_intrinsics", since = "1.59.0")
62343)]
62344#[cfg_attr(
62345    target_arch = "arm",
62346    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62347)]
62348pub fn vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
62349    unsafe extern "unadjusted" {
62350        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v1i64")]
62351        #[cfg_attr(
62352            any(target_arch = "aarch64", target_arch = "arm64ec"),
62353            link_name = "llvm.aarch64.neon.ushl.v1i64"
62354        )]
62355        fn _vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t;
62356    }
62357    unsafe { _vshl_u64(a, b) }
62358}
62359#[doc = "Unsigned Shift left"]
62360#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u64)"]
62361#[inline]
62362#[target_feature(enable = "neon")]
62363#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62364#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62365#[cfg_attr(
62366    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62367    assert_instr(ushl)
62368)]
62369#[cfg_attr(
62370    not(target_arch = "arm"),
62371    stable(feature = "neon_intrinsics", since = "1.59.0")
62372)]
62373#[cfg_attr(
62374    target_arch = "arm",
62375    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62376)]
62377pub fn vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
62378    unsafe extern "unadjusted" {
62379        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v2i64")]
62380        #[cfg_attr(
62381            any(target_arch = "aarch64", target_arch = "arm64ec"),
62382            link_name = "llvm.aarch64.neon.ushl.v2i64"
62383        )]
62384        fn _vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t;
62385    }
62386    unsafe { _vshlq_u64(a, b) }
62387}
62388#[doc = "Signed shift left long"]
62389#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s16)"]
62390#[inline]
62391#[target_feature(enable = "neon")]
62392#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62393#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s16", N = 2))]
62394#[cfg_attr(
62395    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62396    assert_instr(sshll, N = 2)
62397)]
62398#[rustc_legacy_const_generics(1)]
62399#[cfg_attr(
62400    not(target_arch = "arm"),
62401    stable(feature = "neon_intrinsics", since = "1.59.0")
62402)]
62403#[cfg_attr(
62404    target_arch = "arm",
62405    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62406)]
62407pub fn vshll_n_s16<const N: i32>(a: int16x4_t) -> int32x4_t {
62408    static_assert!(N >= 0 && N <= 16);
62409    unsafe { simd_shl(simd_cast(a), vdupq_n_s32(N as _)) }
62410}
62411#[doc = "Signed shift left long"]
62412#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s32)"]
62413#[inline]
62414#[target_feature(enable = "neon")]
62415#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62416#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s32", N = 2))]
62417#[cfg_attr(
62418    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62419    assert_instr(sshll, N = 2)
62420)]
62421#[rustc_legacy_const_generics(1)]
62422#[cfg_attr(
62423    not(target_arch = "arm"),
62424    stable(feature = "neon_intrinsics", since = "1.59.0")
62425)]
62426#[cfg_attr(
62427    target_arch = "arm",
62428    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62429)]
62430pub fn vshll_n_s32<const N: i32>(a: int32x2_t) -> int64x2_t {
62431    static_assert!(N >= 0 && N <= 32);
62432    unsafe { simd_shl(simd_cast(a), vdupq_n_s64(N as _)) }
62433}
62434#[doc = "Signed shift left long"]
62435#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s8)"]
62436#[inline]
62437#[target_feature(enable = "neon")]
62438#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62439#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s8", N = 2))]
62440#[cfg_attr(
62441    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62442    assert_instr(sshll, N = 2)
62443)]
62444#[rustc_legacy_const_generics(1)]
62445#[cfg_attr(
62446    not(target_arch = "arm"),
62447    stable(feature = "neon_intrinsics", since = "1.59.0")
62448)]
62449#[cfg_attr(
62450    target_arch = "arm",
62451    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62452)]
62453pub fn vshll_n_s8<const N: i32>(a: int8x8_t) -> int16x8_t {
62454    static_assert!(N >= 0 && N <= 8);
62455    unsafe { simd_shl(simd_cast(a), vdupq_n_s16(N as _)) }
62456}
62457#[doc = "Signed shift left long"]
62458#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u16)"]
62459#[inline]
62460#[target_feature(enable = "neon")]
62461#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62462#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u16", N = 2))]
62463#[cfg_attr(
62464    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62465    assert_instr(ushll, N = 2)
62466)]
62467#[rustc_legacy_const_generics(1)]
62468#[cfg_attr(
62469    not(target_arch = "arm"),
62470    stable(feature = "neon_intrinsics", since = "1.59.0")
62471)]
62472#[cfg_attr(
62473    target_arch = "arm",
62474    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62475)]
62476pub fn vshll_n_u16<const N: i32>(a: uint16x4_t) -> uint32x4_t {
62477    static_assert!(N >= 0 && N <= 16);
62478    unsafe { simd_shl(simd_cast(a), vdupq_n_u32(N as _)) }
62479}
62480#[doc = "Signed shift left long"]
62481#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u32)"]
62482#[inline]
62483#[target_feature(enable = "neon")]
62484#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62485#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u32", N = 2))]
62486#[cfg_attr(
62487    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62488    assert_instr(ushll, N = 2)
62489)]
62490#[rustc_legacy_const_generics(1)]
62491#[cfg_attr(
62492    not(target_arch = "arm"),
62493    stable(feature = "neon_intrinsics", since = "1.59.0")
62494)]
62495#[cfg_attr(
62496    target_arch = "arm",
62497    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62498)]
62499pub fn vshll_n_u32<const N: i32>(a: uint32x2_t) -> uint64x2_t {
62500    static_assert!(N >= 0 && N <= 32);
62501    unsafe { simd_shl(simd_cast(a), vdupq_n_u64(N as _)) }
62502}
62503#[doc = "Signed shift left long"]
62504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u8)"]
62505#[inline]
62506#[target_feature(enable = "neon")]
62507#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62508#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u8", N = 2))]
62509#[cfg_attr(
62510    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62511    assert_instr(ushll, N = 2)
62512)]
62513#[rustc_legacy_const_generics(1)]
62514#[cfg_attr(
62515    not(target_arch = "arm"),
62516    stable(feature = "neon_intrinsics", since = "1.59.0")
62517)]
62518#[cfg_attr(
62519    target_arch = "arm",
62520    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62521)]
62522pub fn vshll_n_u8<const N: i32>(a: uint8x8_t) -> uint16x8_t {
62523    static_assert!(N >= 0 && N <= 8);
62524    unsafe { simd_shl(simd_cast(a), vdupq_n_u16(N as _)) }
62525}
62526#[doc = "Shift right"]
62527#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s8)"]
62528#[inline]
62529#[target_feature(enable = "neon")]
62530#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62531#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))]
62532#[cfg_attr(
62533    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62534    assert_instr(sshr, N = 2)
62535)]
62536#[rustc_legacy_const_generics(1)]
62537#[cfg_attr(
62538    not(target_arch = "arm"),
62539    stable(feature = "neon_intrinsics", since = "1.59.0")
62540)]
62541#[cfg_attr(
62542    target_arch = "arm",
62543    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62544)]
62545pub fn vshr_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
62546    static_assert!(N >= 1 && N <= 8);
62547    let n: i32 = if N == 8 { 7 } else { N };
62548    unsafe { simd_shr(a, vdup_n_s8(n as _)) }
62549}
62550#[doc = "Shift right"]
62551#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s8)"]
62552#[inline]
62553#[target_feature(enable = "neon")]
62554#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62555#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))]
62556#[cfg_attr(
62557    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62558    assert_instr(sshr, N = 2)
62559)]
62560#[rustc_legacy_const_generics(1)]
62561#[cfg_attr(
62562    not(target_arch = "arm"),
62563    stable(feature = "neon_intrinsics", since = "1.59.0")
62564)]
62565#[cfg_attr(
62566    target_arch = "arm",
62567    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62568)]
62569pub fn vshrq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
62570    static_assert!(N >= 1 && N <= 8);
62571    let n: i32 = if N == 8 { 7 } else { N };
62572    unsafe { simd_shr(a, vdupq_n_s8(n as _)) }
62573}
62574#[doc = "Shift right"]
62575#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s16)"]
62576#[inline]
62577#[target_feature(enable = "neon")]
62578#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62579#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))]
62580#[cfg_attr(
62581    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62582    assert_instr(sshr, N = 2)
62583)]
62584#[rustc_legacy_const_generics(1)]
62585#[cfg_attr(
62586    not(target_arch = "arm"),
62587    stable(feature = "neon_intrinsics", since = "1.59.0")
62588)]
62589#[cfg_attr(
62590    target_arch = "arm",
62591    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62592)]
62593pub fn vshr_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
62594    static_assert!(N >= 1 && N <= 16);
62595    let n: i32 = if N == 16 { 15 } else { N };
62596    unsafe { simd_shr(a, vdup_n_s16(n as _)) }
62597}
62598#[doc = "Shift right"]
62599#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s16)"]
62600#[inline]
62601#[target_feature(enable = "neon")]
62602#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62603#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))]
62604#[cfg_attr(
62605    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62606    assert_instr(sshr, N = 2)
62607)]
62608#[rustc_legacy_const_generics(1)]
62609#[cfg_attr(
62610    not(target_arch = "arm"),
62611    stable(feature = "neon_intrinsics", since = "1.59.0")
62612)]
62613#[cfg_attr(
62614    target_arch = "arm",
62615    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62616)]
62617pub fn vshrq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
62618    static_assert!(N >= 1 && N <= 16);
62619    let n: i32 = if N == 16 { 15 } else { N };
62620    unsafe { simd_shr(a, vdupq_n_s16(n as _)) }
62621}
62622#[doc = "Shift right"]
62623#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s32)"]
62624#[inline]
62625#[target_feature(enable = "neon")]
62626#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62627#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))]
62628#[cfg_attr(
62629    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62630    assert_instr(sshr, N = 2)
62631)]
62632#[rustc_legacy_const_generics(1)]
62633#[cfg_attr(
62634    not(target_arch = "arm"),
62635    stable(feature = "neon_intrinsics", since = "1.59.0")
62636)]
62637#[cfg_attr(
62638    target_arch = "arm",
62639    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62640)]
62641pub fn vshr_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
62642    static_assert!(N >= 1 && N <= 32);
62643    let n: i32 = if N == 32 { 31 } else { N };
62644    unsafe { simd_shr(a, vdup_n_s32(n as _)) }
62645}
62646#[doc = "Shift right"]
62647#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s32)"]
62648#[inline]
62649#[target_feature(enable = "neon")]
62650#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62651#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))]
62652#[cfg_attr(
62653    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62654    assert_instr(sshr, N = 2)
62655)]
62656#[rustc_legacy_const_generics(1)]
62657#[cfg_attr(
62658    not(target_arch = "arm"),
62659    stable(feature = "neon_intrinsics", since = "1.59.0")
62660)]
62661#[cfg_attr(
62662    target_arch = "arm",
62663    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62664)]
62665pub fn vshrq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
62666    static_assert!(N >= 1 && N <= 32);
62667    let n: i32 = if N == 32 { 31 } else { N };
62668    unsafe { simd_shr(a, vdupq_n_s32(n as _)) }
62669}
62670#[doc = "Shift right"]
62671#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s64)"]
62672#[inline]
62673#[target_feature(enable = "neon")]
62674#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62675#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))]
62676#[cfg_attr(
62677    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62678    assert_instr(sshr, N = 2)
62679)]
62680#[rustc_legacy_const_generics(1)]
62681#[cfg_attr(
62682    not(target_arch = "arm"),
62683    stable(feature = "neon_intrinsics", since = "1.59.0")
62684)]
62685#[cfg_attr(
62686    target_arch = "arm",
62687    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62688)]
62689pub fn vshr_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
62690    static_assert!(N >= 1 && N <= 64);
62691    let n: i32 = if N == 64 { 63 } else { N };
62692    unsafe { simd_shr(a, vdup_n_s64(n as _)) }
62693}
62694#[doc = "Shift right"]
62695#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s64)"]
62696#[inline]
62697#[target_feature(enable = "neon")]
62698#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62699#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))]
62700#[cfg_attr(
62701    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62702    assert_instr(sshr, N = 2)
62703)]
62704#[rustc_legacy_const_generics(1)]
62705#[cfg_attr(
62706    not(target_arch = "arm"),
62707    stable(feature = "neon_intrinsics", since = "1.59.0")
62708)]
62709#[cfg_attr(
62710    target_arch = "arm",
62711    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62712)]
62713pub fn vshrq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
62714    static_assert!(N >= 1 && N <= 64);
62715    let n: i32 = if N == 64 { 63 } else { N };
62716    unsafe { simd_shr(a, vdupq_n_s64(n as _)) }
62717}
62718#[doc = "Shift right"]
62719#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u8)"]
62720#[inline]
62721#[target_feature(enable = "neon")]
62722#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62723#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))]
62724#[cfg_attr(
62725    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62726    assert_instr(ushr, N = 2)
62727)]
62728#[rustc_legacy_const_generics(1)]
62729#[cfg_attr(
62730    not(target_arch = "arm"),
62731    stable(feature = "neon_intrinsics", since = "1.59.0")
62732)]
62733#[cfg_attr(
62734    target_arch = "arm",
62735    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62736)]
62737pub fn vshr_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
62738    static_assert!(N >= 1 && N <= 8);
62739    let n: i32 = if N == 8 {
62740        return vdup_n_u8(0);
62741    } else {
62742        N
62743    };
62744    unsafe { simd_shr(a, vdup_n_u8(n as _)) }
62745}
62746#[doc = "Shift right"]
62747#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u8)"]
62748#[inline]
62749#[target_feature(enable = "neon")]
62750#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62751#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))]
62752#[cfg_attr(
62753    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62754    assert_instr(ushr, N = 2)
62755)]
62756#[rustc_legacy_const_generics(1)]
62757#[cfg_attr(
62758    not(target_arch = "arm"),
62759    stable(feature = "neon_intrinsics", since = "1.59.0")
62760)]
62761#[cfg_attr(
62762    target_arch = "arm",
62763    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62764)]
62765pub fn vshrq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
62766    static_assert!(N >= 1 && N <= 8);
62767    let n: i32 = if N == 8 {
62768        return vdupq_n_u8(0);
62769    } else {
62770        N
62771    };
62772    unsafe { simd_shr(a, vdupq_n_u8(n as _)) }
62773}
62774#[doc = "Shift right"]
62775#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u16)"]
62776#[inline]
62777#[target_feature(enable = "neon")]
62778#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62779#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))]
62780#[cfg_attr(
62781    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62782    assert_instr(ushr, N = 2)
62783)]
62784#[rustc_legacy_const_generics(1)]
62785#[cfg_attr(
62786    not(target_arch = "arm"),
62787    stable(feature = "neon_intrinsics", since = "1.59.0")
62788)]
62789#[cfg_attr(
62790    target_arch = "arm",
62791    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62792)]
62793pub fn vshr_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
62794    static_assert!(N >= 1 && N <= 16);
62795    let n: i32 = if N == 16 {
62796        return vdup_n_u16(0);
62797    } else {
62798        N
62799    };
62800    unsafe { simd_shr(a, vdup_n_u16(n as _)) }
62801}
62802#[doc = "Shift right"]
62803#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u16)"]
62804#[inline]
62805#[target_feature(enable = "neon")]
62806#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62807#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))]
62808#[cfg_attr(
62809    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62810    assert_instr(ushr, N = 2)
62811)]
62812#[rustc_legacy_const_generics(1)]
62813#[cfg_attr(
62814    not(target_arch = "arm"),
62815    stable(feature = "neon_intrinsics", since = "1.59.0")
62816)]
62817#[cfg_attr(
62818    target_arch = "arm",
62819    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62820)]
62821pub fn vshrq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
62822    static_assert!(N >= 1 && N <= 16);
62823    let n: i32 = if N == 16 {
62824        return vdupq_n_u16(0);
62825    } else {
62826        N
62827    };
62828    unsafe { simd_shr(a, vdupq_n_u16(n as _)) }
62829}
62830#[doc = "Shift right"]
62831#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u32)"]
62832#[inline]
62833#[target_feature(enable = "neon")]
62834#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62835#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))]
62836#[cfg_attr(
62837    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62838    assert_instr(ushr, N = 2)
62839)]
62840#[rustc_legacy_const_generics(1)]
62841#[cfg_attr(
62842    not(target_arch = "arm"),
62843    stable(feature = "neon_intrinsics", since = "1.59.0")
62844)]
62845#[cfg_attr(
62846    target_arch = "arm",
62847    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62848)]
62849pub fn vshr_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
62850    static_assert!(N >= 1 && N <= 32);
62851    let n: i32 = if N == 32 {
62852        return vdup_n_u32(0);
62853    } else {
62854        N
62855    };
62856    unsafe { simd_shr(a, vdup_n_u32(n as _)) }
62857}
62858#[doc = "Shift right"]
62859#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u32)"]
62860#[inline]
62861#[target_feature(enable = "neon")]
62862#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62863#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))]
62864#[cfg_attr(
62865    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62866    assert_instr(ushr, N = 2)
62867)]
62868#[rustc_legacy_const_generics(1)]
62869#[cfg_attr(
62870    not(target_arch = "arm"),
62871    stable(feature = "neon_intrinsics", since = "1.59.0")
62872)]
62873#[cfg_attr(
62874    target_arch = "arm",
62875    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62876)]
62877pub fn vshrq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
62878    static_assert!(N >= 1 && N <= 32);
62879    let n: i32 = if N == 32 {
62880        return vdupq_n_u32(0);
62881    } else {
62882        N
62883    };
62884    unsafe { simd_shr(a, vdupq_n_u32(n as _)) }
62885}
62886#[doc = "Shift right"]
62887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u64)"]
62888#[inline]
62889#[target_feature(enable = "neon")]
62890#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62891#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))]
62892#[cfg_attr(
62893    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62894    assert_instr(ushr, N = 2)
62895)]
62896#[rustc_legacy_const_generics(1)]
62897#[cfg_attr(
62898    not(target_arch = "arm"),
62899    stable(feature = "neon_intrinsics", since = "1.59.0")
62900)]
62901#[cfg_attr(
62902    target_arch = "arm",
62903    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62904)]
62905pub fn vshr_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
62906    static_assert!(N >= 1 && N <= 64);
62907    let n: i32 = if N == 64 {
62908        return vdup_n_u64(0);
62909    } else {
62910        N
62911    };
62912    unsafe { simd_shr(a, vdup_n_u64(n as _)) }
62913}
62914#[doc = "Shift right"]
62915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u64)"]
62916#[inline]
62917#[target_feature(enable = "neon")]
62918#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62919#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))]
62920#[cfg_attr(
62921    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62922    assert_instr(ushr, N = 2)
62923)]
62924#[rustc_legacy_const_generics(1)]
62925#[cfg_attr(
62926    not(target_arch = "arm"),
62927    stable(feature = "neon_intrinsics", since = "1.59.0")
62928)]
62929#[cfg_attr(
62930    target_arch = "arm",
62931    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62932)]
62933pub fn vshrq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
62934    static_assert!(N >= 1 && N <= 64);
62935    let n: i32 = if N == 64 {
62936        return vdupq_n_u64(0);
62937    } else {
62938        N
62939    };
62940    unsafe { simd_shr(a, vdupq_n_u64(n as _)) }
62941}
62942#[doc = "Shift right narrow"]
62943#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s16)"]
62944#[inline]
62945#[target_feature(enable = "neon")]
62946#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62947#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))]
62948#[cfg_attr(
62949    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62950    assert_instr(shrn, N = 2)
62951)]
62952#[rustc_legacy_const_generics(1)]
62953#[cfg_attr(
62954    not(target_arch = "arm"),
62955    stable(feature = "neon_intrinsics", since = "1.59.0")
62956)]
62957#[cfg_attr(
62958    target_arch = "arm",
62959    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62960)]
62961pub fn vshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
62962    static_assert!(N >= 1 && N <= 8);
62963    unsafe { simd_cast(simd_shr(a, vdupq_n_s16(N as _))) }
62964}
62965#[doc = "Shift right narrow"]
62966#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s32)"]
62967#[inline]
62968#[target_feature(enable = "neon")]
62969#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62970#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))]
62971#[cfg_attr(
62972    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62973    assert_instr(shrn, N = 2)
62974)]
62975#[rustc_legacy_const_generics(1)]
62976#[cfg_attr(
62977    not(target_arch = "arm"),
62978    stable(feature = "neon_intrinsics", since = "1.59.0")
62979)]
62980#[cfg_attr(
62981    target_arch = "arm",
62982    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62983)]
62984pub fn vshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
62985    static_assert!(N >= 1 && N <= 16);
62986    unsafe { simd_cast(simd_shr(a, vdupq_n_s32(N as _))) }
62987}
62988#[doc = "Shift right narrow"]
62989#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s64)"]
62990#[inline]
62991#[target_feature(enable = "neon")]
62992#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62993#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))]
62994#[cfg_attr(
62995    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62996    assert_instr(shrn, N = 2)
62997)]
62998#[rustc_legacy_const_generics(1)]
62999#[cfg_attr(
63000    not(target_arch = "arm"),
63001    stable(feature = "neon_intrinsics", since = "1.59.0")
63002)]
63003#[cfg_attr(
63004    target_arch = "arm",
63005    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63006)]
63007pub fn vshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
63008    static_assert!(N >= 1 && N <= 32);
63009    unsafe { simd_cast(simd_shr(a, vdupq_n_s64(N as _))) }
63010}
63011#[doc = "Shift right narrow"]
63012#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u16)"]
63013#[inline]
63014#[target_feature(enable = "neon")]
63015#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63016#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))]
63017#[cfg_attr(
63018    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63019    assert_instr(shrn, N = 2)
63020)]
63021#[rustc_legacy_const_generics(1)]
63022#[cfg_attr(
63023    not(target_arch = "arm"),
63024    stable(feature = "neon_intrinsics", since = "1.59.0")
63025)]
63026#[cfg_attr(
63027    target_arch = "arm",
63028    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63029)]
63030pub fn vshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
63031    static_assert!(N >= 1 && N <= 8);
63032    unsafe { simd_cast(simd_shr(a, vdupq_n_u16(N as _))) }
63033}
63034#[doc = "Shift right narrow"]
63035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u32)"]
63036#[inline]
63037#[target_feature(enable = "neon")]
63038#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63039#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))]
63040#[cfg_attr(
63041    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63042    assert_instr(shrn, N = 2)
63043)]
63044#[rustc_legacy_const_generics(1)]
63045#[cfg_attr(
63046    not(target_arch = "arm"),
63047    stable(feature = "neon_intrinsics", since = "1.59.0")
63048)]
63049#[cfg_attr(
63050    target_arch = "arm",
63051    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63052)]
63053pub fn vshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
63054    static_assert!(N >= 1 && N <= 16);
63055    unsafe { simd_cast(simd_shr(a, vdupq_n_u32(N as _))) }
63056}
63057#[doc = "Shift right narrow"]
63058#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u64)"]
63059#[inline]
63060#[target_feature(enable = "neon")]
63061#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63062#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))]
63063#[cfg_attr(
63064    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63065    assert_instr(shrn, N = 2)
63066)]
63067#[rustc_legacy_const_generics(1)]
63068#[cfg_attr(
63069    not(target_arch = "arm"),
63070    stable(feature = "neon_intrinsics", since = "1.59.0")
63071)]
63072#[cfg_attr(
63073    target_arch = "arm",
63074    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63075)]
63076pub fn vshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
63077    static_assert!(N >= 1 && N <= 32);
63078    unsafe { simd_cast(simd_shr(a, vdupq_n_u64(N as _))) }
63079}
63080#[doc = "Shift Left and Insert (immediate)"]
63081#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s8)"]
63082#[inline]
63083#[cfg(target_arch = "arm")]
63084#[target_feature(enable = "neon,v7")]
63085#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63086#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
63087#[rustc_legacy_const_generics(2)]
63088pub fn vsli_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
63089    static_assert_uimm_bits!(N, 3);
63090    vshiftins_v8i8(a, b, int8x8_t::splat(N as i8))
63091}
63092#[doc = "Shift Left and Insert (immediate)"]
63093#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s8)"]
63094#[inline]
63095#[cfg(target_arch = "arm")]
63096#[target_feature(enable = "neon,v7")]
63097#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63098#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
63099#[rustc_legacy_const_generics(2)]
63100pub fn vsliq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
63101    static_assert_uimm_bits!(N, 3);
63102    vshiftins_v16i8(a, b, int8x16_t::splat(N as i8))
63103}
63104#[doc = "Shift Left and Insert (immediate)"]
63105#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s16)"]
63106#[inline]
63107#[cfg(target_arch = "arm")]
63108#[target_feature(enable = "neon,v7")]
63109#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63110#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
63111#[rustc_legacy_const_generics(2)]
63112pub fn vsli_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
63113    static_assert_uimm_bits!(N, 4);
63114    vshiftins_v4i16(a, b, int16x4_t::splat(N as i16))
63115}
63116#[doc = "Shift Left and Insert (immediate)"]
63117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s16)"]
63118#[inline]
63119#[cfg(target_arch = "arm")]
63120#[target_feature(enable = "neon,v7")]
63121#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63122#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
63123#[rustc_legacy_const_generics(2)]
63124pub fn vsliq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
63125    static_assert_uimm_bits!(N, 4);
63126    vshiftins_v8i16(a, b, int16x8_t::splat(N as i16))
63127}
63128#[doc = "Shift Left and Insert (immediate)"]
63129#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s32)"]
63130#[inline]
63131#[cfg(target_arch = "arm")]
63132#[target_feature(enable = "neon,v7")]
63133#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63134#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))]
63135#[rustc_legacy_const_generics(2)]
63136pub fn vsli_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
63137    static_assert!(N >= 0 && N <= 31);
63138    vshiftins_v2i32(a, b, int32x2_t::splat(N))
63139}
63140#[doc = "Shift Left and Insert (immediate)"]
63141#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s32)"]
63142#[inline]
63143#[cfg(target_arch = "arm")]
63144#[target_feature(enable = "neon,v7")]
63145#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63146#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))]
63147#[rustc_legacy_const_generics(2)]
63148pub fn vsliq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
63149    static_assert!(N >= 0 && N <= 31);
63150    vshiftins_v4i32(a, b, int32x4_t::splat(N))
63151}
63152#[doc = "Shift Left and Insert (immediate)"]
63153#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s64)"]
63154#[inline]
63155#[cfg(target_arch = "arm")]
63156#[target_feature(enable = "neon,v7")]
63157#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63158#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))]
63159#[rustc_legacy_const_generics(2)]
63160pub fn vsli_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
63161    static_assert!(N >= 0 && N <= 63);
63162    vshiftins_v1i64(a, b, int64x1_t::splat(N as i64))
63163}
63164#[doc = "Shift Left and Insert (immediate)"]
63165#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s64)"]
63166#[inline]
63167#[cfg(target_arch = "arm")]
63168#[target_feature(enable = "neon,v7")]
63169#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63170#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))]
63171#[rustc_legacy_const_generics(2)]
63172pub fn vsliq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
63173    static_assert!(N >= 0 && N <= 63);
63174    vshiftins_v2i64(a, b, int64x2_t::splat(N as i64))
63175}
63176#[doc = "Shift Left and Insert (immediate)"]
63177#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u8)"]
63178#[inline]
63179#[cfg(target_arch = "arm")]
63180#[target_feature(enable = "neon,v7")]
63181#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63182#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
63183#[rustc_legacy_const_generics(2)]
63184pub fn vsli_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
63185    static_assert_uimm_bits!(N, 3);
63186    unsafe {
63187        transmute(vshiftins_v8i8(
63188            transmute(a),
63189            transmute(b),
63190            int8x8_t::splat(N as i8),
63191        ))
63192    }
63193}
63194#[doc = "Shift Left and Insert (immediate)"]
63195#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u8)"]
63196#[inline]
63197#[cfg(target_arch = "arm")]
63198#[target_feature(enable = "neon,v7")]
63199#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63200#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
63201#[rustc_legacy_const_generics(2)]
63202pub fn vsliq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
63203    static_assert_uimm_bits!(N, 3);
63204    unsafe {
63205        transmute(vshiftins_v16i8(
63206            transmute(a),
63207            transmute(b),
63208            int8x16_t::splat(N as i8),
63209        ))
63210    }
63211}
63212#[doc = "Shift Left and Insert (immediate)"]
63213#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u16)"]
63214#[inline]
63215#[cfg(target_arch = "arm")]
63216#[target_feature(enable = "neon,v7")]
63217#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63218#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
63219#[rustc_legacy_const_generics(2)]
63220pub fn vsli_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
63221    static_assert_uimm_bits!(N, 4);
63222    unsafe {
63223        transmute(vshiftins_v4i16(
63224            transmute(a),
63225            transmute(b),
63226            int16x4_t::splat(N as i16),
63227        ))
63228    }
63229}
63230#[doc = "Shift Left and Insert (immediate)"]
63231#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u16)"]
63232#[inline]
63233#[cfg(target_arch = "arm")]
63234#[target_feature(enable = "neon,v7")]
63235#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63236#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
63237#[rustc_legacy_const_generics(2)]
63238pub fn vsliq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
63239    static_assert_uimm_bits!(N, 4);
63240    unsafe {
63241        transmute(vshiftins_v8i16(
63242            transmute(a),
63243            transmute(b),
63244            int16x8_t::splat(N as i16),
63245        ))
63246    }
63247}
63248#[doc = "Shift Left and Insert (immediate)"]
63249#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u32)"]
63250#[inline]
63251#[cfg(target_arch = "arm")]
63252#[target_feature(enable = "neon,v7")]
63253#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63254#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))]
63255#[rustc_legacy_const_generics(2)]
63256pub fn vsli_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
63257    static_assert!(N >= 0 && N <= 31);
63258    unsafe {
63259        transmute(vshiftins_v2i32(
63260            transmute(a),
63261            transmute(b),
63262            int32x2_t::splat(N as i32),
63263        ))
63264    }
63265}
63266#[doc = "Shift Left and Insert (immediate)"]
63267#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u32)"]
63268#[inline]
63269#[cfg(target_arch = "arm")]
63270#[target_feature(enable = "neon,v7")]
63271#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63272#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))]
63273#[rustc_legacy_const_generics(2)]
63274pub fn vsliq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
63275    static_assert!(N >= 0 && N <= 31);
63276    unsafe {
63277        transmute(vshiftins_v4i32(
63278            transmute(a),
63279            transmute(b),
63280            int32x4_t::splat(N as i32),
63281        ))
63282    }
63283}
63284#[doc = "Shift Left and Insert (immediate)"]
63285#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u64)"]
63286#[inline]
63287#[cfg(target_arch = "arm")]
63288#[target_feature(enable = "neon,v7")]
63289#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63290#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))]
63291#[rustc_legacy_const_generics(2)]
63292pub fn vsli_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
63293    static_assert!(N >= 0 && N <= 63);
63294    unsafe {
63295        transmute(vshiftins_v1i64(
63296            transmute(a),
63297            transmute(b),
63298            int64x1_t::splat(N as i64),
63299        ))
63300    }
63301}
63302#[doc = "Shift Left and Insert (immediate)"]
63303#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u64)"]
63304#[inline]
63305#[cfg(target_arch = "arm")]
63306#[target_feature(enable = "neon,v7")]
63307#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63308#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))]
63309#[rustc_legacy_const_generics(2)]
63310pub fn vsliq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
63311    static_assert!(N >= 0 && N <= 63);
63312    unsafe {
63313        transmute(vshiftins_v2i64(
63314            transmute(a),
63315            transmute(b),
63316            int64x2_t::splat(N as i64),
63317        ))
63318    }
63319}
63320#[doc = "Shift Left and Insert (immediate)"]
63321#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p8)"]
63322#[inline]
63323#[cfg(target_arch = "arm")]
63324#[target_feature(enable = "neon,v7")]
63325#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63326#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
63327#[rustc_legacy_const_generics(2)]
63328pub fn vsli_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
63329    static_assert_uimm_bits!(N, 3);
63330    unsafe {
63331        transmute(vshiftins_v8i8(
63332            transmute(a),
63333            transmute(b),
63334            int8x8_t::splat(N as i8),
63335        ))
63336    }
63337}
63338#[doc = "Shift Left and Insert (immediate)"]
63339#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p8)"]
63340#[inline]
63341#[cfg(target_arch = "arm")]
63342#[target_feature(enable = "neon,v7")]
63343#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63344#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
63345#[rustc_legacy_const_generics(2)]
63346pub fn vsliq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
63347    static_assert_uimm_bits!(N, 3);
63348    unsafe {
63349        transmute(vshiftins_v16i8(
63350            transmute(a),
63351            transmute(b),
63352            int8x16_t::splat(N as i8),
63353        ))
63354    }
63355}
63356#[doc = "Shift Left and Insert (immediate)"]
63357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p16)"]
63358#[inline]
63359#[cfg(target_arch = "arm")]
63360#[target_feature(enable = "neon,v7")]
63361#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63362#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
63363#[rustc_legacy_const_generics(2)]
63364pub fn vsli_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
63365    static_assert_uimm_bits!(N, 4);
63366    unsafe {
63367        transmute(vshiftins_v4i16(
63368            transmute(a),
63369            transmute(b),
63370            int16x4_t::splat(N as i16),
63371        ))
63372    }
63373}
63374#[doc = "Shift Left and Insert (immediate)"]
63375#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p16)"]
63376#[inline]
63377#[cfg(target_arch = "arm")]
63378#[target_feature(enable = "neon,v7")]
63379#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63380#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
63381#[rustc_legacy_const_generics(2)]
63382pub fn vsliq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
63383    static_assert_uimm_bits!(N, 4);
63384    unsafe {
63385        transmute(vshiftins_v8i16(
63386            transmute(a),
63387            transmute(b),
63388            int16x8_t::splat(N as i16),
63389        ))
63390    }
63391}
63392#[doc = "Signed shift right and accumulate"]
63393#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s8)"]
63394#[inline]
63395#[target_feature(enable = "neon")]
63396#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63397#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63398#[cfg_attr(
63399    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63400    assert_instr(ssra, N = 2)
63401)]
63402#[rustc_legacy_const_generics(2)]
63403#[cfg_attr(
63404    not(target_arch = "arm"),
63405    stable(feature = "neon_intrinsics", since = "1.59.0")
63406)]
63407#[cfg_attr(
63408    target_arch = "arm",
63409    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63410)]
63411pub fn vsra_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
63412    static_assert!(N >= 1 && N <= 8);
63413    unsafe { simd_add(a, vshr_n_s8::<N>(b)) }
63414}
63415#[doc = "Signed shift right and accumulate"]
63416#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s8)"]
63417#[inline]
63418#[target_feature(enable = "neon")]
63419#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63420#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63421#[cfg_attr(
63422    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63423    assert_instr(ssra, N = 2)
63424)]
63425#[rustc_legacy_const_generics(2)]
63426#[cfg_attr(
63427    not(target_arch = "arm"),
63428    stable(feature = "neon_intrinsics", since = "1.59.0")
63429)]
63430#[cfg_attr(
63431    target_arch = "arm",
63432    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63433)]
63434pub fn vsraq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
63435    static_assert!(N >= 1 && N <= 8);
63436    unsafe { simd_add(a, vshrq_n_s8::<N>(b)) }
63437}
63438#[doc = "Signed shift right and accumulate"]
63439#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s16)"]
63440#[inline]
63441#[target_feature(enable = "neon")]
63442#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63443#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63444#[cfg_attr(
63445    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63446    assert_instr(ssra, N = 2)
63447)]
63448#[rustc_legacy_const_generics(2)]
63449#[cfg_attr(
63450    not(target_arch = "arm"),
63451    stable(feature = "neon_intrinsics", since = "1.59.0")
63452)]
63453#[cfg_attr(
63454    target_arch = "arm",
63455    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63456)]
63457pub fn vsra_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
63458    static_assert!(N >= 1 && N <= 16);
63459    unsafe { simd_add(a, vshr_n_s16::<N>(b)) }
63460}
63461#[doc = "Signed shift right and accumulate"]
63462#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s16)"]
63463#[inline]
63464#[target_feature(enable = "neon")]
63465#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63466#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63467#[cfg_attr(
63468    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63469    assert_instr(ssra, N = 2)
63470)]
63471#[rustc_legacy_const_generics(2)]
63472#[cfg_attr(
63473    not(target_arch = "arm"),
63474    stable(feature = "neon_intrinsics", since = "1.59.0")
63475)]
63476#[cfg_attr(
63477    target_arch = "arm",
63478    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63479)]
63480pub fn vsraq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
63481    static_assert!(N >= 1 && N <= 16);
63482    unsafe { simd_add(a, vshrq_n_s16::<N>(b)) }
63483}
63484#[doc = "Signed shift right and accumulate"]
63485#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s32)"]
63486#[inline]
63487#[target_feature(enable = "neon")]
63488#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63489#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63490#[cfg_attr(
63491    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63492    assert_instr(ssra, N = 2)
63493)]
63494#[rustc_legacy_const_generics(2)]
63495#[cfg_attr(
63496    not(target_arch = "arm"),
63497    stable(feature = "neon_intrinsics", since = "1.59.0")
63498)]
63499#[cfg_attr(
63500    target_arch = "arm",
63501    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63502)]
63503pub fn vsra_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
63504    static_assert!(N >= 1 && N <= 32);
63505    unsafe { simd_add(a, vshr_n_s32::<N>(b)) }
63506}
63507#[doc = "Signed shift right and accumulate"]
63508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s32)"]
63509#[inline]
63510#[target_feature(enable = "neon")]
63511#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63512#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63513#[cfg_attr(
63514    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63515    assert_instr(ssra, N = 2)
63516)]
63517#[rustc_legacy_const_generics(2)]
63518#[cfg_attr(
63519    not(target_arch = "arm"),
63520    stable(feature = "neon_intrinsics", since = "1.59.0")
63521)]
63522#[cfg_attr(
63523    target_arch = "arm",
63524    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63525)]
63526pub fn vsraq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
63527    static_assert!(N >= 1 && N <= 32);
63528    unsafe { simd_add(a, vshrq_n_s32::<N>(b)) }
63529}
63530#[doc = "Signed shift right and accumulate"]
63531#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s64)"]
63532#[inline]
63533#[target_feature(enable = "neon")]
63534#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63535#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63536#[cfg_attr(
63537    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63538    assert_instr(ssra, N = 2)
63539)]
63540#[rustc_legacy_const_generics(2)]
63541#[cfg_attr(
63542    not(target_arch = "arm"),
63543    stable(feature = "neon_intrinsics", since = "1.59.0")
63544)]
63545#[cfg_attr(
63546    target_arch = "arm",
63547    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63548)]
63549pub fn vsra_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
63550    static_assert!(N >= 1 && N <= 64);
63551    unsafe { simd_add(a, vshr_n_s64::<N>(b)) }
63552}
63553#[doc = "Signed shift right and accumulate"]
63554#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s64)"]
63555#[inline]
63556#[target_feature(enable = "neon")]
63557#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63558#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63559#[cfg_attr(
63560    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63561    assert_instr(ssra, N = 2)
63562)]
63563#[rustc_legacy_const_generics(2)]
63564#[cfg_attr(
63565    not(target_arch = "arm"),
63566    stable(feature = "neon_intrinsics", since = "1.59.0")
63567)]
63568#[cfg_attr(
63569    target_arch = "arm",
63570    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63571)]
63572pub fn vsraq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
63573    static_assert!(N >= 1 && N <= 64);
63574    unsafe { simd_add(a, vshrq_n_s64::<N>(b)) }
63575}
63576#[doc = "Unsigned shift right and accumulate"]
63577#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u8)"]
63578#[inline]
63579#[target_feature(enable = "neon")]
63580#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63581#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63582#[cfg_attr(
63583    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63584    assert_instr(usra, N = 2)
63585)]
63586#[rustc_legacy_const_generics(2)]
63587#[cfg_attr(
63588    not(target_arch = "arm"),
63589    stable(feature = "neon_intrinsics", since = "1.59.0")
63590)]
63591#[cfg_attr(
63592    target_arch = "arm",
63593    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63594)]
63595pub fn vsra_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
63596    static_assert!(N >= 1 && N <= 8);
63597    unsafe { simd_add(a, vshr_n_u8::<N>(b)) }
63598}
63599#[doc = "Unsigned shift right and accumulate"]
63600#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u8)"]
63601#[inline]
63602#[target_feature(enable = "neon")]
63603#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63604#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63605#[cfg_attr(
63606    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63607    assert_instr(usra, N = 2)
63608)]
63609#[rustc_legacy_const_generics(2)]
63610#[cfg_attr(
63611    not(target_arch = "arm"),
63612    stable(feature = "neon_intrinsics", since = "1.59.0")
63613)]
63614#[cfg_attr(
63615    target_arch = "arm",
63616    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63617)]
63618pub fn vsraq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
63619    static_assert!(N >= 1 && N <= 8);
63620    unsafe { simd_add(a, vshrq_n_u8::<N>(b)) }
63621}
63622#[doc = "Unsigned shift right and accumulate"]
63623#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u16)"]
63624#[inline]
63625#[target_feature(enable = "neon")]
63626#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63627#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63628#[cfg_attr(
63629    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63630    assert_instr(usra, N = 2)
63631)]
63632#[rustc_legacy_const_generics(2)]
63633#[cfg_attr(
63634    not(target_arch = "arm"),
63635    stable(feature = "neon_intrinsics", since = "1.59.0")
63636)]
63637#[cfg_attr(
63638    target_arch = "arm",
63639    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63640)]
63641pub fn vsra_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
63642    static_assert!(N >= 1 && N <= 16);
63643    unsafe { simd_add(a, vshr_n_u16::<N>(b)) }
63644}
63645#[doc = "Unsigned shift right and accumulate"]
63646#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u16)"]
63647#[inline]
63648#[target_feature(enable = "neon")]
63649#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63650#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63651#[cfg_attr(
63652    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63653    assert_instr(usra, N = 2)
63654)]
63655#[rustc_legacy_const_generics(2)]
63656#[cfg_attr(
63657    not(target_arch = "arm"),
63658    stable(feature = "neon_intrinsics", since = "1.59.0")
63659)]
63660#[cfg_attr(
63661    target_arch = "arm",
63662    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63663)]
63664pub fn vsraq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
63665    static_assert!(N >= 1 && N <= 16);
63666    unsafe { simd_add(a, vshrq_n_u16::<N>(b)) }
63667}
63668#[doc = "Unsigned shift right and accumulate"]
63669#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u32)"]
63670#[inline]
63671#[target_feature(enable = "neon")]
63672#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63673#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63674#[cfg_attr(
63675    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63676    assert_instr(usra, N = 2)
63677)]
63678#[rustc_legacy_const_generics(2)]
63679#[cfg_attr(
63680    not(target_arch = "arm"),
63681    stable(feature = "neon_intrinsics", since = "1.59.0")
63682)]
63683#[cfg_attr(
63684    target_arch = "arm",
63685    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63686)]
63687pub fn vsra_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
63688    static_assert!(N >= 1 && N <= 32);
63689    unsafe { simd_add(a, vshr_n_u32::<N>(b)) }
63690}
63691#[doc = "Unsigned shift right and accumulate"]
63692#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u32)"]
63693#[inline]
63694#[target_feature(enable = "neon")]
63695#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63696#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63697#[cfg_attr(
63698    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63699    assert_instr(usra, N = 2)
63700)]
63701#[rustc_legacy_const_generics(2)]
63702#[cfg_attr(
63703    not(target_arch = "arm"),
63704    stable(feature = "neon_intrinsics", since = "1.59.0")
63705)]
63706#[cfg_attr(
63707    target_arch = "arm",
63708    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63709)]
63710pub fn vsraq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
63711    static_assert!(N >= 1 && N <= 32);
63712    unsafe { simd_add(a, vshrq_n_u32::<N>(b)) }
63713}
63714#[doc = "Unsigned shift right and accumulate"]
63715#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u64)"]
63716#[inline]
63717#[target_feature(enable = "neon")]
63718#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63719#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63720#[cfg_attr(
63721    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63722    assert_instr(usra, N = 2)
63723)]
63724#[rustc_legacy_const_generics(2)]
63725#[cfg_attr(
63726    not(target_arch = "arm"),
63727    stable(feature = "neon_intrinsics", since = "1.59.0")
63728)]
63729#[cfg_attr(
63730    target_arch = "arm",
63731    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63732)]
63733pub fn vsra_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
63734    static_assert!(N >= 1 && N <= 64);
63735    unsafe { simd_add(a, vshr_n_u64::<N>(b)) }
63736}
63737#[doc = "Unsigned shift right and accumulate"]
63738#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u64)"]
63739#[inline]
63740#[target_feature(enable = "neon")]
63741#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63742#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63743#[cfg_attr(
63744    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63745    assert_instr(usra, N = 2)
63746)]
63747#[rustc_legacy_const_generics(2)]
63748#[cfg_attr(
63749    not(target_arch = "arm"),
63750    stable(feature = "neon_intrinsics", since = "1.59.0")
63751)]
63752#[cfg_attr(
63753    target_arch = "arm",
63754    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63755)]
63756pub fn vsraq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
63757    static_assert!(N >= 1 && N <= 64);
63758    unsafe { simd_add(a, vshrq_n_u64::<N>(b)) }
63759}
63760#[doc = "Shift Right and Insert (immediate)"]
63761#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s8)"]
63762#[inline]
63763#[target_feature(enable = "neon,v7")]
63764#[cfg(target_arch = "arm")]
63765#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63766#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
63767#[rustc_legacy_const_generics(2)]
63768pub fn vsri_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
63769    static_assert!(1 <= N && N <= 8);
63770    vshiftins_v8i8(a, b, int8x8_t::splat(-N as i8))
63771}
63772#[doc = "Shift Right and Insert (immediate)"]
63773#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)"]
63774#[inline]
63775#[target_feature(enable = "neon,v7")]
63776#[cfg(target_arch = "arm")]
63777#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63778#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
63779#[rustc_legacy_const_generics(2)]
63780pub fn vsriq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
63781    static_assert!(1 <= N && N <= 8);
63782    vshiftins_v16i8(a, b, int8x16_t::splat(-N as i8))
63783}
63784#[doc = "Shift Right and Insert (immediate)"]
63785#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)"]
63786#[inline]
63787#[target_feature(enable = "neon,v7")]
63788#[cfg(target_arch = "arm")]
63789#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63790#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
63791#[rustc_legacy_const_generics(2)]
63792pub fn vsri_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
63793    static_assert!(1 <= N && N <= 16);
63794    vshiftins_v4i16(a, b, int16x4_t::splat(-N as i16))
63795}
63796#[doc = "Shift Right and Insert (immediate)"]
63797#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)"]
63798#[inline]
63799#[target_feature(enable = "neon,v7")]
63800#[cfg(target_arch = "arm")]
63801#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63802#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
63803#[rustc_legacy_const_generics(2)]
63804pub fn vsriq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
63805    static_assert!(1 <= N && N <= 16);
63806    vshiftins_v8i16(a, b, int16x8_t::splat(-N as i16))
63807}
63808#[doc = "Shift Right and Insert (immediate)"]
63809#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)"]
63810#[inline]
63811#[target_feature(enable = "neon,v7")]
63812#[cfg(target_arch = "arm")]
63813#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63814#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))]
63815#[rustc_legacy_const_generics(2)]
63816pub fn vsri_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
63817    static_assert!(1 <= N && N <= 32);
63818    vshiftins_v2i32(a, b, int32x2_t::splat(-N as i32))
63819}
63820#[doc = "Shift Right and Insert (immediate)"]
63821#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"]
63822#[inline]
63823#[target_feature(enable = "neon,v7")]
63824#[cfg(target_arch = "arm")]
63825#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63826#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))]
63827#[rustc_legacy_const_generics(2)]
63828pub fn vsriq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
63829    static_assert!(1 <= N && N <= 32);
63830    vshiftins_v4i32(a, b, int32x4_t::splat(-N as i32))
63831}
63832#[doc = "Shift Right and Insert (immediate)"]
63833#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"]
63834#[inline]
63835#[target_feature(enable = "neon,v7")]
63836#[cfg(target_arch = "arm")]
63837#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63838#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))]
63839#[rustc_legacy_const_generics(2)]
63840pub fn vsri_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
63841    static_assert!(1 <= N && N <= 64);
63842    vshiftins_v1i64(a, b, int64x1_t::splat(-N as i64))
63843}
63844#[doc = "Shift Right and Insert (immediate)"]
63845#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)"]
63846#[inline]
63847#[target_feature(enable = "neon,v7")]
63848#[cfg(target_arch = "arm")]
63849#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63850#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))]
63851#[rustc_legacy_const_generics(2)]
63852pub fn vsriq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
63853    static_assert!(1 <= N && N <= 64);
63854    vshiftins_v2i64(a, b, int64x2_t::splat(-N as i64))
63855}
63856#[doc = "Shift Right and Insert (immediate)"]
63857#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)"]
63858#[inline]
63859#[cfg(target_arch = "arm")]
63860#[target_feature(enable = "neon,v7")]
63861#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63862#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
63863#[rustc_legacy_const_generics(2)]
63864pub fn vsri_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
63865    static_assert!(1 <= N && N <= 8);
63866    unsafe {
63867        transmute(vshiftins_v8i8(
63868            transmute(a),
63869            transmute(b),
63870            int8x8_t::splat(-N as i8),
63871        ))
63872    }
63873}
63874#[doc = "Shift Right and Insert (immediate)"]
63875#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u8)"]
63876#[inline]
63877#[cfg(target_arch = "arm")]
63878#[target_feature(enable = "neon,v7")]
63879#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63880#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
63881#[rustc_legacy_const_generics(2)]
63882pub fn vsriq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
63883    static_assert!(1 <= N && N <= 8);
63884    unsafe {
63885        transmute(vshiftins_v16i8(
63886            transmute(a),
63887            transmute(b),
63888            int8x16_t::splat(-N as i8),
63889        ))
63890    }
63891}
63892#[doc = "Shift Right and Insert (immediate)"]
63893#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u16)"]
63894#[inline]
63895#[cfg(target_arch = "arm")]
63896#[target_feature(enable = "neon,v7")]
63897#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63898#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
63899#[rustc_legacy_const_generics(2)]
63900pub fn vsri_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
63901    static_assert!(1 <= N && N <= 16);
63902    unsafe {
63903        transmute(vshiftins_v4i16(
63904            transmute(a),
63905            transmute(b),
63906            int16x4_t::splat(-N as i16),
63907        ))
63908    }
63909}
63910#[doc = "Shift Right and Insert (immediate)"]
63911#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u16)"]
63912#[inline]
63913#[cfg(target_arch = "arm")]
63914#[target_feature(enable = "neon,v7")]
63915#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63916#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
63917#[rustc_legacy_const_generics(2)]
63918pub fn vsriq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
63919    static_assert!(1 <= N && N <= 16);
63920    unsafe {
63921        transmute(vshiftins_v8i16(
63922            transmute(a),
63923            transmute(b),
63924            int16x8_t::splat(-N as i16),
63925        ))
63926    }
63927}
63928#[doc = "Shift Right and Insert (immediate)"]
63929#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u32)"]
63930#[inline]
63931#[cfg(target_arch = "arm")]
63932#[target_feature(enable = "neon,v7")]
63933#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63934#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))]
63935#[rustc_legacy_const_generics(2)]
63936pub fn vsri_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
63937    static_assert!(1 <= N && N <= 32);
63938    unsafe {
63939        transmute(vshiftins_v2i32(
63940            transmute(a),
63941            transmute(b),
63942            int32x2_t::splat(-N),
63943        ))
63944    }
63945}
63946#[doc = "Shift Right and Insert (immediate)"]
63947#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u32)"]
63948#[inline]
63949#[cfg(target_arch = "arm")]
63950#[target_feature(enable = "neon,v7")]
63951#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63952#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))]
63953#[rustc_legacy_const_generics(2)]
63954pub fn vsriq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
63955    static_assert!(1 <= N && N <= 32);
63956    unsafe {
63957        transmute(vshiftins_v4i32(
63958            transmute(a),
63959            transmute(b),
63960            int32x4_t::splat(-N),
63961        ))
63962    }
63963}
63964#[doc = "Shift Right and Insert (immediate)"]
63965#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u64)"]
63966#[inline]
63967#[cfg(target_arch = "arm")]
63968#[target_feature(enable = "neon,v7")]
63969#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63970#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))]
63971#[rustc_legacy_const_generics(2)]
63972pub fn vsri_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
63973    static_assert!(1 <= N && N <= 64);
63974    unsafe {
63975        transmute(vshiftins_v1i64(
63976            transmute(a),
63977            transmute(b),
63978            int64x1_t::splat(-N as i64),
63979        ))
63980    }
63981}
63982#[doc = "Shift Right and Insert (immediate)"]
63983#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u64)"]
63984#[inline]
63985#[cfg(target_arch = "arm")]
63986#[target_feature(enable = "neon,v7")]
63987#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63988#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))]
63989#[rustc_legacy_const_generics(2)]
63990pub fn vsriq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
63991    static_assert!(1 <= N && N <= 64);
63992    unsafe {
63993        transmute(vshiftins_v2i64(
63994            transmute(a),
63995            transmute(b),
63996            int64x2_t::splat(-N as i64),
63997        ))
63998    }
63999}
64000#[doc = "Shift Right and Insert (immediate)"]
64001#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p8)"]
64002#[inline]
64003#[cfg(target_arch = "arm")]
64004#[target_feature(enable = "neon,v7")]
64005#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64006#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
64007#[rustc_legacy_const_generics(2)]
64008pub fn vsri_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
64009    static_assert!(1 <= N && N <= 8);
64010    unsafe {
64011        transmute(vshiftins_v8i8(
64012            transmute(a),
64013            transmute(b),
64014            int8x8_t::splat(-N as i8),
64015        ))
64016    }
64017}
64018#[doc = "Shift Right and Insert (immediate)"]
64019#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p8)"]
64020#[inline]
64021#[cfg(target_arch = "arm")]
64022#[target_feature(enable = "neon,v7")]
64023#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64024#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
64025#[rustc_legacy_const_generics(2)]
64026pub fn vsriq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
64027    static_assert!(1 <= N && N <= 8);
64028    unsafe {
64029        transmute(vshiftins_v16i8(
64030            transmute(a),
64031            transmute(b),
64032            int8x16_t::splat(-N as i8),
64033        ))
64034    }
64035}
64036#[doc = "Shift Right and Insert (immediate)"]
64037#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p16)"]
64038#[inline]
64039#[cfg(target_arch = "arm")]
64040#[target_feature(enable = "neon,v7")]
64041#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64042#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
64043#[rustc_legacy_const_generics(2)]
64044pub fn vsri_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
64045    static_assert!(1 <= N && N <= 16);
64046    unsafe {
64047        transmute(vshiftins_v4i16(
64048            transmute(a),
64049            transmute(b),
64050            int16x4_t::splat(-N as i16),
64051        ))
64052    }
64053}
64054#[doc = "Shift Right and Insert (immediate)"]
64055#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p16)"]
64056#[inline]
64057#[cfg(target_arch = "arm")]
64058#[target_feature(enable = "neon,v7")]
64059#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64060#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
64061#[rustc_legacy_const_generics(2)]
64062pub fn vsriq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
64063    static_assert!(1 <= N && N <= 16);
64064    unsafe {
64065        transmute(vshiftins_v8i16(
64066            transmute(a),
64067            transmute(b),
64068            int16x8_t::splat(-N as i16),
64069        ))
64070    }
64071}
64072#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64073#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"]
64074#[doc = "## Safety"]
64075#[doc = "  * Neon instrinsic unsafe"]
64076#[inline]
64077#[cfg(target_arch = "arm")]
64078#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64079#[target_feature(enable = "neon,fp16")]
64080#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64081#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64082pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) {
64083    vst1_v4f16(
64084        ptr as *const i8,
64085        transmute(a),
64086        crate::mem::align_of::<f16>() as i32,
64087    )
64088}
64089#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64090#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"]
64091#[doc = "## Safety"]
64092#[doc = "  * Neon instrinsic unsafe"]
64093#[inline]
64094#[cfg(target_arch = "arm")]
64095#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64096#[target_feature(enable = "neon,fp16")]
64097#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64098#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64099pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) {
64100    vst1q_v8f16(
64101        ptr as *const i8,
64102        transmute(a),
64103        crate::mem::align_of::<f16>() as i32,
64104    )
64105}
64106#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64107#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"]
64108#[doc = "## Safety"]
64109#[doc = "  * Neon instrinsic unsafe"]
64110#[inline]
64111#[cfg(target_arch = "arm")]
64112#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64113#[cfg_attr(test, assert_instr(vst1))]
64114#[target_feature(enable = "neon,fp16")]
64115#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64116pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) {
64117    unsafe extern "unadjusted" {
64118        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0.v4f16")]
64119        fn _vst1_f16_x2(ptr: *mut f16, a: float16x4_t, b: float16x4_t);
64120    }
64121    _vst1_f16_x2(a, b.0, b.1)
64122}
64123#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64124#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"]
64125#[doc = "## Safety"]
64126#[doc = "  * Neon instrinsic unsafe"]
64127#[inline]
64128#[cfg(target_arch = "arm")]
64129#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64130#[cfg_attr(test, assert_instr(vst1))]
64131#[target_feature(enable = "neon,fp16")]
64132#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64133pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) {
64134    unsafe extern "unadjusted" {
64135        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0.v8f16")]
64136        fn _vst1q_f16_x2(ptr: *mut f16, a: float16x8_t, b: float16x8_t);
64137    }
64138    _vst1q_f16_x2(a, b.0, b.1)
64139}
64140#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64141#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"]
64142#[doc = "## Safety"]
64143#[doc = "  * Neon instrinsic unsafe"]
64144#[inline]
64145#[cfg(not(target_arch = "arm"))]
64146#[cfg_attr(test, assert_instr(st1))]
64147#[target_feature(enable = "neon,fp16")]
64148#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64149pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) {
64150    unsafe extern "unadjusted" {
64151        #[cfg_attr(
64152            any(target_arch = "aarch64", target_arch = "arm64ec"),
64153            link_name = "llvm.aarch64.neon.st1x2.v4f16.p0"
64154        )]
64155        fn _vst1_f16_x2(a: float16x4_t, b: float16x4_t, ptr: *mut f16);
64156    }
64157    _vst1_f16_x2(b.0, b.1, a)
64158}
64159#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64160#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"]
64161#[doc = "## Safety"]
64162#[doc = "  * Neon instrinsic unsafe"]
64163#[inline]
64164#[cfg(not(target_arch = "arm"))]
64165#[cfg_attr(test, assert_instr(st1))]
64166#[target_feature(enable = "neon,fp16")]
64167#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64168pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) {
64169    unsafe extern "unadjusted" {
64170        #[cfg_attr(
64171            any(target_arch = "aarch64", target_arch = "arm64ec"),
64172            link_name = "llvm.aarch64.neon.st1x2.v8f16.p0"
64173        )]
64174        fn _vst1q_f16_x2(a: float16x8_t, b: float16x8_t, ptr: *mut f16);
64175    }
64176    _vst1q_f16_x2(b.0, b.1, a)
64177}
64178#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"]
64180#[doc = "## Safety"]
64181#[doc = "  * Neon instrinsic unsafe"]
64182#[inline]
64183#[cfg(target_arch = "arm")]
64184#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64185#[cfg_attr(test, assert_instr(vst1))]
64186#[target_feature(enable = "neon,fp16")]
64187#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64188pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) {
64189    unsafe extern "unadjusted" {
64190        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0.v4f16")]
64191        fn _vst1_f16_x3(ptr: *mut f16, a: float16x4_t, b: float16x4_t, c: float16x4_t);
64192    }
64193    _vst1_f16_x3(a, b.0, b.1, b.2)
64194}
64195#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64196#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"]
64197#[doc = "## Safety"]
64198#[doc = "  * Neon instrinsic unsafe"]
64199#[inline]
64200#[cfg(target_arch = "arm")]
64201#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64202#[cfg_attr(test, assert_instr(vst1))]
64203#[target_feature(enable = "neon,fp16")]
64204#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64205pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) {
64206    unsafe extern "unadjusted" {
64207        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0.v8f16")]
64208        fn _vst1q_f16_x3(ptr: *mut f16, a: float16x8_t, b: float16x8_t, c: float16x8_t);
64209    }
64210    _vst1q_f16_x3(a, b.0, b.1, b.2)
64211}
64212#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64213#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"]
64214#[doc = "## Safety"]
64215#[doc = "  * Neon instrinsic unsafe"]
64216#[inline]
64217#[cfg(not(target_arch = "arm"))]
64218#[cfg_attr(test, assert_instr(st1))]
64219#[target_feature(enable = "neon,fp16")]
64220#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64221pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) {
64222    unsafe extern "unadjusted" {
64223        #[cfg_attr(
64224            any(target_arch = "aarch64", target_arch = "arm64ec"),
64225            link_name = "llvm.aarch64.neon.st1x3.v4f16.p0"
64226        )]
64227        fn _vst1_f16_x3(a: float16x4_t, b: float16x4_t, c: float16x4_t, ptr: *mut f16);
64228    }
64229    _vst1_f16_x3(b.0, b.1, b.2, a)
64230}
64231#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64232#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"]
64233#[doc = "## Safety"]
64234#[doc = "  * Neon instrinsic unsafe"]
64235#[inline]
64236#[cfg(not(target_arch = "arm"))]
64237#[cfg_attr(test, assert_instr(st1))]
64238#[target_feature(enable = "neon,fp16")]
64239#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64240pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) {
64241    unsafe extern "unadjusted" {
64242        #[cfg_attr(
64243            any(target_arch = "aarch64", target_arch = "arm64ec"),
64244            link_name = "llvm.aarch64.neon.st1x3.v8f16.p0"
64245        )]
64246        fn _vst1q_f16_x3(a: float16x8_t, b: float16x8_t, c: float16x8_t, ptr: *mut f16);
64247    }
64248    _vst1q_f16_x3(b.0, b.1, b.2, a)
64249}
64250#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"]
64252#[doc = "## Safety"]
64253#[doc = "  * Neon instrinsic unsafe"]
64254#[inline]
64255#[cfg(target_arch = "arm")]
64256#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64257#[target_feature(enable = "neon,fp16")]
64258#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64259#[cfg_attr(test, assert_instr(vst1))]
64260pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) {
64261    unsafe extern "unadjusted" {
64262        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v4f16")]
64263        fn _vst1_f16_x4(
64264            ptr: *mut f16,
64265            a: float16x4_t,
64266            b: float16x4_t,
64267            c: float16x4_t,
64268            d: float16x4_t,
64269        );
64270    }
64271    _vst1_f16_x4(a, b.0, b.1, b.2, b.3)
64272}
64273#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64274#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"]
64275#[doc = "## Safety"]
64276#[doc = "  * Neon instrinsic unsafe"]
64277#[inline]
64278#[cfg(target_arch = "arm")]
64279#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64280#[target_feature(enable = "neon,fp16")]
64281#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64282#[cfg_attr(test, assert_instr(vst1))]
64283pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) {
64284    unsafe extern "unadjusted" {
64285        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v8f16")]
64286        fn _vst1q_f16_x4(
64287            ptr: *mut f16,
64288            a: float16x8_t,
64289            b: float16x8_t,
64290            c: float16x8_t,
64291            d: float16x8_t,
64292        );
64293    }
64294    _vst1q_f16_x4(a, b.0, b.1, b.2, b.3)
64295}
64296#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64297#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"]
64298#[doc = "## Safety"]
64299#[doc = "  * Neon instrinsic unsafe"]
64300#[inline]
64301#[cfg(not(target_arch = "arm"))]
64302#[cfg_attr(test, assert_instr(st1))]
64303#[target_feature(enable = "neon,fp16")]
64304#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64305pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) {
64306    unsafe extern "unadjusted" {
64307        #[cfg_attr(
64308            any(target_arch = "aarch64", target_arch = "arm64ec"),
64309            link_name = "llvm.aarch64.neon.st1x4.v4f16.p0"
64310        )]
64311        fn _vst1_f16_x4(
64312            a: float16x4_t,
64313            b: float16x4_t,
64314            c: float16x4_t,
64315            d: float16x4_t,
64316            ptr: *mut f16,
64317        );
64318    }
64319    _vst1_f16_x4(b.0, b.1, b.2, b.3, a)
64320}
64321#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"]
64323#[doc = "## Safety"]
64324#[doc = "  * Neon instrinsic unsafe"]
64325#[inline]
64326#[cfg(not(target_arch = "arm"))]
64327#[cfg_attr(test, assert_instr(st1))]
64328#[target_feature(enable = "neon,fp16")]
64329#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64330pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) {
64331    unsafe extern "unadjusted" {
64332        #[cfg_attr(
64333            any(target_arch = "aarch64", target_arch = "arm64ec"),
64334            link_name = "llvm.aarch64.neon.st1x4.v8f16.p0"
64335        )]
64336        fn _vst1q_f16_x4(
64337            a: float16x8_t,
64338            b: float16x8_t,
64339            c: float16x8_t,
64340            d: float16x8_t,
64341            ptr: *mut f16,
64342        );
64343    }
64344    _vst1q_f16_x4(b.0, b.1, b.2, b.3, a)
64345}
64346#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64347#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"]
64348#[doc = "## Safety"]
64349#[doc = "  * Neon instrinsic unsafe"]
64350#[inline]
64351#[target_feature(enable = "neon")]
64352#[cfg(target_arch = "arm")]
64353#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64354#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64355#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
64356pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) {
64357    vst1_v2f32(
64358        ptr as *const i8,
64359        transmute(a),
64360        crate::mem::align_of::<f32>() as i32,
64361    )
64362}
64363#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"]
64365#[doc = "## Safety"]
64366#[doc = "  * Neon instrinsic unsafe"]
64367#[inline]
64368#[target_feature(enable = "neon")]
64369#[cfg(target_arch = "arm")]
64370#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64371#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64372#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
64373pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) {
64374    vst1q_v4f32(
64375        ptr as *const i8,
64376        transmute(a),
64377        crate::mem::align_of::<f32>() as i32,
64378    )
64379}
64380#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64381#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"]
64382#[doc = "## Safety"]
64383#[doc = "  * Neon instrinsic unsafe"]
64384#[inline]
64385#[target_feature(enable = "neon")]
64386#[cfg(target_arch = "arm")]
64387#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64388#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64389#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64390pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) {
64391    vst1_v8i8(ptr as *const i8, a, crate::mem::align_of::<i8>() as i32)
64392}
64393#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"]
64395#[doc = "## Safety"]
64396#[doc = "  * Neon instrinsic unsafe"]
64397#[inline]
64398#[target_feature(enable = "neon")]
64399#[cfg(target_arch = "arm")]
64400#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64401#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64402#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64403pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) {
64404    vst1q_v16i8(ptr as *const i8, a, crate::mem::align_of::<i8>() as i32)
64405}
64406#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64407#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"]
64408#[doc = "## Safety"]
64409#[doc = "  * Neon instrinsic unsafe"]
64410#[inline]
64411#[target_feature(enable = "neon")]
64412#[cfg(target_arch = "arm")]
64413#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64414#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64415#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64416pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) {
64417    vst1_v4i16(ptr as *const i8, a, crate::mem::align_of::<i16>() as i32)
64418}
64419#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64420#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"]
64421#[doc = "## Safety"]
64422#[doc = "  * Neon instrinsic unsafe"]
64423#[inline]
64424#[target_feature(enable = "neon")]
64425#[cfg(target_arch = "arm")]
64426#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64427#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64428#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64429pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) {
64430    vst1q_v8i16(ptr as *const i8, a, crate::mem::align_of::<i16>() as i32)
64431}
64432#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64433#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"]
64434#[doc = "## Safety"]
64435#[doc = "  * Neon instrinsic unsafe"]
64436#[inline]
64437#[target_feature(enable = "neon")]
64438#[cfg(target_arch = "arm")]
64439#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64440#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64441#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
64442pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) {
64443    vst1_v2i32(ptr as *const i8, a, crate::mem::align_of::<i32>() as i32)
64444}
64445#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64446#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"]
64447#[doc = "## Safety"]
64448#[doc = "  * Neon instrinsic unsafe"]
64449#[inline]
64450#[target_feature(enable = "neon")]
64451#[cfg(target_arch = "arm")]
64452#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64453#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64454#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
64455pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) {
64456    vst1q_v4i32(ptr as *const i8, a, crate::mem::align_of::<i32>() as i32)
64457}
64458#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64459#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"]
64460#[doc = "## Safety"]
64461#[doc = "  * Neon instrinsic unsafe"]
64462#[inline]
64463#[target_feature(enable = "neon")]
64464#[cfg(target_arch = "arm")]
64465#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64466#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64467#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64468pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) {
64469    vst1_v1i64(ptr as *const i8, a, crate::mem::align_of::<i64>() as i32)
64470}
64471#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64472#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"]
64473#[doc = "## Safety"]
64474#[doc = "  * Neon instrinsic unsafe"]
64475#[inline]
64476#[target_feature(enable = "neon")]
64477#[cfg(target_arch = "arm")]
64478#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64479#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64480#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64481pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) {
64482    vst1q_v2i64(ptr as *const i8, a, crate::mem::align_of::<i64>() as i32)
64483}
64484#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64485#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"]
64486#[doc = "## Safety"]
64487#[doc = "  * Neon instrinsic unsafe"]
64488#[inline]
64489#[target_feature(enable = "neon")]
64490#[cfg(target_arch = "arm")]
64491#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64492#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64493#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64494pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) {
64495    vst1_v8i8(
64496        ptr as *const i8,
64497        transmute(a),
64498        crate::mem::align_of::<u8>() as i32,
64499    )
64500}
64501#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64502#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"]
64503#[doc = "## Safety"]
64504#[doc = "  * Neon instrinsic unsafe"]
64505#[inline]
64506#[target_feature(enable = "neon")]
64507#[cfg(target_arch = "arm")]
64508#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64509#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64510#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64511pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) {
64512    vst1q_v16i8(
64513        ptr as *const i8,
64514        transmute(a),
64515        crate::mem::align_of::<u8>() as i32,
64516    )
64517}
64518#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64519#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"]
64520#[doc = "## Safety"]
64521#[doc = "  * Neon instrinsic unsafe"]
64522#[inline]
64523#[target_feature(enable = "neon")]
64524#[cfg(target_arch = "arm")]
64525#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64526#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64527#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64528pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) {
64529    vst1_v4i16(
64530        ptr as *const i8,
64531        transmute(a),
64532        crate::mem::align_of::<u16>() as i32,
64533    )
64534}
64535#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64536#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"]
64537#[doc = "## Safety"]
64538#[doc = "  * Neon instrinsic unsafe"]
64539#[inline]
64540#[target_feature(enable = "neon")]
64541#[cfg(target_arch = "arm")]
64542#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64543#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64544#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64545pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) {
64546    vst1q_v8i16(
64547        ptr as *const i8,
64548        transmute(a),
64549        crate::mem::align_of::<u16>() as i32,
64550    )
64551}
64552#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64553#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"]
64554#[doc = "## Safety"]
64555#[doc = "  * Neon instrinsic unsafe"]
64556#[inline]
64557#[target_feature(enable = "neon")]
64558#[cfg(target_arch = "arm")]
64559#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64560#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64561#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
64562pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) {
64563    vst1_v2i32(
64564        ptr as *const i8,
64565        transmute(a),
64566        crate::mem::align_of::<u32>() as i32,
64567    )
64568}
64569#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64570#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"]
64571#[doc = "## Safety"]
64572#[doc = "  * Neon instrinsic unsafe"]
64573#[inline]
64574#[target_feature(enable = "neon")]
64575#[cfg(target_arch = "arm")]
64576#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64577#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64578#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
64579pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) {
64580    vst1q_v4i32(
64581        ptr as *const i8,
64582        transmute(a),
64583        crate::mem::align_of::<u32>() as i32,
64584    )
64585}
64586#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64587#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"]
64588#[doc = "## Safety"]
64589#[doc = "  * Neon instrinsic unsafe"]
64590#[inline]
64591#[target_feature(enable = "neon")]
64592#[cfg(target_arch = "arm")]
64593#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64594#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64595#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64596pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) {
64597    vst1_v1i64(
64598        ptr as *const i8,
64599        transmute(a),
64600        crate::mem::align_of::<u64>() as i32,
64601    )
64602}
64603#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64604#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"]
64605#[doc = "## Safety"]
64606#[doc = "  * Neon instrinsic unsafe"]
64607#[inline]
64608#[target_feature(enable = "neon")]
64609#[cfg(target_arch = "arm")]
64610#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64611#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64612#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64613pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) {
64614    vst1q_v2i64(
64615        ptr as *const i8,
64616        transmute(a),
64617        crate::mem::align_of::<u64>() as i32,
64618    )
64619}
64620#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64621#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"]
64622#[doc = "## Safety"]
64623#[doc = "  * Neon instrinsic unsafe"]
64624#[inline]
64625#[target_feature(enable = "neon")]
64626#[cfg(target_arch = "arm")]
64627#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64628#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64629#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64630pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) {
64631    vst1_v8i8(
64632        ptr as *const i8,
64633        transmute(a),
64634        crate::mem::align_of::<p8>() as i32,
64635    )
64636}
64637#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64638#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"]
64639#[doc = "## Safety"]
64640#[doc = "  * Neon instrinsic unsafe"]
64641#[inline]
64642#[target_feature(enable = "neon")]
64643#[cfg(target_arch = "arm")]
64644#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64645#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64646#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64647pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) {
64648    vst1q_v16i8(
64649        ptr as *const i8,
64650        transmute(a),
64651        crate::mem::align_of::<p8>() as i32,
64652    )
64653}
64654#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64655#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"]
64656#[doc = "## Safety"]
64657#[doc = "  * Neon instrinsic unsafe"]
64658#[inline]
64659#[target_feature(enable = "neon")]
64660#[cfg(target_arch = "arm")]
64661#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64662#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64663#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64664pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) {
64665    vst1_v4i16(
64666        ptr as *const i8,
64667        transmute(a),
64668        crate::mem::align_of::<p16>() as i32,
64669    )
64670}
64671#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"]
64673#[doc = "## Safety"]
64674#[doc = "  * Neon instrinsic unsafe"]
64675#[inline]
64676#[target_feature(enable = "neon")]
64677#[cfg(target_arch = "arm")]
64678#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64679#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64680#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64681pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) {
64682    vst1q_v8i16(
64683        ptr as *const i8,
64684        transmute(a),
64685        crate::mem::align_of::<p16>() as i32,
64686    )
64687}
64688#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64689#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"]
64690#[doc = "## Safety"]
64691#[doc = "  * Neon instrinsic unsafe"]
64692#[inline]
64693#[target_feature(enable = "neon")]
64694#[cfg(target_arch = "arm")]
64695#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64696#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64697#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64698pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) {
64699    vst1_v1i64(
64700        ptr as *const i8,
64701        transmute(a),
64702        crate::mem::align_of::<p64>() as i32,
64703    )
64704}
64705#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64706#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"]
64707#[doc = "## Safety"]
64708#[doc = "  * Neon instrinsic unsafe"]
64709#[inline]
64710#[target_feature(enable = "neon")]
64711#[cfg(target_arch = "arm")]
64712#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64713#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64714#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64715pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) {
64716    vst1q_v2i64(
64717        ptr as *const i8,
64718        transmute(a),
64719        crate::mem::align_of::<p64>() as i32,
64720    )
64721}
64722#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"]
64724#[doc = "## Safety"]
64725#[doc = "  * Neon instrinsic unsafe"]
64726#[inline]
64727#[cfg(target_arch = "arm")]
64728#[target_feature(enable = "neon,v7")]
64729#[cfg_attr(test, assert_instr(vst1))]
64730#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64731pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) {
64732    unsafe extern "unadjusted" {
64733        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v2f32.p0")]
64734        fn _vst1_f32_x2(ptr: *mut f32, a: float32x2_t, b: float32x2_t);
64735    }
64736    _vst1_f32_x2(a, b.0, b.1)
64737}
64738#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64739#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"]
64740#[doc = "## Safety"]
64741#[doc = "  * Neon instrinsic unsafe"]
64742#[inline]
64743#[cfg(target_arch = "arm")]
64744#[target_feature(enable = "neon,v7")]
64745#[cfg_attr(test, assert_instr(vst1))]
64746#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64747pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) {
64748    unsafe extern "unadjusted" {
64749        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v4f32.p0")]
64750        fn _vst1q_f32_x2(ptr: *mut f32, a: float32x4_t, b: float32x4_t);
64751    }
64752    _vst1q_f32_x2(a, b.0, b.1)
64753}
64754#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64755#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"]
64756#[doc = "## Safety"]
64757#[doc = "  * Neon instrinsic unsafe"]
64758#[inline]
64759#[target_feature(enable = "neon")]
64760#[cfg(not(target_arch = "arm"))]
64761#[cfg_attr(test, assert_instr(st1))]
64762#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64763pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) {
64764    unsafe extern "unadjusted" {
64765        #[cfg_attr(
64766            any(target_arch = "aarch64", target_arch = "arm64ec"),
64767            link_name = "llvm.aarch64.neon.st1x2.v2f32.p0"
64768        )]
64769        fn _vst1_f32_x2(a: float32x2_t, b: float32x2_t, ptr: *mut f32);
64770    }
64771    _vst1_f32_x2(b.0, b.1, a)
64772}
64773#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"]
64775#[doc = "## Safety"]
64776#[doc = "  * Neon instrinsic unsafe"]
64777#[inline]
64778#[target_feature(enable = "neon")]
64779#[cfg(not(target_arch = "arm"))]
64780#[cfg_attr(test, assert_instr(st1))]
64781#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64782pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) {
64783    unsafe extern "unadjusted" {
64784        #[cfg_attr(
64785            any(target_arch = "aarch64", target_arch = "arm64ec"),
64786            link_name = "llvm.aarch64.neon.st1x2.v4f32.p0"
64787        )]
64788        fn _vst1q_f32_x2(a: float32x4_t, b: float32x4_t, ptr: *mut f32);
64789    }
64790    _vst1q_f32_x2(b.0, b.1, a)
64791}
64792#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64793#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x3)"]
64794#[doc = "## Safety"]
64795#[doc = "  * Neon instrinsic unsafe"]
64796#[inline]
64797#[target_feature(enable = "neon")]
64798#[cfg(not(target_arch = "arm"))]
64799#[cfg_attr(test, assert_instr(st1))]
64800#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64801pub unsafe fn vst1_f32_x3(a: *mut f32, b: float32x2x3_t) {
64802    unsafe extern "unadjusted" {
64803        #[cfg_attr(
64804            any(target_arch = "aarch64", target_arch = "arm64ec"),
64805            link_name = "llvm.aarch64.neon.st1x3.v2f32.p0"
64806        )]
64807        fn _vst1_f32_x3(a: float32x2_t, b: float32x2_t, c: float32x2_t, ptr: *mut f32);
64808    }
64809    _vst1_f32_x3(b.0, b.1, b.2, a)
64810}
64811#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64812#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x3)"]
64813#[doc = "## Safety"]
64814#[doc = "  * Neon instrinsic unsafe"]
64815#[inline]
64816#[target_feature(enable = "neon")]
64817#[cfg(not(target_arch = "arm"))]
64818#[cfg_attr(test, assert_instr(st1))]
64819#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64820pub unsafe fn vst1q_f32_x3(a: *mut f32, b: float32x4x3_t) {
64821    unsafe extern "unadjusted" {
64822        #[cfg_attr(
64823            any(target_arch = "aarch64", target_arch = "arm64ec"),
64824            link_name = "llvm.aarch64.neon.st1x3.v4f32.p0"
64825        )]
64826        fn _vst1q_f32_x3(a: float32x4_t, b: float32x4_t, c: float32x4_t, ptr: *mut f32);
64827    }
64828    _vst1q_f32_x3(b.0, b.1, b.2, a)
64829}
64830#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64831#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"]
64832#[doc = "## Safety"]
64833#[doc = "  * Neon instrinsic unsafe"]
64834#[inline]
64835#[cfg(target_arch = "arm")]
64836#[target_feature(enable = "neon,v7")]
64837#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64838#[cfg_attr(test, assert_instr(vst1))]
64839pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) {
64840    unsafe extern "unadjusted" {
64841        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v2f32.p0")]
64842        fn _vst1_f32_x4(
64843            ptr: *mut f32,
64844            a: float32x2_t,
64845            b: float32x2_t,
64846            c: float32x2_t,
64847            d: float32x2_t,
64848        );
64849    }
64850    _vst1_f32_x4(a, b.0, b.1, b.2, b.3)
64851}
64852#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64853#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"]
64854#[doc = "## Safety"]
64855#[doc = "  * Neon instrinsic unsafe"]
64856#[inline]
64857#[cfg(target_arch = "arm")]
64858#[target_feature(enable = "neon,v7")]
64859#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64860#[cfg_attr(test, assert_instr(vst1))]
64861pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) {
64862    unsafe extern "unadjusted" {
64863        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v4f32.p0")]
64864        fn _vst1q_f32_x4(
64865            ptr: *mut f32,
64866            a: float32x4_t,
64867            b: float32x4_t,
64868            c: float32x4_t,
64869            d: float32x4_t,
64870        );
64871    }
64872    _vst1q_f32_x4(a, b.0, b.1, b.2, b.3)
64873}
64874#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64875#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"]
64876#[doc = "## Safety"]
64877#[doc = "  * Neon instrinsic unsafe"]
64878#[inline]
64879#[target_feature(enable = "neon")]
64880#[cfg(not(target_arch = "arm"))]
64881#[cfg_attr(test, assert_instr(st1))]
64882#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64883pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) {
64884    unsafe extern "unadjusted" {
64885        #[cfg_attr(
64886            any(target_arch = "aarch64", target_arch = "arm64ec"),
64887            link_name = "llvm.aarch64.neon.st1x4.v2f32.p0"
64888        )]
64889        fn _vst1_f32_x4(
64890            a: float32x2_t,
64891            b: float32x2_t,
64892            c: float32x2_t,
64893            d: float32x2_t,
64894            ptr: *mut f32,
64895        );
64896    }
64897    _vst1_f32_x4(b.0, b.1, b.2, b.3, a)
64898}
64899#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64900#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"]
64901#[doc = "## Safety"]
64902#[doc = "  * Neon instrinsic unsafe"]
64903#[inline]
64904#[target_feature(enable = "neon")]
64905#[cfg(not(target_arch = "arm"))]
64906#[cfg_attr(test, assert_instr(st1))]
64907#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64908pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) {
64909    unsafe extern "unadjusted" {
64910        #[cfg_attr(
64911            any(target_arch = "aarch64", target_arch = "arm64ec"),
64912            link_name = "llvm.aarch64.neon.st1x4.v4f32.p0"
64913        )]
64914        fn _vst1q_f32_x4(
64915            a: float32x4_t,
64916            b: float32x4_t,
64917            c: float32x4_t,
64918            d: float32x4_t,
64919            ptr: *mut f32,
64920        );
64921    }
64922    _vst1q_f32_x4(b.0, b.1, b.2, b.3, a)
64923}
64924#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64925#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f16)"]
64926#[doc = "## Safety"]
64927#[doc = "  * Neon instrinsic unsafe"]
64928#[inline]
64929#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64930#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64931#[cfg_attr(
64932    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64933    assert_instr(nop, LANE = 0)
64934)]
64935#[rustc_legacy_const_generics(2)]
64936#[target_feature(enable = "neon,fp16")]
64937#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64938pub unsafe fn vst1_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4_t) {
64939    static_assert_uimm_bits!(LANE, 2);
64940    *a = simd_extract!(b, LANE as u32);
64941}
64942#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64943#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f16)"]
64944#[doc = "## Safety"]
64945#[doc = "  * Neon instrinsic unsafe"]
64946#[inline]
64947#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64948#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64949#[cfg_attr(
64950    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64951    assert_instr(nop, LANE = 0)
64952)]
64953#[rustc_legacy_const_generics(2)]
64954#[target_feature(enable = "neon,fp16")]
64955#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64956pub unsafe fn vst1q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8_t) {
64957    static_assert_uimm_bits!(LANE, 3);
64958    *a = simd_extract!(b, LANE as u32);
64959}
64960#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f32)"]
64962#[doc = "## Safety"]
64963#[doc = "  * Neon instrinsic unsafe"]
64964#[inline]
64965#[target_feature(enable = "neon")]
64966#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64967#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64968#[cfg_attr(
64969    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64970    assert_instr(nop, LANE = 0)
64971)]
64972#[rustc_legacy_const_generics(2)]
64973#[cfg_attr(
64974    not(target_arch = "arm"),
64975    stable(feature = "neon_intrinsics", since = "1.59.0")
64976)]
64977#[cfg_attr(
64978    target_arch = "arm",
64979    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64980)]
64981pub unsafe fn vst1_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2_t) {
64982    static_assert_uimm_bits!(LANE, 1);
64983    *a = simd_extract!(b, LANE as u32);
64984}
64985#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64986#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f32)"]
64987#[doc = "## Safety"]
64988#[doc = "  * Neon instrinsic unsafe"]
64989#[inline]
64990#[target_feature(enable = "neon")]
64991#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64992#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64993#[cfg_attr(
64994    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64995    assert_instr(nop, LANE = 0)
64996)]
64997#[rustc_legacy_const_generics(2)]
64998#[cfg_attr(
64999    not(target_arch = "arm"),
65000    stable(feature = "neon_intrinsics", since = "1.59.0")
65001)]
65002#[cfg_attr(
65003    target_arch = "arm",
65004    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65005)]
65006pub unsafe fn vst1q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4_t) {
65007    static_assert_uimm_bits!(LANE, 2);
65008    *a = simd_extract!(b, LANE as u32);
65009}
65010#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65011#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s8)"]
65012#[doc = "## Safety"]
65013#[doc = "  * Neon instrinsic unsafe"]
65014#[inline]
65015#[target_feature(enable = "neon")]
65016#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65017#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65018#[cfg_attr(
65019    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65020    assert_instr(nop, LANE = 0)
65021)]
65022#[rustc_legacy_const_generics(2)]
65023#[cfg_attr(
65024    not(target_arch = "arm"),
65025    stable(feature = "neon_intrinsics", since = "1.59.0")
65026)]
65027#[cfg_attr(
65028    target_arch = "arm",
65029    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65030)]
65031pub unsafe fn vst1_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8_t) {
65032    static_assert_uimm_bits!(LANE, 3);
65033    *a = simd_extract!(b, LANE as u32);
65034}
65035#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65036#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s8)"]
65037#[doc = "## Safety"]
65038#[doc = "  * Neon instrinsic unsafe"]
65039#[inline]
65040#[target_feature(enable = "neon")]
65041#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65042#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65043#[cfg_attr(
65044    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65045    assert_instr(nop, LANE = 0)
65046)]
65047#[rustc_legacy_const_generics(2)]
65048#[cfg_attr(
65049    not(target_arch = "arm"),
65050    stable(feature = "neon_intrinsics", since = "1.59.0")
65051)]
65052#[cfg_attr(
65053    target_arch = "arm",
65054    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65055)]
65056pub unsafe fn vst1q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16_t) {
65057    static_assert_uimm_bits!(LANE, 4);
65058    *a = simd_extract!(b, LANE as u32);
65059}
65060#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65061#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s16)"]
65062#[doc = "## Safety"]
65063#[doc = "  * Neon instrinsic unsafe"]
65064#[inline]
65065#[target_feature(enable = "neon")]
65066#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65067#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65068#[cfg_attr(
65069    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65070    assert_instr(nop, LANE = 0)
65071)]
65072#[rustc_legacy_const_generics(2)]
65073#[cfg_attr(
65074    not(target_arch = "arm"),
65075    stable(feature = "neon_intrinsics", since = "1.59.0")
65076)]
65077#[cfg_attr(
65078    target_arch = "arm",
65079    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65080)]
65081pub unsafe fn vst1_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4_t) {
65082    static_assert_uimm_bits!(LANE, 2);
65083    *a = simd_extract!(b, LANE as u32);
65084}
65085#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65086#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s16)"]
65087#[doc = "## Safety"]
65088#[doc = "  * Neon instrinsic unsafe"]
65089#[inline]
65090#[target_feature(enable = "neon")]
65091#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65092#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65093#[cfg_attr(
65094    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65095    assert_instr(nop, LANE = 0)
65096)]
65097#[rustc_legacy_const_generics(2)]
65098#[cfg_attr(
65099    not(target_arch = "arm"),
65100    stable(feature = "neon_intrinsics", since = "1.59.0")
65101)]
65102#[cfg_attr(
65103    target_arch = "arm",
65104    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65105)]
65106pub unsafe fn vst1q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8_t) {
65107    static_assert_uimm_bits!(LANE, 3);
65108    *a = simd_extract!(b, LANE as u32);
65109}
65110#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65111#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s32)"]
65112#[doc = "## Safety"]
65113#[doc = "  * Neon instrinsic unsafe"]
65114#[inline]
65115#[target_feature(enable = "neon")]
65116#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65117#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65118#[cfg_attr(
65119    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65120    assert_instr(nop, LANE = 0)
65121)]
65122#[rustc_legacy_const_generics(2)]
65123#[cfg_attr(
65124    not(target_arch = "arm"),
65125    stable(feature = "neon_intrinsics", since = "1.59.0")
65126)]
65127#[cfg_attr(
65128    target_arch = "arm",
65129    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65130)]
65131pub unsafe fn vst1_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2_t) {
65132    static_assert_uimm_bits!(LANE, 1);
65133    *a = simd_extract!(b, LANE as u32);
65134}
65135#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65136#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s32)"]
65137#[doc = "## Safety"]
65138#[doc = "  * Neon instrinsic unsafe"]
65139#[inline]
65140#[target_feature(enable = "neon")]
65141#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65142#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65143#[cfg_attr(
65144    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65145    assert_instr(nop, LANE = 0)
65146)]
65147#[rustc_legacy_const_generics(2)]
65148#[cfg_attr(
65149    not(target_arch = "arm"),
65150    stable(feature = "neon_intrinsics", since = "1.59.0")
65151)]
65152#[cfg_attr(
65153    target_arch = "arm",
65154    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65155)]
65156pub unsafe fn vst1q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4_t) {
65157    static_assert_uimm_bits!(LANE, 2);
65158    *a = simd_extract!(b, LANE as u32);
65159}
65160#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65161#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s64)"]
65162#[doc = "## Safety"]
65163#[doc = "  * Neon instrinsic unsafe"]
65164#[inline]
65165#[target_feature(enable = "neon")]
65166#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65167#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65168#[cfg_attr(
65169    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65170    assert_instr(nop, LANE = 0)
65171)]
65172#[rustc_legacy_const_generics(2)]
65173#[cfg_attr(
65174    not(target_arch = "arm"),
65175    stable(feature = "neon_intrinsics", since = "1.59.0")
65176)]
65177#[cfg_attr(
65178    target_arch = "arm",
65179    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65180)]
65181pub unsafe fn vst1q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2_t) {
65182    static_assert_uimm_bits!(LANE, 1);
65183    *a = simd_extract!(b, LANE as u32);
65184}
65185#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65186#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u8)"]
65187#[doc = "## Safety"]
65188#[doc = "  * Neon instrinsic unsafe"]
65189#[inline]
65190#[target_feature(enable = "neon")]
65191#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65192#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65193#[cfg_attr(
65194    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65195    assert_instr(nop, LANE = 0)
65196)]
65197#[rustc_legacy_const_generics(2)]
65198#[cfg_attr(
65199    not(target_arch = "arm"),
65200    stable(feature = "neon_intrinsics", since = "1.59.0")
65201)]
65202#[cfg_attr(
65203    target_arch = "arm",
65204    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65205)]
65206pub unsafe fn vst1_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8_t) {
65207    static_assert_uimm_bits!(LANE, 3);
65208    *a = simd_extract!(b, LANE as u32);
65209}
65210#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u8)"]
65212#[doc = "## Safety"]
65213#[doc = "  * Neon instrinsic unsafe"]
65214#[inline]
65215#[target_feature(enable = "neon")]
65216#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65217#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65218#[cfg_attr(
65219    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65220    assert_instr(nop, LANE = 0)
65221)]
65222#[rustc_legacy_const_generics(2)]
65223#[cfg_attr(
65224    not(target_arch = "arm"),
65225    stable(feature = "neon_intrinsics", since = "1.59.0")
65226)]
65227#[cfg_attr(
65228    target_arch = "arm",
65229    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65230)]
65231pub unsafe fn vst1q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16_t) {
65232    static_assert_uimm_bits!(LANE, 4);
65233    *a = simd_extract!(b, LANE as u32);
65234}
65235#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65236#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u16)"]
65237#[doc = "## Safety"]
65238#[doc = "  * Neon instrinsic unsafe"]
65239#[inline]
65240#[target_feature(enable = "neon")]
65241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65242#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65243#[cfg_attr(
65244    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65245    assert_instr(nop, LANE = 0)
65246)]
65247#[rustc_legacy_const_generics(2)]
65248#[cfg_attr(
65249    not(target_arch = "arm"),
65250    stable(feature = "neon_intrinsics", since = "1.59.0")
65251)]
65252#[cfg_attr(
65253    target_arch = "arm",
65254    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65255)]
65256pub unsafe fn vst1_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4_t) {
65257    static_assert_uimm_bits!(LANE, 2);
65258    *a = simd_extract!(b, LANE as u32);
65259}
65260#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u16)"]
65262#[doc = "## Safety"]
65263#[doc = "  * Neon instrinsic unsafe"]
65264#[inline]
65265#[target_feature(enable = "neon")]
65266#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65267#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65268#[cfg_attr(
65269    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65270    assert_instr(nop, LANE = 0)
65271)]
65272#[rustc_legacy_const_generics(2)]
65273#[cfg_attr(
65274    not(target_arch = "arm"),
65275    stable(feature = "neon_intrinsics", since = "1.59.0")
65276)]
65277#[cfg_attr(
65278    target_arch = "arm",
65279    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65280)]
65281pub unsafe fn vst1q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8_t) {
65282    static_assert_uimm_bits!(LANE, 3);
65283    *a = simd_extract!(b, LANE as u32);
65284}
65285#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65286#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u32)"]
65287#[doc = "## Safety"]
65288#[doc = "  * Neon instrinsic unsafe"]
65289#[inline]
65290#[target_feature(enable = "neon")]
65291#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65292#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65293#[cfg_attr(
65294    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65295    assert_instr(nop, LANE = 0)
65296)]
65297#[rustc_legacy_const_generics(2)]
65298#[cfg_attr(
65299    not(target_arch = "arm"),
65300    stable(feature = "neon_intrinsics", since = "1.59.0")
65301)]
65302#[cfg_attr(
65303    target_arch = "arm",
65304    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65305)]
65306pub unsafe fn vst1_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2_t) {
65307    static_assert_uimm_bits!(LANE, 1);
65308    *a = simd_extract!(b, LANE as u32);
65309}
65310#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u32)"]
65312#[doc = "## Safety"]
65313#[doc = "  * Neon instrinsic unsafe"]
65314#[inline]
65315#[target_feature(enable = "neon")]
65316#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65317#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65318#[cfg_attr(
65319    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65320    assert_instr(nop, LANE = 0)
65321)]
65322#[rustc_legacy_const_generics(2)]
65323#[cfg_attr(
65324    not(target_arch = "arm"),
65325    stable(feature = "neon_intrinsics", since = "1.59.0")
65326)]
65327#[cfg_attr(
65328    target_arch = "arm",
65329    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65330)]
65331pub unsafe fn vst1q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4_t) {
65332    static_assert_uimm_bits!(LANE, 2);
65333    *a = simd_extract!(b, LANE as u32);
65334}
65335#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u64)"]
65337#[doc = "## Safety"]
65338#[doc = "  * Neon instrinsic unsafe"]
65339#[inline]
65340#[target_feature(enable = "neon")]
65341#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65342#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65343#[cfg_attr(
65344    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65345    assert_instr(nop, LANE = 0)
65346)]
65347#[rustc_legacy_const_generics(2)]
65348#[cfg_attr(
65349    not(target_arch = "arm"),
65350    stable(feature = "neon_intrinsics", since = "1.59.0")
65351)]
65352#[cfg_attr(
65353    target_arch = "arm",
65354    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65355)]
65356pub unsafe fn vst1q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2_t) {
65357    static_assert_uimm_bits!(LANE, 1);
65358    *a = simd_extract!(b, LANE as u32);
65359}
65360#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65361#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p8)"]
65362#[doc = "## Safety"]
65363#[doc = "  * Neon instrinsic unsafe"]
65364#[inline]
65365#[target_feature(enable = "neon")]
65366#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65367#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65368#[cfg_attr(
65369    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65370    assert_instr(nop, LANE = 0)
65371)]
65372#[rustc_legacy_const_generics(2)]
65373#[cfg_attr(
65374    not(target_arch = "arm"),
65375    stable(feature = "neon_intrinsics", since = "1.59.0")
65376)]
65377#[cfg_attr(
65378    target_arch = "arm",
65379    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65380)]
65381pub unsafe fn vst1_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8_t) {
65382    static_assert_uimm_bits!(LANE, 3);
65383    *a = simd_extract!(b, LANE as u32);
65384}
65385#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65386#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p8)"]
65387#[doc = "## Safety"]
65388#[doc = "  * Neon instrinsic unsafe"]
65389#[inline]
65390#[target_feature(enable = "neon")]
65391#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65392#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65393#[cfg_attr(
65394    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65395    assert_instr(nop, LANE = 0)
65396)]
65397#[rustc_legacy_const_generics(2)]
65398#[cfg_attr(
65399    not(target_arch = "arm"),
65400    stable(feature = "neon_intrinsics", since = "1.59.0")
65401)]
65402#[cfg_attr(
65403    target_arch = "arm",
65404    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65405)]
65406pub unsafe fn vst1q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16_t) {
65407    static_assert_uimm_bits!(LANE, 4);
65408    *a = simd_extract!(b, LANE as u32);
65409}
65410#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65411#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p16)"]
65412#[doc = "## Safety"]
65413#[doc = "  * Neon instrinsic unsafe"]
65414#[inline]
65415#[target_feature(enable = "neon")]
65416#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65417#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65418#[cfg_attr(
65419    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65420    assert_instr(nop, LANE = 0)
65421)]
65422#[rustc_legacy_const_generics(2)]
65423#[cfg_attr(
65424    not(target_arch = "arm"),
65425    stable(feature = "neon_intrinsics", since = "1.59.0")
65426)]
65427#[cfg_attr(
65428    target_arch = "arm",
65429    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65430)]
65431pub unsafe fn vst1_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4_t) {
65432    static_assert_uimm_bits!(LANE, 2);
65433    *a = simd_extract!(b, LANE as u32);
65434}
65435#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65436#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p16)"]
65437#[doc = "## Safety"]
65438#[doc = "  * Neon instrinsic unsafe"]
65439#[inline]
65440#[target_feature(enable = "neon")]
65441#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65442#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65443#[cfg_attr(
65444    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65445    assert_instr(nop, LANE = 0)
65446)]
65447#[rustc_legacy_const_generics(2)]
65448#[cfg_attr(
65449    not(target_arch = "arm"),
65450    stable(feature = "neon_intrinsics", since = "1.59.0")
65451)]
65452#[cfg_attr(
65453    target_arch = "arm",
65454    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65455)]
65456pub unsafe fn vst1q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8_t) {
65457    static_assert_uimm_bits!(LANE, 3);
65458    *a = simd_extract!(b, LANE as u32);
65459}
65460#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65461#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p64)"]
65462#[doc = "## Safety"]
65463#[doc = "  * Neon instrinsic unsafe"]
65464#[inline]
65465#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65466#[target_feature(enable = "neon,aes")]
65467#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65468#[cfg_attr(
65469    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65470    assert_instr(nop, LANE = 0)
65471)]
65472#[rustc_legacy_const_generics(2)]
65473#[cfg_attr(
65474    not(target_arch = "arm"),
65475    stable(feature = "neon_intrinsics", since = "1.59.0")
65476)]
65477#[cfg_attr(
65478    target_arch = "arm",
65479    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65480)]
65481pub unsafe fn vst1_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1_t) {
65482    static_assert!(LANE == 0);
65483    *a = simd_extract!(b, LANE as u32);
65484}
65485#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65486#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s64)"]
65487#[doc = "## Safety"]
65488#[doc = "  * Neon instrinsic unsafe"]
65489#[inline]
65490#[target_feature(enable = "neon")]
65491#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65492#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65493#[cfg_attr(
65494    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65495    assert_instr(nop, LANE = 0)
65496)]
65497#[rustc_legacy_const_generics(2)]
65498#[cfg_attr(
65499    not(target_arch = "arm"),
65500    stable(feature = "neon_intrinsics", since = "1.59.0")
65501)]
65502#[cfg_attr(
65503    target_arch = "arm",
65504    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65505)]
65506pub unsafe fn vst1_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1_t) {
65507    static_assert!(LANE == 0);
65508    *a = simd_extract!(b, LANE as u32);
65509}
65510#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65511#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u64)"]
65512#[doc = "## Safety"]
65513#[doc = "  * Neon instrinsic unsafe"]
65514#[inline]
65515#[target_feature(enable = "neon")]
65516#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65517#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65518#[cfg_attr(
65519    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65520    assert_instr(nop, LANE = 0)
65521)]
65522#[rustc_legacy_const_generics(2)]
65523#[cfg_attr(
65524    not(target_arch = "arm"),
65525    stable(feature = "neon_intrinsics", since = "1.59.0")
65526)]
65527#[cfg_attr(
65528    target_arch = "arm",
65529    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65530)]
65531pub unsafe fn vst1_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1_t) {
65532    static_assert!(LANE == 0);
65533    *a = simd_extract!(b, LANE as u32);
65534}
65535#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65536#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x2)"]
65537#[doc = "## Safety"]
65538#[doc = "  * Neon instrinsic unsafe"]
65539#[inline]
65540#[target_feature(enable = "neon,aes")]
65541#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65542#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
65543#[cfg_attr(
65544    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65545    assert_instr(st1)
65546)]
65547#[cfg_attr(
65548    not(target_arch = "arm"),
65549    stable(feature = "neon_intrinsics", since = "1.59.0")
65550)]
65551#[cfg_attr(
65552    target_arch = "arm",
65553    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65554)]
65555pub unsafe fn vst1_p64_x2(a: *mut p64, b: poly64x1x2_t) {
65556    vst1_s64_x2(transmute(a), transmute(b))
65557}
65558#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x3)"]
65560#[doc = "## Safety"]
65561#[doc = "  * Neon instrinsic unsafe"]
65562#[inline]
65563#[target_feature(enable = "neon,aes")]
65564#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65565#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
65566#[cfg_attr(
65567    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65568    assert_instr(st1)
65569)]
65570#[cfg_attr(
65571    not(target_arch = "arm"),
65572    stable(feature = "neon_intrinsics", since = "1.59.0")
65573)]
65574#[cfg_attr(
65575    target_arch = "arm",
65576    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65577)]
65578pub unsafe fn vst1_p64_x3(a: *mut p64, b: poly64x1x3_t) {
65579    vst1_s64_x3(transmute(a), transmute(b))
65580}
65581#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65582#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x4)"]
65583#[doc = "## Safety"]
65584#[doc = "  * Neon instrinsic unsafe"]
65585#[inline]
65586#[target_feature(enable = "neon,aes")]
65587#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65588#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
65589#[cfg_attr(
65590    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65591    assert_instr(st1)
65592)]
65593#[cfg_attr(
65594    not(target_arch = "arm"),
65595    stable(feature = "neon_intrinsics", since = "1.59.0")
65596)]
65597#[cfg_attr(
65598    target_arch = "arm",
65599    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65600)]
65601pub unsafe fn vst1_p64_x4(a: *mut p64, b: poly64x1x4_t) {
65602    vst1_s64_x4(transmute(a), transmute(b))
65603}
65604#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65605#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x2)"]
65606#[doc = "## Safety"]
65607#[doc = "  * Neon instrinsic unsafe"]
65608#[inline]
65609#[target_feature(enable = "neon,aes")]
65610#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65611#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
65612#[cfg_attr(
65613    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65614    assert_instr(st1)
65615)]
65616#[cfg_attr(
65617    not(target_arch = "arm"),
65618    stable(feature = "neon_intrinsics", since = "1.59.0")
65619)]
65620#[cfg_attr(
65621    target_arch = "arm",
65622    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65623)]
65624pub unsafe fn vst1q_p64_x2(a: *mut p64, b: poly64x2x2_t) {
65625    vst1q_s64_x2(transmute(a), transmute(b))
65626}
65627#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65628#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x3)"]
65629#[doc = "## Safety"]
65630#[doc = "  * Neon instrinsic unsafe"]
65631#[inline]
65632#[target_feature(enable = "neon,aes")]
65633#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65634#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
65635#[cfg_attr(
65636    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65637    assert_instr(st1)
65638)]
65639#[cfg_attr(
65640    not(target_arch = "arm"),
65641    stable(feature = "neon_intrinsics", since = "1.59.0")
65642)]
65643#[cfg_attr(
65644    target_arch = "arm",
65645    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65646)]
65647pub unsafe fn vst1q_p64_x3(a: *mut p64, b: poly64x2x3_t) {
65648    vst1q_s64_x3(transmute(a), transmute(b))
65649}
65650#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65651#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x4)"]
65652#[doc = "## Safety"]
65653#[doc = "  * Neon instrinsic unsafe"]
65654#[inline]
65655#[target_feature(enable = "neon,aes")]
65656#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65657#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
65658#[cfg_attr(
65659    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65660    assert_instr(st1)
65661)]
65662#[cfg_attr(
65663    not(target_arch = "arm"),
65664    stable(feature = "neon_intrinsics", since = "1.59.0")
65665)]
65666#[cfg_attr(
65667    target_arch = "arm",
65668    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65669)]
65670pub unsafe fn vst1q_p64_x4(a: *mut p64, b: poly64x2x4_t) {
65671    vst1q_s64_x4(transmute(a), transmute(b))
65672}
65673#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65674#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"]
65675#[doc = "## Safety"]
65676#[doc = "  * Neon instrinsic unsafe"]
65677#[inline]
65678#[target_feature(enable = "neon")]
65679#[cfg(not(target_arch = "arm"))]
65680#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65681#[cfg_attr(test, assert_instr(st1))]
65682pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) {
65683    unsafe extern "unadjusted" {
65684        #[cfg_attr(
65685            any(target_arch = "aarch64", target_arch = "arm64ec"),
65686            link_name = "llvm.aarch64.neon.st1x2.v8i8.p0"
65687        )]
65688        fn _vst1_s8_x2(a: int8x8_t, b: int8x8_t, ptr: *mut i8);
65689    }
65690    _vst1_s8_x2(b.0, b.1, a)
65691}
65692#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65693#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"]
65694#[doc = "## Safety"]
65695#[doc = "  * Neon instrinsic unsafe"]
65696#[inline]
65697#[target_feature(enable = "neon")]
65698#[cfg(not(target_arch = "arm"))]
65699#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65700#[cfg_attr(test, assert_instr(st1))]
65701pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) {
65702    unsafe extern "unadjusted" {
65703        #[cfg_attr(
65704            any(target_arch = "aarch64", target_arch = "arm64ec"),
65705            link_name = "llvm.aarch64.neon.st1x2.v16i8.p0"
65706        )]
65707        fn _vst1q_s8_x2(a: int8x16_t, b: int8x16_t, ptr: *mut i8);
65708    }
65709    _vst1q_s8_x2(b.0, b.1, a)
65710}
65711#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65712#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"]
65713#[doc = "## Safety"]
65714#[doc = "  * Neon instrinsic unsafe"]
65715#[inline]
65716#[target_feature(enable = "neon")]
65717#[cfg(not(target_arch = "arm"))]
65718#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65719#[cfg_attr(test, assert_instr(st1))]
65720pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) {
65721    unsafe extern "unadjusted" {
65722        #[cfg_attr(
65723            any(target_arch = "aarch64", target_arch = "arm64ec"),
65724            link_name = "llvm.aarch64.neon.st1x2.v4i16.p0"
65725        )]
65726        fn _vst1_s16_x2(a: int16x4_t, b: int16x4_t, ptr: *mut i16);
65727    }
65728    _vst1_s16_x2(b.0, b.1, a)
65729}
65730#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65731#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"]
65732#[doc = "## Safety"]
65733#[doc = "  * Neon instrinsic unsafe"]
65734#[inline]
65735#[target_feature(enable = "neon")]
65736#[cfg(not(target_arch = "arm"))]
65737#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65738#[cfg_attr(test, assert_instr(st1))]
65739pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) {
65740    unsafe extern "unadjusted" {
65741        #[cfg_attr(
65742            any(target_arch = "aarch64", target_arch = "arm64ec"),
65743            link_name = "llvm.aarch64.neon.st1x2.v8i16.p0"
65744        )]
65745        fn _vst1q_s16_x2(a: int16x8_t, b: int16x8_t, ptr: *mut i16);
65746    }
65747    _vst1q_s16_x2(b.0, b.1, a)
65748}
65749#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65750#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"]
65751#[doc = "## Safety"]
65752#[doc = "  * Neon instrinsic unsafe"]
65753#[inline]
65754#[target_feature(enable = "neon")]
65755#[cfg(not(target_arch = "arm"))]
65756#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65757#[cfg_attr(test, assert_instr(st1))]
65758pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) {
65759    unsafe extern "unadjusted" {
65760        #[cfg_attr(
65761            any(target_arch = "aarch64", target_arch = "arm64ec"),
65762            link_name = "llvm.aarch64.neon.st1x2.v2i32.p0"
65763        )]
65764        fn _vst1_s32_x2(a: int32x2_t, b: int32x2_t, ptr: *mut i32);
65765    }
65766    _vst1_s32_x2(b.0, b.1, a)
65767}
65768#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65769#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"]
65770#[doc = "## Safety"]
65771#[doc = "  * Neon instrinsic unsafe"]
65772#[inline]
65773#[target_feature(enable = "neon")]
65774#[cfg(not(target_arch = "arm"))]
65775#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65776#[cfg_attr(test, assert_instr(st1))]
65777pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) {
65778    unsafe extern "unadjusted" {
65779        #[cfg_attr(
65780            any(target_arch = "aarch64", target_arch = "arm64ec"),
65781            link_name = "llvm.aarch64.neon.st1x2.v4i32.p0"
65782        )]
65783        fn _vst1q_s32_x2(a: int32x4_t, b: int32x4_t, ptr: *mut i32);
65784    }
65785    _vst1q_s32_x2(b.0, b.1, a)
65786}
65787#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65788#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"]
65789#[doc = "## Safety"]
65790#[doc = "  * Neon instrinsic unsafe"]
65791#[inline]
65792#[target_feature(enable = "neon")]
65793#[cfg(not(target_arch = "arm"))]
65794#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65795#[cfg_attr(test, assert_instr(st1))]
65796pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) {
65797    unsafe extern "unadjusted" {
65798        #[cfg_attr(
65799            any(target_arch = "aarch64", target_arch = "arm64ec"),
65800            link_name = "llvm.aarch64.neon.st1x2.v1i64.p0"
65801        )]
65802        fn _vst1_s64_x2(a: int64x1_t, b: int64x1_t, ptr: *mut i64);
65803    }
65804    _vst1_s64_x2(b.0, b.1, a)
65805}
65806#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"]
65808#[doc = "## Safety"]
65809#[doc = "  * Neon instrinsic unsafe"]
65810#[inline]
65811#[target_feature(enable = "neon")]
65812#[cfg(not(target_arch = "arm"))]
65813#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65814#[cfg_attr(test, assert_instr(st1))]
65815pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) {
65816    unsafe extern "unadjusted" {
65817        #[cfg_attr(
65818            any(target_arch = "aarch64", target_arch = "arm64ec"),
65819            link_name = "llvm.aarch64.neon.st1x2.v2i64.p0"
65820        )]
65821        fn _vst1q_s64_x2(a: int64x2_t, b: int64x2_t, ptr: *mut i64);
65822    }
65823    _vst1q_s64_x2(b.0, b.1, a)
65824}
65825#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65826#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"]
65827#[doc = "## Safety"]
65828#[doc = "  * Neon instrinsic unsafe"]
65829#[inline]
65830#[target_feature(enable = "neon,v7")]
65831#[cfg(target_arch = "arm")]
65832#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65833#[cfg_attr(test, assert_instr(vst1))]
65834pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) {
65835    unsafe extern "unadjusted" {
65836        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v8i8.p0")]
65837        fn _vst1_s8_x2(ptr: *mut i8, a: int8x8_t, b: int8x8_t);
65838    }
65839    _vst1_s8_x2(a, b.0, b.1)
65840}
65841#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65842#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"]
65843#[doc = "## Safety"]
65844#[doc = "  * Neon instrinsic unsafe"]
65845#[inline]
65846#[target_feature(enable = "neon,v7")]
65847#[cfg(target_arch = "arm")]
65848#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65849#[cfg_attr(test, assert_instr(vst1))]
65850pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) {
65851    unsafe extern "unadjusted" {
65852        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v16i8.p0")]
65853        fn _vst1q_s8_x2(ptr: *mut i8, a: int8x16_t, b: int8x16_t);
65854    }
65855    _vst1q_s8_x2(a, b.0, b.1)
65856}
65857#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65858#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"]
65859#[doc = "## Safety"]
65860#[doc = "  * Neon instrinsic unsafe"]
65861#[inline]
65862#[target_feature(enable = "neon,v7")]
65863#[cfg(target_arch = "arm")]
65864#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65865#[cfg_attr(test, assert_instr(vst1))]
65866pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) {
65867    unsafe extern "unadjusted" {
65868        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v4i16.p0")]
65869        fn _vst1_s16_x2(ptr: *mut i16, a: int16x4_t, b: int16x4_t);
65870    }
65871    _vst1_s16_x2(a, b.0, b.1)
65872}
65873#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65874#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"]
65875#[doc = "## Safety"]
65876#[doc = "  * Neon instrinsic unsafe"]
65877#[inline]
65878#[target_feature(enable = "neon,v7")]
65879#[cfg(target_arch = "arm")]
65880#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65881#[cfg_attr(test, assert_instr(vst1))]
65882pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) {
65883    unsafe extern "unadjusted" {
65884        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v8i16.p0")]
65885        fn _vst1q_s16_x2(ptr: *mut i16, a: int16x8_t, b: int16x8_t);
65886    }
65887    _vst1q_s16_x2(a, b.0, b.1)
65888}
65889#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65890#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"]
65891#[doc = "## Safety"]
65892#[doc = "  * Neon instrinsic unsafe"]
65893#[inline]
65894#[target_feature(enable = "neon,v7")]
65895#[cfg(target_arch = "arm")]
65896#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65897#[cfg_attr(test, assert_instr(vst1))]
65898pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) {
65899    unsafe extern "unadjusted" {
65900        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v2i32.p0")]
65901        fn _vst1_s32_x2(ptr: *mut i32, a: int32x2_t, b: int32x2_t);
65902    }
65903    _vst1_s32_x2(a, b.0, b.1)
65904}
65905#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65906#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"]
65907#[doc = "## Safety"]
65908#[doc = "  * Neon instrinsic unsafe"]
65909#[inline]
65910#[target_feature(enable = "neon,v7")]
65911#[cfg(target_arch = "arm")]
65912#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65913#[cfg_attr(test, assert_instr(vst1))]
65914pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) {
65915    unsafe extern "unadjusted" {
65916        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v4i32.p0")]
65917        fn _vst1q_s32_x2(ptr: *mut i32, a: int32x4_t, b: int32x4_t);
65918    }
65919    _vst1q_s32_x2(a, b.0, b.1)
65920}
65921#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65922#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"]
65923#[doc = "## Safety"]
65924#[doc = "  * Neon instrinsic unsafe"]
65925#[inline]
65926#[target_feature(enable = "neon,v7")]
65927#[cfg(target_arch = "arm")]
65928#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65929#[cfg_attr(test, assert_instr(vst1))]
65930pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) {
65931    unsafe extern "unadjusted" {
65932        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v1i64.p0")]
65933        fn _vst1_s64_x2(ptr: *mut i64, a: int64x1_t, b: int64x1_t);
65934    }
65935    _vst1_s64_x2(a, b.0, b.1)
65936}
65937#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65938#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"]
65939#[doc = "## Safety"]
65940#[doc = "  * Neon instrinsic unsafe"]
65941#[inline]
65942#[target_feature(enable = "neon,v7")]
65943#[cfg(target_arch = "arm")]
65944#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65945#[cfg_attr(test, assert_instr(vst1))]
65946pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) {
65947    unsafe extern "unadjusted" {
65948        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v2i64.p0")]
65949        fn _vst1q_s64_x2(ptr: *mut i64, a: int64x2_t, b: int64x2_t);
65950    }
65951    _vst1q_s64_x2(a, b.0, b.1)
65952}
65953#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65954#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"]
65955#[doc = "## Safety"]
65956#[doc = "  * Neon instrinsic unsafe"]
65957#[inline]
65958#[target_feature(enable = "neon")]
65959#[cfg(not(target_arch = "arm"))]
65960#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65961#[cfg_attr(test, assert_instr(st1))]
65962pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) {
65963    unsafe extern "unadjusted" {
65964        #[cfg_attr(
65965            any(target_arch = "aarch64", target_arch = "arm64ec"),
65966            link_name = "llvm.aarch64.neon.st1x3.v8i8.p0"
65967        )]
65968        fn _vst1_s8_x3(a: int8x8_t, b: int8x8_t, c: int8x8_t, ptr: *mut i8);
65969    }
65970    _vst1_s8_x3(b.0, b.1, b.2, a)
65971}
65972#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65973#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"]
65974#[doc = "## Safety"]
65975#[doc = "  * Neon instrinsic unsafe"]
65976#[inline]
65977#[target_feature(enable = "neon")]
65978#[cfg(not(target_arch = "arm"))]
65979#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65980#[cfg_attr(test, assert_instr(st1))]
65981pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) {
65982    unsafe extern "unadjusted" {
65983        #[cfg_attr(
65984            any(target_arch = "aarch64", target_arch = "arm64ec"),
65985            link_name = "llvm.aarch64.neon.st1x3.v16i8.p0"
65986        )]
65987        fn _vst1q_s8_x3(a: int8x16_t, b: int8x16_t, c: int8x16_t, ptr: *mut i8);
65988    }
65989    _vst1q_s8_x3(b.0, b.1, b.2, a)
65990}
65991#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65992#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"]
65993#[doc = "## Safety"]
65994#[doc = "  * Neon instrinsic unsafe"]
65995#[inline]
65996#[target_feature(enable = "neon")]
65997#[cfg(not(target_arch = "arm"))]
65998#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65999#[cfg_attr(test, assert_instr(st1))]
66000pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) {
66001    unsafe extern "unadjusted" {
66002        #[cfg_attr(
66003            any(target_arch = "aarch64", target_arch = "arm64ec"),
66004            link_name = "llvm.aarch64.neon.st1x3.v4i16.p0"
66005        )]
66006        fn _vst1_s16_x3(a: int16x4_t, b: int16x4_t, c: int16x4_t, ptr: *mut i16);
66007    }
66008    _vst1_s16_x3(b.0, b.1, b.2, a)
66009}
66010#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66011#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"]
66012#[doc = "## Safety"]
66013#[doc = "  * Neon instrinsic unsafe"]
66014#[inline]
66015#[target_feature(enable = "neon")]
66016#[cfg(not(target_arch = "arm"))]
66017#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66018#[cfg_attr(test, assert_instr(st1))]
66019pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) {
66020    unsafe extern "unadjusted" {
66021        #[cfg_attr(
66022            any(target_arch = "aarch64", target_arch = "arm64ec"),
66023            link_name = "llvm.aarch64.neon.st1x3.v8i16.p0"
66024        )]
66025        fn _vst1q_s16_x3(a: int16x8_t, b: int16x8_t, c: int16x8_t, ptr: *mut i16);
66026    }
66027    _vst1q_s16_x3(b.0, b.1, b.2, a)
66028}
66029#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66030#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"]
66031#[doc = "## Safety"]
66032#[doc = "  * Neon instrinsic unsafe"]
66033#[inline]
66034#[target_feature(enable = "neon")]
66035#[cfg(not(target_arch = "arm"))]
66036#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66037#[cfg_attr(test, assert_instr(st1))]
66038pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) {
66039    unsafe extern "unadjusted" {
66040        #[cfg_attr(
66041            any(target_arch = "aarch64", target_arch = "arm64ec"),
66042            link_name = "llvm.aarch64.neon.st1x3.v2i32.p0"
66043        )]
66044        fn _vst1_s32_x3(a: int32x2_t, b: int32x2_t, c: int32x2_t, ptr: *mut i32);
66045    }
66046    _vst1_s32_x3(b.0, b.1, b.2, a)
66047}
66048#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66049#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"]
66050#[doc = "## Safety"]
66051#[doc = "  * Neon instrinsic unsafe"]
66052#[inline]
66053#[target_feature(enable = "neon")]
66054#[cfg(not(target_arch = "arm"))]
66055#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66056#[cfg_attr(test, assert_instr(st1))]
66057pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) {
66058    unsafe extern "unadjusted" {
66059        #[cfg_attr(
66060            any(target_arch = "aarch64", target_arch = "arm64ec"),
66061            link_name = "llvm.aarch64.neon.st1x3.v4i32.p0"
66062        )]
66063        fn _vst1q_s32_x3(a: int32x4_t, b: int32x4_t, c: int32x4_t, ptr: *mut i32);
66064    }
66065    _vst1q_s32_x3(b.0, b.1, b.2, a)
66066}
66067#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66068#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"]
66069#[doc = "## Safety"]
66070#[doc = "  * Neon instrinsic unsafe"]
66071#[inline]
66072#[target_feature(enable = "neon")]
66073#[cfg(not(target_arch = "arm"))]
66074#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66075#[cfg_attr(test, assert_instr(st1))]
66076pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) {
66077    unsafe extern "unadjusted" {
66078        #[cfg_attr(
66079            any(target_arch = "aarch64", target_arch = "arm64ec"),
66080            link_name = "llvm.aarch64.neon.st1x3.v1i64.p0"
66081        )]
66082        fn _vst1_s64_x3(a: int64x1_t, b: int64x1_t, c: int64x1_t, ptr: *mut i64);
66083    }
66084    _vst1_s64_x3(b.0, b.1, b.2, a)
66085}
66086#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66087#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"]
66088#[doc = "## Safety"]
66089#[doc = "  * Neon instrinsic unsafe"]
66090#[inline]
66091#[target_feature(enable = "neon")]
66092#[cfg(not(target_arch = "arm"))]
66093#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66094#[cfg_attr(test, assert_instr(st1))]
66095pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) {
66096    unsafe extern "unadjusted" {
66097        #[cfg_attr(
66098            any(target_arch = "aarch64", target_arch = "arm64ec"),
66099            link_name = "llvm.aarch64.neon.st1x3.v2i64.p0"
66100        )]
66101        fn _vst1q_s64_x3(a: int64x2_t, b: int64x2_t, c: int64x2_t, ptr: *mut i64);
66102    }
66103    _vst1q_s64_x3(b.0, b.1, b.2, a)
66104}
66105#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66106#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"]
66107#[doc = "## Safety"]
66108#[doc = "  * Neon instrinsic unsafe"]
66109#[inline]
66110#[target_feature(enable = "neon,v7")]
66111#[cfg(target_arch = "arm")]
66112#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66113#[cfg_attr(test, assert_instr(vst1))]
66114pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) {
66115    unsafe extern "unadjusted" {
66116        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0.v8i8.p0")]
66117        fn _vst1_s8_x3(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t);
66118    }
66119    _vst1_s8_x3(a, b.0, b.1, b.2)
66120}
66121#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66122#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"]
66123#[doc = "## Safety"]
66124#[doc = "  * Neon instrinsic unsafe"]
66125#[inline]
66126#[target_feature(enable = "neon,v7")]
66127#[cfg(target_arch = "arm")]
66128#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66129#[cfg_attr(test, assert_instr(vst1))]
66130pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) {
66131    unsafe extern "unadjusted" {
66132        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0.v16i8.p0")]
66133        fn _vst1q_s8_x3(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t);
66134    }
66135    _vst1q_s8_x3(a, b.0, b.1, b.2)
66136}
66137#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66138#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"]
66139#[doc = "## Safety"]
66140#[doc = "  * Neon instrinsic unsafe"]
66141#[inline]
66142#[target_feature(enable = "neon,v7")]
66143#[cfg(target_arch = "arm")]
66144#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66145#[cfg_attr(test, assert_instr(vst1))]
66146pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) {
66147    unsafe extern "unadjusted" {
66148        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0.v4i16.p0")]
66149        fn _vst1_s16_x3(ptr: *mut i16, a: int16x4_t, b: int16x4_t, c: int16x4_t);
66150    }
66151    _vst1_s16_x3(a, b.0, b.1, b.2)
66152}
66153#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66154#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"]
66155#[doc = "## Safety"]
66156#[doc = "  * Neon instrinsic unsafe"]
66157#[inline]
66158#[target_feature(enable = "neon,v7")]
66159#[cfg(target_arch = "arm")]
66160#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66161#[cfg_attr(test, assert_instr(vst1))]
66162pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) {
66163    unsafe extern "unadjusted" {
66164        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0.v8i16.p0")]
66165        fn _vst1q_s16_x3(ptr: *mut i16, a: int16x8_t, b: int16x8_t, c: int16x8_t);
66166    }
66167    _vst1q_s16_x3(a, b.0, b.1, b.2)
66168}
66169#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66170#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"]
66171#[doc = "## Safety"]
66172#[doc = "  * Neon instrinsic unsafe"]
66173#[inline]
66174#[target_feature(enable = "neon,v7")]
66175#[cfg(target_arch = "arm")]
66176#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66177#[cfg_attr(test, assert_instr(vst1))]
66178pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) {
66179    unsafe extern "unadjusted" {
66180        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0.v2i32.p0")]
66181        fn _vst1_s32_x3(ptr: *mut i32, a: int32x2_t, b: int32x2_t, c: int32x2_t);
66182    }
66183    _vst1_s32_x3(a, b.0, b.1, b.2)
66184}
66185#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66186#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"]
66187#[doc = "## Safety"]
66188#[doc = "  * Neon instrinsic unsafe"]
66189#[inline]
66190#[target_feature(enable = "neon,v7")]
66191#[cfg(target_arch = "arm")]
66192#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66193#[cfg_attr(test, assert_instr(vst1))]
66194pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) {
66195    unsafe extern "unadjusted" {
66196        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0.v4i32.p0")]
66197        fn _vst1q_s32_x3(ptr: *mut i32, a: int32x4_t, b: int32x4_t, c: int32x4_t);
66198    }
66199    _vst1q_s32_x3(a, b.0, b.1, b.2)
66200}
66201#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66202#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"]
66203#[doc = "## Safety"]
66204#[doc = "  * Neon instrinsic unsafe"]
66205#[inline]
66206#[target_feature(enable = "neon,v7")]
66207#[cfg(target_arch = "arm")]
66208#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66209#[cfg_attr(test, assert_instr(vst1))]
66210pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) {
66211    unsafe extern "unadjusted" {
66212        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0.v1i64.p0")]
66213        fn _vst1_s64_x3(ptr: *mut i64, a: int64x1_t, b: int64x1_t, c: int64x1_t);
66214    }
66215    _vst1_s64_x3(a, b.0, b.1, b.2)
66216}
66217#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66218#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"]
66219#[doc = "## Safety"]
66220#[doc = "  * Neon instrinsic unsafe"]
66221#[inline]
66222#[target_feature(enable = "neon,v7")]
66223#[cfg(target_arch = "arm")]
66224#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66225#[cfg_attr(test, assert_instr(vst1))]
66226pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) {
66227    unsafe extern "unadjusted" {
66228        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0.v2i64.p0")]
66229        fn _vst1q_s64_x3(ptr: *mut i64, a: int64x2_t, b: int64x2_t, c: int64x2_t);
66230    }
66231    _vst1q_s64_x3(a, b.0, b.1, b.2)
66232}
66233#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66234#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"]
66235#[doc = "## Safety"]
66236#[doc = "  * Neon instrinsic unsafe"]
66237#[inline]
66238#[target_feature(enable = "neon")]
66239#[cfg(not(target_arch = "arm"))]
66240#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66241#[cfg_attr(test, assert_instr(st1))]
66242pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) {
66243    unsafe extern "unadjusted" {
66244        #[cfg_attr(
66245            any(target_arch = "aarch64", target_arch = "arm64ec"),
66246            link_name = "llvm.aarch64.neon.st1x4.v8i8.p0"
66247        )]
66248        fn _vst1_s8_x4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, ptr: *mut i8);
66249    }
66250    _vst1_s8_x4(b.0, b.1, b.2, b.3, a)
66251}
66252#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66253#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"]
66254#[doc = "## Safety"]
66255#[doc = "  * Neon instrinsic unsafe"]
66256#[inline]
66257#[target_feature(enable = "neon")]
66258#[cfg(not(target_arch = "arm"))]
66259#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66260#[cfg_attr(test, assert_instr(st1))]
66261pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) {
66262    unsafe extern "unadjusted" {
66263        #[cfg_attr(
66264            any(target_arch = "aarch64", target_arch = "arm64ec"),
66265            link_name = "llvm.aarch64.neon.st1x4.v16i8.p0"
66266        )]
66267        fn _vst1q_s8_x4(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, ptr: *mut i8);
66268    }
66269    _vst1q_s8_x4(b.0, b.1, b.2, b.3, a)
66270}
66271#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66272#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"]
66273#[doc = "## Safety"]
66274#[doc = "  * Neon instrinsic unsafe"]
66275#[inline]
66276#[target_feature(enable = "neon")]
66277#[cfg(not(target_arch = "arm"))]
66278#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66279#[cfg_attr(test, assert_instr(st1))]
66280pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) {
66281    unsafe extern "unadjusted" {
66282        #[cfg_attr(
66283            any(target_arch = "aarch64", target_arch = "arm64ec"),
66284            link_name = "llvm.aarch64.neon.st1x4.v4i16.p0"
66285        )]
66286        fn _vst1_s16_x4(a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t, ptr: *mut i16);
66287    }
66288    _vst1_s16_x4(b.0, b.1, b.2, b.3, a)
66289}
66290#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66291#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"]
66292#[doc = "## Safety"]
66293#[doc = "  * Neon instrinsic unsafe"]
66294#[inline]
66295#[target_feature(enable = "neon")]
66296#[cfg(not(target_arch = "arm"))]
66297#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66298#[cfg_attr(test, assert_instr(st1))]
66299pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) {
66300    unsafe extern "unadjusted" {
66301        #[cfg_attr(
66302            any(target_arch = "aarch64", target_arch = "arm64ec"),
66303            link_name = "llvm.aarch64.neon.st1x4.v8i16.p0"
66304        )]
66305        fn _vst1q_s16_x4(a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t, ptr: *mut i16);
66306    }
66307    _vst1q_s16_x4(b.0, b.1, b.2, b.3, a)
66308}
66309#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66310#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"]
66311#[doc = "## Safety"]
66312#[doc = "  * Neon instrinsic unsafe"]
66313#[inline]
66314#[target_feature(enable = "neon")]
66315#[cfg(not(target_arch = "arm"))]
66316#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66317#[cfg_attr(test, assert_instr(st1))]
66318pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) {
66319    unsafe extern "unadjusted" {
66320        #[cfg_attr(
66321            any(target_arch = "aarch64", target_arch = "arm64ec"),
66322            link_name = "llvm.aarch64.neon.st1x4.v2i32.p0"
66323        )]
66324        fn _vst1_s32_x4(a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t, ptr: *mut i32);
66325    }
66326    _vst1_s32_x4(b.0, b.1, b.2, b.3, a)
66327}
66328#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"]
66330#[doc = "## Safety"]
66331#[doc = "  * Neon instrinsic unsafe"]
66332#[inline]
66333#[target_feature(enable = "neon")]
66334#[cfg(not(target_arch = "arm"))]
66335#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66336#[cfg_attr(test, assert_instr(st1))]
66337pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) {
66338    unsafe extern "unadjusted" {
66339        #[cfg_attr(
66340            any(target_arch = "aarch64", target_arch = "arm64ec"),
66341            link_name = "llvm.aarch64.neon.st1x4.v4i32.p0"
66342        )]
66343        fn _vst1q_s32_x4(a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t, ptr: *mut i32);
66344    }
66345    _vst1q_s32_x4(b.0, b.1, b.2, b.3, a)
66346}
66347#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66348#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"]
66349#[doc = "## Safety"]
66350#[doc = "  * Neon instrinsic unsafe"]
66351#[inline]
66352#[target_feature(enable = "neon")]
66353#[cfg(not(target_arch = "arm"))]
66354#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66355#[cfg_attr(test, assert_instr(st1))]
66356pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) {
66357    unsafe extern "unadjusted" {
66358        #[cfg_attr(
66359            any(target_arch = "aarch64", target_arch = "arm64ec"),
66360            link_name = "llvm.aarch64.neon.st1x4.v1i64.p0"
66361        )]
66362        fn _vst1_s64_x4(a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t, ptr: *mut i64);
66363    }
66364    _vst1_s64_x4(b.0, b.1, b.2, b.3, a)
66365}
66366#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66367#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"]
66368#[doc = "## Safety"]
66369#[doc = "  * Neon instrinsic unsafe"]
66370#[inline]
66371#[target_feature(enable = "neon")]
66372#[cfg(not(target_arch = "arm"))]
66373#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66374#[cfg_attr(test, assert_instr(st1))]
66375pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) {
66376    unsafe extern "unadjusted" {
66377        #[cfg_attr(
66378            any(target_arch = "aarch64", target_arch = "arm64ec"),
66379            link_name = "llvm.aarch64.neon.st1x4.v2i64.p0"
66380        )]
66381        fn _vst1q_s64_x4(a: int64x2_t, b: int64x2_t, c: int64x2_t, d: int64x2_t, ptr: *mut i64);
66382    }
66383    _vst1q_s64_x4(b.0, b.1, b.2, b.3, a)
66384}
66385#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66386#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"]
66387#[doc = "## Safety"]
66388#[doc = "  * Neon instrinsic unsafe"]
66389#[inline]
66390#[cfg(target_arch = "arm")]
66391#[target_feature(enable = "neon,v7")]
66392#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66393#[cfg_attr(test, assert_instr(vst1))]
66394pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) {
66395    unsafe extern "unadjusted" {
66396        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v8i8.p0")]
66397        fn _vst1_s8_x4(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t);
66398    }
66399    _vst1_s8_x4(a, b.0, b.1, b.2, b.3)
66400}
66401#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66402#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"]
66403#[doc = "## Safety"]
66404#[doc = "  * Neon instrinsic unsafe"]
66405#[inline]
66406#[cfg(target_arch = "arm")]
66407#[target_feature(enable = "neon,v7")]
66408#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66409#[cfg_attr(test, assert_instr(vst1))]
66410pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) {
66411    unsafe extern "unadjusted" {
66412        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v16i8.p0")]
66413        fn _vst1q_s8_x4(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t);
66414    }
66415    _vst1q_s8_x4(a, b.0, b.1, b.2, b.3)
66416}
66417#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"]
66419#[doc = "## Safety"]
66420#[doc = "  * Neon instrinsic unsafe"]
66421#[inline]
66422#[cfg(target_arch = "arm")]
66423#[target_feature(enable = "neon,v7")]
66424#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66425#[cfg_attr(test, assert_instr(vst1))]
66426pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) {
66427    unsafe extern "unadjusted" {
66428        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v4i16.p0")]
66429        fn _vst1_s16_x4(ptr: *mut i16, a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t);
66430    }
66431    _vst1_s16_x4(a, b.0, b.1, b.2, b.3)
66432}
66433#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66434#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"]
66435#[doc = "## Safety"]
66436#[doc = "  * Neon instrinsic unsafe"]
66437#[inline]
66438#[cfg(target_arch = "arm")]
66439#[target_feature(enable = "neon,v7")]
66440#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66441#[cfg_attr(test, assert_instr(vst1))]
66442pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) {
66443    unsafe extern "unadjusted" {
66444        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v8i16.p0")]
66445        fn _vst1q_s16_x4(ptr: *mut i16, a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t);
66446    }
66447    _vst1q_s16_x4(a, b.0, b.1, b.2, b.3)
66448}
66449#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66450#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"]
66451#[doc = "## Safety"]
66452#[doc = "  * Neon instrinsic unsafe"]
66453#[inline]
66454#[cfg(target_arch = "arm")]
66455#[target_feature(enable = "neon,v7")]
66456#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66457#[cfg_attr(test, assert_instr(vst1))]
66458pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) {
66459    unsafe extern "unadjusted" {
66460        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v2i32.p0")]
66461        fn _vst1_s32_x4(ptr: *mut i32, a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t);
66462    }
66463    _vst1_s32_x4(a, b.0, b.1, b.2, b.3)
66464}
66465#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66466#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"]
66467#[doc = "## Safety"]
66468#[doc = "  * Neon instrinsic unsafe"]
66469#[inline]
66470#[cfg(target_arch = "arm")]
66471#[target_feature(enable = "neon,v7")]
66472#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66473#[cfg_attr(test, assert_instr(vst1))]
66474pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) {
66475    unsafe extern "unadjusted" {
66476        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v4i32.p0")]
66477        fn _vst1q_s32_x4(ptr: *mut i32, a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t);
66478    }
66479    _vst1q_s32_x4(a, b.0, b.1, b.2, b.3)
66480}
66481#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"]
66483#[doc = "## Safety"]
66484#[doc = "  * Neon instrinsic unsafe"]
66485#[inline]
66486#[cfg(target_arch = "arm")]
66487#[target_feature(enable = "neon,v7")]
66488#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66489#[cfg_attr(test, assert_instr(vst1))]
66490pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) {
66491    unsafe extern "unadjusted" {
66492        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v1i64.p0")]
66493        fn _vst1_s64_x4(ptr: *mut i64, a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t);
66494    }
66495    _vst1_s64_x4(a, b.0, b.1, b.2, b.3)
66496}
66497#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66498#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"]
66499#[doc = "## Safety"]
66500#[doc = "  * Neon instrinsic unsafe"]
66501#[inline]
66502#[cfg(target_arch = "arm")]
66503#[target_feature(enable = "neon,v7")]
66504#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66505#[cfg_attr(test, assert_instr(vst1))]
66506pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) {
66507    unsafe extern "unadjusted" {
66508        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v2i64.p0")]
66509        fn _vst1q_s64_x4(ptr: *mut i64, a: int64x2_t, b: int64x2_t, c: int64x2_t, d: int64x2_t);
66510    }
66511    _vst1q_s64_x4(a, b.0, b.1, b.2, b.3)
66512}
66513#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66514#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x2)"]
66515#[doc = "## Safety"]
66516#[doc = "  * Neon instrinsic unsafe"]
66517#[inline]
66518#[target_feature(enable = "neon")]
66519#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66520#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66521#[cfg_attr(
66522    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66523    assert_instr(st1)
66524)]
66525#[cfg_attr(
66526    not(target_arch = "arm"),
66527    stable(feature = "neon_intrinsics", since = "1.59.0")
66528)]
66529#[cfg_attr(
66530    target_arch = "arm",
66531    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66532)]
66533pub unsafe fn vst1_u8_x2(a: *mut u8, b: uint8x8x2_t) {
66534    vst1_s8_x2(transmute(a), transmute(b))
66535}
66536#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66537#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x3)"]
66538#[doc = "## Safety"]
66539#[doc = "  * Neon instrinsic unsafe"]
66540#[inline]
66541#[target_feature(enable = "neon")]
66542#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66543#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66544#[cfg_attr(
66545    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66546    assert_instr(st1)
66547)]
66548#[cfg_attr(
66549    not(target_arch = "arm"),
66550    stable(feature = "neon_intrinsics", since = "1.59.0")
66551)]
66552#[cfg_attr(
66553    target_arch = "arm",
66554    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66555)]
66556pub unsafe fn vst1_u8_x3(a: *mut u8, b: uint8x8x3_t) {
66557    vst1_s8_x3(transmute(a), transmute(b))
66558}
66559#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66560#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x4)"]
66561#[doc = "## Safety"]
66562#[doc = "  * Neon instrinsic unsafe"]
66563#[inline]
66564#[target_feature(enable = "neon")]
66565#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66566#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66567#[cfg_attr(
66568    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66569    assert_instr(st1)
66570)]
66571#[cfg_attr(
66572    not(target_arch = "arm"),
66573    stable(feature = "neon_intrinsics", since = "1.59.0")
66574)]
66575#[cfg_attr(
66576    target_arch = "arm",
66577    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66578)]
66579pub unsafe fn vst1_u8_x4(a: *mut u8, b: uint8x8x4_t) {
66580    vst1_s8_x4(transmute(a), transmute(b))
66581}
66582#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66583#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x2)"]
66584#[doc = "## Safety"]
66585#[doc = "  * Neon instrinsic unsafe"]
66586#[inline]
66587#[target_feature(enable = "neon")]
66588#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66589#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66590#[cfg_attr(
66591    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66592    assert_instr(st1)
66593)]
66594#[cfg_attr(
66595    not(target_arch = "arm"),
66596    stable(feature = "neon_intrinsics", since = "1.59.0")
66597)]
66598#[cfg_attr(
66599    target_arch = "arm",
66600    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66601)]
66602pub unsafe fn vst1q_u8_x2(a: *mut u8, b: uint8x16x2_t) {
66603    vst1q_s8_x2(transmute(a), transmute(b))
66604}
66605#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66606#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x3)"]
66607#[doc = "## Safety"]
66608#[doc = "  * Neon instrinsic unsafe"]
66609#[inline]
66610#[target_feature(enable = "neon")]
66611#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66612#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66613#[cfg_attr(
66614    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66615    assert_instr(st1)
66616)]
66617#[cfg_attr(
66618    not(target_arch = "arm"),
66619    stable(feature = "neon_intrinsics", since = "1.59.0")
66620)]
66621#[cfg_attr(
66622    target_arch = "arm",
66623    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66624)]
66625pub unsafe fn vst1q_u8_x3(a: *mut u8, b: uint8x16x3_t) {
66626    vst1q_s8_x3(transmute(a), transmute(b))
66627}
66628#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66629#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x4)"]
66630#[doc = "## Safety"]
66631#[doc = "  * Neon instrinsic unsafe"]
66632#[inline]
66633#[target_feature(enable = "neon")]
66634#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66635#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66636#[cfg_attr(
66637    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66638    assert_instr(st1)
66639)]
66640#[cfg_attr(
66641    not(target_arch = "arm"),
66642    stable(feature = "neon_intrinsics", since = "1.59.0")
66643)]
66644#[cfg_attr(
66645    target_arch = "arm",
66646    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66647)]
66648pub unsafe fn vst1q_u8_x4(a: *mut u8, b: uint8x16x4_t) {
66649    vst1q_s8_x4(transmute(a), transmute(b))
66650}
66651#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66652#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x2)"]
66653#[doc = "## Safety"]
66654#[doc = "  * Neon instrinsic unsafe"]
66655#[inline]
66656#[target_feature(enable = "neon")]
66657#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66658#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66659#[cfg_attr(
66660    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66661    assert_instr(st1)
66662)]
66663#[cfg_attr(
66664    not(target_arch = "arm"),
66665    stable(feature = "neon_intrinsics", since = "1.59.0")
66666)]
66667#[cfg_attr(
66668    target_arch = "arm",
66669    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66670)]
66671pub unsafe fn vst1_u16_x2(a: *mut u16, b: uint16x4x2_t) {
66672    vst1_s16_x2(transmute(a), transmute(b))
66673}
66674#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66675#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x3)"]
66676#[doc = "## Safety"]
66677#[doc = "  * Neon instrinsic unsafe"]
66678#[inline]
66679#[target_feature(enable = "neon")]
66680#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66681#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66682#[cfg_attr(
66683    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66684    assert_instr(st1)
66685)]
66686#[cfg_attr(
66687    not(target_arch = "arm"),
66688    stable(feature = "neon_intrinsics", since = "1.59.0")
66689)]
66690#[cfg_attr(
66691    target_arch = "arm",
66692    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66693)]
66694pub unsafe fn vst1_u16_x3(a: *mut u16, b: uint16x4x3_t) {
66695    vst1_s16_x3(transmute(a), transmute(b))
66696}
66697#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66698#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x4)"]
66699#[doc = "## Safety"]
66700#[doc = "  * Neon instrinsic unsafe"]
66701#[inline]
66702#[target_feature(enable = "neon")]
66703#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66704#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66705#[cfg_attr(
66706    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66707    assert_instr(st1)
66708)]
66709#[cfg_attr(
66710    not(target_arch = "arm"),
66711    stable(feature = "neon_intrinsics", since = "1.59.0")
66712)]
66713#[cfg_attr(
66714    target_arch = "arm",
66715    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66716)]
66717pub unsafe fn vst1_u16_x4(a: *mut u16, b: uint16x4x4_t) {
66718    vst1_s16_x4(transmute(a), transmute(b))
66719}
66720#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66721#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x2)"]
66722#[doc = "## Safety"]
66723#[doc = "  * Neon instrinsic unsafe"]
66724#[inline]
66725#[target_feature(enable = "neon")]
66726#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66727#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66728#[cfg_attr(
66729    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66730    assert_instr(st1)
66731)]
66732#[cfg_attr(
66733    not(target_arch = "arm"),
66734    stable(feature = "neon_intrinsics", since = "1.59.0")
66735)]
66736#[cfg_attr(
66737    target_arch = "arm",
66738    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66739)]
66740pub unsafe fn vst1q_u16_x2(a: *mut u16, b: uint16x8x2_t) {
66741    vst1q_s16_x2(transmute(a), transmute(b))
66742}
66743#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66744#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x3)"]
66745#[doc = "## Safety"]
66746#[doc = "  * Neon instrinsic unsafe"]
66747#[inline]
66748#[target_feature(enable = "neon")]
66749#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66750#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66751#[cfg_attr(
66752    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66753    assert_instr(st1)
66754)]
66755#[cfg_attr(
66756    not(target_arch = "arm"),
66757    stable(feature = "neon_intrinsics", since = "1.59.0")
66758)]
66759#[cfg_attr(
66760    target_arch = "arm",
66761    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66762)]
66763pub unsafe fn vst1q_u16_x3(a: *mut u16, b: uint16x8x3_t) {
66764    vst1q_s16_x3(transmute(a), transmute(b))
66765}
66766#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66767#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x4)"]
66768#[doc = "## Safety"]
66769#[doc = "  * Neon instrinsic unsafe"]
66770#[inline]
66771#[target_feature(enable = "neon")]
66772#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66773#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66774#[cfg_attr(
66775    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66776    assert_instr(st1)
66777)]
66778#[cfg_attr(
66779    not(target_arch = "arm"),
66780    stable(feature = "neon_intrinsics", since = "1.59.0")
66781)]
66782#[cfg_attr(
66783    target_arch = "arm",
66784    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66785)]
66786pub unsafe fn vst1q_u16_x4(a: *mut u16, b: uint16x8x4_t) {
66787    vst1q_s16_x4(transmute(a), transmute(b))
66788}
66789#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66790#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x2)"]
66791#[doc = "## Safety"]
66792#[doc = "  * Neon instrinsic unsafe"]
66793#[inline]
66794#[target_feature(enable = "neon")]
66795#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66796#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66797#[cfg_attr(
66798    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66799    assert_instr(st1)
66800)]
66801#[cfg_attr(
66802    not(target_arch = "arm"),
66803    stable(feature = "neon_intrinsics", since = "1.59.0")
66804)]
66805#[cfg_attr(
66806    target_arch = "arm",
66807    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66808)]
66809pub unsafe fn vst1_u32_x2(a: *mut u32, b: uint32x2x2_t) {
66810    vst1_s32_x2(transmute(a), transmute(b))
66811}
66812#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66813#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x3)"]
66814#[doc = "## Safety"]
66815#[doc = "  * Neon instrinsic unsafe"]
66816#[inline]
66817#[target_feature(enable = "neon")]
66818#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66819#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66820#[cfg_attr(
66821    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66822    assert_instr(st1)
66823)]
66824#[cfg_attr(
66825    not(target_arch = "arm"),
66826    stable(feature = "neon_intrinsics", since = "1.59.0")
66827)]
66828#[cfg_attr(
66829    target_arch = "arm",
66830    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66831)]
66832pub unsafe fn vst1_u32_x3(a: *mut u32, b: uint32x2x3_t) {
66833    vst1_s32_x3(transmute(a), transmute(b))
66834}
66835#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66836#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x4)"]
66837#[doc = "## Safety"]
66838#[doc = "  * Neon instrinsic unsafe"]
66839#[inline]
66840#[target_feature(enable = "neon")]
66841#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66842#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66843#[cfg_attr(
66844    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66845    assert_instr(st1)
66846)]
66847#[cfg_attr(
66848    not(target_arch = "arm"),
66849    stable(feature = "neon_intrinsics", since = "1.59.0")
66850)]
66851#[cfg_attr(
66852    target_arch = "arm",
66853    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66854)]
66855pub unsafe fn vst1_u32_x4(a: *mut u32, b: uint32x2x4_t) {
66856    vst1_s32_x4(transmute(a), transmute(b))
66857}
66858#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66859#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x2)"]
66860#[doc = "## Safety"]
66861#[doc = "  * Neon instrinsic unsafe"]
66862#[inline]
66863#[target_feature(enable = "neon")]
66864#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66865#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66866#[cfg_attr(
66867    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66868    assert_instr(st1)
66869)]
66870#[cfg_attr(
66871    not(target_arch = "arm"),
66872    stable(feature = "neon_intrinsics", since = "1.59.0")
66873)]
66874#[cfg_attr(
66875    target_arch = "arm",
66876    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66877)]
66878pub unsafe fn vst1q_u32_x2(a: *mut u32, b: uint32x4x2_t) {
66879    vst1q_s32_x2(transmute(a), transmute(b))
66880}
66881#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x3)"]
66883#[doc = "## Safety"]
66884#[doc = "  * Neon instrinsic unsafe"]
66885#[inline]
66886#[target_feature(enable = "neon")]
66887#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66888#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66889#[cfg_attr(
66890    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66891    assert_instr(st1)
66892)]
66893#[cfg_attr(
66894    not(target_arch = "arm"),
66895    stable(feature = "neon_intrinsics", since = "1.59.0")
66896)]
66897#[cfg_attr(
66898    target_arch = "arm",
66899    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66900)]
66901pub unsafe fn vst1q_u32_x3(a: *mut u32, b: uint32x4x3_t) {
66902    vst1q_s32_x3(transmute(a), transmute(b))
66903}
66904#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66905#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x4)"]
66906#[doc = "## Safety"]
66907#[doc = "  * Neon instrinsic unsafe"]
66908#[inline]
66909#[target_feature(enable = "neon")]
66910#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66911#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66912#[cfg_attr(
66913    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66914    assert_instr(st1)
66915)]
66916#[cfg_attr(
66917    not(target_arch = "arm"),
66918    stable(feature = "neon_intrinsics", since = "1.59.0")
66919)]
66920#[cfg_attr(
66921    target_arch = "arm",
66922    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66923)]
66924pub unsafe fn vst1q_u32_x4(a: *mut u32, b: uint32x4x4_t) {
66925    vst1q_s32_x4(transmute(a), transmute(b))
66926}
66927#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66928#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x2)"]
66929#[doc = "## Safety"]
66930#[doc = "  * Neon instrinsic unsafe"]
66931#[inline]
66932#[target_feature(enable = "neon")]
66933#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66934#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66935#[cfg_attr(
66936    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66937    assert_instr(st1)
66938)]
66939#[cfg_attr(
66940    not(target_arch = "arm"),
66941    stable(feature = "neon_intrinsics", since = "1.59.0")
66942)]
66943#[cfg_attr(
66944    target_arch = "arm",
66945    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66946)]
66947pub unsafe fn vst1_u64_x2(a: *mut u64, b: uint64x1x2_t) {
66948    vst1_s64_x2(transmute(a), transmute(b))
66949}
66950#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x3)"]
66952#[doc = "## Safety"]
66953#[doc = "  * Neon instrinsic unsafe"]
66954#[inline]
66955#[target_feature(enable = "neon")]
66956#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66957#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66958#[cfg_attr(
66959    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66960    assert_instr(st1)
66961)]
66962#[cfg_attr(
66963    not(target_arch = "arm"),
66964    stable(feature = "neon_intrinsics", since = "1.59.0")
66965)]
66966#[cfg_attr(
66967    target_arch = "arm",
66968    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66969)]
66970pub unsafe fn vst1_u64_x3(a: *mut u64, b: uint64x1x3_t) {
66971    vst1_s64_x3(transmute(a), transmute(b))
66972}
66973#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66974#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x4)"]
66975#[doc = "## Safety"]
66976#[doc = "  * Neon instrinsic unsafe"]
66977#[inline]
66978#[target_feature(enable = "neon")]
66979#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66980#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66981#[cfg_attr(
66982    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66983    assert_instr(st1)
66984)]
66985#[cfg_attr(
66986    not(target_arch = "arm"),
66987    stable(feature = "neon_intrinsics", since = "1.59.0")
66988)]
66989#[cfg_attr(
66990    target_arch = "arm",
66991    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66992)]
66993pub unsafe fn vst1_u64_x4(a: *mut u64, b: uint64x1x4_t) {
66994    vst1_s64_x4(transmute(a), transmute(b))
66995}
66996#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x2)"]
66998#[doc = "## Safety"]
66999#[doc = "  * Neon instrinsic unsafe"]
67000#[inline]
67001#[target_feature(enable = "neon")]
67002#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67003#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67004#[cfg_attr(
67005    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67006    assert_instr(st1)
67007)]
67008#[cfg_attr(
67009    not(target_arch = "arm"),
67010    stable(feature = "neon_intrinsics", since = "1.59.0")
67011)]
67012#[cfg_attr(
67013    target_arch = "arm",
67014    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67015)]
67016pub unsafe fn vst1q_u64_x2(a: *mut u64, b: uint64x2x2_t) {
67017    vst1q_s64_x2(transmute(a), transmute(b))
67018}
67019#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67020#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x3)"]
67021#[doc = "## Safety"]
67022#[doc = "  * Neon instrinsic unsafe"]
67023#[inline]
67024#[target_feature(enable = "neon")]
67025#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67026#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67027#[cfg_attr(
67028    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67029    assert_instr(st1)
67030)]
67031#[cfg_attr(
67032    not(target_arch = "arm"),
67033    stable(feature = "neon_intrinsics", since = "1.59.0")
67034)]
67035#[cfg_attr(
67036    target_arch = "arm",
67037    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67038)]
67039pub unsafe fn vst1q_u64_x3(a: *mut u64, b: uint64x2x3_t) {
67040    vst1q_s64_x3(transmute(a), transmute(b))
67041}
67042#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67043#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x4)"]
67044#[doc = "## Safety"]
67045#[doc = "  * Neon instrinsic unsafe"]
67046#[inline]
67047#[target_feature(enable = "neon")]
67048#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67049#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67050#[cfg_attr(
67051    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67052    assert_instr(st1)
67053)]
67054#[cfg_attr(
67055    not(target_arch = "arm"),
67056    stable(feature = "neon_intrinsics", since = "1.59.0")
67057)]
67058#[cfg_attr(
67059    target_arch = "arm",
67060    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67061)]
67062pub unsafe fn vst1q_u64_x4(a: *mut u64, b: uint64x2x4_t) {
67063    vst1q_s64_x4(transmute(a), transmute(b))
67064}
67065#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67066#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x2)"]
67067#[doc = "## Safety"]
67068#[doc = "  * Neon instrinsic unsafe"]
67069#[inline]
67070#[target_feature(enable = "neon")]
67071#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67072#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67073#[cfg_attr(
67074    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67075    assert_instr(st1)
67076)]
67077#[cfg_attr(
67078    not(target_arch = "arm"),
67079    stable(feature = "neon_intrinsics", since = "1.59.0")
67080)]
67081#[cfg_attr(
67082    target_arch = "arm",
67083    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67084)]
67085pub unsafe fn vst1_p8_x2(a: *mut p8, b: poly8x8x2_t) {
67086    vst1_s8_x2(transmute(a), transmute(b))
67087}
67088#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67089#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x3)"]
67090#[doc = "## Safety"]
67091#[doc = "  * Neon instrinsic unsafe"]
67092#[inline]
67093#[target_feature(enable = "neon")]
67094#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67095#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67096#[cfg_attr(
67097    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67098    assert_instr(st1)
67099)]
67100#[cfg_attr(
67101    not(target_arch = "arm"),
67102    stable(feature = "neon_intrinsics", since = "1.59.0")
67103)]
67104#[cfg_attr(
67105    target_arch = "arm",
67106    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67107)]
67108pub unsafe fn vst1_p8_x3(a: *mut p8, b: poly8x8x3_t) {
67109    vst1_s8_x3(transmute(a), transmute(b))
67110}
67111#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67112#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x4)"]
67113#[doc = "## Safety"]
67114#[doc = "  * Neon instrinsic unsafe"]
67115#[inline]
67116#[target_feature(enable = "neon")]
67117#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67118#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67119#[cfg_attr(
67120    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67121    assert_instr(st1)
67122)]
67123#[cfg_attr(
67124    not(target_arch = "arm"),
67125    stable(feature = "neon_intrinsics", since = "1.59.0")
67126)]
67127#[cfg_attr(
67128    target_arch = "arm",
67129    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67130)]
67131pub unsafe fn vst1_p8_x4(a: *mut p8, b: poly8x8x4_t) {
67132    vst1_s8_x4(transmute(a), transmute(b))
67133}
67134#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67135#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x2)"]
67136#[doc = "## Safety"]
67137#[doc = "  * Neon instrinsic unsafe"]
67138#[inline]
67139#[target_feature(enable = "neon")]
67140#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67141#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67142#[cfg_attr(
67143    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67144    assert_instr(st1)
67145)]
67146#[cfg_attr(
67147    not(target_arch = "arm"),
67148    stable(feature = "neon_intrinsics", since = "1.59.0")
67149)]
67150#[cfg_attr(
67151    target_arch = "arm",
67152    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67153)]
67154pub unsafe fn vst1q_p8_x2(a: *mut p8, b: poly8x16x2_t) {
67155    vst1q_s8_x2(transmute(a), transmute(b))
67156}
67157#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67158#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x3)"]
67159#[doc = "## Safety"]
67160#[doc = "  * Neon instrinsic unsafe"]
67161#[inline]
67162#[target_feature(enable = "neon")]
67163#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67164#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67165#[cfg_attr(
67166    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67167    assert_instr(st1)
67168)]
67169#[cfg_attr(
67170    not(target_arch = "arm"),
67171    stable(feature = "neon_intrinsics", since = "1.59.0")
67172)]
67173#[cfg_attr(
67174    target_arch = "arm",
67175    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67176)]
67177pub unsafe fn vst1q_p8_x3(a: *mut p8, b: poly8x16x3_t) {
67178    vst1q_s8_x3(transmute(a), transmute(b))
67179}
67180#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x4)"]
67182#[doc = "## Safety"]
67183#[doc = "  * Neon instrinsic unsafe"]
67184#[inline]
67185#[target_feature(enable = "neon")]
67186#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67187#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67188#[cfg_attr(
67189    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67190    assert_instr(st1)
67191)]
67192#[cfg_attr(
67193    not(target_arch = "arm"),
67194    stable(feature = "neon_intrinsics", since = "1.59.0")
67195)]
67196#[cfg_attr(
67197    target_arch = "arm",
67198    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67199)]
67200pub unsafe fn vst1q_p8_x4(a: *mut p8, b: poly8x16x4_t) {
67201    vst1q_s8_x4(transmute(a), transmute(b))
67202}
67203#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x2)"]
67205#[doc = "## Safety"]
67206#[doc = "  * Neon instrinsic unsafe"]
67207#[inline]
67208#[target_feature(enable = "neon")]
67209#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67210#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67211#[cfg_attr(
67212    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67213    assert_instr(st1)
67214)]
67215#[cfg_attr(
67216    not(target_arch = "arm"),
67217    stable(feature = "neon_intrinsics", since = "1.59.0")
67218)]
67219#[cfg_attr(
67220    target_arch = "arm",
67221    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67222)]
67223pub unsafe fn vst1_p16_x2(a: *mut p16, b: poly16x4x2_t) {
67224    vst1_s16_x2(transmute(a), transmute(b))
67225}
67226#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67227#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x3)"]
67228#[doc = "## Safety"]
67229#[doc = "  * Neon instrinsic unsafe"]
67230#[inline]
67231#[target_feature(enable = "neon")]
67232#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67233#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67234#[cfg_attr(
67235    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67236    assert_instr(st1)
67237)]
67238#[cfg_attr(
67239    not(target_arch = "arm"),
67240    stable(feature = "neon_intrinsics", since = "1.59.0")
67241)]
67242#[cfg_attr(
67243    target_arch = "arm",
67244    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67245)]
67246pub unsafe fn vst1_p16_x3(a: *mut p16, b: poly16x4x3_t) {
67247    vst1_s16_x3(transmute(a), transmute(b))
67248}
67249#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67250#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x4)"]
67251#[doc = "## Safety"]
67252#[doc = "  * Neon instrinsic unsafe"]
67253#[inline]
67254#[target_feature(enable = "neon")]
67255#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67256#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67257#[cfg_attr(
67258    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67259    assert_instr(st1)
67260)]
67261#[cfg_attr(
67262    not(target_arch = "arm"),
67263    stable(feature = "neon_intrinsics", since = "1.59.0")
67264)]
67265#[cfg_attr(
67266    target_arch = "arm",
67267    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67268)]
67269pub unsafe fn vst1_p16_x4(a: *mut p16, b: poly16x4x4_t) {
67270    vst1_s16_x4(transmute(a), transmute(b))
67271}
67272#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67273#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x2)"]
67274#[doc = "## Safety"]
67275#[doc = "  * Neon instrinsic unsafe"]
67276#[inline]
67277#[target_feature(enable = "neon")]
67278#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67279#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67280#[cfg_attr(
67281    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67282    assert_instr(st1)
67283)]
67284#[cfg_attr(
67285    not(target_arch = "arm"),
67286    stable(feature = "neon_intrinsics", since = "1.59.0")
67287)]
67288#[cfg_attr(
67289    target_arch = "arm",
67290    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67291)]
67292pub unsafe fn vst1q_p16_x2(a: *mut p16, b: poly16x8x2_t) {
67293    vst1q_s16_x2(transmute(a), transmute(b))
67294}
67295#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67296#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x3)"]
67297#[doc = "## Safety"]
67298#[doc = "  * Neon instrinsic unsafe"]
67299#[inline]
67300#[target_feature(enable = "neon")]
67301#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67302#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67303#[cfg_attr(
67304    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67305    assert_instr(st1)
67306)]
67307#[cfg_attr(
67308    not(target_arch = "arm"),
67309    stable(feature = "neon_intrinsics", since = "1.59.0")
67310)]
67311#[cfg_attr(
67312    target_arch = "arm",
67313    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67314)]
67315pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) {
67316    vst1q_s16_x3(transmute(a), transmute(b))
67317}
67318#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67319#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x4)"]
67320#[doc = "## Safety"]
67321#[doc = "  * Neon instrinsic unsafe"]
67322#[inline]
67323#[target_feature(enable = "neon")]
67324#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67325#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67326#[cfg_attr(
67327    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67328    assert_instr(st1)
67329)]
67330#[cfg_attr(
67331    not(target_arch = "arm"),
67332    stable(feature = "neon_intrinsics", since = "1.59.0")
67333)]
67334#[cfg_attr(
67335    target_arch = "arm",
67336    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67337)]
67338pub unsafe fn vst1q_p16_x4(a: *mut p16, b: poly16x8x4_t) {
67339    vst1q_s16_x4(transmute(a), transmute(b))
67340}
67341#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67342#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v1i64)"]
67343#[doc = "## Safety"]
67344#[doc = "  * Neon instrinsic unsafe"]
67345#[inline]
67346#[target_feature(enable = "neon")]
67347#[cfg(target_arch = "arm")]
67348#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67349#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67350#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
67351unsafe fn vst1_v1i64(addr: *const i8, val: int64x1_t, align: i32) {
67352    unsafe extern "unadjusted" {
67353        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v1i64.p0")]
67354        fn _vst1_v1i64(addr: *const i8, val: int64x1_t, align: i32);
67355    }
67356    _vst1_v1i64(addr, val, align)
67357}
67358#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67359#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v2f32)"]
67360#[doc = "## Safety"]
67361#[doc = "  * Neon instrinsic unsafe"]
67362#[inline]
67363#[target_feature(enable = "neon")]
67364#[cfg(target_arch = "arm")]
67365#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67366#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67367#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
67368unsafe fn vst1_v2f32(addr: *const i8, val: float32x2_t, align: i32) {
67369    unsafe extern "unadjusted" {
67370        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v2f32.p0")]
67371        fn _vst1_v2f32(addr: *const i8, val: float32x2_t, align: i32);
67372    }
67373    _vst1_v2f32(addr, val, align)
67374}
67375#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v2i32)"]
67377#[doc = "## Safety"]
67378#[doc = "  * Neon instrinsic unsafe"]
67379#[inline]
67380#[target_feature(enable = "neon")]
67381#[cfg(target_arch = "arm")]
67382#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67383#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67384#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
67385unsafe fn vst1_v2i32(addr: *const i8, val: int32x2_t, align: i32) {
67386    unsafe extern "unadjusted" {
67387        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v2i32.p0")]
67388        fn _vst1_v2i32(addr: *const i8, val: int32x2_t, align: i32);
67389    }
67390    _vst1_v2i32(addr, val, align)
67391}
67392#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67393#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v4i16)"]
67394#[doc = "## Safety"]
67395#[doc = "  * Neon instrinsic unsafe"]
67396#[inline]
67397#[target_feature(enable = "neon")]
67398#[cfg(target_arch = "arm")]
67399#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67400#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67401#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
67402unsafe fn vst1_v4i16(addr: *const i8, val: int16x4_t, align: i32) {
67403    unsafe extern "unadjusted" {
67404        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v4i16.p0")]
67405        fn _vst1_v4i16(addr: *const i8, val: int16x4_t, align: i32);
67406    }
67407    _vst1_v4i16(addr, val, align)
67408}
67409#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67410#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v8i8)"]
67411#[doc = "## Safety"]
67412#[doc = "  * Neon instrinsic unsafe"]
67413#[inline]
67414#[target_feature(enable = "neon")]
67415#[cfg(target_arch = "arm")]
67416#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67417#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67418#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
67419unsafe fn vst1_v8i8(addr: *const i8, val: int8x8_t, align: i32) {
67420    unsafe extern "unadjusted" {
67421        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v8i8.p0")]
67422        fn _vst1_v8i8(addr: *const i8, val: int8x8_t, align: i32);
67423    }
67424    _vst1_v8i8(addr, val, align)
67425}
67426#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67427#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v16i8)"]
67428#[doc = "## Safety"]
67429#[doc = "  * Neon instrinsic unsafe"]
67430#[inline]
67431#[target_feature(enable = "neon")]
67432#[cfg(target_arch = "arm")]
67433#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67434#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67435#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
67436unsafe fn vst1q_v16i8(addr: *const i8, val: int8x16_t, align: i32) {
67437    unsafe extern "unadjusted" {
67438        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v16i8.p0")]
67439        fn _vst1q_v16i8(addr: *const i8, val: int8x16_t, align: i32);
67440    }
67441    _vst1q_v16i8(addr, val, align)
67442}
67443#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67444#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v2i64)"]
67445#[doc = "## Safety"]
67446#[doc = "  * Neon instrinsic unsafe"]
67447#[inline]
67448#[target_feature(enable = "neon")]
67449#[cfg(target_arch = "arm")]
67450#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67451#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67452#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
67453unsafe fn vst1q_v2i64(addr: *const i8, val: int64x2_t, align: i32) {
67454    unsafe extern "unadjusted" {
67455        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v2i64.p0")]
67456        fn _vst1q_v2i64(addr: *const i8, val: int64x2_t, align: i32);
67457    }
67458    _vst1q_v2i64(addr, val, align)
67459}
67460#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67461#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v4f32)"]
67462#[doc = "## Safety"]
67463#[doc = "  * Neon instrinsic unsafe"]
67464#[inline]
67465#[target_feature(enable = "neon")]
67466#[cfg(target_arch = "arm")]
67467#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67468#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67469#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
67470unsafe fn vst1q_v4f32(addr: *const i8, val: float32x4_t, align: i32) {
67471    unsafe extern "unadjusted" {
67472        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v4f32.p0")]
67473        fn _vst1q_v4f32(addr: *const i8, val: float32x4_t, align: i32);
67474    }
67475    _vst1q_v4f32(addr, val, align)
67476}
67477#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67478#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v4i32)"]
67479#[doc = "## Safety"]
67480#[doc = "  * Neon instrinsic unsafe"]
67481#[inline]
67482#[target_feature(enable = "neon")]
67483#[cfg(target_arch = "arm")]
67484#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67485#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67486#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
67487unsafe fn vst1q_v4i32(addr: *const i8, val: int32x4_t, align: i32) {
67488    unsafe extern "unadjusted" {
67489        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v4i32.p0")]
67490        fn _vst1q_v4i32(addr: *const i8, val: int32x4_t, align: i32);
67491    }
67492    _vst1q_v4i32(addr, val, align)
67493}
67494#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67495#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v8i16)"]
67496#[doc = "## Safety"]
67497#[doc = "  * Neon instrinsic unsafe"]
67498#[inline]
67499#[target_feature(enable = "neon")]
67500#[cfg(target_arch = "arm")]
67501#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67502#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67503#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
67504unsafe fn vst1q_v8i16(addr: *const i8, val: int16x8_t, align: i32) {
67505    unsafe extern "unadjusted" {
67506        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v8i16.p0")]
67507        fn _vst1q_v8i16(addr: *const i8, val: int16x8_t, align: i32);
67508    }
67509    _vst1q_v8i16(addr, val, align)
67510}
67511#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67512#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v4f16)"]
67513#[doc = "## Safety"]
67514#[doc = "  * Neon instrinsic unsafe"]
67515#[inline]
67516#[cfg(target_arch = "arm")]
67517#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67518#[target_feature(enable = "neon,fp16")]
67519#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67520#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
67521unsafe fn vst1_v4f16(addr: *const i8, val: float16x4_t, align: i32) {
67522    unsafe extern "unadjusted" {
67523        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v4f16.p0")]
67524        fn _vst1_v4f16(addr: *const i8, val: float16x4_t, align: i32);
67525    }
67526    _vst1_v4f16(addr, val, align)
67527}
67528#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67529#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v8f16)"]
67530#[doc = "## Safety"]
67531#[doc = "  * Neon instrinsic unsafe"]
67532#[inline]
67533#[cfg(target_arch = "arm")]
67534#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67535#[target_feature(enable = "neon,fp16")]
67536#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67537#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
67538unsafe fn vst1q_v8f16(addr: *const i8, val: float16x8_t, align: i32) {
67539    unsafe extern "unadjusted" {
67540        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v8f16.p0")]
67541        fn _vst1q_v8f16(addr: *const i8, val: float16x8_t, align: i32);
67542    }
67543    _vst1q_v8f16(addr, val, align)
67544}
67545#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
67546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p64)"]
67547#[doc = "## Safety"]
67548#[doc = "  * Neon instrinsic unsafe"]
67549#[inline]
67550#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
67551#[target_feature(enable = "neon,aes")]
67552#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
67553#[cfg_attr(
67554    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67555    assert_instr(nop, LANE = 0)
67556)]
67557#[rustc_legacy_const_generics(2)]
67558#[cfg_attr(
67559    not(target_arch = "arm"),
67560    stable(feature = "neon_intrinsics", since = "1.59.0")
67561)]
67562#[cfg_attr(
67563    target_arch = "arm",
67564    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67565)]
67566pub unsafe fn vst1q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2_t) {
67567    static_assert_uimm_bits!(LANE, 1);
67568    *a = simd_extract!(b, LANE as u32);
67569}
67570#[doc = "Store multiple 2-element structures from two registers"]
67571#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"]
67572#[doc = "## Safety"]
67573#[doc = "  * Neon instrinsic unsafe"]
67574#[inline]
67575#[cfg(not(target_arch = "arm"))]
67576#[target_feature(enable = "neon,fp16")]
67577#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67578#[cfg_attr(test, assert_instr(st2))]
67579pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) {
67580    unsafe extern "unadjusted" {
67581        #[cfg_attr(
67582            any(target_arch = "aarch64", target_arch = "arm64ec"),
67583            link_name = "llvm.aarch64.neon.st2.v4f16.p0"
67584        )]
67585        fn _vst2_f16(a: float16x4_t, b: float16x4_t, ptr: *mut i8);
67586    }
67587    _vst2_f16(b.0, b.1, a as _)
67588}
67589#[doc = "Store multiple 2-element structures from two registers"]
67590#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"]
67591#[doc = "## Safety"]
67592#[doc = "  * Neon instrinsic unsafe"]
67593#[inline]
67594#[cfg(not(target_arch = "arm"))]
67595#[target_feature(enable = "neon,fp16")]
67596#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67597#[cfg_attr(test, assert_instr(st2))]
67598pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) {
67599    unsafe extern "unadjusted" {
67600        #[cfg_attr(
67601            any(target_arch = "aarch64", target_arch = "arm64ec"),
67602            link_name = "llvm.aarch64.neon.st2.v8f16.p0"
67603        )]
67604        fn _vst2q_f16(a: float16x8_t, b: float16x8_t, ptr: *mut i8);
67605    }
67606    _vst2q_f16(b.0, b.1, a as _)
67607}
67608#[doc = "Store multiple 2-element structures from two registers"]
67609#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"]
67610#[doc = "## Safety"]
67611#[doc = "  * Neon instrinsic unsafe"]
67612#[inline]
67613#[cfg(target_arch = "arm")]
67614#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67615#[target_feature(enable = "neon,fp16")]
67616#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67617#[cfg_attr(test, assert_instr(vst2))]
67618pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) {
67619    unsafe extern "unadjusted" {
67620        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0.v4f16")]
67621        fn _vst2_f16(ptr: *mut i8, a: float16x4_t, b: float16x4_t, size: i32);
67622    }
67623    _vst2_f16(a as _, b.0, b.1, 2)
67624}
67625#[doc = "Store multiple 2-element structures from two registers"]
67626#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"]
67627#[doc = "## Safety"]
67628#[doc = "  * Neon instrinsic unsafe"]
67629#[inline]
67630#[cfg(target_arch = "arm")]
67631#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67632#[target_feature(enable = "neon,fp16")]
67633#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67634#[cfg_attr(test, assert_instr(vst2))]
67635pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) {
67636    unsafe extern "unadjusted" {
67637        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0.v8f16")]
67638        fn _vst2q_f16(ptr: *mut i8, a: float16x8_t, b: float16x8_t, size: i32);
67639    }
67640    _vst2q_f16(a as _, b.0, b.1, 2)
67641}
67642#[doc = "Store multiple 2-element structures from two registers"]
67643#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"]
67644#[doc = "## Safety"]
67645#[doc = "  * Neon instrinsic unsafe"]
67646#[inline]
67647#[target_feature(enable = "neon")]
67648#[cfg(not(target_arch = "arm"))]
67649#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67650#[cfg_attr(test, assert_instr(st2))]
67651pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) {
67652    unsafe extern "unadjusted" {
67653        #[cfg_attr(
67654            any(target_arch = "aarch64", target_arch = "arm64ec"),
67655            link_name = "llvm.aarch64.neon.st2.v2f32.p0"
67656        )]
67657        fn _vst2_f32(a: float32x2_t, b: float32x2_t, ptr: *mut i8);
67658    }
67659    _vst2_f32(b.0, b.1, a as _)
67660}
67661#[doc = "Store multiple 2-element structures from two registers"]
67662#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"]
67663#[doc = "## Safety"]
67664#[doc = "  * Neon instrinsic unsafe"]
67665#[inline]
67666#[target_feature(enable = "neon")]
67667#[cfg(not(target_arch = "arm"))]
67668#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67669#[cfg_attr(test, assert_instr(st2))]
67670pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) {
67671    unsafe extern "unadjusted" {
67672        #[cfg_attr(
67673            any(target_arch = "aarch64", target_arch = "arm64ec"),
67674            link_name = "llvm.aarch64.neon.st2.v4f32.p0"
67675        )]
67676        fn _vst2q_f32(a: float32x4_t, b: float32x4_t, ptr: *mut i8);
67677    }
67678    _vst2q_f32(b.0, b.1, a as _)
67679}
67680#[doc = "Store multiple 2-element structures from two registers"]
67681#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"]
67682#[doc = "## Safety"]
67683#[doc = "  * Neon instrinsic unsafe"]
67684#[inline]
67685#[target_feature(enable = "neon")]
67686#[cfg(not(target_arch = "arm"))]
67687#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67688#[cfg_attr(test, assert_instr(st2))]
67689pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) {
67690    unsafe extern "unadjusted" {
67691        #[cfg_attr(
67692            any(target_arch = "aarch64", target_arch = "arm64ec"),
67693            link_name = "llvm.aarch64.neon.st2.v8i8.p0"
67694        )]
67695        fn _vst2_s8(a: int8x8_t, b: int8x8_t, ptr: *mut i8);
67696    }
67697    _vst2_s8(b.0, b.1, a as _)
67698}
67699#[doc = "Store multiple 2-element structures from two registers"]
67700#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"]
67701#[doc = "## Safety"]
67702#[doc = "  * Neon instrinsic unsafe"]
67703#[inline]
67704#[target_feature(enable = "neon")]
67705#[cfg(not(target_arch = "arm"))]
67706#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67707#[cfg_attr(test, assert_instr(st2))]
67708pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) {
67709    unsafe extern "unadjusted" {
67710        #[cfg_attr(
67711            any(target_arch = "aarch64", target_arch = "arm64ec"),
67712            link_name = "llvm.aarch64.neon.st2.v16i8.p0"
67713        )]
67714        fn _vst2q_s8(a: int8x16_t, b: int8x16_t, ptr: *mut i8);
67715    }
67716    _vst2q_s8(b.0, b.1, a as _)
67717}
67718#[doc = "Store multiple 2-element structures from two registers"]
67719#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"]
67720#[doc = "## Safety"]
67721#[doc = "  * Neon instrinsic unsafe"]
67722#[inline]
67723#[target_feature(enable = "neon")]
67724#[cfg(not(target_arch = "arm"))]
67725#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67726#[cfg_attr(test, assert_instr(st2))]
67727pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) {
67728    unsafe extern "unadjusted" {
67729        #[cfg_attr(
67730            any(target_arch = "aarch64", target_arch = "arm64ec"),
67731            link_name = "llvm.aarch64.neon.st2.v4i16.p0"
67732        )]
67733        fn _vst2_s16(a: int16x4_t, b: int16x4_t, ptr: *mut i8);
67734    }
67735    _vst2_s16(b.0, b.1, a as _)
67736}
67737#[doc = "Store multiple 2-element structures from two registers"]
67738#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"]
67739#[doc = "## Safety"]
67740#[doc = "  * Neon instrinsic unsafe"]
67741#[inline]
67742#[target_feature(enable = "neon")]
67743#[cfg(not(target_arch = "arm"))]
67744#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67745#[cfg_attr(test, assert_instr(st2))]
67746pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) {
67747    unsafe extern "unadjusted" {
67748        #[cfg_attr(
67749            any(target_arch = "aarch64", target_arch = "arm64ec"),
67750            link_name = "llvm.aarch64.neon.st2.v8i16.p0"
67751        )]
67752        fn _vst2q_s16(a: int16x8_t, b: int16x8_t, ptr: *mut i8);
67753    }
67754    _vst2q_s16(b.0, b.1, a as _)
67755}
67756#[doc = "Store multiple 2-element structures from two registers"]
67757#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"]
67758#[doc = "## Safety"]
67759#[doc = "  * Neon instrinsic unsafe"]
67760#[inline]
67761#[target_feature(enable = "neon")]
67762#[cfg(not(target_arch = "arm"))]
67763#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67764#[cfg_attr(test, assert_instr(st2))]
67765pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) {
67766    unsafe extern "unadjusted" {
67767        #[cfg_attr(
67768            any(target_arch = "aarch64", target_arch = "arm64ec"),
67769            link_name = "llvm.aarch64.neon.st2.v2i32.p0"
67770        )]
67771        fn _vst2_s32(a: int32x2_t, b: int32x2_t, ptr: *mut i8);
67772    }
67773    _vst2_s32(b.0, b.1, a as _)
67774}
67775#[doc = "Store multiple 2-element structures from two registers"]
67776#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"]
67777#[doc = "## Safety"]
67778#[doc = "  * Neon instrinsic unsafe"]
67779#[inline]
67780#[target_feature(enable = "neon")]
67781#[cfg(not(target_arch = "arm"))]
67782#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67783#[cfg_attr(test, assert_instr(st2))]
67784pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) {
67785    unsafe extern "unadjusted" {
67786        #[cfg_attr(
67787            any(target_arch = "aarch64", target_arch = "arm64ec"),
67788            link_name = "llvm.aarch64.neon.st2.v4i32.p0"
67789        )]
67790        fn _vst2q_s32(a: int32x4_t, b: int32x4_t, ptr: *mut i8);
67791    }
67792    _vst2q_s32(b.0, b.1, a as _)
67793}
67794#[doc = "Store multiple 2-element structures from two registers"]
67795#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"]
67796#[doc = "## Safety"]
67797#[doc = "  * Neon instrinsic unsafe"]
67798#[inline]
67799#[cfg(target_arch = "arm")]
67800#[target_feature(enable = "neon,v7")]
67801#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67802#[cfg_attr(test, assert_instr(vst2))]
67803pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) {
67804    unsafe extern "unadjusted" {
67805        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v2f32.p0")]
67806        fn _vst2_f32(ptr: *mut i8, a: float32x2_t, b: float32x2_t, size: i32);
67807    }
67808    _vst2_f32(a as _, b.0, b.1, 4)
67809}
67810#[doc = "Store multiple 2-element structures from two registers"]
67811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"]
67812#[doc = "## Safety"]
67813#[doc = "  * Neon instrinsic unsafe"]
67814#[inline]
67815#[cfg(target_arch = "arm")]
67816#[target_feature(enable = "neon,v7")]
67817#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67818#[cfg_attr(test, assert_instr(vst2))]
67819pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) {
67820    unsafe extern "unadjusted" {
67821        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v4f32.p0")]
67822        fn _vst2q_f32(ptr: *mut i8, a: float32x4_t, b: float32x4_t, size: i32);
67823    }
67824    _vst2q_f32(a as _, b.0, b.1, 4)
67825}
67826#[doc = "Store multiple 2-element structures from two registers"]
67827#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"]
67828#[doc = "## Safety"]
67829#[doc = "  * Neon instrinsic unsafe"]
67830#[inline]
67831#[cfg(target_arch = "arm")]
67832#[target_feature(enable = "neon,v7")]
67833#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67834#[cfg_attr(test, assert_instr(vst2))]
67835pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) {
67836    unsafe extern "unadjusted" {
67837        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v8i8.p0")]
67838        fn _vst2_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, size: i32);
67839    }
67840    _vst2_s8(a as _, b.0, b.1, 1)
67841}
67842#[doc = "Store multiple 2-element structures from two registers"]
67843#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"]
67844#[doc = "## Safety"]
67845#[doc = "  * Neon instrinsic unsafe"]
67846#[inline]
67847#[cfg(target_arch = "arm")]
67848#[target_feature(enable = "neon,v7")]
67849#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67850#[cfg_attr(test, assert_instr(vst2))]
67851pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) {
67852    unsafe extern "unadjusted" {
67853        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v16i8.p0")]
67854        fn _vst2q_s8(ptr: *mut i8, a: int8x16_t, b: int8x16_t, size: i32);
67855    }
67856    _vst2q_s8(a as _, b.0, b.1, 1)
67857}
67858#[doc = "Store multiple 2-element structures from two registers"]
67859#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"]
67860#[doc = "## Safety"]
67861#[doc = "  * Neon instrinsic unsafe"]
67862#[inline]
67863#[cfg(target_arch = "arm")]
67864#[target_feature(enable = "neon,v7")]
67865#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67866#[cfg_attr(test, assert_instr(vst2))]
67867pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) {
67868    unsafe extern "unadjusted" {
67869        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v4i16.p0")]
67870        fn _vst2_s16(ptr: *mut i8, a: int16x4_t, b: int16x4_t, size: i32);
67871    }
67872    _vst2_s16(a as _, b.0, b.1, 2)
67873}
67874#[doc = "Store multiple 2-element structures from two registers"]
67875#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"]
67876#[doc = "## Safety"]
67877#[doc = "  * Neon instrinsic unsafe"]
67878#[inline]
67879#[cfg(target_arch = "arm")]
67880#[target_feature(enable = "neon,v7")]
67881#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67882#[cfg_attr(test, assert_instr(vst2))]
67883pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) {
67884    unsafe extern "unadjusted" {
67885        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v8i16.p0")]
67886        fn _vst2q_s16(ptr: *mut i8, a: int16x8_t, b: int16x8_t, size: i32);
67887    }
67888    _vst2q_s16(a as _, b.0, b.1, 2)
67889}
67890#[doc = "Store multiple 2-element structures from two registers"]
67891#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"]
67892#[doc = "## Safety"]
67893#[doc = "  * Neon instrinsic unsafe"]
67894#[inline]
67895#[cfg(target_arch = "arm")]
67896#[target_feature(enable = "neon,v7")]
67897#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67898#[cfg_attr(test, assert_instr(vst2))]
67899pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) {
67900    unsafe extern "unadjusted" {
67901        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v2i32.p0")]
67902        fn _vst2_s32(ptr: *mut i8, a: int32x2_t, b: int32x2_t, size: i32);
67903    }
67904    _vst2_s32(a as _, b.0, b.1, 4)
67905}
67906#[doc = "Store multiple 2-element structures from two registers"]
67907#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"]
67908#[doc = "## Safety"]
67909#[doc = "  * Neon instrinsic unsafe"]
67910#[inline]
67911#[cfg(target_arch = "arm")]
67912#[target_feature(enable = "neon,v7")]
67913#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67914#[cfg_attr(test, assert_instr(vst2))]
67915pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) {
67916    unsafe extern "unadjusted" {
67917        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v4i32.p0")]
67918        fn _vst2q_s32(ptr: *mut i8, a: int32x4_t, b: int32x4_t, size: i32);
67919    }
67920    _vst2q_s32(a as _, b.0, b.1, 4)
67921}
67922#[doc = "Store multiple 2-element structures from two registers"]
67923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"]
67924#[doc = "## Safety"]
67925#[doc = "  * Neon instrinsic unsafe"]
67926#[inline]
67927#[cfg(not(target_arch = "arm"))]
67928#[rustc_legacy_const_generics(2)]
67929#[cfg_attr(test, assert_instr(st2, LANE = 0))]
67930#[target_feature(enable = "neon,fp16")]
67931#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67932pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
67933    static_assert_uimm_bits!(LANE, 2);
67934    unsafe extern "unadjusted" {
67935        #[cfg_attr(
67936            any(target_arch = "aarch64", target_arch = "arm64ec"),
67937            link_name = "llvm.aarch64.neon.st2lane.v4f16.p0"
67938        )]
67939        fn _vst2_lane_f16(a: float16x4_t, b: float16x4_t, n: i64, ptr: *mut i8);
67940    }
67941    _vst2_lane_f16(b.0, b.1, LANE as i64, a as _)
67942}
67943#[doc = "Store multiple 2-element structures from two registers"]
67944#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"]
67945#[doc = "## Safety"]
67946#[doc = "  * Neon instrinsic unsafe"]
67947#[inline]
67948#[cfg(not(target_arch = "arm"))]
67949#[rustc_legacy_const_generics(2)]
67950#[cfg_attr(test, assert_instr(st2, LANE = 0))]
67951#[target_feature(enable = "neon,fp16")]
67952#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67953pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
67954    static_assert_uimm_bits!(LANE, 3);
67955    unsafe extern "unadjusted" {
67956        #[cfg_attr(
67957            any(target_arch = "aarch64", target_arch = "arm64ec"),
67958            link_name = "llvm.aarch64.neon.st2lane.v8f16.p0"
67959        )]
67960        fn _vst2q_lane_f16(a: float16x8_t, b: float16x8_t, n: i64, ptr: *mut i8);
67961    }
67962    _vst2q_lane_f16(b.0, b.1, LANE as i64, a as _)
67963}
67964#[doc = "Store multiple 2-element structures from two registers"]
67965#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"]
67966#[doc = "## Safety"]
67967#[doc = "  * Neon instrinsic unsafe"]
67968#[inline]
67969#[cfg(target_arch = "arm")]
67970#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67971#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
67972#[rustc_legacy_const_generics(2)]
67973#[target_feature(enable = "neon,fp16")]
67974#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67975pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
67976    static_assert_uimm_bits!(LANE, 2);
67977    unsafe extern "unadjusted" {
67978        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0.v4f16")]
67979        fn _vst2_lane_f16(ptr: *mut i8, a: float16x4_t, b: float16x4_t, n: i32, size: i32);
67980    }
67981    _vst2_lane_f16(a as _, b.0, b.1, LANE, 2)
67982}
67983#[doc = "Store multiple 2-element structures from two registers"]
67984#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"]
67985#[doc = "## Safety"]
67986#[doc = "  * Neon instrinsic unsafe"]
67987#[inline]
67988#[cfg(target_arch = "arm")]
67989#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67990#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
67991#[rustc_legacy_const_generics(2)]
67992#[target_feature(enable = "neon,fp16")]
67993#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67994pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
67995    static_assert_uimm_bits!(LANE, 1);
67996    unsafe extern "unadjusted" {
67997        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0.v8f16")]
67998        fn _vst2q_lane_f16(ptr: *mut i8, a: float16x8_t, b: float16x8_t, n: i32, size: i32);
67999    }
68000    _vst2q_lane_f16(a as _, b.0, b.1, LANE, 2)
68001}
68002#[doc = "Store multiple 2-element structures from two registers"]
68003#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"]
68004#[doc = "## Safety"]
68005#[doc = "  * Neon instrinsic unsafe"]
68006#[inline]
68007#[target_feature(enable = "neon")]
68008#[cfg(not(target_arch = "arm"))]
68009#[rustc_legacy_const_generics(2)]
68010#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68011#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68012pub unsafe fn vst2_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x2_t) {
68013    static_assert_uimm_bits!(LANE, 1);
68014    unsafe extern "unadjusted" {
68015        #[cfg_attr(
68016            any(target_arch = "aarch64", target_arch = "arm64ec"),
68017            link_name = "llvm.aarch64.neon.st2lane.v2f32.p0"
68018        )]
68019        fn _vst2_lane_f32(a: float32x2_t, b: float32x2_t, n: i64, ptr: *mut i8);
68020    }
68021    _vst2_lane_f32(b.0, b.1, LANE as i64, a as _)
68022}
68023#[doc = "Store multiple 2-element structures from two registers"]
68024#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"]
68025#[doc = "## Safety"]
68026#[doc = "  * Neon instrinsic unsafe"]
68027#[inline]
68028#[target_feature(enable = "neon")]
68029#[cfg(not(target_arch = "arm"))]
68030#[rustc_legacy_const_generics(2)]
68031#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68032#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68033pub unsafe fn vst2q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x2_t) {
68034    static_assert_uimm_bits!(LANE, 2);
68035    unsafe extern "unadjusted" {
68036        #[cfg_attr(
68037            any(target_arch = "aarch64", target_arch = "arm64ec"),
68038            link_name = "llvm.aarch64.neon.st2lane.v4f32.p0"
68039        )]
68040        fn _vst2q_lane_f32(a: float32x4_t, b: float32x4_t, n: i64, ptr: *mut i8);
68041    }
68042    _vst2q_lane_f32(b.0, b.1, LANE as i64, a as _)
68043}
68044#[doc = "Store multiple 2-element structures from two registers"]
68045#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"]
68046#[doc = "## Safety"]
68047#[doc = "  * Neon instrinsic unsafe"]
68048#[inline]
68049#[target_feature(enable = "neon")]
68050#[cfg(not(target_arch = "arm"))]
68051#[rustc_legacy_const_generics(2)]
68052#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68053#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68054pub unsafe fn vst2_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x2_t) {
68055    static_assert_uimm_bits!(LANE, 3);
68056    unsafe extern "unadjusted" {
68057        #[cfg_attr(
68058            any(target_arch = "aarch64", target_arch = "arm64ec"),
68059            link_name = "llvm.aarch64.neon.st2lane.v8i8.p0"
68060        )]
68061        fn _vst2_lane_s8(a: int8x8_t, b: int8x8_t, n: i64, ptr: *mut i8);
68062    }
68063    _vst2_lane_s8(b.0, b.1, LANE as i64, a as _)
68064}
68065#[doc = "Store multiple 2-element structures from two registers"]
68066#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"]
68067#[doc = "## Safety"]
68068#[doc = "  * Neon instrinsic unsafe"]
68069#[inline]
68070#[target_feature(enable = "neon")]
68071#[cfg(not(target_arch = "arm"))]
68072#[rustc_legacy_const_generics(2)]
68073#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68074#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68075pub unsafe fn vst2_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x2_t) {
68076    static_assert_uimm_bits!(LANE, 2);
68077    unsafe extern "unadjusted" {
68078        #[cfg_attr(
68079            any(target_arch = "aarch64", target_arch = "arm64ec"),
68080            link_name = "llvm.aarch64.neon.st2lane.v4i16.p0"
68081        )]
68082        fn _vst2_lane_s16(a: int16x4_t, b: int16x4_t, n: i64, ptr: *mut i8);
68083    }
68084    _vst2_lane_s16(b.0, b.1, LANE as i64, a as _)
68085}
68086#[doc = "Store multiple 2-element structures from two registers"]
68087#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"]
68088#[doc = "## Safety"]
68089#[doc = "  * Neon instrinsic unsafe"]
68090#[inline]
68091#[target_feature(enable = "neon")]
68092#[cfg(not(target_arch = "arm"))]
68093#[rustc_legacy_const_generics(2)]
68094#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68095#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68096pub unsafe fn vst2q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x2_t) {
68097    static_assert_uimm_bits!(LANE, 3);
68098    unsafe extern "unadjusted" {
68099        #[cfg_attr(
68100            any(target_arch = "aarch64", target_arch = "arm64ec"),
68101            link_name = "llvm.aarch64.neon.st2lane.v8i16.p0"
68102        )]
68103        fn _vst2q_lane_s16(a: int16x8_t, b: int16x8_t, n: i64, ptr: *mut i8);
68104    }
68105    _vst2q_lane_s16(b.0, b.1, LANE as i64, a as _)
68106}
68107#[doc = "Store multiple 2-element structures from two registers"]
68108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"]
68109#[doc = "## Safety"]
68110#[doc = "  * Neon instrinsic unsafe"]
68111#[inline]
68112#[target_feature(enable = "neon")]
68113#[cfg(not(target_arch = "arm"))]
68114#[rustc_legacy_const_generics(2)]
68115#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68116#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68117pub unsafe fn vst2_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x2_t) {
68118    static_assert_uimm_bits!(LANE, 1);
68119    unsafe extern "unadjusted" {
68120        #[cfg_attr(
68121            any(target_arch = "aarch64", target_arch = "arm64ec"),
68122            link_name = "llvm.aarch64.neon.st2lane.v2i32.p0"
68123        )]
68124        fn _vst2_lane_s32(a: int32x2_t, b: int32x2_t, n: i64, ptr: *mut i8);
68125    }
68126    _vst2_lane_s32(b.0, b.1, LANE as i64, a as _)
68127}
68128#[doc = "Store multiple 2-element structures from two registers"]
68129#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"]
68130#[doc = "## Safety"]
68131#[doc = "  * Neon instrinsic unsafe"]
68132#[inline]
68133#[target_feature(enable = "neon")]
68134#[cfg(not(target_arch = "arm"))]
68135#[rustc_legacy_const_generics(2)]
68136#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68137#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68138pub unsafe fn vst2q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x2_t) {
68139    static_assert_uimm_bits!(LANE, 2);
68140    unsafe extern "unadjusted" {
68141        #[cfg_attr(
68142            any(target_arch = "aarch64", target_arch = "arm64ec"),
68143            link_name = "llvm.aarch64.neon.st2lane.v4i32.p0"
68144        )]
68145        fn _vst2q_lane_s32(a: int32x4_t, b: int32x4_t, n: i64, ptr: *mut i8);
68146    }
68147    _vst2q_lane_s32(b.0, b.1, LANE as i64, a as _)
68148}
68149#[doc = "Store multiple 2-element structures from two registers"]
68150#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"]
68151#[doc = "## Safety"]
68152#[doc = "  * Neon instrinsic unsafe"]
68153#[inline]
68154#[cfg(target_arch = "arm")]
68155#[target_feature(enable = "neon,v7")]
68156#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68157#[rustc_legacy_const_generics(2)]
68158#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68159pub unsafe fn vst2_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x2_t) {
68160    static_assert_uimm_bits!(LANE, 1);
68161    unsafe extern "unadjusted" {
68162        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v2f32.p0")]
68163        fn _vst2_lane_f32(ptr: *mut i8, a: float32x2_t, b: float32x2_t, n: i32, size: i32);
68164    }
68165    _vst2_lane_f32(a as _, b.0, b.1, LANE, 4)
68166}
68167#[doc = "Store multiple 2-element structures from two registers"]
68168#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"]
68169#[doc = "## Safety"]
68170#[doc = "  * Neon instrinsic unsafe"]
68171#[inline]
68172#[cfg(target_arch = "arm")]
68173#[target_feature(enable = "neon,v7")]
68174#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68175#[rustc_legacy_const_generics(2)]
68176#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68177pub unsafe fn vst2q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x2_t) {
68178    static_assert_uimm_bits!(LANE, 2);
68179    unsafe extern "unadjusted" {
68180        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v4f32.p0")]
68181        fn _vst2q_lane_f32(ptr: *mut i8, a: float32x4_t, b: float32x4_t, n: i32, size: i32);
68182    }
68183    _vst2q_lane_f32(a as _, b.0, b.1, LANE, 4)
68184}
68185#[doc = "Store multiple 2-element structures from two registers"]
68186#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"]
68187#[doc = "## Safety"]
68188#[doc = "  * Neon instrinsic unsafe"]
68189#[inline]
68190#[cfg(target_arch = "arm")]
68191#[target_feature(enable = "neon,v7")]
68192#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68193#[rustc_legacy_const_generics(2)]
68194#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68195pub unsafe fn vst2_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x2_t) {
68196    static_assert_uimm_bits!(LANE, 3);
68197    unsafe extern "unadjusted" {
68198        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v8i8.p0")]
68199        fn _vst2_lane_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, n: i32, size: i32);
68200    }
68201    _vst2_lane_s8(a as _, b.0, b.1, LANE, 1)
68202}
68203#[doc = "Store multiple 2-element structures from two registers"]
68204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"]
68205#[doc = "## Safety"]
68206#[doc = "  * Neon instrinsic unsafe"]
68207#[inline]
68208#[cfg(target_arch = "arm")]
68209#[target_feature(enable = "neon,v7")]
68210#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68211#[rustc_legacy_const_generics(2)]
68212#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68213pub unsafe fn vst2_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x2_t) {
68214    static_assert_uimm_bits!(LANE, 2);
68215    unsafe extern "unadjusted" {
68216        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v4i16.p0")]
68217        fn _vst2_lane_s16(ptr: *mut i8, a: int16x4_t, b: int16x4_t, n: i32, size: i32);
68218    }
68219    _vst2_lane_s16(a as _, b.0, b.1, LANE, 2)
68220}
68221#[doc = "Store multiple 2-element structures from two registers"]
68222#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"]
68223#[doc = "## Safety"]
68224#[doc = "  * Neon instrinsic unsafe"]
68225#[inline]
68226#[cfg(target_arch = "arm")]
68227#[target_feature(enable = "neon,v7")]
68228#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68229#[rustc_legacy_const_generics(2)]
68230#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68231pub unsafe fn vst2q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x2_t) {
68232    static_assert_uimm_bits!(LANE, 3);
68233    unsafe extern "unadjusted" {
68234        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v8i16.p0")]
68235        fn _vst2q_lane_s16(ptr: *mut i8, a: int16x8_t, b: int16x8_t, n: i32, size: i32);
68236    }
68237    _vst2q_lane_s16(a as _, b.0, b.1, LANE, 2)
68238}
68239#[doc = "Store multiple 2-element structures from two registers"]
68240#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"]
68241#[doc = "## Safety"]
68242#[doc = "  * Neon instrinsic unsafe"]
68243#[inline]
68244#[cfg(target_arch = "arm")]
68245#[target_feature(enable = "neon,v7")]
68246#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68247#[rustc_legacy_const_generics(2)]
68248#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68249pub unsafe fn vst2_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x2_t) {
68250    static_assert_uimm_bits!(LANE, 1);
68251    unsafe extern "unadjusted" {
68252        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v2i32.p0")]
68253        fn _vst2_lane_s32(ptr: *mut i8, a: int32x2_t, b: int32x2_t, n: i32, size: i32);
68254    }
68255    _vst2_lane_s32(a as _, b.0, b.1, LANE, 4)
68256}
68257#[doc = "Store multiple 2-element structures from two registers"]
68258#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"]
68259#[doc = "## Safety"]
68260#[doc = "  * Neon instrinsic unsafe"]
68261#[inline]
68262#[cfg(target_arch = "arm")]
68263#[target_feature(enable = "neon,v7")]
68264#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68265#[rustc_legacy_const_generics(2)]
68266#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68267pub unsafe fn vst2q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x2_t) {
68268    static_assert_uimm_bits!(LANE, 2);
68269    unsafe extern "unadjusted" {
68270        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v4i32.p0")]
68271        fn _vst2q_lane_s32(ptr: *mut i8, a: int32x4_t, b: int32x4_t, n: i32, size: i32);
68272    }
68273    _vst2q_lane_s32(a as _, b.0, b.1, LANE, 4)
68274}
68275#[doc = "Store multiple 2-element structures from two registers"]
68276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u8)"]
68277#[doc = "## Safety"]
68278#[doc = "  * Neon instrinsic unsafe"]
68279#[inline]
68280#[target_feature(enable = "neon")]
68281#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68282#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68283#[cfg_attr(
68284    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68285    assert_instr(st2, LANE = 0)
68286)]
68287#[rustc_legacy_const_generics(2)]
68288#[cfg_attr(
68289    not(target_arch = "arm"),
68290    stable(feature = "neon_intrinsics", since = "1.59.0")
68291)]
68292#[cfg_attr(
68293    target_arch = "arm",
68294    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68295)]
68296pub unsafe fn vst2_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x2_t) {
68297    static_assert_uimm_bits!(LANE, 3);
68298    vst2_lane_s8::<LANE>(transmute(a), transmute(b))
68299}
68300#[doc = "Store multiple 2-element structures from two registers"]
68301#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u16)"]
68302#[doc = "## Safety"]
68303#[doc = "  * Neon instrinsic unsafe"]
68304#[inline]
68305#[target_feature(enable = "neon")]
68306#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68307#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68308#[cfg_attr(
68309    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68310    assert_instr(st2, LANE = 0)
68311)]
68312#[rustc_legacy_const_generics(2)]
68313#[cfg_attr(
68314    not(target_arch = "arm"),
68315    stable(feature = "neon_intrinsics", since = "1.59.0")
68316)]
68317#[cfg_attr(
68318    target_arch = "arm",
68319    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68320)]
68321pub unsafe fn vst2_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x2_t) {
68322    static_assert_uimm_bits!(LANE, 2);
68323    vst2_lane_s16::<LANE>(transmute(a), transmute(b))
68324}
68325#[doc = "Store multiple 2-element structures from two registers"]
68326#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u16)"]
68327#[doc = "## Safety"]
68328#[doc = "  * Neon instrinsic unsafe"]
68329#[inline]
68330#[target_feature(enable = "neon")]
68331#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68332#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68333#[cfg_attr(
68334    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68335    assert_instr(st2, LANE = 0)
68336)]
68337#[rustc_legacy_const_generics(2)]
68338#[cfg_attr(
68339    not(target_arch = "arm"),
68340    stable(feature = "neon_intrinsics", since = "1.59.0")
68341)]
68342#[cfg_attr(
68343    target_arch = "arm",
68344    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68345)]
68346pub unsafe fn vst2q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x2_t) {
68347    static_assert_uimm_bits!(LANE, 3);
68348    vst2q_lane_s16::<LANE>(transmute(a), transmute(b))
68349}
68350#[doc = "Store multiple 2-element structures from two registers"]
68351#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u32)"]
68352#[doc = "## Safety"]
68353#[doc = "  * Neon instrinsic unsafe"]
68354#[inline]
68355#[target_feature(enable = "neon")]
68356#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68357#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68358#[cfg_attr(
68359    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68360    assert_instr(st2, LANE = 0)
68361)]
68362#[rustc_legacy_const_generics(2)]
68363#[cfg_attr(
68364    not(target_arch = "arm"),
68365    stable(feature = "neon_intrinsics", since = "1.59.0")
68366)]
68367#[cfg_attr(
68368    target_arch = "arm",
68369    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68370)]
68371pub unsafe fn vst2_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x2_t) {
68372    static_assert_uimm_bits!(LANE, 1);
68373    vst2_lane_s32::<LANE>(transmute(a), transmute(b))
68374}
68375#[doc = "Store multiple 2-element structures from two registers"]
68376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u32)"]
68377#[doc = "## Safety"]
68378#[doc = "  * Neon instrinsic unsafe"]
68379#[inline]
68380#[target_feature(enable = "neon")]
68381#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68382#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68383#[cfg_attr(
68384    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68385    assert_instr(st2, LANE = 0)
68386)]
68387#[rustc_legacy_const_generics(2)]
68388#[cfg_attr(
68389    not(target_arch = "arm"),
68390    stable(feature = "neon_intrinsics", since = "1.59.0")
68391)]
68392#[cfg_attr(
68393    target_arch = "arm",
68394    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68395)]
68396pub unsafe fn vst2q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x2_t) {
68397    static_assert_uimm_bits!(LANE, 2);
68398    vst2q_lane_s32::<LANE>(transmute(a), transmute(b))
68399}
68400#[doc = "Store multiple 2-element structures from two registers"]
68401#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p8)"]
68402#[doc = "## Safety"]
68403#[doc = "  * Neon instrinsic unsafe"]
68404#[inline]
68405#[target_feature(enable = "neon")]
68406#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68407#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68408#[cfg_attr(
68409    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68410    assert_instr(st2, LANE = 0)
68411)]
68412#[rustc_legacy_const_generics(2)]
68413#[cfg_attr(
68414    not(target_arch = "arm"),
68415    stable(feature = "neon_intrinsics", since = "1.59.0")
68416)]
68417#[cfg_attr(
68418    target_arch = "arm",
68419    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68420)]
68421pub unsafe fn vst2_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x2_t) {
68422    static_assert_uimm_bits!(LANE, 3);
68423    vst2_lane_s8::<LANE>(transmute(a), transmute(b))
68424}
68425#[doc = "Store multiple 2-element structures from two registers"]
68426#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p16)"]
68427#[doc = "## Safety"]
68428#[doc = "  * Neon instrinsic unsafe"]
68429#[inline]
68430#[target_feature(enable = "neon")]
68431#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68432#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68433#[cfg_attr(
68434    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68435    assert_instr(st2, LANE = 0)
68436)]
68437#[rustc_legacy_const_generics(2)]
68438#[cfg_attr(
68439    not(target_arch = "arm"),
68440    stable(feature = "neon_intrinsics", since = "1.59.0")
68441)]
68442#[cfg_attr(
68443    target_arch = "arm",
68444    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68445)]
68446pub unsafe fn vst2_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x2_t) {
68447    static_assert_uimm_bits!(LANE, 2);
68448    vst2_lane_s16::<LANE>(transmute(a), transmute(b))
68449}
68450#[doc = "Store multiple 2-element structures from two registers"]
68451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p16)"]
68452#[doc = "## Safety"]
68453#[doc = "  * Neon instrinsic unsafe"]
68454#[inline]
68455#[target_feature(enable = "neon")]
68456#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68457#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68458#[cfg_attr(
68459    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68460    assert_instr(st2, LANE = 0)
68461)]
68462#[rustc_legacy_const_generics(2)]
68463#[cfg_attr(
68464    not(target_arch = "arm"),
68465    stable(feature = "neon_intrinsics", since = "1.59.0")
68466)]
68467#[cfg_attr(
68468    target_arch = "arm",
68469    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68470)]
68471pub unsafe fn vst2q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x2_t) {
68472    static_assert_uimm_bits!(LANE, 3);
68473    vst2q_lane_s16::<LANE>(transmute(a), transmute(b))
68474}
68475#[doc = "Store multiple 2-element structures from two registers"]
68476#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p64)"]
68477#[doc = "## Safety"]
68478#[doc = "  * Neon instrinsic unsafe"]
68479#[inline]
68480#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
68481#[target_feature(enable = "neon,aes")]
68482#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
68483#[cfg_attr(
68484    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68485    assert_instr(nop)
68486)]
68487#[cfg_attr(
68488    not(target_arch = "arm"),
68489    stable(feature = "neon_intrinsics", since = "1.59.0")
68490)]
68491#[cfg_attr(
68492    target_arch = "arm",
68493    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68494)]
68495pub unsafe fn vst2_p64(a: *mut p64, b: poly64x1x2_t) {
68496    vst2_s64(transmute(a), transmute(b))
68497}
68498#[doc = "Store multiple 2-element structures from two registers"]
68499#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"]
68500#[doc = "## Safety"]
68501#[doc = "  * Neon instrinsic unsafe"]
68502#[inline]
68503#[cfg(target_arch = "arm")]
68504#[target_feature(enable = "neon,v7")]
68505#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68506#[cfg_attr(test, assert_instr(nop))]
68507pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) {
68508    unsafe extern "unadjusted" {
68509        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v1i64.p0")]
68510        fn _vst2_s64(ptr: *mut i8, a: int64x1_t, b: int64x1_t, size: i32);
68511    }
68512    _vst2_s64(a as _, b.0, b.1, 8)
68513}
68514#[doc = "Store multiple 2-element structures from two registers"]
68515#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"]
68516#[doc = "## Safety"]
68517#[doc = "  * Neon instrinsic unsafe"]
68518#[inline]
68519#[target_feature(enable = "neon")]
68520#[cfg(not(target_arch = "arm"))]
68521#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68522#[cfg_attr(test, assert_instr(nop))]
68523pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) {
68524    unsafe extern "unadjusted" {
68525        #[cfg_attr(
68526            any(target_arch = "aarch64", target_arch = "arm64ec"),
68527            link_name = "llvm.aarch64.neon.st2.v1i64.p0"
68528        )]
68529        fn _vst2_s64(a: int64x1_t, b: int64x1_t, ptr: *mut i8);
68530    }
68531    _vst2_s64(b.0, b.1, a as _)
68532}
68533#[doc = "Store multiple 2-element structures from two registers"]
68534#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u64)"]
68535#[doc = "## Safety"]
68536#[doc = "  * Neon instrinsic unsafe"]
68537#[inline]
68538#[target_feature(enable = "neon")]
68539#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68540#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
68541#[cfg_attr(
68542    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68543    assert_instr(nop)
68544)]
68545#[cfg_attr(
68546    not(target_arch = "arm"),
68547    stable(feature = "neon_intrinsics", since = "1.59.0")
68548)]
68549#[cfg_attr(
68550    target_arch = "arm",
68551    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68552)]
68553pub unsafe fn vst2_u64(a: *mut u64, b: uint64x1x2_t) {
68554    vst2_s64(transmute(a), transmute(b))
68555}
68556#[doc = "Store multiple 2-element structures from two registers"]
68557#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u8)"]
68558#[doc = "## Safety"]
68559#[doc = "  * Neon instrinsic unsafe"]
68560#[inline]
68561#[target_feature(enable = "neon")]
68562#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68563#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68564#[cfg_attr(
68565    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68566    assert_instr(st2)
68567)]
68568#[cfg_attr(
68569    not(target_arch = "arm"),
68570    stable(feature = "neon_intrinsics", since = "1.59.0")
68571)]
68572#[cfg_attr(
68573    target_arch = "arm",
68574    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68575)]
68576pub unsafe fn vst2_u8(a: *mut u8, b: uint8x8x2_t) {
68577    vst2_s8(transmute(a), transmute(b))
68578}
68579#[doc = "Store multiple 2-element structures from two registers"]
68580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u8)"]
68581#[doc = "## Safety"]
68582#[doc = "  * Neon instrinsic unsafe"]
68583#[inline]
68584#[target_feature(enable = "neon")]
68585#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68586#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68587#[cfg_attr(
68588    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68589    assert_instr(st2)
68590)]
68591#[cfg_attr(
68592    not(target_arch = "arm"),
68593    stable(feature = "neon_intrinsics", since = "1.59.0")
68594)]
68595#[cfg_attr(
68596    target_arch = "arm",
68597    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68598)]
68599pub unsafe fn vst2q_u8(a: *mut u8, b: uint8x16x2_t) {
68600    vst2q_s8(transmute(a), transmute(b))
68601}
68602#[doc = "Store multiple 2-element structures from two registers"]
68603#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u16)"]
68604#[doc = "## Safety"]
68605#[doc = "  * Neon instrinsic unsafe"]
68606#[inline]
68607#[target_feature(enable = "neon")]
68608#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68609#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68610#[cfg_attr(
68611    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68612    assert_instr(st2)
68613)]
68614#[cfg_attr(
68615    not(target_arch = "arm"),
68616    stable(feature = "neon_intrinsics", since = "1.59.0")
68617)]
68618#[cfg_attr(
68619    target_arch = "arm",
68620    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68621)]
68622pub unsafe fn vst2_u16(a: *mut u16, b: uint16x4x2_t) {
68623    vst2_s16(transmute(a), transmute(b))
68624}
68625#[doc = "Store multiple 2-element structures from two registers"]
68626#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u16)"]
68627#[doc = "## Safety"]
68628#[doc = "  * Neon instrinsic unsafe"]
68629#[inline]
68630#[target_feature(enable = "neon")]
68631#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68632#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68633#[cfg_attr(
68634    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68635    assert_instr(st2)
68636)]
68637#[cfg_attr(
68638    not(target_arch = "arm"),
68639    stable(feature = "neon_intrinsics", since = "1.59.0")
68640)]
68641#[cfg_attr(
68642    target_arch = "arm",
68643    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68644)]
68645pub unsafe fn vst2q_u16(a: *mut u16, b: uint16x8x2_t) {
68646    vst2q_s16(transmute(a), transmute(b))
68647}
68648#[doc = "Store multiple 2-element structures from two registers"]
68649#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u32)"]
68650#[doc = "## Safety"]
68651#[doc = "  * Neon instrinsic unsafe"]
68652#[inline]
68653#[target_feature(enable = "neon")]
68654#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68655#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68656#[cfg_attr(
68657    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68658    assert_instr(st2)
68659)]
68660#[cfg_attr(
68661    not(target_arch = "arm"),
68662    stable(feature = "neon_intrinsics", since = "1.59.0")
68663)]
68664#[cfg_attr(
68665    target_arch = "arm",
68666    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68667)]
68668pub unsafe fn vst2_u32(a: *mut u32, b: uint32x2x2_t) {
68669    vst2_s32(transmute(a), transmute(b))
68670}
68671#[doc = "Store multiple 2-element structures from two registers"]
68672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u32)"]
68673#[doc = "## Safety"]
68674#[doc = "  * Neon instrinsic unsafe"]
68675#[inline]
68676#[target_feature(enable = "neon")]
68677#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68678#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68679#[cfg_attr(
68680    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68681    assert_instr(st2)
68682)]
68683#[cfg_attr(
68684    not(target_arch = "arm"),
68685    stable(feature = "neon_intrinsics", since = "1.59.0")
68686)]
68687#[cfg_attr(
68688    target_arch = "arm",
68689    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68690)]
68691pub unsafe fn vst2q_u32(a: *mut u32, b: uint32x4x2_t) {
68692    vst2q_s32(transmute(a), transmute(b))
68693}
68694#[doc = "Store multiple 2-element structures from two registers"]
68695#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p8)"]
68696#[doc = "## Safety"]
68697#[doc = "  * Neon instrinsic unsafe"]
68698#[inline]
68699#[target_feature(enable = "neon")]
68700#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68701#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68702#[cfg_attr(
68703    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68704    assert_instr(st2)
68705)]
68706#[cfg_attr(
68707    not(target_arch = "arm"),
68708    stable(feature = "neon_intrinsics", since = "1.59.0")
68709)]
68710#[cfg_attr(
68711    target_arch = "arm",
68712    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68713)]
68714pub unsafe fn vst2_p8(a: *mut p8, b: poly8x8x2_t) {
68715    vst2_s8(transmute(a), transmute(b))
68716}
68717#[doc = "Store multiple 2-element structures from two registers"]
68718#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p8)"]
68719#[doc = "## Safety"]
68720#[doc = "  * Neon instrinsic unsafe"]
68721#[inline]
68722#[target_feature(enable = "neon")]
68723#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68724#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68725#[cfg_attr(
68726    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68727    assert_instr(st2)
68728)]
68729#[cfg_attr(
68730    not(target_arch = "arm"),
68731    stable(feature = "neon_intrinsics", since = "1.59.0")
68732)]
68733#[cfg_attr(
68734    target_arch = "arm",
68735    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68736)]
68737pub unsafe fn vst2q_p8(a: *mut p8, b: poly8x16x2_t) {
68738    vst2q_s8(transmute(a), transmute(b))
68739}
68740#[doc = "Store multiple 2-element structures from two registers"]
68741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p16)"]
68742#[doc = "## Safety"]
68743#[doc = "  * Neon instrinsic unsafe"]
68744#[inline]
68745#[target_feature(enable = "neon")]
68746#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68747#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68748#[cfg_attr(
68749    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68750    assert_instr(st2)
68751)]
68752#[cfg_attr(
68753    not(target_arch = "arm"),
68754    stable(feature = "neon_intrinsics", since = "1.59.0")
68755)]
68756#[cfg_attr(
68757    target_arch = "arm",
68758    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68759)]
68760pub unsafe fn vst2_p16(a: *mut p16, b: poly16x4x2_t) {
68761    vst2_s16(transmute(a), transmute(b))
68762}
68763#[doc = "Store multiple 2-element structures from two registers"]
68764#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p16)"]
68765#[doc = "## Safety"]
68766#[doc = "  * Neon instrinsic unsafe"]
68767#[inline]
68768#[target_feature(enable = "neon")]
68769#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68770#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68771#[cfg_attr(
68772    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68773    assert_instr(st2)
68774)]
68775#[cfg_attr(
68776    not(target_arch = "arm"),
68777    stable(feature = "neon_intrinsics", since = "1.59.0")
68778)]
68779#[cfg_attr(
68780    target_arch = "arm",
68781    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68782)]
68783pub unsafe fn vst2q_p16(a: *mut p16, b: poly16x8x2_t) {
68784    vst2q_s16(transmute(a), transmute(b))
68785}
68786#[doc = "Store multiple 3-element structures from three registers"]
68787#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"]
68788#[doc = "## Safety"]
68789#[doc = "  * Neon instrinsic unsafe"]
68790#[inline]
68791#[cfg(target_arch = "arm")]
68792#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68793#[target_feature(enable = "neon,fp16")]
68794#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68795#[cfg_attr(test, assert_instr(vst3))]
68796pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) {
68797    unsafe extern "unadjusted" {
68798        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v4f16")]
68799        fn _vst3_f16(ptr: *mut i8, a: float16x4_t, b: float16x4_t, c: float16x4_t, size: i32);
68800    }
68801    _vst3_f16(a as _, b.0, b.1, b.2, 2)
68802}
68803#[doc = "Store multiple 3-element structures from three registers"]
68804#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"]
68805#[doc = "## Safety"]
68806#[doc = "  * Neon instrinsic unsafe"]
68807#[inline]
68808#[cfg(target_arch = "arm")]
68809#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68810#[target_feature(enable = "neon,fp16")]
68811#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68812#[cfg_attr(test, assert_instr(vst3))]
68813pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) {
68814    unsafe extern "unadjusted" {
68815        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v8f16")]
68816        fn _vst3q_f16(ptr: *mut i8, a: float16x8_t, b: float16x8_t, c: float16x8_t, size: i32);
68817    }
68818    _vst3q_f16(a as _, b.0, b.1, b.2, 2)
68819}
68820#[doc = "Store multiple 3-element structures from three registers"]
68821#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"]
68822#[doc = "## Safety"]
68823#[doc = "  * Neon instrinsic unsafe"]
68824#[inline]
68825#[cfg(not(target_arch = "arm"))]
68826#[target_feature(enable = "neon,fp16")]
68827#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68828#[cfg_attr(test, assert_instr(st3))]
68829pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) {
68830    unsafe extern "unadjusted" {
68831        #[cfg_attr(
68832            any(target_arch = "aarch64", target_arch = "arm64ec"),
68833            link_name = "llvm.aarch64.neon.st3.v4f16.p0"
68834        )]
68835        fn _vst3_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t, ptr: *mut i8);
68836    }
68837    _vst3_f16(b.0, b.1, b.2, a as _)
68838}
68839#[doc = "Store multiple 3-element structures from three registers"]
68840#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"]
68841#[doc = "## Safety"]
68842#[doc = "  * Neon instrinsic unsafe"]
68843#[inline]
68844#[cfg(not(target_arch = "arm"))]
68845#[target_feature(enable = "neon,fp16")]
68846#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68847#[cfg_attr(test, assert_instr(st3))]
68848pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) {
68849    unsafe extern "unadjusted" {
68850        #[cfg_attr(
68851            any(target_arch = "aarch64", target_arch = "arm64ec"),
68852            link_name = "llvm.aarch64.neon.st3.v8f16.p0"
68853        )]
68854        fn _vst3q_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t, ptr: *mut i8);
68855    }
68856    _vst3q_f16(b.0, b.1, b.2, a as _)
68857}
68858#[doc = "Store multiple 3-element structures from three registers"]
68859#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"]
68860#[doc = "## Safety"]
68861#[doc = "  * Neon instrinsic unsafe"]
68862#[inline]
68863#[cfg(target_arch = "arm")]
68864#[target_feature(enable = "neon,v7")]
68865#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68866#[cfg_attr(test, assert_instr(vst3))]
68867pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
68868    unsafe extern "unadjusted" {
68869        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v2f32")]
68870        fn _vst3_f32(ptr: *mut i8, a: float32x2_t, b: float32x2_t, c: float32x2_t, size: i32);
68871    }
68872    _vst3_f32(a as _, b.0, b.1, b.2, 4)
68873}
68874#[doc = "Store multiple 3-element structures from three registers"]
68875#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"]
68876#[doc = "## Safety"]
68877#[doc = "  * Neon instrinsic unsafe"]
68878#[inline]
68879#[cfg(target_arch = "arm")]
68880#[target_feature(enable = "neon,v7")]
68881#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68882#[cfg_attr(test, assert_instr(vst3))]
68883pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
68884    unsafe extern "unadjusted" {
68885        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v4f32")]
68886        fn _vst3q_f32(ptr: *mut i8, a: float32x4_t, b: float32x4_t, c: float32x4_t, size: i32);
68887    }
68888    _vst3q_f32(a as _, b.0, b.1, b.2, 4)
68889}
68890#[doc = "Store multiple 3-element structures from three registers"]
68891#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"]
68892#[doc = "## Safety"]
68893#[doc = "  * Neon instrinsic unsafe"]
68894#[inline]
68895#[cfg(target_arch = "arm")]
68896#[target_feature(enable = "neon,v7")]
68897#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68898#[cfg_attr(test, assert_instr(vst3))]
68899pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
68900    unsafe extern "unadjusted" {
68901        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v8i8")]
68902        fn _vst3_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, size: i32);
68903    }
68904    _vst3_s8(a as _, b.0, b.1, b.2, 1)
68905}
68906#[doc = "Store multiple 3-element structures from three registers"]
68907#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"]
68908#[doc = "## Safety"]
68909#[doc = "  * Neon instrinsic unsafe"]
68910#[inline]
68911#[cfg(target_arch = "arm")]
68912#[target_feature(enable = "neon,v7")]
68913#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68914#[cfg_attr(test, assert_instr(vst3))]
68915pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
68916    unsafe extern "unadjusted" {
68917        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v16i8")]
68918        fn _vst3q_s8(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t, size: i32);
68919    }
68920    _vst3q_s8(a as _, b.0, b.1, b.2, 1)
68921}
68922#[doc = "Store multiple 3-element structures from three registers"]
68923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"]
68924#[doc = "## Safety"]
68925#[doc = "  * Neon instrinsic unsafe"]
68926#[inline]
68927#[cfg(target_arch = "arm")]
68928#[target_feature(enable = "neon,v7")]
68929#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68930#[cfg_attr(test, assert_instr(vst3))]
68931pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
68932    unsafe extern "unadjusted" {
68933        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v4i16")]
68934        fn _vst3_s16(ptr: *mut i8, a: int16x4_t, b: int16x4_t, c: int16x4_t, size: i32);
68935    }
68936    _vst3_s16(a as _, b.0, b.1, b.2, 2)
68937}
68938#[doc = "Store multiple 3-element structures from three registers"]
68939#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"]
68940#[doc = "## Safety"]
68941#[doc = "  * Neon instrinsic unsafe"]
68942#[inline]
68943#[cfg(target_arch = "arm")]
68944#[target_feature(enable = "neon,v7")]
68945#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68946#[cfg_attr(test, assert_instr(vst3))]
68947pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
68948    unsafe extern "unadjusted" {
68949        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v8i16")]
68950        fn _vst3q_s16(ptr: *mut i8, a: int16x8_t, b: int16x8_t, c: int16x8_t, size: i32);
68951    }
68952    _vst3q_s16(a as _, b.0, b.1, b.2, 2)
68953}
68954#[doc = "Store multiple 3-element structures from three registers"]
68955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"]
68956#[doc = "## Safety"]
68957#[doc = "  * Neon instrinsic unsafe"]
68958#[inline]
68959#[cfg(target_arch = "arm")]
68960#[target_feature(enable = "neon,v7")]
68961#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68962#[cfg_attr(test, assert_instr(vst3))]
68963pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
68964    unsafe extern "unadjusted" {
68965        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v2i32")]
68966        fn _vst3_s32(ptr: *mut i8, a: int32x2_t, b: int32x2_t, c: int32x2_t, size: i32);
68967    }
68968    _vst3_s32(a as _, b.0, b.1, b.2, 4)
68969}
68970#[doc = "Store multiple 3-element structures from three registers"]
68971#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"]
68972#[doc = "## Safety"]
68973#[doc = "  * Neon instrinsic unsafe"]
68974#[inline]
68975#[cfg(target_arch = "arm")]
68976#[target_feature(enable = "neon,v7")]
68977#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68978#[cfg_attr(test, assert_instr(vst3))]
68979pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
68980    unsafe extern "unadjusted" {
68981        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v4i32")]
68982        fn _vst3q_s32(ptr: *mut i8, a: int32x4_t, b: int32x4_t, c: int32x4_t, size: i32);
68983    }
68984    _vst3q_s32(a as _, b.0, b.1, b.2, 4)
68985}
68986#[doc = "Store multiple 3-element structures from three registers"]
68987#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"]
68988#[doc = "## Safety"]
68989#[doc = "  * Neon instrinsic unsafe"]
68990#[inline]
68991#[target_feature(enable = "neon")]
68992#[cfg(not(target_arch = "arm"))]
68993#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68994#[cfg_attr(test, assert_instr(st3))]
68995pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
68996    unsafe extern "unadjusted" {
68997        #[cfg_attr(
68998            any(target_arch = "aarch64", target_arch = "arm64ec"),
68999            link_name = "llvm.aarch64.neon.st3.v2f32.p0"
69000        )]
69001        fn _vst3_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, ptr: *mut i8);
69002    }
69003    _vst3_f32(b.0, b.1, b.2, a as _)
69004}
69005#[doc = "Store multiple 3-element structures from three registers"]
69006#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"]
69007#[doc = "## Safety"]
69008#[doc = "  * Neon instrinsic unsafe"]
69009#[inline]
69010#[target_feature(enable = "neon")]
69011#[cfg(not(target_arch = "arm"))]
69012#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69013#[cfg_attr(test, assert_instr(st3))]
69014pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
69015    unsafe extern "unadjusted" {
69016        #[cfg_attr(
69017            any(target_arch = "aarch64", target_arch = "arm64ec"),
69018            link_name = "llvm.aarch64.neon.st3.v4f32.p0"
69019        )]
69020        fn _vst3q_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, ptr: *mut i8);
69021    }
69022    _vst3q_f32(b.0, b.1, b.2, a as _)
69023}
69024#[doc = "Store multiple 3-element structures from three registers"]
69025#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"]
69026#[doc = "## Safety"]
69027#[doc = "  * Neon instrinsic unsafe"]
69028#[inline]
69029#[target_feature(enable = "neon")]
69030#[cfg(not(target_arch = "arm"))]
69031#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69032#[cfg_attr(test, assert_instr(st3))]
69033pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
69034    unsafe extern "unadjusted" {
69035        #[cfg_attr(
69036            any(target_arch = "aarch64", target_arch = "arm64ec"),
69037            link_name = "llvm.aarch64.neon.st3.v8i8.p0"
69038        )]
69039        fn _vst3_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, ptr: *mut i8);
69040    }
69041    _vst3_s8(b.0, b.1, b.2, a as _)
69042}
69043#[doc = "Store multiple 3-element structures from three registers"]
69044#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"]
69045#[doc = "## Safety"]
69046#[doc = "  * Neon instrinsic unsafe"]
69047#[inline]
69048#[target_feature(enable = "neon")]
69049#[cfg(not(target_arch = "arm"))]
69050#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69051#[cfg_attr(test, assert_instr(st3))]
69052pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
69053    unsafe extern "unadjusted" {
69054        #[cfg_attr(
69055            any(target_arch = "aarch64", target_arch = "arm64ec"),
69056            link_name = "llvm.aarch64.neon.st3.v16i8.p0"
69057        )]
69058        fn _vst3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t, ptr: *mut i8);
69059    }
69060    _vst3q_s8(b.0, b.1, b.2, a as _)
69061}
69062#[doc = "Store multiple 3-element structures from three registers"]
69063#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"]
69064#[doc = "## Safety"]
69065#[doc = "  * Neon instrinsic unsafe"]
69066#[inline]
69067#[target_feature(enable = "neon")]
69068#[cfg(not(target_arch = "arm"))]
69069#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69070#[cfg_attr(test, assert_instr(st3))]
69071pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
69072    unsafe extern "unadjusted" {
69073        #[cfg_attr(
69074            any(target_arch = "aarch64", target_arch = "arm64ec"),
69075            link_name = "llvm.aarch64.neon.st3.v4i16.p0"
69076        )]
69077        fn _vst3_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, ptr: *mut i8);
69078    }
69079    _vst3_s16(b.0, b.1, b.2, a as _)
69080}
69081#[doc = "Store multiple 3-element structures from three registers"]
69082#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"]
69083#[doc = "## Safety"]
69084#[doc = "  * Neon instrinsic unsafe"]
69085#[inline]
69086#[target_feature(enable = "neon")]
69087#[cfg(not(target_arch = "arm"))]
69088#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69089#[cfg_attr(test, assert_instr(st3))]
69090pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
69091    unsafe extern "unadjusted" {
69092        #[cfg_attr(
69093            any(target_arch = "aarch64", target_arch = "arm64ec"),
69094            link_name = "llvm.aarch64.neon.st3.v8i16.p0"
69095        )]
69096        fn _vst3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, ptr: *mut i8);
69097    }
69098    _vst3q_s16(b.0, b.1, b.2, a as _)
69099}
69100#[doc = "Store multiple 3-element structures from three registers"]
69101#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"]
69102#[doc = "## Safety"]
69103#[doc = "  * Neon instrinsic unsafe"]
69104#[inline]
69105#[target_feature(enable = "neon")]
69106#[cfg(not(target_arch = "arm"))]
69107#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69108#[cfg_attr(test, assert_instr(st3))]
69109pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
69110    unsafe extern "unadjusted" {
69111        #[cfg_attr(
69112            any(target_arch = "aarch64", target_arch = "arm64ec"),
69113            link_name = "llvm.aarch64.neon.st3.v2i32.p0"
69114        )]
69115        fn _vst3_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, ptr: *mut i8);
69116    }
69117    _vst3_s32(b.0, b.1, b.2, a as _)
69118}
69119#[doc = "Store multiple 3-element structures from three registers"]
69120#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"]
69121#[doc = "## Safety"]
69122#[doc = "  * Neon instrinsic unsafe"]
69123#[inline]
69124#[target_feature(enable = "neon")]
69125#[cfg(not(target_arch = "arm"))]
69126#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69127#[cfg_attr(test, assert_instr(st3))]
69128pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
69129    unsafe extern "unadjusted" {
69130        #[cfg_attr(
69131            any(target_arch = "aarch64", target_arch = "arm64ec"),
69132            link_name = "llvm.aarch64.neon.st3.v4i32.p0"
69133        )]
69134        fn _vst3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, ptr: *mut i8);
69135    }
69136    _vst3q_s32(b.0, b.1, b.2, a as _)
69137}
69138#[doc = "Store multiple 3-element structures from three registers"]
69139#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"]
69140#[doc = "## Safety"]
69141#[doc = "  * Neon instrinsic unsafe"]
69142#[inline]
69143#[cfg(target_arch = "arm")]
69144#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69145#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69146#[rustc_legacy_const_generics(2)]
69147#[target_feature(enable = "neon,fp16")]
69148#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
69149pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
69150    static_assert_uimm_bits!(LANE, 2);
69151    unsafe extern "unadjusted" {
69152        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0.v4f16")]
69153        fn _vst3_lane_f16(
69154            ptr: *mut i8,
69155            a: float16x4_t,
69156            b: float16x4_t,
69157            c: float16x4_t,
69158            n: i32,
69159            size: i32,
69160        );
69161    }
69162    _vst3_lane_f16(a as _, b.0, b.1, b.2, LANE, 4)
69163}
69164#[doc = "Store multiple 3-element structures from three registers"]
69165#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"]
69166#[doc = "## Safety"]
69167#[doc = "  * Neon instrinsic unsafe"]
69168#[inline]
69169#[cfg(target_arch = "arm")]
69170#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69171#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69172#[rustc_legacy_const_generics(2)]
69173#[target_feature(enable = "neon,fp16")]
69174#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
69175pub unsafe fn vst3q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x3_t) {
69176    static_assert_uimm_bits!(LANE, 3);
69177    unsafe extern "unadjusted" {
69178        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0.v8f16")]
69179        fn _vst3q_lane_f16(
69180            ptr: *mut i8,
69181            a: float16x8_t,
69182            b: float16x8_t,
69183            c: float16x8_t,
69184            n: i32,
69185            size: i32,
69186        );
69187    }
69188    _vst3q_lane_f16(a as _, b.0, b.1, b.2, LANE, 4)
69189}
69190#[doc = "Store multiple 3-element structures from three registers"]
69191#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"]
69192#[doc = "## Safety"]
69193#[doc = "  * Neon instrinsic unsafe"]
69194#[inline]
69195#[cfg(not(target_arch = "arm"))]
69196#[rustc_legacy_const_generics(2)]
69197#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69198#[target_feature(enable = "neon,fp16")]
69199#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
69200pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
69201    static_assert_uimm_bits!(LANE, 2);
69202    unsafe extern "unadjusted" {
69203        #[cfg_attr(
69204            any(target_arch = "aarch64", target_arch = "arm64ec"),
69205            link_name = "llvm.aarch64.neon.st3lane.v4f16.p0"
69206        )]
69207        fn _vst3_lane_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t, n: i64, ptr: *mut i8);
69208    }
69209    _vst3_lane_f16(b.0, b.1, b.2, LANE as i64, a as _)
69210}
69211#[doc = "Store multiple 3-element structures from three registers"]
69212#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"]
69213#[doc = "## Safety"]
69214#[doc = "  * Neon instrinsic unsafe"]
69215#[inline]
69216#[cfg(not(target_arch = "arm"))]
69217#[rustc_legacy_const_generics(2)]
69218#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69219#[target_feature(enable = "neon,fp16")]
69220#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
69221pub unsafe fn vst3q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x3_t) {
69222    static_assert_uimm_bits!(LANE, 3);
69223    unsafe extern "unadjusted" {
69224        #[cfg_attr(
69225            any(target_arch = "aarch64", target_arch = "arm64ec"),
69226            link_name = "llvm.aarch64.neon.st3lane.v8f16.p0"
69227        )]
69228        fn _vst3q_lane_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t, n: i64, ptr: *mut i8);
69229    }
69230    _vst3q_lane_f16(b.0, b.1, b.2, LANE as i64, a as _)
69231}
69232#[doc = "Store multiple 3-element structures from three registers"]
69233#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"]
69234#[doc = "## Safety"]
69235#[doc = "  * Neon instrinsic unsafe"]
69236#[inline]
69237#[cfg(target_arch = "arm")]
69238#[target_feature(enable = "neon,v7")]
69239#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69240#[rustc_legacy_const_generics(2)]
69241#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69242pub unsafe fn vst3_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x3_t) {
69243    static_assert_uimm_bits!(LANE, 1);
69244    unsafe extern "unadjusted" {
69245        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0.v2f32")]
69246        fn _vst3_lane_f32(
69247            ptr: *mut i8,
69248            a: float32x2_t,
69249            b: float32x2_t,
69250            c: float32x2_t,
69251            n: i32,
69252            size: i32,
69253        );
69254    }
69255    _vst3_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
69256}
69257#[doc = "Store multiple 3-element structures from three registers"]
69258#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"]
69259#[doc = "## Safety"]
69260#[doc = "  * Neon instrinsic unsafe"]
69261#[inline]
69262#[cfg(target_arch = "arm")]
69263#[target_feature(enable = "neon,v7")]
69264#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69265#[rustc_legacy_const_generics(2)]
69266#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69267pub unsafe fn vst3q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x3_t) {
69268    static_assert_uimm_bits!(LANE, 2);
69269    unsafe extern "unadjusted" {
69270        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0.v4f32")]
69271        fn _vst3q_lane_f32(
69272            ptr: *mut i8,
69273            a: float32x4_t,
69274            b: float32x4_t,
69275            c: float32x4_t,
69276            n: i32,
69277            size: i32,
69278        );
69279    }
69280    _vst3q_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
69281}
69282#[doc = "Store multiple 3-element structures from three registers"]
69283#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"]
69284#[doc = "## Safety"]
69285#[doc = "  * Neon instrinsic unsafe"]
69286#[inline]
69287#[cfg(target_arch = "arm")]
69288#[target_feature(enable = "neon,v7")]
69289#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69290#[rustc_legacy_const_generics(2)]
69291#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69292pub unsafe fn vst3_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x3_t) {
69293    static_assert_uimm_bits!(LANE, 3);
69294    unsafe extern "unadjusted" {
69295        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0.v8i8")]
69296        fn _vst3_lane_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, n: i32, size: i32);
69297    }
69298    _vst3_lane_s8(a as _, b.0, b.1, b.2, LANE, 1)
69299}
69300#[doc = "Store multiple 3-element structures from three registers"]
69301#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"]
69302#[doc = "## Safety"]
69303#[doc = "  * Neon instrinsic unsafe"]
69304#[inline]
69305#[cfg(target_arch = "arm")]
69306#[target_feature(enable = "neon,v7")]
69307#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69308#[rustc_legacy_const_generics(2)]
69309#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69310pub unsafe fn vst3_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x3_t) {
69311    static_assert_uimm_bits!(LANE, 2);
69312    unsafe extern "unadjusted" {
69313        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0.v4i16")]
69314        fn _vst3_lane_s16(
69315            ptr: *mut i8,
69316            a: int16x4_t,
69317            b: int16x4_t,
69318            c: int16x4_t,
69319            n: i32,
69320            size: i32,
69321        );
69322    }
69323    _vst3_lane_s16(a as _, b.0, b.1, b.2, LANE, 2)
69324}
69325#[doc = "Store multiple 3-element structures from three registers"]
69326#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"]
69327#[doc = "## Safety"]
69328#[doc = "  * Neon instrinsic unsafe"]
69329#[inline]
69330#[cfg(target_arch = "arm")]
69331#[target_feature(enable = "neon,v7")]
69332#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69333#[rustc_legacy_const_generics(2)]
69334#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69335pub unsafe fn vst3q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x3_t) {
69336    static_assert_uimm_bits!(LANE, 3);
69337    unsafe extern "unadjusted" {
69338        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0.v8i16")]
69339        fn _vst3q_lane_s16(
69340            ptr: *mut i8,
69341            a: int16x8_t,
69342            b: int16x8_t,
69343            c: int16x8_t,
69344            n: i32,
69345            size: i32,
69346        );
69347    }
69348    _vst3q_lane_s16(a as _, b.0, b.1, b.2, LANE, 2)
69349}
69350#[doc = "Store multiple 3-element structures from three registers"]
69351#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"]
69352#[doc = "## Safety"]
69353#[doc = "  * Neon instrinsic unsafe"]
69354#[inline]
69355#[cfg(target_arch = "arm")]
69356#[target_feature(enable = "neon,v7")]
69357#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69358#[rustc_legacy_const_generics(2)]
69359#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69360pub unsafe fn vst3_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x3_t) {
69361    static_assert_uimm_bits!(LANE, 1);
69362    unsafe extern "unadjusted" {
69363        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0.v2i32")]
69364        fn _vst3_lane_s32(
69365            ptr: *mut i8,
69366            a: int32x2_t,
69367            b: int32x2_t,
69368            c: int32x2_t,
69369            n: i32,
69370            size: i32,
69371        );
69372    }
69373    _vst3_lane_s32(a as _, b.0, b.1, b.2, LANE, 4)
69374}
69375#[doc = "Store multiple 3-element structures from three registers"]
69376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"]
69377#[doc = "## Safety"]
69378#[doc = "  * Neon instrinsic unsafe"]
69379#[inline]
69380#[cfg(target_arch = "arm")]
69381#[target_feature(enable = "neon,v7")]
69382#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69383#[rustc_legacy_const_generics(2)]
69384#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69385pub unsafe fn vst3q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x3_t) {
69386    static_assert_uimm_bits!(LANE, 2);
69387    unsafe extern "unadjusted" {
69388        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0.v4i32")]
69389        fn _vst3q_lane_s32(
69390            ptr: *mut i8,
69391            a: int32x4_t,
69392            b: int32x4_t,
69393            c: int32x4_t,
69394            n: i32,
69395            size: i32,
69396        );
69397    }
69398    _vst3q_lane_s32(a as _, b.0, b.1, b.2, LANE, 4)
69399}
69400#[doc = "Store multiple 3-element structures from three registers"]
69401#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"]
69402#[doc = "## Safety"]
69403#[doc = "  * Neon instrinsic unsafe"]
69404#[inline]
69405#[target_feature(enable = "neon")]
69406#[cfg(not(target_arch = "arm"))]
69407#[rustc_legacy_const_generics(2)]
69408#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69409#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69410pub unsafe fn vst3_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x3_t) {
69411    static_assert_uimm_bits!(LANE, 1);
69412    unsafe extern "unadjusted" {
69413        #[cfg_attr(
69414            any(target_arch = "aarch64", target_arch = "arm64ec"),
69415            link_name = "llvm.aarch64.neon.st3lane.v2f32.p0"
69416        )]
69417        fn _vst3_lane_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, n: i64, ptr: *mut i8);
69418    }
69419    _vst3_lane_f32(b.0, b.1, b.2, LANE as i64, a as _)
69420}
69421#[doc = "Store multiple 3-element structures from three registers"]
69422#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"]
69423#[doc = "## Safety"]
69424#[doc = "  * Neon instrinsic unsafe"]
69425#[inline]
69426#[target_feature(enable = "neon")]
69427#[cfg(not(target_arch = "arm"))]
69428#[rustc_legacy_const_generics(2)]
69429#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69430#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69431pub unsafe fn vst3q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x3_t) {
69432    static_assert_uimm_bits!(LANE, 2);
69433    unsafe extern "unadjusted" {
69434        #[cfg_attr(
69435            any(target_arch = "aarch64", target_arch = "arm64ec"),
69436            link_name = "llvm.aarch64.neon.st3lane.v4f32.p0"
69437        )]
69438        fn _vst3q_lane_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, n: i64, ptr: *mut i8);
69439    }
69440    _vst3q_lane_f32(b.0, b.1, b.2, LANE as i64, a as _)
69441}
69442#[doc = "Store multiple 3-element structures from three registers"]
69443#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"]
69444#[doc = "## Safety"]
69445#[doc = "  * Neon instrinsic unsafe"]
69446#[inline]
69447#[target_feature(enable = "neon")]
69448#[cfg(not(target_arch = "arm"))]
69449#[rustc_legacy_const_generics(2)]
69450#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69451#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69452pub unsafe fn vst3_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x3_t) {
69453    static_assert_uimm_bits!(LANE, 3);
69454    unsafe extern "unadjusted" {
69455        #[cfg_attr(
69456            any(target_arch = "aarch64", target_arch = "arm64ec"),
69457            link_name = "llvm.aarch64.neon.st3lane.v8i8.p0"
69458        )]
69459        fn _vst3_lane_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, n: i64, ptr: *mut i8);
69460    }
69461    _vst3_lane_s8(b.0, b.1, b.2, LANE as i64, a as _)
69462}
69463#[doc = "Store multiple 3-element structures from three registers"]
69464#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"]
69465#[doc = "## Safety"]
69466#[doc = "  * Neon instrinsic unsafe"]
69467#[inline]
69468#[target_feature(enable = "neon")]
69469#[cfg(not(target_arch = "arm"))]
69470#[rustc_legacy_const_generics(2)]
69471#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69472#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69473pub unsafe fn vst3_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x3_t) {
69474    static_assert_uimm_bits!(LANE, 2);
69475    unsafe extern "unadjusted" {
69476        #[cfg_attr(
69477            any(target_arch = "aarch64", target_arch = "arm64ec"),
69478            link_name = "llvm.aarch64.neon.st3lane.v4i16.p0"
69479        )]
69480        fn _vst3_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, n: i64, ptr: *mut i8);
69481    }
69482    _vst3_lane_s16(b.0, b.1, b.2, LANE as i64, a as _)
69483}
69484#[doc = "Store multiple 3-element structures from three registers"]
69485#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"]
69486#[doc = "## Safety"]
69487#[doc = "  * Neon instrinsic unsafe"]
69488#[inline]
69489#[target_feature(enable = "neon")]
69490#[cfg(not(target_arch = "arm"))]
69491#[rustc_legacy_const_generics(2)]
69492#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69493#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69494pub unsafe fn vst3q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x3_t) {
69495    static_assert_uimm_bits!(LANE, 3);
69496    unsafe extern "unadjusted" {
69497        #[cfg_attr(
69498            any(target_arch = "aarch64", target_arch = "arm64ec"),
69499            link_name = "llvm.aarch64.neon.st3lane.v8i16.p0"
69500        )]
69501        fn _vst3q_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, n: i64, ptr: *mut i8);
69502    }
69503    _vst3q_lane_s16(b.0, b.1, b.2, LANE as i64, a as _)
69504}
69505#[doc = "Store multiple 3-element structures from three registers"]
69506#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"]
69507#[doc = "## Safety"]
69508#[doc = "  * Neon instrinsic unsafe"]
69509#[inline]
69510#[target_feature(enable = "neon")]
69511#[cfg(not(target_arch = "arm"))]
69512#[rustc_legacy_const_generics(2)]
69513#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69514#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69515pub unsafe fn vst3_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x3_t) {
69516    static_assert_uimm_bits!(LANE, 1);
69517    unsafe extern "unadjusted" {
69518        #[cfg_attr(
69519            any(target_arch = "aarch64", target_arch = "arm64ec"),
69520            link_name = "llvm.aarch64.neon.st3lane.v2i32.p0"
69521        )]
69522        fn _vst3_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, n: i64, ptr: *mut i8);
69523    }
69524    _vst3_lane_s32(b.0, b.1, b.2, LANE as i64, a as _)
69525}
69526#[doc = "Store multiple 3-element structures from three registers"]
69527#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"]
69528#[doc = "## Safety"]
69529#[doc = "  * Neon instrinsic unsafe"]
69530#[inline]
69531#[target_feature(enable = "neon")]
69532#[cfg(not(target_arch = "arm"))]
69533#[rustc_legacy_const_generics(2)]
69534#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69535#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69536pub unsafe fn vst3q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x3_t) {
69537    static_assert_uimm_bits!(LANE, 2);
69538    unsafe extern "unadjusted" {
69539        #[cfg_attr(
69540            any(target_arch = "aarch64", target_arch = "arm64ec"),
69541            link_name = "llvm.aarch64.neon.st3lane.v4i32.p0"
69542        )]
69543        fn _vst3q_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, n: i64, ptr: *mut i8);
69544    }
69545    _vst3q_lane_s32(b.0, b.1, b.2, LANE as i64, a as _)
69546}
69547#[doc = "Store multiple 3-element structures from three registers"]
69548#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u8)"]
69549#[doc = "## Safety"]
69550#[doc = "  * Neon instrinsic unsafe"]
69551#[inline]
69552#[target_feature(enable = "neon")]
69553#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69554#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69555#[cfg_attr(
69556    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69557    assert_instr(st3, LANE = 0)
69558)]
69559#[rustc_legacy_const_generics(2)]
69560#[cfg_attr(
69561    not(target_arch = "arm"),
69562    stable(feature = "neon_intrinsics", since = "1.59.0")
69563)]
69564#[cfg_attr(
69565    target_arch = "arm",
69566    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69567)]
69568pub unsafe fn vst3_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x3_t) {
69569    static_assert_uimm_bits!(LANE, 3);
69570    vst3_lane_s8::<LANE>(transmute(a), transmute(b))
69571}
69572#[doc = "Store multiple 3-element structures from three registers"]
69573#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u16)"]
69574#[doc = "## Safety"]
69575#[doc = "  * Neon instrinsic unsafe"]
69576#[inline]
69577#[target_feature(enable = "neon")]
69578#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69579#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69580#[cfg_attr(
69581    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69582    assert_instr(st3, LANE = 0)
69583)]
69584#[rustc_legacy_const_generics(2)]
69585#[cfg_attr(
69586    not(target_arch = "arm"),
69587    stable(feature = "neon_intrinsics", since = "1.59.0")
69588)]
69589#[cfg_attr(
69590    target_arch = "arm",
69591    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69592)]
69593pub unsafe fn vst3_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x3_t) {
69594    static_assert_uimm_bits!(LANE, 2);
69595    vst3_lane_s16::<LANE>(transmute(a), transmute(b))
69596}
69597#[doc = "Store multiple 3-element structures from three registers"]
69598#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u16)"]
69599#[doc = "## Safety"]
69600#[doc = "  * Neon instrinsic unsafe"]
69601#[inline]
69602#[target_feature(enable = "neon")]
69603#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69604#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69605#[cfg_attr(
69606    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69607    assert_instr(st3, LANE = 0)
69608)]
69609#[rustc_legacy_const_generics(2)]
69610#[cfg_attr(
69611    not(target_arch = "arm"),
69612    stable(feature = "neon_intrinsics", since = "1.59.0")
69613)]
69614#[cfg_attr(
69615    target_arch = "arm",
69616    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69617)]
69618pub unsafe fn vst3q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x3_t) {
69619    static_assert_uimm_bits!(LANE, 3);
69620    vst3q_lane_s16::<LANE>(transmute(a), transmute(b))
69621}
69622#[doc = "Store multiple 3-element structures from three registers"]
69623#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u32)"]
69624#[doc = "## Safety"]
69625#[doc = "  * Neon instrinsic unsafe"]
69626#[inline]
69627#[target_feature(enable = "neon")]
69628#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69629#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69630#[cfg_attr(
69631    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69632    assert_instr(st3, LANE = 0)
69633)]
69634#[rustc_legacy_const_generics(2)]
69635#[cfg_attr(
69636    not(target_arch = "arm"),
69637    stable(feature = "neon_intrinsics", since = "1.59.0")
69638)]
69639#[cfg_attr(
69640    target_arch = "arm",
69641    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69642)]
69643pub unsafe fn vst3_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x3_t) {
69644    static_assert_uimm_bits!(LANE, 1);
69645    vst3_lane_s32::<LANE>(transmute(a), transmute(b))
69646}
69647#[doc = "Store multiple 3-element structures from three registers"]
69648#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u32)"]
69649#[doc = "## Safety"]
69650#[doc = "  * Neon instrinsic unsafe"]
69651#[inline]
69652#[target_feature(enable = "neon")]
69653#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69654#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69655#[cfg_attr(
69656    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69657    assert_instr(st3, LANE = 0)
69658)]
69659#[rustc_legacy_const_generics(2)]
69660#[cfg_attr(
69661    not(target_arch = "arm"),
69662    stable(feature = "neon_intrinsics", since = "1.59.0")
69663)]
69664#[cfg_attr(
69665    target_arch = "arm",
69666    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69667)]
69668pub unsafe fn vst3q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x3_t) {
69669    static_assert_uimm_bits!(LANE, 2);
69670    vst3q_lane_s32::<LANE>(transmute(a), transmute(b))
69671}
69672#[doc = "Store multiple 3-element structures from three registers"]
69673#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p8)"]
69674#[doc = "## Safety"]
69675#[doc = "  * Neon instrinsic unsafe"]
69676#[inline]
69677#[target_feature(enable = "neon")]
69678#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69679#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69680#[cfg_attr(
69681    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69682    assert_instr(st3, LANE = 0)
69683)]
69684#[rustc_legacy_const_generics(2)]
69685#[cfg_attr(
69686    not(target_arch = "arm"),
69687    stable(feature = "neon_intrinsics", since = "1.59.0")
69688)]
69689#[cfg_attr(
69690    target_arch = "arm",
69691    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69692)]
69693pub unsafe fn vst3_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x3_t) {
69694    static_assert_uimm_bits!(LANE, 3);
69695    vst3_lane_s8::<LANE>(transmute(a), transmute(b))
69696}
69697#[doc = "Store multiple 3-element structures from three registers"]
69698#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p16)"]
69699#[doc = "## Safety"]
69700#[doc = "  * Neon instrinsic unsafe"]
69701#[inline]
69702#[target_feature(enable = "neon")]
69703#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69704#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69705#[cfg_attr(
69706    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69707    assert_instr(st3, LANE = 0)
69708)]
69709#[rustc_legacy_const_generics(2)]
69710#[cfg_attr(
69711    not(target_arch = "arm"),
69712    stable(feature = "neon_intrinsics", since = "1.59.0")
69713)]
69714#[cfg_attr(
69715    target_arch = "arm",
69716    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69717)]
69718pub unsafe fn vst3_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x3_t) {
69719    static_assert_uimm_bits!(LANE, 2);
69720    vst3_lane_s16::<LANE>(transmute(a), transmute(b))
69721}
69722#[doc = "Store multiple 3-element structures from three registers"]
69723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p16)"]
69724#[doc = "## Safety"]
69725#[doc = "  * Neon instrinsic unsafe"]
69726#[inline]
69727#[target_feature(enable = "neon")]
69728#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69729#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69730#[cfg_attr(
69731    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69732    assert_instr(st3, LANE = 0)
69733)]
69734#[rustc_legacy_const_generics(2)]
69735#[cfg_attr(
69736    not(target_arch = "arm"),
69737    stable(feature = "neon_intrinsics", since = "1.59.0")
69738)]
69739#[cfg_attr(
69740    target_arch = "arm",
69741    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69742)]
69743pub unsafe fn vst3q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x3_t) {
69744    static_assert_uimm_bits!(LANE, 3);
69745    vst3q_lane_s16::<LANE>(transmute(a), transmute(b))
69746}
69747#[doc = "Store multiple 3-element structures from three registers"]
69748#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p64)"]
69749#[doc = "## Safety"]
69750#[doc = "  * Neon instrinsic unsafe"]
69751#[inline]
69752#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
69753#[target_feature(enable = "neon,aes")]
69754#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
69755#[cfg_attr(
69756    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69757    assert_instr(nop)
69758)]
69759#[cfg_attr(
69760    not(target_arch = "arm"),
69761    stable(feature = "neon_intrinsics", since = "1.59.0")
69762)]
69763#[cfg_attr(
69764    target_arch = "arm",
69765    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69766)]
69767pub unsafe fn vst3_p64(a: *mut p64, b: poly64x1x3_t) {
69768    vst3_s64(transmute(a), transmute(b))
69769}
69770#[doc = "Store multiple 3-element structures from three registers"]
69771#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"]
69772#[doc = "## Safety"]
69773#[doc = "  * Neon instrinsic unsafe"]
69774#[inline]
69775#[target_feature(enable = "neon")]
69776#[cfg(not(target_arch = "arm"))]
69777#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69778#[cfg_attr(test, assert_instr(nop))]
69779pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) {
69780    unsafe extern "unadjusted" {
69781        #[cfg_attr(
69782            any(target_arch = "aarch64", target_arch = "arm64ec"),
69783            link_name = "llvm.aarch64.neon.st3.v1i64.p0"
69784        )]
69785        fn _vst3_s64(a: int64x1_t, b: int64x1_t, c: int64x1_t, ptr: *mut i8);
69786    }
69787    _vst3_s64(b.0, b.1, b.2, a as _)
69788}
69789#[doc = "Store multiple 3-element structures from three registers"]
69790#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"]
69791#[doc = "## Safety"]
69792#[doc = "  * Neon instrinsic unsafe"]
69793#[inline]
69794#[cfg(target_arch = "arm")]
69795#[target_feature(enable = "neon,v7")]
69796#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69797#[cfg_attr(test, assert_instr(nop))]
69798pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) {
69799    unsafe extern "unadjusted" {
69800        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v1i64")]
69801        fn _vst3_s64(ptr: *mut i8, a: int64x1_t, b: int64x1_t, c: int64x1_t, size: i32);
69802    }
69803    _vst3_s64(a as _, b.0, b.1, b.2, 8)
69804}
69805#[doc = "Store multiple 3-element structures from three registers"]
69806#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u64)"]
69807#[doc = "## Safety"]
69808#[doc = "  * Neon instrinsic unsafe"]
69809#[inline]
69810#[target_feature(enable = "neon")]
69811#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69812#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
69813#[cfg_attr(
69814    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69815    assert_instr(nop)
69816)]
69817#[cfg_attr(
69818    not(target_arch = "arm"),
69819    stable(feature = "neon_intrinsics", since = "1.59.0")
69820)]
69821#[cfg_attr(
69822    target_arch = "arm",
69823    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69824)]
69825pub unsafe fn vst3_u64(a: *mut u64, b: uint64x1x3_t) {
69826    vst3_s64(transmute(a), transmute(b))
69827}
69828#[doc = "Store multiple 3-element structures from three registers"]
69829#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u8)"]
69830#[doc = "## Safety"]
69831#[doc = "  * Neon instrinsic unsafe"]
69832#[inline]
69833#[target_feature(enable = "neon")]
69834#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69835#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69836#[cfg_attr(
69837    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69838    assert_instr(st3)
69839)]
69840#[cfg_attr(
69841    not(target_arch = "arm"),
69842    stable(feature = "neon_intrinsics", since = "1.59.0")
69843)]
69844#[cfg_attr(
69845    target_arch = "arm",
69846    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69847)]
69848pub unsafe fn vst3_u8(a: *mut u8, b: uint8x8x3_t) {
69849    vst3_s8(transmute(a), transmute(b))
69850}
69851#[doc = "Store multiple 3-element structures from three registers"]
69852#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u8)"]
69853#[doc = "## Safety"]
69854#[doc = "  * Neon instrinsic unsafe"]
69855#[inline]
69856#[target_feature(enable = "neon")]
69857#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69858#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69859#[cfg_attr(
69860    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69861    assert_instr(st3)
69862)]
69863#[cfg_attr(
69864    not(target_arch = "arm"),
69865    stable(feature = "neon_intrinsics", since = "1.59.0")
69866)]
69867#[cfg_attr(
69868    target_arch = "arm",
69869    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69870)]
69871pub unsafe fn vst3q_u8(a: *mut u8, b: uint8x16x3_t) {
69872    vst3q_s8(transmute(a), transmute(b))
69873}
69874#[doc = "Store multiple 3-element structures from three registers"]
69875#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u16)"]
69876#[doc = "## Safety"]
69877#[doc = "  * Neon instrinsic unsafe"]
69878#[inline]
69879#[target_feature(enable = "neon")]
69880#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69881#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69882#[cfg_attr(
69883    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69884    assert_instr(st3)
69885)]
69886#[cfg_attr(
69887    not(target_arch = "arm"),
69888    stable(feature = "neon_intrinsics", since = "1.59.0")
69889)]
69890#[cfg_attr(
69891    target_arch = "arm",
69892    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69893)]
69894pub unsafe fn vst3_u16(a: *mut u16, b: uint16x4x3_t) {
69895    vst3_s16(transmute(a), transmute(b))
69896}
69897#[doc = "Store multiple 3-element structures from three registers"]
69898#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u16)"]
69899#[doc = "## Safety"]
69900#[doc = "  * Neon instrinsic unsafe"]
69901#[inline]
69902#[target_feature(enable = "neon")]
69903#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69904#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69905#[cfg_attr(
69906    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69907    assert_instr(st3)
69908)]
69909#[cfg_attr(
69910    not(target_arch = "arm"),
69911    stable(feature = "neon_intrinsics", since = "1.59.0")
69912)]
69913#[cfg_attr(
69914    target_arch = "arm",
69915    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69916)]
69917pub unsafe fn vst3q_u16(a: *mut u16, b: uint16x8x3_t) {
69918    vst3q_s16(transmute(a), transmute(b))
69919}
69920#[doc = "Store multiple 3-element structures from three registers"]
69921#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u32)"]
69922#[doc = "## Safety"]
69923#[doc = "  * Neon instrinsic unsafe"]
69924#[inline]
69925#[target_feature(enable = "neon")]
69926#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69927#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69928#[cfg_attr(
69929    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69930    assert_instr(st3)
69931)]
69932#[cfg_attr(
69933    not(target_arch = "arm"),
69934    stable(feature = "neon_intrinsics", since = "1.59.0")
69935)]
69936#[cfg_attr(
69937    target_arch = "arm",
69938    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69939)]
69940pub unsafe fn vst3_u32(a: *mut u32, b: uint32x2x3_t) {
69941    vst3_s32(transmute(a), transmute(b))
69942}
69943#[doc = "Store multiple 3-element structures from three registers"]
69944#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u32)"]
69945#[doc = "## Safety"]
69946#[doc = "  * Neon instrinsic unsafe"]
69947#[inline]
69948#[target_feature(enable = "neon")]
69949#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69950#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69951#[cfg_attr(
69952    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69953    assert_instr(st3)
69954)]
69955#[cfg_attr(
69956    not(target_arch = "arm"),
69957    stable(feature = "neon_intrinsics", since = "1.59.0")
69958)]
69959#[cfg_attr(
69960    target_arch = "arm",
69961    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69962)]
69963pub unsafe fn vst3q_u32(a: *mut u32, b: uint32x4x3_t) {
69964    vst3q_s32(transmute(a), transmute(b))
69965}
69966#[doc = "Store multiple 3-element structures from three registers"]
69967#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p8)"]
69968#[doc = "## Safety"]
69969#[doc = "  * Neon instrinsic unsafe"]
69970#[inline]
69971#[target_feature(enable = "neon")]
69972#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69973#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69974#[cfg_attr(
69975    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69976    assert_instr(st3)
69977)]
69978#[cfg_attr(
69979    not(target_arch = "arm"),
69980    stable(feature = "neon_intrinsics", since = "1.59.0")
69981)]
69982#[cfg_attr(
69983    target_arch = "arm",
69984    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69985)]
69986pub unsafe fn vst3_p8(a: *mut p8, b: poly8x8x3_t) {
69987    vst3_s8(transmute(a), transmute(b))
69988}
69989#[doc = "Store multiple 3-element structures from three registers"]
69990#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p8)"]
69991#[doc = "## Safety"]
69992#[doc = "  * Neon instrinsic unsafe"]
69993#[inline]
69994#[target_feature(enable = "neon")]
69995#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69996#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69997#[cfg_attr(
69998    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69999    assert_instr(st3)
70000)]
70001#[cfg_attr(
70002    not(target_arch = "arm"),
70003    stable(feature = "neon_intrinsics", since = "1.59.0")
70004)]
70005#[cfg_attr(
70006    target_arch = "arm",
70007    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70008)]
70009pub unsafe fn vst3q_p8(a: *mut p8, b: poly8x16x3_t) {
70010    vst3q_s8(transmute(a), transmute(b))
70011}
70012#[doc = "Store multiple 3-element structures from three registers"]
70013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p16)"]
70014#[doc = "## Safety"]
70015#[doc = "  * Neon instrinsic unsafe"]
70016#[inline]
70017#[target_feature(enable = "neon")]
70018#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70019#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
70020#[cfg_attr(
70021    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70022    assert_instr(st3)
70023)]
70024#[cfg_attr(
70025    not(target_arch = "arm"),
70026    stable(feature = "neon_intrinsics", since = "1.59.0")
70027)]
70028#[cfg_attr(
70029    target_arch = "arm",
70030    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70031)]
70032pub unsafe fn vst3_p16(a: *mut p16, b: poly16x4x3_t) {
70033    vst3_s16(transmute(a), transmute(b))
70034}
70035#[doc = "Store multiple 3-element structures from three registers"]
70036#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p16)"]
70037#[doc = "## Safety"]
70038#[doc = "  * Neon instrinsic unsafe"]
70039#[inline]
70040#[target_feature(enable = "neon")]
70041#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70042#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
70043#[cfg_attr(
70044    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70045    assert_instr(st3)
70046)]
70047#[cfg_attr(
70048    not(target_arch = "arm"),
70049    stable(feature = "neon_intrinsics", since = "1.59.0")
70050)]
70051#[cfg_attr(
70052    target_arch = "arm",
70053    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70054)]
70055pub unsafe fn vst3q_p16(a: *mut p16, b: poly16x8x3_t) {
70056    vst3q_s16(transmute(a), transmute(b))
70057}
70058#[doc = "Store multiple 4-element structures from four registers"]
70059#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"]
70060#[doc = "## Safety"]
70061#[doc = "  * Neon instrinsic unsafe"]
70062#[inline]
70063#[cfg(target_arch = "arm")]
70064#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70065#[target_feature(enable = "neon,fp16")]
70066#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70067#[cfg_attr(test, assert_instr(vst4))]
70068pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) {
70069    unsafe extern "unadjusted" {
70070        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v4f16")]
70071        fn _vst4_f16(
70072            ptr: *mut i8,
70073            a: float16x4_t,
70074            b: float16x4_t,
70075            c: float16x4_t,
70076            d: float16x4_t,
70077            size: i32,
70078        );
70079    }
70080    _vst4_f16(a as _, b.0, b.1, b.2, b.3, 2)
70081}
70082#[doc = "Store multiple 4-element structures from four registers"]
70083#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"]
70084#[doc = "## Safety"]
70085#[doc = "  * Neon instrinsic unsafe"]
70086#[inline]
70087#[cfg(target_arch = "arm")]
70088#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70089#[target_feature(enable = "neon,fp16")]
70090#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70091#[cfg_attr(test, assert_instr(vst4))]
70092pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) {
70093    unsafe extern "unadjusted" {
70094        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v8f16")]
70095        fn _vst4q_f16(
70096            ptr: *mut i8,
70097            a: float16x8_t,
70098            b: float16x8_t,
70099            c: float16x8_t,
70100            d: float16x8_t,
70101            size: i32,
70102        );
70103    }
70104    _vst4q_f16(a as _, b.0, b.1, b.2, b.3, 2)
70105}
70106#[doc = "Store multiple 4-element structures from four registers"]
70107#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"]
70108#[doc = "## Safety"]
70109#[doc = "  * Neon instrinsic unsafe"]
70110#[inline]
70111#[cfg(not(target_arch = "arm"))]
70112#[target_feature(enable = "neon,fp16")]
70113#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70114#[cfg_attr(test, assert_instr(st4))]
70115pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) {
70116    unsafe extern "unadjusted" {
70117        #[cfg_attr(
70118            any(target_arch = "aarch64", target_arch = "arm64ec"),
70119            link_name = "llvm.aarch64.neon.st4.v4f16.p0"
70120        )]
70121        fn _vst4_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t, d: float16x4_t, ptr: *mut i8);
70122    }
70123    _vst4_f16(b.0, b.1, b.2, b.3, a as _)
70124}
70125#[doc = "Store multiple 4-element structures from four registers"]
70126#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"]
70127#[doc = "## Safety"]
70128#[doc = "  * Neon instrinsic unsafe"]
70129#[inline]
70130#[cfg(not(target_arch = "arm"))]
70131#[target_feature(enable = "neon,fp16")]
70132#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70133#[cfg_attr(test, assert_instr(st4))]
70134pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) {
70135    unsafe extern "unadjusted" {
70136        #[cfg_attr(
70137            any(target_arch = "aarch64", target_arch = "arm64ec"),
70138            link_name = "llvm.aarch64.neon.st4.v8f16.p0"
70139        )]
70140        fn _vst4q_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t, d: float16x8_t, ptr: *mut i8);
70141    }
70142    _vst4q_f16(b.0, b.1, b.2, b.3, a as _)
70143}
70144#[doc = "Store multiple 4-element structures from four registers"]
70145#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"]
70146#[doc = "## Safety"]
70147#[doc = "  * Neon instrinsic unsafe"]
70148#[inline]
70149#[cfg(target_arch = "arm")]
70150#[target_feature(enable = "neon,v7")]
70151#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70152#[cfg_attr(test, assert_instr(vst4))]
70153pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) {
70154    unsafe extern "unadjusted" {
70155        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v2f32")]
70156        fn _vst4_f32(
70157            ptr: *mut i8,
70158            a: float32x2_t,
70159            b: float32x2_t,
70160            c: float32x2_t,
70161            d: float32x2_t,
70162            size: i32,
70163        );
70164    }
70165    _vst4_f32(a as _, b.0, b.1, b.2, b.3, 4)
70166}
70167#[doc = "Store multiple 4-element structures from four registers"]
70168#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"]
70169#[doc = "## Safety"]
70170#[doc = "  * Neon instrinsic unsafe"]
70171#[inline]
70172#[cfg(target_arch = "arm")]
70173#[target_feature(enable = "neon,v7")]
70174#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70175#[cfg_attr(test, assert_instr(vst4))]
70176pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) {
70177    unsafe extern "unadjusted" {
70178        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v4f32")]
70179        fn _vst4q_f32(
70180            ptr: *mut i8,
70181            a: float32x4_t,
70182            b: float32x4_t,
70183            c: float32x4_t,
70184            d: float32x4_t,
70185            size: i32,
70186        );
70187    }
70188    _vst4q_f32(a as _, b.0, b.1, b.2, b.3, 4)
70189}
70190#[doc = "Store multiple 4-element structures from four registers"]
70191#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"]
70192#[doc = "## Safety"]
70193#[doc = "  * Neon instrinsic unsafe"]
70194#[inline]
70195#[cfg(target_arch = "arm")]
70196#[target_feature(enable = "neon,v7")]
70197#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70198#[cfg_attr(test, assert_instr(vst4))]
70199pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) {
70200    unsafe extern "unadjusted" {
70201        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v8i8")]
70202        fn _vst4_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, size: i32);
70203    }
70204    _vst4_s8(a as _, b.0, b.1, b.2, b.3, 1)
70205}
70206#[doc = "Store multiple 4-element structures from four registers"]
70207#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"]
70208#[doc = "## Safety"]
70209#[doc = "  * Neon instrinsic unsafe"]
70210#[inline]
70211#[cfg(target_arch = "arm")]
70212#[target_feature(enable = "neon,v7")]
70213#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70214#[cfg_attr(test, assert_instr(vst4))]
70215pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) {
70216    unsafe extern "unadjusted" {
70217        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v16i8")]
70218        fn _vst4q_s8(
70219            ptr: *mut i8,
70220            a: int8x16_t,
70221            b: int8x16_t,
70222            c: int8x16_t,
70223            d: int8x16_t,
70224            size: i32,
70225        );
70226    }
70227    _vst4q_s8(a as _, b.0, b.1, b.2, b.3, 1)
70228}
70229#[doc = "Store multiple 4-element structures from four registers"]
70230#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"]
70231#[doc = "## Safety"]
70232#[doc = "  * Neon instrinsic unsafe"]
70233#[inline]
70234#[cfg(target_arch = "arm")]
70235#[target_feature(enable = "neon,v7")]
70236#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70237#[cfg_attr(test, assert_instr(vst4))]
70238pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) {
70239    unsafe extern "unadjusted" {
70240        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v4i16")]
70241        fn _vst4_s16(
70242            ptr: *mut i8,
70243            a: int16x4_t,
70244            b: int16x4_t,
70245            c: int16x4_t,
70246            d: int16x4_t,
70247            size: i32,
70248        );
70249    }
70250    _vst4_s16(a as _, b.0, b.1, b.2, b.3, 2)
70251}
70252#[doc = "Store multiple 4-element structures from four registers"]
70253#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"]
70254#[doc = "## Safety"]
70255#[doc = "  * Neon instrinsic unsafe"]
70256#[inline]
70257#[cfg(target_arch = "arm")]
70258#[target_feature(enable = "neon,v7")]
70259#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70260#[cfg_attr(test, assert_instr(vst4))]
70261pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) {
70262    unsafe extern "unadjusted" {
70263        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v8i16")]
70264        fn _vst4q_s16(
70265            ptr: *mut i8,
70266            a: int16x8_t,
70267            b: int16x8_t,
70268            c: int16x8_t,
70269            d: int16x8_t,
70270            size: i32,
70271        );
70272    }
70273    _vst4q_s16(a as _, b.0, b.1, b.2, b.3, 2)
70274}
70275#[doc = "Store multiple 4-element structures from four registers"]
70276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"]
70277#[doc = "## Safety"]
70278#[doc = "  * Neon instrinsic unsafe"]
70279#[inline]
70280#[cfg(target_arch = "arm")]
70281#[target_feature(enable = "neon,v7")]
70282#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70283#[cfg_attr(test, assert_instr(vst4))]
70284pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) {
70285    unsafe extern "unadjusted" {
70286        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v2i32")]
70287        fn _vst4_s32(
70288            ptr: *mut i8,
70289            a: int32x2_t,
70290            b: int32x2_t,
70291            c: int32x2_t,
70292            d: int32x2_t,
70293            size: i32,
70294        );
70295    }
70296    _vst4_s32(a as _, b.0, b.1, b.2, b.3, 4)
70297}
70298#[doc = "Store multiple 4-element structures from four registers"]
70299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"]
70300#[doc = "## Safety"]
70301#[doc = "  * Neon instrinsic unsafe"]
70302#[inline]
70303#[cfg(target_arch = "arm")]
70304#[target_feature(enable = "neon,v7")]
70305#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70306#[cfg_attr(test, assert_instr(vst4))]
70307pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) {
70308    unsafe extern "unadjusted" {
70309        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v4i32")]
70310        fn _vst4q_s32(
70311            ptr: *mut i8,
70312            a: int32x4_t,
70313            b: int32x4_t,
70314            c: int32x4_t,
70315            d: int32x4_t,
70316            size: i32,
70317        );
70318    }
70319    _vst4q_s32(a as _, b.0, b.1, b.2, b.3, 4)
70320}
70321#[doc = "Store multiple 4-element structures from four registers"]
70322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"]
70323#[doc = "## Safety"]
70324#[doc = "  * Neon instrinsic unsafe"]
70325#[inline]
70326#[target_feature(enable = "neon")]
70327#[cfg(not(target_arch = "arm"))]
70328#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70329#[cfg_attr(test, assert_instr(st4))]
70330pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) {
70331    unsafe extern "unadjusted" {
70332        #[cfg_attr(
70333            any(target_arch = "aarch64", target_arch = "arm64ec"),
70334            link_name = "llvm.aarch64.neon.st4.v2f32.p0"
70335        )]
70336        fn _vst4_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, d: float32x2_t, ptr: *mut i8);
70337    }
70338    _vst4_f32(b.0, b.1, b.2, b.3, a as _)
70339}
70340#[doc = "Store multiple 4-element structures from four registers"]
70341#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"]
70342#[doc = "## Safety"]
70343#[doc = "  * Neon instrinsic unsafe"]
70344#[inline]
70345#[target_feature(enable = "neon")]
70346#[cfg(not(target_arch = "arm"))]
70347#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70348#[cfg_attr(test, assert_instr(st4))]
70349pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) {
70350    unsafe extern "unadjusted" {
70351        #[cfg_attr(
70352            any(target_arch = "aarch64", target_arch = "arm64ec"),
70353            link_name = "llvm.aarch64.neon.st4.v4f32.p0"
70354        )]
70355        fn _vst4q_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, d: float32x4_t, ptr: *mut i8);
70356    }
70357    _vst4q_f32(b.0, b.1, b.2, b.3, a as _)
70358}
70359#[doc = "Store multiple 4-element structures from four registers"]
70360#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"]
70361#[doc = "## Safety"]
70362#[doc = "  * Neon instrinsic unsafe"]
70363#[inline]
70364#[target_feature(enable = "neon")]
70365#[cfg(not(target_arch = "arm"))]
70366#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70367#[cfg_attr(test, assert_instr(st4))]
70368pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) {
70369    unsafe extern "unadjusted" {
70370        #[cfg_attr(
70371            any(target_arch = "aarch64", target_arch = "arm64ec"),
70372            link_name = "llvm.aarch64.neon.st4.v8i8.p0"
70373        )]
70374        fn _vst4_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, ptr: *mut i8);
70375    }
70376    _vst4_s8(b.0, b.1, b.2, b.3, a as _)
70377}
70378#[doc = "Store multiple 4-element structures from four registers"]
70379#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"]
70380#[doc = "## Safety"]
70381#[doc = "  * Neon instrinsic unsafe"]
70382#[inline]
70383#[target_feature(enable = "neon")]
70384#[cfg(not(target_arch = "arm"))]
70385#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70386#[cfg_attr(test, assert_instr(st4))]
70387pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) {
70388    unsafe extern "unadjusted" {
70389        #[cfg_attr(
70390            any(target_arch = "aarch64", target_arch = "arm64ec"),
70391            link_name = "llvm.aarch64.neon.st4.v16i8.p0"
70392        )]
70393        fn _vst4q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, ptr: *mut i8);
70394    }
70395    _vst4q_s8(b.0, b.1, b.2, b.3, a as _)
70396}
70397#[doc = "Store multiple 4-element structures from four registers"]
70398#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"]
70399#[doc = "## Safety"]
70400#[doc = "  * Neon instrinsic unsafe"]
70401#[inline]
70402#[target_feature(enable = "neon")]
70403#[cfg(not(target_arch = "arm"))]
70404#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70405#[cfg_attr(test, assert_instr(st4))]
70406pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) {
70407    unsafe extern "unadjusted" {
70408        #[cfg_attr(
70409            any(target_arch = "aarch64", target_arch = "arm64ec"),
70410            link_name = "llvm.aarch64.neon.st4.v4i16.p0"
70411        )]
70412        fn _vst4_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t, ptr: *mut i8);
70413    }
70414    _vst4_s16(b.0, b.1, b.2, b.3, a as _)
70415}
70416#[doc = "Store multiple 4-element structures from four registers"]
70417#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"]
70418#[doc = "## Safety"]
70419#[doc = "  * Neon instrinsic unsafe"]
70420#[inline]
70421#[target_feature(enable = "neon")]
70422#[cfg(not(target_arch = "arm"))]
70423#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70424#[cfg_attr(test, assert_instr(st4))]
70425pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) {
70426    unsafe extern "unadjusted" {
70427        #[cfg_attr(
70428            any(target_arch = "aarch64", target_arch = "arm64ec"),
70429            link_name = "llvm.aarch64.neon.st4.v8i16.p0"
70430        )]
70431        fn _vst4q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t, ptr: *mut i8);
70432    }
70433    _vst4q_s16(b.0, b.1, b.2, b.3, a as _)
70434}
70435#[doc = "Store multiple 4-element structures from four registers"]
70436#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"]
70437#[doc = "## Safety"]
70438#[doc = "  * Neon instrinsic unsafe"]
70439#[inline]
70440#[target_feature(enable = "neon")]
70441#[cfg(not(target_arch = "arm"))]
70442#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70443#[cfg_attr(test, assert_instr(st4))]
70444pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) {
70445    unsafe extern "unadjusted" {
70446        #[cfg_attr(
70447            any(target_arch = "aarch64", target_arch = "arm64ec"),
70448            link_name = "llvm.aarch64.neon.st4.v2i32.p0"
70449        )]
70450        fn _vst4_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t, ptr: *mut i8);
70451    }
70452    _vst4_s32(b.0, b.1, b.2, b.3, a as _)
70453}
70454#[doc = "Store multiple 4-element structures from four registers"]
70455#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"]
70456#[doc = "## Safety"]
70457#[doc = "  * Neon instrinsic unsafe"]
70458#[inline]
70459#[target_feature(enable = "neon")]
70460#[cfg(not(target_arch = "arm"))]
70461#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70462#[cfg_attr(test, assert_instr(st4))]
70463pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) {
70464    unsafe extern "unadjusted" {
70465        #[cfg_attr(
70466            any(target_arch = "aarch64", target_arch = "arm64ec"),
70467            link_name = "llvm.aarch64.neon.st4.v4i32.p0"
70468        )]
70469        fn _vst4q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t, ptr: *mut i8);
70470    }
70471    _vst4q_s32(b.0, b.1, b.2, b.3, a as _)
70472}
70473#[doc = "Store multiple 4-element structures from four registers"]
70474#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"]
70475#[doc = "## Safety"]
70476#[doc = "  * Neon instrinsic unsafe"]
70477#[inline]
70478#[cfg(target_arch = "arm")]
70479#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70480#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70481#[rustc_legacy_const_generics(2)]
70482#[target_feature(enable = "neon,fp16")]
70483#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70484pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
70485    static_assert_uimm_bits!(LANE, 2);
70486    unsafe extern "unadjusted" {
70487        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v4f16")]
70488        fn _vst4_lane_f16(
70489            ptr: *mut i8,
70490            a: float16x4_t,
70491            b: float16x4_t,
70492            c: float16x4_t,
70493            d: float16x4_t,
70494            n: i32,
70495            size: i32,
70496        );
70497    }
70498    _vst4_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
70499}
70500#[doc = "Store multiple 4-element structures from four registers"]
70501#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"]
70502#[doc = "## Safety"]
70503#[doc = "  * Neon instrinsic unsafe"]
70504#[inline]
70505#[cfg(target_arch = "arm")]
70506#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70507#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70508#[rustc_legacy_const_generics(2)]
70509#[target_feature(enable = "neon,fp16")]
70510#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70511pub unsafe fn vst4q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x4_t) {
70512    static_assert_uimm_bits!(LANE, 3);
70513    unsafe extern "unadjusted" {
70514        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v8f16")]
70515        fn _vst4q_lane_f16(
70516            ptr: *mut i8,
70517            a: float16x8_t,
70518            b: float16x8_t,
70519            c: float16x8_t,
70520            d: float16x8_t,
70521            n: i32,
70522            size: i32,
70523        );
70524    }
70525    _vst4q_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
70526}
70527#[doc = "Store multiple 4-element structures from four registers"]
70528#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"]
70529#[doc = "## Safety"]
70530#[doc = "  * Neon instrinsic unsafe"]
70531#[inline]
70532#[cfg(not(target_arch = "arm"))]
70533#[rustc_legacy_const_generics(2)]
70534#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70535#[target_feature(enable = "neon,fp16")]
70536#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70537pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
70538    static_assert_uimm_bits!(LANE, 2);
70539    unsafe extern "unadjusted" {
70540        #[cfg_attr(
70541            any(target_arch = "aarch64", target_arch = "arm64ec"),
70542            link_name = "llvm.aarch64.neon.st4lane.v4f16.p0"
70543        )]
70544        fn _vst4_lane_f16(
70545            a: float16x4_t,
70546            b: float16x4_t,
70547            c: float16x4_t,
70548            d: float16x4_t,
70549            n: i64,
70550            ptr: *mut i8,
70551        );
70552    }
70553    _vst4_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70554}
70555#[doc = "Store multiple 4-element structures from four registers"]
70556#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"]
70557#[doc = "## Safety"]
70558#[doc = "  * Neon instrinsic unsafe"]
70559#[inline]
70560#[cfg(not(target_arch = "arm"))]
70561#[rustc_legacy_const_generics(2)]
70562#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70563#[target_feature(enable = "neon,fp16")]
70564#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70565pub unsafe fn vst4q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x4_t) {
70566    static_assert_uimm_bits!(LANE, 3);
70567    unsafe extern "unadjusted" {
70568        #[cfg_attr(
70569            any(target_arch = "aarch64", target_arch = "arm64ec"),
70570            link_name = "llvm.aarch64.neon.st4lane.v8f16.p0"
70571        )]
70572        fn _vst4q_lane_f16(
70573            a: float16x8_t,
70574            b: float16x8_t,
70575            c: float16x8_t,
70576            d: float16x8_t,
70577            n: i64,
70578            ptr: *mut i8,
70579        );
70580    }
70581    _vst4q_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70582}
70583#[doc = "Store multiple 4-element structures from four registers"]
70584#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"]
70585#[doc = "## Safety"]
70586#[doc = "  * Neon instrinsic unsafe"]
70587#[inline]
70588#[cfg(target_arch = "arm")]
70589#[target_feature(enable = "neon,v7")]
70590#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70591#[rustc_legacy_const_generics(2)]
70592#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70593pub unsafe fn vst4_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x4_t) {
70594    static_assert_uimm_bits!(LANE, 1);
70595    unsafe extern "unadjusted" {
70596        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v2f32")]
70597        fn _vst4_lane_f32(
70598            ptr: *mut i8,
70599            a: float32x2_t,
70600            b: float32x2_t,
70601            c: float32x2_t,
70602            d: float32x2_t,
70603            n: i32,
70604            size: i32,
70605        );
70606    }
70607    _vst4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
70608}
70609#[doc = "Store multiple 4-element structures from four registers"]
70610#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"]
70611#[doc = "## Safety"]
70612#[doc = "  * Neon instrinsic unsafe"]
70613#[inline]
70614#[cfg(target_arch = "arm")]
70615#[target_feature(enable = "neon,v7")]
70616#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70617#[rustc_legacy_const_generics(2)]
70618#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70619pub unsafe fn vst4q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x4_t) {
70620    static_assert_uimm_bits!(LANE, 2);
70621    unsafe extern "unadjusted" {
70622        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v4f32")]
70623        fn _vst4q_lane_f32(
70624            ptr: *mut i8,
70625            a: float32x4_t,
70626            b: float32x4_t,
70627            c: float32x4_t,
70628            d: float32x4_t,
70629            n: i32,
70630            size: i32,
70631        );
70632    }
70633    _vst4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
70634}
70635#[doc = "Store multiple 4-element structures from four registers"]
70636#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"]
70637#[doc = "## Safety"]
70638#[doc = "  * Neon instrinsic unsafe"]
70639#[inline]
70640#[cfg(target_arch = "arm")]
70641#[target_feature(enable = "neon,v7")]
70642#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70643#[rustc_legacy_const_generics(2)]
70644#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70645pub unsafe fn vst4_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x4_t) {
70646    static_assert_uimm_bits!(LANE, 3);
70647    unsafe extern "unadjusted" {
70648        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v8i8")]
70649        fn _vst4_lane_s8(
70650            ptr: *mut i8,
70651            a: int8x8_t,
70652            b: int8x8_t,
70653            c: int8x8_t,
70654            d: int8x8_t,
70655            n: i32,
70656            size: i32,
70657        );
70658    }
70659    _vst4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1)
70660}
70661#[doc = "Store multiple 4-element structures from four registers"]
70662#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"]
70663#[doc = "## Safety"]
70664#[doc = "  * Neon instrinsic unsafe"]
70665#[inline]
70666#[cfg(target_arch = "arm")]
70667#[target_feature(enable = "neon,v7")]
70668#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70669#[rustc_legacy_const_generics(2)]
70670#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70671pub unsafe fn vst4_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x4_t) {
70672    static_assert_uimm_bits!(LANE, 2);
70673    unsafe extern "unadjusted" {
70674        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v4i16")]
70675        fn _vst4_lane_s16(
70676            ptr: *mut i8,
70677            a: int16x4_t,
70678            b: int16x4_t,
70679            c: int16x4_t,
70680            d: int16x4_t,
70681            n: i32,
70682            size: i32,
70683        );
70684    }
70685    _vst4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
70686}
70687#[doc = "Store multiple 4-element structures from four registers"]
70688#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"]
70689#[doc = "## Safety"]
70690#[doc = "  * Neon instrinsic unsafe"]
70691#[inline]
70692#[cfg(target_arch = "arm")]
70693#[target_feature(enable = "neon,v7")]
70694#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70695#[rustc_legacy_const_generics(2)]
70696#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70697pub unsafe fn vst4q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x4_t) {
70698    static_assert_uimm_bits!(LANE, 3);
70699    unsafe extern "unadjusted" {
70700        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v8i16")]
70701        fn _vst4q_lane_s16(
70702            ptr: *mut i8,
70703            a: int16x8_t,
70704            b: int16x8_t,
70705            c: int16x8_t,
70706            d: int16x8_t,
70707            n: i32,
70708            size: i32,
70709        );
70710    }
70711    _vst4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
70712}
70713#[doc = "Store multiple 4-element structures from four registers"]
70714#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"]
70715#[doc = "## Safety"]
70716#[doc = "  * Neon instrinsic unsafe"]
70717#[inline]
70718#[cfg(target_arch = "arm")]
70719#[target_feature(enable = "neon,v7")]
70720#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70721#[rustc_legacy_const_generics(2)]
70722#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70723pub unsafe fn vst4_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x4_t) {
70724    static_assert_uimm_bits!(LANE, 1);
70725    unsafe extern "unadjusted" {
70726        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v2i32")]
70727        fn _vst4_lane_s32(
70728            ptr: *mut i8,
70729            a: int32x2_t,
70730            b: int32x2_t,
70731            c: int32x2_t,
70732            d: int32x2_t,
70733            n: i32,
70734            size: i32,
70735        );
70736    }
70737    _vst4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
70738}
70739#[doc = "Store multiple 4-element structures from four registers"]
70740#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"]
70741#[doc = "## Safety"]
70742#[doc = "  * Neon instrinsic unsafe"]
70743#[inline]
70744#[cfg(target_arch = "arm")]
70745#[target_feature(enable = "neon,v7")]
70746#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70747#[rustc_legacy_const_generics(2)]
70748#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70749pub unsafe fn vst4q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x4_t) {
70750    static_assert_uimm_bits!(LANE, 2);
70751    unsafe extern "unadjusted" {
70752        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v4i32")]
70753        fn _vst4q_lane_s32(
70754            ptr: *mut i8,
70755            a: int32x4_t,
70756            b: int32x4_t,
70757            c: int32x4_t,
70758            d: int32x4_t,
70759            n: i32,
70760            size: i32,
70761        );
70762    }
70763    _vst4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
70764}
70765#[doc = "Store multiple 4-element structures from four registers"]
70766#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"]
70767#[doc = "## Safety"]
70768#[doc = "  * Neon instrinsic unsafe"]
70769#[inline]
70770#[target_feature(enable = "neon")]
70771#[cfg(not(target_arch = "arm"))]
70772#[rustc_legacy_const_generics(2)]
70773#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70774#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70775pub unsafe fn vst4_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x4_t) {
70776    static_assert_uimm_bits!(LANE, 1);
70777    unsafe extern "unadjusted" {
70778        #[cfg_attr(
70779            any(target_arch = "aarch64", target_arch = "arm64ec"),
70780            link_name = "llvm.aarch64.neon.st4lane.v2f32.p0"
70781        )]
70782        fn _vst4_lane_f32(
70783            a: float32x2_t,
70784            b: float32x2_t,
70785            c: float32x2_t,
70786            d: float32x2_t,
70787            n: i64,
70788            ptr: *mut i8,
70789        );
70790    }
70791    _vst4_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70792}
70793#[doc = "Store multiple 4-element structures from four registers"]
70794#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"]
70795#[doc = "## Safety"]
70796#[doc = "  * Neon instrinsic unsafe"]
70797#[inline]
70798#[target_feature(enable = "neon")]
70799#[cfg(not(target_arch = "arm"))]
70800#[rustc_legacy_const_generics(2)]
70801#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70802#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70803pub unsafe fn vst4q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x4_t) {
70804    static_assert_uimm_bits!(LANE, 2);
70805    unsafe extern "unadjusted" {
70806        #[cfg_attr(
70807            any(target_arch = "aarch64", target_arch = "arm64ec"),
70808            link_name = "llvm.aarch64.neon.st4lane.v4f32.p0"
70809        )]
70810        fn _vst4q_lane_f32(
70811            a: float32x4_t,
70812            b: float32x4_t,
70813            c: float32x4_t,
70814            d: float32x4_t,
70815            n: i64,
70816            ptr: *mut i8,
70817        );
70818    }
70819    _vst4q_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70820}
70821#[doc = "Store multiple 4-element structures from four registers"]
70822#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"]
70823#[doc = "## Safety"]
70824#[doc = "  * Neon instrinsic unsafe"]
70825#[inline]
70826#[target_feature(enable = "neon")]
70827#[cfg(not(target_arch = "arm"))]
70828#[rustc_legacy_const_generics(2)]
70829#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70830#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70831pub unsafe fn vst4_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x4_t) {
70832    static_assert_uimm_bits!(LANE, 3);
70833    unsafe extern "unadjusted" {
70834        #[cfg_attr(
70835            any(target_arch = "aarch64", target_arch = "arm64ec"),
70836            link_name = "llvm.aarch64.neon.st4lane.v8i8.p0"
70837        )]
70838        fn _vst4_lane_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, n: i64, ptr: *mut i8);
70839    }
70840    _vst4_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70841}
70842#[doc = "Store multiple 4-element structures from four registers"]
70843#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"]
70844#[doc = "## Safety"]
70845#[doc = "  * Neon instrinsic unsafe"]
70846#[inline]
70847#[target_feature(enable = "neon")]
70848#[cfg(not(target_arch = "arm"))]
70849#[rustc_legacy_const_generics(2)]
70850#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70851#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70852pub unsafe fn vst4_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x4_t) {
70853    static_assert_uimm_bits!(LANE, 2);
70854    unsafe extern "unadjusted" {
70855        #[cfg_attr(
70856            any(target_arch = "aarch64", target_arch = "arm64ec"),
70857            link_name = "llvm.aarch64.neon.st4lane.v4i16.p0"
70858        )]
70859        fn _vst4_lane_s16(
70860            a: int16x4_t,
70861            b: int16x4_t,
70862            c: int16x4_t,
70863            d: int16x4_t,
70864            n: i64,
70865            ptr: *mut i8,
70866        );
70867    }
70868    _vst4_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70869}
70870#[doc = "Store multiple 4-element structures from four registers"]
70871#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"]
70872#[doc = "## Safety"]
70873#[doc = "  * Neon instrinsic unsafe"]
70874#[inline]
70875#[target_feature(enable = "neon")]
70876#[cfg(not(target_arch = "arm"))]
70877#[rustc_legacy_const_generics(2)]
70878#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70879#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70880pub unsafe fn vst4q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x4_t) {
70881    static_assert_uimm_bits!(LANE, 3);
70882    unsafe extern "unadjusted" {
70883        #[cfg_attr(
70884            any(target_arch = "aarch64", target_arch = "arm64ec"),
70885            link_name = "llvm.aarch64.neon.st4lane.v8i16.p0"
70886        )]
70887        fn _vst4q_lane_s16(
70888            a: int16x8_t,
70889            b: int16x8_t,
70890            c: int16x8_t,
70891            d: int16x8_t,
70892            n: i64,
70893            ptr: *mut i8,
70894        );
70895    }
70896    _vst4q_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70897}
70898#[doc = "Store multiple 4-element structures from four registers"]
70899#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"]
70900#[doc = "## Safety"]
70901#[doc = "  * Neon instrinsic unsafe"]
70902#[inline]
70903#[target_feature(enable = "neon")]
70904#[cfg(not(target_arch = "arm"))]
70905#[rustc_legacy_const_generics(2)]
70906#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70907#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70908pub unsafe fn vst4_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x4_t) {
70909    static_assert_uimm_bits!(LANE, 1);
70910    unsafe extern "unadjusted" {
70911        #[cfg_attr(
70912            any(target_arch = "aarch64", target_arch = "arm64ec"),
70913            link_name = "llvm.aarch64.neon.st4lane.v2i32.p0"
70914        )]
70915        fn _vst4_lane_s32(
70916            a: int32x2_t,
70917            b: int32x2_t,
70918            c: int32x2_t,
70919            d: int32x2_t,
70920            n: i64,
70921            ptr: *mut i8,
70922        );
70923    }
70924    _vst4_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70925}
70926#[doc = "Store multiple 4-element structures from four registers"]
70927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"]
70928#[doc = "## Safety"]
70929#[doc = "  * Neon instrinsic unsafe"]
70930#[inline]
70931#[target_feature(enable = "neon")]
70932#[cfg(not(target_arch = "arm"))]
70933#[rustc_legacy_const_generics(2)]
70934#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70935#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70936pub unsafe fn vst4q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x4_t) {
70937    static_assert_uimm_bits!(LANE, 2);
70938    unsafe extern "unadjusted" {
70939        #[cfg_attr(
70940            any(target_arch = "aarch64", target_arch = "arm64ec"),
70941            link_name = "llvm.aarch64.neon.st4lane.v4i32.p0"
70942        )]
70943        fn _vst4q_lane_s32(
70944            a: int32x4_t,
70945            b: int32x4_t,
70946            c: int32x4_t,
70947            d: int32x4_t,
70948            n: i64,
70949            ptr: *mut i8,
70950        );
70951    }
70952    _vst4q_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70953}
70954#[doc = "Store multiple 4-element structures from four registers"]
70955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u8)"]
70956#[doc = "## Safety"]
70957#[doc = "  * Neon instrinsic unsafe"]
70958#[inline]
70959#[target_feature(enable = "neon")]
70960#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70961#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
70962#[cfg_attr(
70963    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70964    assert_instr(st4, LANE = 0)
70965)]
70966#[rustc_legacy_const_generics(2)]
70967#[cfg_attr(
70968    not(target_arch = "arm"),
70969    stable(feature = "neon_intrinsics", since = "1.59.0")
70970)]
70971#[cfg_attr(
70972    target_arch = "arm",
70973    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70974)]
70975pub unsafe fn vst4_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x4_t) {
70976    static_assert_uimm_bits!(LANE, 3);
70977    vst4_lane_s8::<LANE>(transmute(a), transmute(b))
70978}
70979#[doc = "Store multiple 4-element structures from four registers"]
70980#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u16)"]
70981#[doc = "## Safety"]
70982#[doc = "  * Neon instrinsic unsafe"]
70983#[inline]
70984#[target_feature(enable = "neon")]
70985#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70986#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
70987#[cfg_attr(
70988    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70989    assert_instr(st4, LANE = 0)
70990)]
70991#[rustc_legacy_const_generics(2)]
70992#[cfg_attr(
70993    not(target_arch = "arm"),
70994    stable(feature = "neon_intrinsics", since = "1.59.0")
70995)]
70996#[cfg_attr(
70997    target_arch = "arm",
70998    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70999)]
71000pub unsafe fn vst4_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x4_t) {
71001    static_assert_uimm_bits!(LANE, 2);
71002    vst4_lane_s16::<LANE>(transmute(a), transmute(b))
71003}
71004#[doc = "Store multiple 4-element structures from four registers"]
71005#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u16)"]
71006#[doc = "## Safety"]
71007#[doc = "  * Neon instrinsic unsafe"]
71008#[inline]
71009#[target_feature(enable = "neon")]
71010#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71011#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
71012#[cfg_attr(
71013    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71014    assert_instr(st4, LANE = 0)
71015)]
71016#[rustc_legacy_const_generics(2)]
71017#[cfg_attr(
71018    not(target_arch = "arm"),
71019    stable(feature = "neon_intrinsics", since = "1.59.0")
71020)]
71021#[cfg_attr(
71022    target_arch = "arm",
71023    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71024)]
71025pub unsafe fn vst4q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x4_t) {
71026    static_assert_uimm_bits!(LANE, 3);
71027    vst4q_lane_s16::<LANE>(transmute(a), transmute(b))
71028}
71029#[doc = "Store multiple 4-element structures from four registers"]
71030#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u32)"]
71031#[doc = "## Safety"]
71032#[doc = "  * Neon instrinsic unsafe"]
71033#[inline]
71034#[target_feature(enable = "neon")]
71035#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71036#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
71037#[cfg_attr(
71038    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71039    assert_instr(st4, LANE = 0)
71040)]
71041#[rustc_legacy_const_generics(2)]
71042#[cfg_attr(
71043    not(target_arch = "arm"),
71044    stable(feature = "neon_intrinsics", since = "1.59.0")
71045)]
71046#[cfg_attr(
71047    target_arch = "arm",
71048    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71049)]
71050pub unsafe fn vst4_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x4_t) {
71051    static_assert_uimm_bits!(LANE, 1);
71052    vst4_lane_s32::<LANE>(transmute(a), transmute(b))
71053}
71054#[doc = "Store multiple 4-element structures from four registers"]
71055#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u32)"]
71056#[doc = "## Safety"]
71057#[doc = "  * Neon instrinsic unsafe"]
71058#[inline]
71059#[target_feature(enable = "neon")]
71060#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71061#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
71062#[cfg_attr(
71063    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71064    assert_instr(st4, LANE = 0)
71065)]
71066#[rustc_legacy_const_generics(2)]
71067#[cfg_attr(
71068    not(target_arch = "arm"),
71069    stable(feature = "neon_intrinsics", since = "1.59.0")
71070)]
71071#[cfg_attr(
71072    target_arch = "arm",
71073    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71074)]
71075pub unsafe fn vst4q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x4_t) {
71076    static_assert_uimm_bits!(LANE, 2);
71077    vst4q_lane_s32::<LANE>(transmute(a), transmute(b))
71078}
71079#[doc = "Store multiple 4-element structures from four registers"]
71080#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p8)"]
71081#[doc = "## Safety"]
71082#[doc = "  * Neon instrinsic unsafe"]
71083#[inline]
71084#[target_feature(enable = "neon")]
71085#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71086#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
71087#[cfg_attr(
71088    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71089    assert_instr(st4, LANE = 0)
71090)]
71091#[rustc_legacy_const_generics(2)]
71092#[cfg_attr(
71093    not(target_arch = "arm"),
71094    stable(feature = "neon_intrinsics", since = "1.59.0")
71095)]
71096#[cfg_attr(
71097    target_arch = "arm",
71098    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71099)]
71100pub unsafe fn vst4_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x4_t) {
71101    static_assert_uimm_bits!(LANE, 3);
71102    vst4_lane_s8::<LANE>(transmute(a), transmute(b))
71103}
71104#[doc = "Store multiple 4-element structures from four registers"]
71105#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p16)"]
71106#[doc = "## Safety"]
71107#[doc = "  * Neon instrinsic unsafe"]
71108#[inline]
71109#[target_feature(enable = "neon")]
71110#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71111#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
71112#[cfg_attr(
71113    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71114    assert_instr(st4, LANE = 0)
71115)]
71116#[rustc_legacy_const_generics(2)]
71117#[cfg_attr(
71118    not(target_arch = "arm"),
71119    stable(feature = "neon_intrinsics", since = "1.59.0")
71120)]
71121#[cfg_attr(
71122    target_arch = "arm",
71123    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71124)]
71125pub unsafe fn vst4_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x4_t) {
71126    static_assert_uimm_bits!(LANE, 2);
71127    vst4_lane_s16::<LANE>(transmute(a), transmute(b))
71128}
71129#[doc = "Store multiple 4-element structures from four registers"]
71130#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p16)"]
71131#[doc = "## Safety"]
71132#[doc = "  * Neon instrinsic unsafe"]
71133#[inline]
71134#[target_feature(enable = "neon")]
71135#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71136#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
71137#[cfg_attr(
71138    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71139    assert_instr(st4, LANE = 0)
71140)]
71141#[rustc_legacy_const_generics(2)]
71142#[cfg_attr(
71143    not(target_arch = "arm"),
71144    stable(feature = "neon_intrinsics", since = "1.59.0")
71145)]
71146#[cfg_attr(
71147    target_arch = "arm",
71148    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71149)]
71150pub unsafe fn vst4q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x4_t) {
71151    static_assert_uimm_bits!(LANE, 3);
71152    vst4q_lane_s16::<LANE>(transmute(a), transmute(b))
71153}
71154#[doc = "Store multiple 4-element structures from four registers"]
71155#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p64)"]
71156#[doc = "## Safety"]
71157#[doc = "  * Neon instrinsic unsafe"]
71158#[inline]
71159#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
71160#[target_feature(enable = "neon,aes")]
71161#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
71162#[cfg_attr(
71163    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71164    assert_instr(nop)
71165)]
71166#[cfg_attr(
71167    not(target_arch = "arm"),
71168    stable(feature = "neon_intrinsics", since = "1.59.0")
71169)]
71170#[cfg_attr(
71171    target_arch = "arm",
71172    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71173)]
71174pub unsafe fn vst4_p64(a: *mut p64, b: poly64x1x4_t) {
71175    vst4_s64(transmute(a), transmute(b))
71176}
71177#[doc = "Store multiple 4-element structures from four registers"]
71178#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"]
71179#[doc = "## Safety"]
71180#[doc = "  * Neon instrinsic unsafe"]
71181#[inline]
71182#[cfg(target_arch = "arm")]
71183#[target_feature(enable = "neon,v7")]
71184#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
71185#[cfg_attr(test, assert_instr(nop))]
71186pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) {
71187    unsafe extern "unadjusted" {
71188        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v1i64")]
71189        fn _vst4_s64(
71190            ptr: *mut i8,
71191            a: int64x1_t,
71192            b: int64x1_t,
71193            c: int64x1_t,
71194            d: int64x1_t,
71195            size: i32,
71196        );
71197    }
71198    _vst4_s64(a as _, b.0, b.1, b.2, b.3, 8)
71199}
71200#[doc = "Store multiple 4-element structures from four registers"]
71201#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"]
71202#[doc = "## Safety"]
71203#[doc = "  * Neon instrinsic unsafe"]
71204#[inline]
71205#[target_feature(enable = "neon")]
71206#[cfg(not(target_arch = "arm"))]
71207#[stable(feature = "neon_intrinsics", since = "1.59.0")]
71208#[cfg_attr(test, assert_instr(nop))]
71209pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) {
71210    unsafe extern "unadjusted" {
71211        #[cfg_attr(
71212            any(target_arch = "aarch64", target_arch = "arm64ec"),
71213            link_name = "llvm.aarch64.neon.st4.v1i64.p0"
71214        )]
71215        fn _vst4_s64(a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t, ptr: *mut i8);
71216    }
71217    _vst4_s64(b.0, b.1, b.2, b.3, a as _)
71218}
71219#[doc = "Store multiple 4-element structures from four registers"]
71220#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u64)"]
71221#[doc = "## Safety"]
71222#[doc = "  * Neon instrinsic unsafe"]
71223#[inline]
71224#[target_feature(enable = "neon")]
71225#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71226#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
71227#[cfg_attr(
71228    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71229    assert_instr(nop)
71230)]
71231#[cfg_attr(
71232    not(target_arch = "arm"),
71233    stable(feature = "neon_intrinsics", since = "1.59.0")
71234)]
71235#[cfg_attr(
71236    target_arch = "arm",
71237    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71238)]
71239pub unsafe fn vst4_u64(a: *mut u64, b: uint64x1x4_t) {
71240    vst4_s64(transmute(a), transmute(b))
71241}
71242#[doc = "Store multiple 4-element structures from four registers"]
71243#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u8)"]
71244#[doc = "## Safety"]
71245#[doc = "  * Neon instrinsic unsafe"]
71246#[inline]
71247#[target_feature(enable = "neon")]
71248#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71249#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71250#[cfg_attr(
71251    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71252    assert_instr(st4)
71253)]
71254#[cfg_attr(
71255    not(target_arch = "arm"),
71256    stable(feature = "neon_intrinsics", since = "1.59.0")
71257)]
71258#[cfg_attr(
71259    target_arch = "arm",
71260    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71261)]
71262pub unsafe fn vst4_u8(a: *mut u8, b: uint8x8x4_t) {
71263    vst4_s8(transmute(a), transmute(b))
71264}
71265#[doc = "Store multiple 4-element structures from four registers"]
71266#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u8)"]
71267#[doc = "## Safety"]
71268#[doc = "  * Neon instrinsic unsafe"]
71269#[inline]
71270#[target_feature(enable = "neon")]
71271#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71272#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71273#[cfg_attr(
71274    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71275    assert_instr(st4)
71276)]
71277#[cfg_attr(
71278    not(target_arch = "arm"),
71279    stable(feature = "neon_intrinsics", since = "1.59.0")
71280)]
71281#[cfg_attr(
71282    target_arch = "arm",
71283    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71284)]
71285pub unsafe fn vst4q_u8(a: *mut u8, b: uint8x16x4_t) {
71286    vst4q_s8(transmute(a), transmute(b))
71287}
71288#[doc = "Store multiple 4-element structures from four registers"]
71289#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u16)"]
71290#[doc = "## Safety"]
71291#[doc = "  * Neon instrinsic unsafe"]
71292#[inline]
71293#[target_feature(enable = "neon")]
71294#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71295#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71296#[cfg_attr(
71297    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71298    assert_instr(st4)
71299)]
71300#[cfg_attr(
71301    not(target_arch = "arm"),
71302    stable(feature = "neon_intrinsics", since = "1.59.0")
71303)]
71304#[cfg_attr(
71305    target_arch = "arm",
71306    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71307)]
71308pub unsafe fn vst4_u16(a: *mut u16, b: uint16x4x4_t) {
71309    vst4_s16(transmute(a), transmute(b))
71310}
71311#[doc = "Store multiple 4-element structures from four registers"]
71312#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u16)"]
71313#[doc = "## Safety"]
71314#[doc = "  * Neon instrinsic unsafe"]
71315#[inline]
71316#[target_feature(enable = "neon")]
71317#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71318#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71319#[cfg_attr(
71320    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71321    assert_instr(st4)
71322)]
71323#[cfg_attr(
71324    not(target_arch = "arm"),
71325    stable(feature = "neon_intrinsics", since = "1.59.0")
71326)]
71327#[cfg_attr(
71328    target_arch = "arm",
71329    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71330)]
71331pub unsafe fn vst4q_u16(a: *mut u16, b: uint16x8x4_t) {
71332    vst4q_s16(transmute(a), transmute(b))
71333}
71334#[doc = "Store multiple 4-element structures from four registers"]
71335#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u32)"]
71336#[doc = "## Safety"]
71337#[doc = "  * Neon instrinsic unsafe"]
71338#[inline]
71339#[target_feature(enable = "neon")]
71340#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71341#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71342#[cfg_attr(
71343    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71344    assert_instr(st4)
71345)]
71346#[cfg_attr(
71347    not(target_arch = "arm"),
71348    stable(feature = "neon_intrinsics", since = "1.59.0")
71349)]
71350#[cfg_attr(
71351    target_arch = "arm",
71352    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71353)]
71354pub unsafe fn vst4_u32(a: *mut u32, b: uint32x2x4_t) {
71355    vst4_s32(transmute(a), transmute(b))
71356}
71357#[doc = "Store multiple 4-element structures from four registers"]
71358#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u32)"]
71359#[doc = "## Safety"]
71360#[doc = "  * Neon instrinsic unsafe"]
71361#[inline]
71362#[target_feature(enable = "neon")]
71363#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71364#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71365#[cfg_attr(
71366    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71367    assert_instr(st4)
71368)]
71369#[cfg_attr(
71370    not(target_arch = "arm"),
71371    stable(feature = "neon_intrinsics", since = "1.59.0")
71372)]
71373#[cfg_attr(
71374    target_arch = "arm",
71375    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71376)]
71377pub unsafe fn vst4q_u32(a: *mut u32, b: uint32x4x4_t) {
71378    vst4q_s32(transmute(a), transmute(b))
71379}
71380#[doc = "Store multiple 4-element structures from four registers"]
71381#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p8)"]
71382#[doc = "## Safety"]
71383#[doc = "  * Neon instrinsic unsafe"]
71384#[inline]
71385#[target_feature(enable = "neon")]
71386#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71387#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71388#[cfg_attr(
71389    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71390    assert_instr(st4)
71391)]
71392#[cfg_attr(
71393    not(target_arch = "arm"),
71394    stable(feature = "neon_intrinsics", since = "1.59.0")
71395)]
71396#[cfg_attr(
71397    target_arch = "arm",
71398    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71399)]
71400pub unsafe fn vst4_p8(a: *mut p8, b: poly8x8x4_t) {
71401    vst4_s8(transmute(a), transmute(b))
71402}
71403#[doc = "Store multiple 4-element structures from four registers"]
71404#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p8)"]
71405#[doc = "## Safety"]
71406#[doc = "  * Neon instrinsic unsafe"]
71407#[inline]
71408#[target_feature(enable = "neon")]
71409#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71410#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71411#[cfg_attr(
71412    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71413    assert_instr(st4)
71414)]
71415#[cfg_attr(
71416    not(target_arch = "arm"),
71417    stable(feature = "neon_intrinsics", since = "1.59.0")
71418)]
71419#[cfg_attr(
71420    target_arch = "arm",
71421    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71422)]
71423pub unsafe fn vst4q_p8(a: *mut p8, b: poly8x16x4_t) {
71424    vst4q_s8(transmute(a), transmute(b))
71425}
71426#[doc = "Store multiple 4-element structures from four registers"]
71427#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p16)"]
71428#[doc = "## Safety"]
71429#[doc = "  * Neon instrinsic unsafe"]
71430#[inline]
71431#[target_feature(enable = "neon")]
71432#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71433#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71434#[cfg_attr(
71435    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71436    assert_instr(st4)
71437)]
71438#[cfg_attr(
71439    not(target_arch = "arm"),
71440    stable(feature = "neon_intrinsics", since = "1.59.0")
71441)]
71442#[cfg_attr(
71443    target_arch = "arm",
71444    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71445)]
71446pub unsafe fn vst4_p16(a: *mut p16, b: poly16x4x4_t) {
71447    vst4_s16(transmute(a), transmute(b))
71448}
71449#[doc = "Store multiple 4-element structures from four registers"]
71450#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p16)"]
71451#[doc = "## Safety"]
71452#[doc = "  * Neon instrinsic unsafe"]
71453#[inline]
71454#[target_feature(enable = "neon")]
71455#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71456#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71457#[cfg_attr(
71458    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71459    assert_instr(st4)
71460)]
71461#[cfg_attr(
71462    not(target_arch = "arm"),
71463    stable(feature = "neon_intrinsics", since = "1.59.0")
71464)]
71465#[cfg_attr(
71466    target_arch = "arm",
71467    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71468)]
71469pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) {
71470    vst4q_s16(transmute(a), transmute(b))
71471}
71472#[doc = "Store SIMD&FP register (immediate offset)"]
71473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstrq_p128)"]
71474#[doc = "## Safety"]
71475#[doc = "  * Neon instrinsic unsafe"]
71476#[inline]
71477#[target_feature(enable = "neon")]
71478#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71479#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
71480#[cfg_attr(
71481    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71482    assert_instr(nop)
71483)]
71484#[cfg_attr(
71485    not(target_arch = "arm"),
71486    stable(feature = "neon_intrinsics", since = "1.59.0")
71487)]
71488#[cfg_attr(
71489    target_arch = "arm",
71490    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71491)]
71492pub unsafe fn vstrq_p128(a: *mut p128, b: p128) {
71493    *a = b
71494}
71495#[doc = "Subtract"]
71496#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f16)"]
71497#[inline]
71498#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
71499#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))]
71500#[cfg_attr(
71501    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71502    assert_instr(fsub)
71503)]
71504#[target_feature(enable = "neon,fp16")]
71505#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
71506pub fn vsub_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
71507    unsafe { simd_sub(a, b) }
71508}
71509#[doc = "Subtract"]
71510#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f16)"]
71511#[inline]
71512#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
71513#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))]
71514#[cfg_attr(
71515    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71516    assert_instr(fsub)
71517)]
71518#[target_feature(enable = "neon,fp16")]
71519#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
71520pub fn vsubq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
71521    unsafe { simd_sub(a, b) }
71522}
71523#[doc = "Subtract"]
71524#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f32)"]
71525#[inline]
71526#[target_feature(enable = "neon")]
71527#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71528#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))]
71529#[cfg_attr(
71530    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71531    assert_instr(fsub)
71532)]
71533#[cfg_attr(
71534    not(target_arch = "arm"),
71535    stable(feature = "neon_intrinsics", since = "1.59.0")
71536)]
71537#[cfg_attr(
71538    target_arch = "arm",
71539    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71540)]
71541pub fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
71542    unsafe { simd_sub(a, b) }
71543}
71544#[doc = "Subtract"]
71545#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f32)"]
71546#[inline]
71547#[target_feature(enable = "neon")]
71548#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71549#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))]
71550#[cfg_attr(
71551    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71552    assert_instr(fsub)
71553)]
71554#[cfg_attr(
71555    not(target_arch = "arm"),
71556    stable(feature = "neon_intrinsics", since = "1.59.0")
71557)]
71558#[cfg_attr(
71559    target_arch = "arm",
71560    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71561)]
71562pub fn vsubq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
71563    unsafe { simd_sub(a, b) }
71564}
71565#[doc = "Subtract"]
71566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s16)"]
71567#[inline]
71568#[target_feature(enable = "neon")]
71569#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71570#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
71571#[cfg_attr(
71572    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71573    assert_instr(sub)
71574)]
71575#[cfg_attr(
71576    not(target_arch = "arm"),
71577    stable(feature = "neon_intrinsics", since = "1.59.0")
71578)]
71579#[cfg_attr(
71580    target_arch = "arm",
71581    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71582)]
71583pub fn vsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
71584    unsafe { simd_sub(a, b) }
71585}
71586#[doc = "Subtract"]
71587#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s16)"]
71588#[inline]
71589#[target_feature(enable = "neon")]
71590#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71591#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
71592#[cfg_attr(
71593    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71594    assert_instr(sub)
71595)]
71596#[cfg_attr(
71597    not(target_arch = "arm"),
71598    stable(feature = "neon_intrinsics", since = "1.59.0")
71599)]
71600#[cfg_attr(
71601    target_arch = "arm",
71602    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71603)]
71604pub fn vsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
71605    unsafe { simd_sub(a, b) }
71606}
71607#[doc = "Subtract"]
71608#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u16)"]
71609#[inline]
71610#[target_feature(enable = "neon")]
71611#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71612#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
71613#[cfg_attr(
71614    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71615    assert_instr(sub)
71616)]
71617#[cfg_attr(
71618    not(target_arch = "arm"),
71619    stable(feature = "neon_intrinsics", since = "1.59.0")
71620)]
71621#[cfg_attr(
71622    target_arch = "arm",
71623    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71624)]
71625pub fn vsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
71626    unsafe { simd_sub(a, b) }
71627}
71628#[doc = "Subtract"]
71629#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u16)"]
71630#[inline]
71631#[target_feature(enable = "neon")]
71632#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71633#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
71634#[cfg_attr(
71635    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71636    assert_instr(sub)
71637)]
71638#[cfg_attr(
71639    not(target_arch = "arm"),
71640    stable(feature = "neon_intrinsics", since = "1.59.0")
71641)]
71642#[cfg_attr(
71643    target_arch = "arm",
71644    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71645)]
71646pub fn vsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
71647    unsafe { simd_sub(a, b) }
71648}
71649#[doc = "Subtract"]
71650#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s32)"]
71651#[inline]
71652#[target_feature(enable = "neon")]
71653#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71654#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
71655#[cfg_attr(
71656    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71657    assert_instr(sub)
71658)]
71659#[cfg_attr(
71660    not(target_arch = "arm"),
71661    stable(feature = "neon_intrinsics", since = "1.59.0")
71662)]
71663#[cfg_attr(
71664    target_arch = "arm",
71665    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71666)]
71667pub fn vsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
71668    unsafe { simd_sub(a, b) }
71669}
71670#[doc = "Subtract"]
71671#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s32)"]
71672#[inline]
71673#[target_feature(enable = "neon")]
71674#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71675#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
71676#[cfg_attr(
71677    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71678    assert_instr(sub)
71679)]
71680#[cfg_attr(
71681    not(target_arch = "arm"),
71682    stable(feature = "neon_intrinsics", since = "1.59.0")
71683)]
71684#[cfg_attr(
71685    target_arch = "arm",
71686    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71687)]
71688pub fn vsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
71689    unsafe { simd_sub(a, b) }
71690}
71691#[doc = "Subtract"]
71692#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u32)"]
71693#[inline]
71694#[target_feature(enable = "neon")]
71695#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71696#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
71697#[cfg_attr(
71698    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71699    assert_instr(sub)
71700)]
71701#[cfg_attr(
71702    not(target_arch = "arm"),
71703    stable(feature = "neon_intrinsics", since = "1.59.0")
71704)]
71705#[cfg_attr(
71706    target_arch = "arm",
71707    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71708)]
71709pub fn vsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
71710    unsafe { simd_sub(a, b) }
71711}
71712#[doc = "Subtract"]
71713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u32)"]
71714#[inline]
71715#[target_feature(enable = "neon")]
71716#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71717#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
71718#[cfg_attr(
71719    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71720    assert_instr(sub)
71721)]
71722#[cfg_attr(
71723    not(target_arch = "arm"),
71724    stable(feature = "neon_intrinsics", since = "1.59.0")
71725)]
71726#[cfg_attr(
71727    target_arch = "arm",
71728    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71729)]
71730pub fn vsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
71731    unsafe { simd_sub(a, b) }
71732}
71733#[doc = "Subtract"]
71734#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s64)"]
71735#[inline]
71736#[target_feature(enable = "neon")]
71737#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71738#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
71739#[cfg_attr(
71740    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71741    assert_instr(sub)
71742)]
71743#[cfg_attr(
71744    not(target_arch = "arm"),
71745    stable(feature = "neon_intrinsics", since = "1.59.0")
71746)]
71747#[cfg_attr(
71748    target_arch = "arm",
71749    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71750)]
71751pub fn vsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
71752    unsafe { simd_sub(a, b) }
71753}
71754#[doc = "Subtract"]
71755#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s64)"]
71756#[inline]
71757#[target_feature(enable = "neon")]
71758#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71759#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
71760#[cfg_attr(
71761    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71762    assert_instr(sub)
71763)]
71764#[cfg_attr(
71765    not(target_arch = "arm"),
71766    stable(feature = "neon_intrinsics", since = "1.59.0")
71767)]
71768#[cfg_attr(
71769    target_arch = "arm",
71770    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71771)]
71772pub fn vsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
71773    unsafe { simd_sub(a, b) }
71774}
71775#[doc = "Subtract"]
71776#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u64)"]
71777#[inline]
71778#[target_feature(enable = "neon")]
71779#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71780#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
71781#[cfg_attr(
71782    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71783    assert_instr(sub)
71784)]
71785#[cfg_attr(
71786    not(target_arch = "arm"),
71787    stable(feature = "neon_intrinsics", since = "1.59.0")
71788)]
71789#[cfg_attr(
71790    target_arch = "arm",
71791    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71792)]
71793pub fn vsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
71794    unsafe { simd_sub(a, b) }
71795}
71796#[doc = "Subtract"]
71797#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u64)"]
71798#[inline]
71799#[target_feature(enable = "neon")]
71800#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71801#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
71802#[cfg_attr(
71803    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71804    assert_instr(sub)
71805)]
71806#[cfg_attr(
71807    not(target_arch = "arm"),
71808    stable(feature = "neon_intrinsics", since = "1.59.0")
71809)]
71810#[cfg_attr(
71811    target_arch = "arm",
71812    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71813)]
71814pub fn vsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
71815    unsafe { simd_sub(a, b) }
71816}
71817#[doc = "Subtract"]
71818#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s8)"]
71819#[inline]
71820#[target_feature(enable = "neon")]
71821#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71822#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
71823#[cfg_attr(
71824    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71825    assert_instr(sub)
71826)]
71827#[cfg_attr(
71828    not(target_arch = "arm"),
71829    stable(feature = "neon_intrinsics", since = "1.59.0")
71830)]
71831#[cfg_attr(
71832    target_arch = "arm",
71833    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71834)]
71835pub fn vsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
71836    unsafe { simd_sub(a, b) }
71837}
71838#[doc = "Subtract"]
71839#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s8)"]
71840#[inline]
71841#[target_feature(enable = "neon")]
71842#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71843#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
71844#[cfg_attr(
71845    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71846    assert_instr(sub)
71847)]
71848#[cfg_attr(
71849    not(target_arch = "arm"),
71850    stable(feature = "neon_intrinsics", since = "1.59.0")
71851)]
71852#[cfg_attr(
71853    target_arch = "arm",
71854    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71855)]
71856pub fn vsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
71857    unsafe { simd_sub(a, b) }
71858}
71859#[doc = "Subtract"]
71860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u8)"]
71861#[inline]
71862#[target_feature(enable = "neon")]
71863#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71864#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
71865#[cfg_attr(
71866    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71867    assert_instr(sub)
71868)]
71869#[cfg_attr(
71870    not(target_arch = "arm"),
71871    stable(feature = "neon_intrinsics", since = "1.59.0")
71872)]
71873#[cfg_attr(
71874    target_arch = "arm",
71875    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71876)]
71877pub fn vsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
71878    unsafe { simd_sub(a, b) }
71879}
71880#[doc = "Subtract"]
71881#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u8)"]
71882#[inline]
71883#[target_feature(enable = "neon")]
71884#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71885#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
71886#[cfg_attr(
71887    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71888    assert_instr(sub)
71889)]
71890#[cfg_attr(
71891    not(target_arch = "arm"),
71892    stable(feature = "neon_intrinsics", since = "1.59.0")
71893)]
71894#[cfg_attr(
71895    target_arch = "arm",
71896    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71897)]
71898pub fn vsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
71899    unsafe { simd_sub(a, b) }
71900}
71901#[doc = "Subtract returning high narrow"]
71902#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s16)"]
71903#[inline]
71904#[target_feature(enable = "neon")]
71905#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71906#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
71907#[cfg_attr(
71908    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71909    assert_instr(subhn2)
71910)]
71911#[cfg_attr(
71912    not(target_arch = "arm"),
71913    stable(feature = "neon_intrinsics", since = "1.59.0")
71914)]
71915#[cfg_attr(
71916    target_arch = "arm",
71917    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71918)]
71919pub fn vsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
71920    let d: int8x8_t = vsubhn_s16(b, c);
71921    unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
71922}
71923#[doc = "Subtract returning high narrow"]
71924#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s32)"]
71925#[inline]
71926#[target_feature(enable = "neon")]
71927#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71928#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
71929#[cfg_attr(
71930    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71931    assert_instr(subhn2)
71932)]
71933#[cfg_attr(
71934    not(target_arch = "arm"),
71935    stable(feature = "neon_intrinsics", since = "1.59.0")
71936)]
71937#[cfg_attr(
71938    target_arch = "arm",
71939    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71940)]
71941pub fn vsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
71942    let d: int16x4_t = vsubhn_s32(b, c);
71943    unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) }
71944}
71945#[doc = "Subtract returning high narrow"]
71946#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s64)"]
71947#[inline]
71948#[target_feature(enable = "neon")]
71949#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71950#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
71951#[cfg_attr(
71952    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71953    assert_instr(subhn2)
71954)]
71955#[cfg_attr(
71956    not(target_arch = "arm"),
71957    stable(feature = "neon_intrinsics", since = "1.59.0")
71958)]
71959#[cfg_attr(
71960    target_arch = "arm",
71961    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71962)]
71963pub fn vsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
71964    let d: int32x2_t = vsubhn_s64(b, c);
71965    unsafe { simd_shuffle!(a, d, [0, 1, 2, 3]) }
71966}
71967#[doc = "Subtract returning high narrow"]
71968#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u16)"]
71969#[inline]
71970#[target_feature(enable = "neon")]
71971#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71972#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
71973#[cfg_attr(
71974    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71975    assert_instr(subhn2)
71976)]
71977#[cfg_attr(
71978    not(target_arch = "arm"),
71979    stable(feature = "neon_intrinsics", since = "1.59.0")
71980)]
71981#[cfg_attr(
71982    target_arch = "arm",
71983    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71984)]
71985pub fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t {
71986    let d: uint8x8_t = vsubhn_u16(b, c);
71987    unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
71988}
71989#[doc = "Subtract returning high narrow"]
71990#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u32)"]
71991#[inline]
71992#[target_feature(enable = "neon")]
71993#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71994#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
71995#[cfg_attr(
71996    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71997    assert_instr(subhn2)
71998)]
71999#[cfg_attr(
72000    not(target_arch = "arm"),
72001    stable(feature = "neon_intrinsics", since = "1.59.0")
72002)]
72003#[cfg_attr(
72004    target_arch = "arm",
72005    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72006)]
72007pub fn vsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t {
72008    let d: uint16x4_t = vsubhn_u32(b, c);
72009    unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) }
72010}
72011#[doc = "Subtract returning high narrow"]
72012#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u64)"]
72013#[inline]
72014#[target_feature(enable = "neon")]
72015#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72016#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72017#[cfg_attr(
72018    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72019    assert_instr(subhn2)
72020)]
72021#[cfg_attr(
72022    not(target_arch = "arm"),
72023    stable(feature = "neon_intrinsics", since = "1.59.0")
72024)]
72025#[cfg_attr(
72026    target_arch = "arm",
72027    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72028)]
72029pub fn vsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t {
72030    let d: uint32x2_t = vsubhn_u64(b, c);
72031    unsafe { simd_shuffle!(a, d, [0, 1, 2, 3]) }
72032}
72033#[doc = "Subtract returning high narrow"]
72034#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s16)"]
72035#[inline]
72036#[target_feature(enable = "neon")]
72037#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72038#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72039#[cfg_attr(
72040    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72041    assert_instr(subhn)
72042)]
72043#[cfg_attr(
72044    not(target_arch = "arm"),
72045    stable(feature = "neon_intrinsics", since = "1.59.0")
72046)]
72047#[cfg_attr(
72048    target_arch = "arm",
72049    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72050)]
72051pub fn vsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
72052    let c: i16x8 = i16x8::new(8, 8, 8, 8, 8, 8, 8, 8);
72053    unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
72054}
72055#[doc = "Subtract returning high narrow"]
72056#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s32)"]
72057#[inline]
72058#[target_feature(enable = "neon")]
72059#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72060#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72061#[cfg_attr(
72062    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72063    assert_instr(subhn)
72064)]
72065#[cfg_attr(
72066    not(target_arch = "arm"),
72067    stable(feature = "neon_intrinsics", since = "1.59.0")
72068)]
72069#[cfg_attr(
72070    target_arch = "arm",
72071    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72072)]
72073pub fn vsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
72074    let c: i32x4 = i32x4::new(16, 16, 16, 16);
72075    unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
72076}
72077#[doc = "Subtract returning high narrow"]
72078#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s64)"]
72079#[inline]
72080#[target_feature(enable = "neon")]
72081#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72082#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72083#[cfg_attr(
72084    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72085    assert_instr(subhn)
72086)]
72087#[cfg_attr(
72088    not(target_arch = "arm"),
72089    stable(feature = "neon_intrinsics", since = "1.59.0")
72090)]
72091#[cfg_attr(
72092    target_arch = "arm",
72093    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72094)]
72095pub fn vsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
72096    let c: i64x2 = i64x2::new(32, 32);
72097    unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
72098}
72099#[doc = "Subtract returning high narrow"]
72100#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u16)"]
72101#[inline]
72102#[target_feature(enable = "neon")]
72103#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72104#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72105#[cfg_attr(
72106    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72107    assert_instr(subhn)
72108)]
72109#[cfg_attr(
72110    not(target_arch = "arm"),
72111    stable(feature = "neon_intrinsics", since = "1.59.0")
72112)]
72113#[cfg_attr(
72114    target_arch = "arm",
72115    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72116)]
72117pub fn vsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
72118    let c: u16x8 = u16x8::new(8, 8, 8, 8, 8, 8, 8, 8);
72119    unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
72120}
72121#[doc = "Subtract returning high narrow"]
72122#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u32)"]
72123#[inline]
72124#[target_feature(enable = "neon")]
72125#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72126#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72127#[cfg_attr(
72128    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72129    assert_instr(subhn)
72130)]
72131#[cfg_attr(
72132    not(target_arch = "arm"),
72133    stable(feature = "neon_intrinsics", since = "1.59.0")
72134)]
72135#[cfg_attr(
72136    target_arch = "arm",
72137    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72138)]
72139pub fn vsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
72140    let c: u32x4 = u32x4::new(16, 16, 16, 16);
72141    unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
72142}
72143#[doc = "Subtract returning high narrow"]
72144#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u64)"]
72145#[inline]
72146#[target_feature(enable = "neon")]
72147#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72148#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72149#[cfg_attr(
72150    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72151    assert_instr(subhn)
72152)]
72153#[cfg_attr(
72154    not(target_arch = "arm"),
72155    stable(feature = "neon_intrinsics", since = "1.59.0")
72156)]
72157#[cfg_attr(
72158    target_arch = "arm",
72159    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72160)]
72161pub fn vsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
72162    let c: u64x2 = u64x2::new(32, 32);
72163    unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
72164}
72165#[doc = "Signed Subtract Long"]
72166#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s8)"]
72167#[inline]
72168#[target_feature(enable = "neon")]
72169#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72170#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
72171#[cfg_attr(
72172    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72173    assert_instr(ssubl)
72174)]
72175#[cfg_attr(
72176    not(target_arch = "arm"),
72177    stable(feature = "neon_intrinsics", since = "1.59.0")
72178)]
72179#[cfg_attr(
72180    target_arch = "arm",
72181    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72182)]
72183pub fn vsubl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
72184    unsafe {
72185        let c: int16x8_t = simd_cast(a);
72186        let d: int16x8_t = simd_cast(b);
72187        simd_sub(c, d)
72188    }
72189}
72190#[doc = "Signed Subtract Long"]
72191#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s16)"]
72192#[inline]
72193#[target_feature(enable = "neon")]
72194#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72195#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
72196#[cfg_attr(
72197    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72198    assert_instr(ssubl)
72199)]
72200#[cfg_attr(
72201    not(target_arch = "arm"),
72202    stable(feature = "neon_intrinsics", since = "1.59.0")
72203)]
72204#[cfg_attr(
72205    target_arch = "arm",
72206    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72207)]
72208pub fn vsubl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
72209    unsafe {
72210        let c: int32x4_t = simd_cast(a);
72211        let d: int32x4_t = simd_cast(b);
72212        simd_sub(c, d)
72213    }
72214}
72215#[doc = "Signed Subtract Long"]
72216#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s32)"]
72217#[inline]
72218#[target_feature(enable = "neon")]
72219#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72220#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
72221#[cfg_attr(
72222    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72223    assert_instr(ssubl)
72224)]
72225#[cfg_attr(
72226    not(target_arch = "arm"),
72227    stable(feature = "neon_intrinsics", since = "1.59.0")
72228)]
72229#[cfg_attr(
72230    target_arch = "arm",
72231    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72232)]
72233pub fn vsubl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
72234    unsafe {
72235        let c: int64x2_t = simd_cast(a);
72236        let d: int64x2_t = simd_cast(b);
72237        simd_sub(c, d)
72238    }
72239}
72240#[doc = "Unsigned Subtract Long"]
72241#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u8)"]
72242#[inline]
72243#[target_feature(enable = "neon")]
72244#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72245#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
72246#[cfg_attr(
72247    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72248    assert_instr(usubl)
72249)]
72250#[cfg_attr(
72251    not(target_arch = "arm"),
72252    stable(feature = "neon_intrinsics", since = "1.59.0")
72253)]
72254#[cfg_attr(
72255    target_arch = "arm",
72256    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72257)]
72258pub fn vsubl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
72259    unsafe {
72260        let c: uint16x8_t = simd_cast(a);
72261        let d: uint16x8_t = simd_cast(b);
72262        simd_sub(c, d)
72263    }
72264}
72265#[doc = "Unsigned Subtract Long"]
72266#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u16)"]
72267#[inline]
72268#[target_feature(enable = "neon")]
72269#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72270#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
72271#[cfg_attr(
72272    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72273    assert_instr(usubl)
72274)]
72275#[cfg_attr(
72276    not(target_arch = "arm"),
72277    stable(feature = "neon_intrinsics", since = "1.59.0")
72278)]
72279#[cfg_attr(
72280    target_arch = "arm",
72281    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72282)]
72283pub fn vsubl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
72284    unsafe {
72285        let c: uint32x4_t = simd_cast(a);
72286        let d: uint32x4_t = simd_cast(b);
72287        simd_sub(c, d)
72288    }
72289}
72290#[doc = "Unsigned Subtract Long"]
72291#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u32)"]
72292#[inline]
72293#[target_feature(enable = "neon")]
72294#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72295#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
72296#[cfg_attr(
72297    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72298    assert_instr(usubl)
72299)]
72300#[cfg_attr(
72301    not(target_arch = "arm"),
72302    stable(feature = "neon_intrinsics", since = "1.59.0")
72303)]
72304#[cfg_attr(
72305    target_arch = "arm",
72306    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72307)]
72308pub fn vsubl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
72309    unsafe {
72310        let c: uint64x2_t = simd_cast(a);
72311        let d: uint64x2_t = simd_cast(b);
72312        simd_sub(c, d)
72313    }
72314}
72315#[doc = "Signed Subtract Wide"]
72316#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s8)"]
72317#[inline]
72318#[target_feature(enable = "neon")]
72319#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72320#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
72321#[cfg_attr(
72322    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72323    assert_instr(ssubw)
72324)]
72325#[cfg_attr(
72326    not(target_arch = "arm"),
72327    stable(feature = "neon_intrinsics", since = "1.59.0")
72328)]
72329#[cfg_attr(
72330    target_arch = "arm",
72331    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72332)]
72333pub fn vsubw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t {
72334    unsafe { simd_sub(a, simd_cast(b)) }
72335}
72336#[doc = "Signed Subtract Wide"]
72337#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s16)"]
72338#[inline]
72339#[target_feature(enable = "neon")]
72340#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72341#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
72342#[cfg_attr(
72343    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72344    assert_instr(ssubw)
72345)]
72346#[cfg_attr(
72347    not(target_arch = "arm"),
72348    stable(feature = "neon_intrinsics", since = "1.59.0")
72349)]
72350#[cfg_attr(
72351    target_arch = "arm",
72352    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72353)]
72354pub fn vsubw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t {
72355    unsafe { simd_sub(a, simd_cast(b)) }
72356}
72357#[doc = "Signed Subtract Wide"]
72358#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s32)"]
72359#[inline]
72360#[target_feature(enable = "neon")]
72361#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72362#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
72363#[cfg_attr(
72364    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72365    assert_instr(ssubw)
72366)]
72367#[cfg_attr(
72368    not(target_arch = "arm"),
72369    stable(feature = "neon_intrinsics", since = "1.59.0")
72370)]
72371#[cfg_attr(
72372    target_arch = "arm",
72373    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72374)]
72375pub fn vsubw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t {
72376    unsafe { simd_sub(a, simd_cast(b)) }
72377}
72378#[doc = "Unsigned Subtract Wide"]
72379#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u8)"]
72380#[inline]
72381#[target_feature(enable = "neon")]
72382#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72383#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
72384#[cfg_attr(
72385    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72386    assert_instr(usubw)
72387)]
72388#[cfg_attr(
72389    not(target_arch = "arm"),
72390    stable(feature = "neon_intrinsics", since = "1.59.0")
72391)]
72392#[cfg_attr(
72393    target_arch = "arm",
72394    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72395)]
72396pub fn vsubw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t {
72397    unsafe { simd_sub(a, simd_cast(b)) }
72398}
72399#[doc = "Unsigned Subtract Wide"]
72400#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u16)"]
72401#[inline]
72402#[target_feature(enable = "neon")]
72403#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72404#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
72405#[cfg_attr(
72406    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72407    assert_instr(usubw)
72408)]
72409#[cfg_attr(
72410    not(target_arch = "arm"),
72411    stable(feature = "neon_intrinsics", since = "1.59.0")
72412)]
72413#[cfg_attr(
72414    target_arch = "arm",
72415    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72416)]
72417pub fn vsubw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t {
72418    unsafe { simd_sub(a, simd_cast(b)) }
72419}
72420#[doc = "Unsigned Subtract Wide"]
72421#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u32)"]
72422#[inline]
72423#[target_feature(enable = "neon")]
72424#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72425#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
72426#[cfg_attr(
72427    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72428    assert_instr(usubw)
72429)]
72430#[cfg_attr(
72431    not(target_arch = "arm"),
72432    stable(feature = "neon_intrinsics", since = "1.59.0")
72433)]
72434#[cfg_attr(
72435    target_arch = "arm",
72436    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72437)]
72438pub fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t {
72439    unsafe { simd_sub(a, simd_cast(b)) }
72440}
72441#[doc = "Dot product index form with signed and unsigned integers"]
72442#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"]
72443#[inline]
72444#[target_feature(enable = "neon,i8mm")]
72445#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
72446#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))]
72447#[cfg_attr(
72448    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72449    assert_instr(sudot, LANE = 0)
72450)]
72451#[rustc_legacy_const_generics(3)]
72452#[cfg_attr(
72453    not(target_arch = "arm"),
72454    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
72455)]
72456#[cfg_attr(
72457    target_arch = "arm",
72458    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72459)]
72460pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t) -> int32x2_t {
72461    static_assert_uimm_bits!(LANE, 1);
72462    unsafe {
72463        let c: uint32x2_t = transmute(c);
72464        let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
72465        vusdot_s32(a, transmute(c), b)
72466    }
72467}
72468#[doc = "Dot product index form with signed and unsigned integers"]
72469#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"]
72470#[inline]
72471#[target_feature(enable = "neon,i8mm")]
72472#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
72473#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))]
72474#[cfg_attr(
72475    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72476    assert_instr(sudot, LANE = 0)
72477)]
72478#[rustc_legacy_const_generics(3)]
72479#[cfg_attr(
72480    not(target_arch = "arm"),
72481    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
72482)]
72483#[cfg_attr(
72484    target_arch = "arm",
72485    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72486)]
72487pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_t) -> int32x4_t {
72488    static_assert_uimm_bits!(LANE, 1);
72489    unsafe {
72490        let c: uint32x2_t = transmute(c);
72491        let c: uint32x4_t =
72492            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
72493        vusdotq_s32(a, transmute(c), b)
72494    }
72495}
72496#[doc = "Table look-up"]
72497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1)"]
72498#[inline]
72499#[target_feature(enable = "neon")]
72500#[cfg(target_arch = "arm")]
72501#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72502#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72503#[cfg_attr(test, assert_instr(vtbl))]
72504fn vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t {
72505    unsafe extern "unadjusted" {
72506        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl1")]
72507        fn _vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t;
72508    }
72509    unsafe { _vtbl1(a, b) }
72510}
72511#[doc = "Table look-up"]
72512#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"]
72513#[inline]
72514#[target_feature(enable = "neon")]
72515#[cfg(target_arch = "arm")]
72516#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72517#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72518#[cfg_attr(test, assert_instr(vtbl))]
72519pub fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
72520    vtbl1(a, b)
72521}
72522#[doc = "Table look-up"]
72523#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"]
72524#[inline]
72525#[cfg(target_endian = "little")]
72526#[target_feature(enable = "neon")]
72527#[cfg(target_arch = "arm")]
72528#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72529#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72530#[cfg_attr(test, assert_instr(vtbl))]
72531pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
72532    unsafe { transmute(vtbl1(transmute(a), transmute(b))) }
72533}
72534#[doc = "Table look-up"]
72535#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"]
72536#[inline]
72537#[cfg(target_endian = "big")]
72538#[target_feature(enable = "neon")]
72539#[cfg(target_arch = "arm")]
72540#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72541#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72542#[cfg_attr(test, assert_instr(vtbl))]
72543pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
72544    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
72545    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72546    unsafe {
72547        let ret_val: uint8x8_t = transmute(vtbl1(transmute(a), transmute(b)));
72548        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72549    }
72550}
72551#[doc = "Table look-up"]
72552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"]
72553#[inline]
72554#[cfg(target_endian = "little")]
72555#[target_feature(enable = "neon")]
72556#[cfg(target_arch = "arm")]
72557#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72558#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72559#[cfg_attr(test, assert_instr(vtbl))]
72560pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
72561    unsafe { transmute(vtbl1(transmute(a), transmute(b))) }
72562}
72563#[doc = "Table look-up"]
72564#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"]
72565#[inline]
72566#[cfg(target_endian = "big")]
72567#[target_feature(enable = "neon")]
72568#[cfg(target_arch = "arm")]
72569#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72570#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72571#[cfg_attr(test, assert_instr(vtbl))]
72572pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
72573    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
72574    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72575    unsafe {
72576        let ret_val: poly8x8_t = transmute(vtbl1(transmute(a), transmute(b)));
72577        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72578    }
72579}
72580#[doc = "Table look-up"]
72581#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2)"]
72582#[inline]
72583#[target_feature(enable = "neon")]
72584#[cfg(target_arch = "arm")]
72585#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72586#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72587#[cfg_attr(test, assert_instr(vtbl))]
72588fn vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
72589    unsafe extern "unadjusted" {
72590        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl2")]
72591        fn _vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t;
72592    }
72593    unsafe { _vtbl2(a, b, c) }
72594}
72595#[doc = "Table look-up"]
72596#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_s8)"]
72597#[inline]
72598#[target_feature(enable = "neon")]
72599#[cfg(target_arch = "arm")]
72600#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72601#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72602#[cfg_attr(test, assert_instr(vtbl))]
72603pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t {
72604    vtbl2(a.0, a.1, b)
72605}
72606#[doc = "Table look-up"]
72607#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
72608#[inline]
72609#[cfg(target_endian = "little")]
72610#[target_feature(enable = "neon")]
72611#[cfg(target_arch = "arm")]
72612#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72613#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72614#[cfg_attr(test, assert_instr(vtbl))]
72615pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
72616    unsafe { transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) }
72617}
72618#[doc = "Table look-up"]
72619#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
72620#[inline]
72621#[cfg(target_endian = "big")]
72622#[target_feature(enable = "neon")]
72623#[cfg(target_arch = "arm")]
72624#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72625#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72626#[cfg_attr(test, assert_instr(vtbl))]
72627pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
72628    let mut a: uint8x8x2_t = a;
72629    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72630    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72631    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72632    unsafe {
72633        let ret_val: uint8x8_t = transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b)));
72634        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72635    }
72636}
72637#[doc = "Table look-up"]
72638#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
72639#[inline]
72640#[cfg(target_endian = "little")]
72641#[target_feature(enable = "neon")]
72642#[cfg(target_arch = "arm")]
72643#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72644#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72645#[cfg_attr(test, assert_instr(vtbl))]
72646pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
72647    unsafe { transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) }
72648}
72649#[doc = "Table look-up"]
72650#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
72651#[inline]
72652#[cfg(target_endian = "big")]
72653#[target_feature(enable = "neon")]
72654#[cfg(target_arch = "arm")]
72655#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72656#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72657#[cfg_attr(test, assert_instr(vtbl))]
72658pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
72659    let mut a: poly8x8x2_t = a;
72660    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72661    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72662    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72663    unsafe {
72664        let ret_val: poly8x8_t = transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b)));
72665        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72666    }
72667}
72668#[doc = "Table look-up"]
72669#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3)"]
72670#[inline]
72671#[target_feature(enable = "neon")]
72672#[cfg(target_arch = "arm")]
72673#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72674#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72675#[cfg_attr(test, assert_instr(vtbl))]
72676fn vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t {
72677    unsafe extern "unadjusted" {
72678        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl3")]
72679        fn _vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t;
72680    }
72681    unsafe { _vtbl3(a, b, c, d) }
72682}
72683#[doc = "Table look-up"]
72684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"]
72685#[inline]
72686#[target_feature(enable = "neon")]
72687#[cfg(target_arch = "arm")]
72688#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72689#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72690#[cfg_attr(test, assert_instr(vtbl))]
72691pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t {
72692    vtbl3(a.0, a.1, a.2, b)
72693}
72694#[doc = "Table look-up"]
72695#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
72696#[inline]
72697#[cfg(target_endian = "little")]
72698#[target_feature(enable = "neon")]
72699#[cfg(target_arch = "arm")]
72700#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72701#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72702#[cfg_attr(test, assert_instr(vtbl))]
72703pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
72704    unsafe {
72705        transmute(vtbl3(
72706            transmute(a.0),
72707            transmute(a.1),
72708            transmute(a.2),
72709            transmute(b),
72710        ))
72711    }
72712}
72713#[doc = "Table look-up"]
72714#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
72715#[inline]
72716#[cfg(target_endian = "big")]
72717#[target_feature(enable = "neon")]
72718#[cfg(target_arch = "arm")]
72719#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72720#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72721#[cfg_attr(test, assert_instr(vtbl))]
72722pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
72723    let mut a: uint8x8x3_t = a;
72724    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72725    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72726    a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
72727    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72728    unsafe {
72729        let ret_val: uint8x8_t = transmute(vtbl3(
72730            transmute(a.0),
72731            transmute(a.1),
72732            transmute(a.2),
72733            transmute(b),
72734        ));
72735        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72736    }
72737}
72738#[doc = "Table look-up"]
72739#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
72740#[inline]
72741#[cfg(target_endian = "little")]
72742#[target_feature(enable = "neon")]
72743#[cfg(target_arch = "arm")]
72744#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72745#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72746#[cfg_attr(test, assert_instr(vtbl))]
72747pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
72748    unsafe {
72749        transmute(vtbl3(
72750            transmute(a.0),
72751            transmute(a.1),
72752            transmute(a.2),
72753            transmute(b),
72754        ))
72755    }
72756}
72757#[doc = "Table look-up"]
72758#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
72759#[inline]
72760#[cfg(target_endian = "big")]
72761#[target_feature(enable = "neon")]
72762#[cfg(target_arch = "arm")]
72763#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72764#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72765#[cfg_attr(test, assert_instr(vtbl))]
72766pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
72767    let mut a: poly8x8x3_t = a;
72768    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72769    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72770    a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
72771    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72772    unsafe {
72773        let ret_val: poly8x8_t = transmute(vtbl3(
72774            transmute(a.0),
72775            transmute(a.1),
72776            transmute(a.2),
72777            transmute(b),
72778        ));
72779        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72780    }
72781}
72782#[doc = "Table look-up"]
72783#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4)"]
72784#[inline]
72785#[target_feature(enable = "neon")]
72786#[cfg(target_arch = "arm")]
72787#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72788#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72789#[cfg_attr(test, assert_instr(vtbl))]
72790fn vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t {
72791    unsafe extern "unadjusted" {
72792        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl4")]
72793        fn _vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t;
72794    }
72795    unsafe { _vtbl4(a, b, c, d, e) }
72796}
72797#[doc = "Table look-up"]
72798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"]
72799#[inline]
72800#[target_feature(enable = "neon")]
72801#[cfg(target_arch = "arm")]
72802#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72803#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72804#[cfg_attr(test, assert_instr(vtbl))]
72805pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t {
72806    vtbl4(a.0, a.1, a.2, a.3, b)
72807}
72808#[doc = "Table look-up"]
72809#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
72810#[inline]
72811#[cfg(target_endian = "little")]
72812#[target_feature(enable = "neon")]
72813#[cfg(target_arch = "arm")]
72814#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72815#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72816#[cfg_attr(test, assert_instr(vtbl))]
72817pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
72818    unsafe {
72819        transmute(vtbl4(
72820            transmute(a.0),
72821            transmute(a.1),
72822            transmute(a.2),
72823            transmute(a.3),
72824            transmute(b),
72825        ))
72826    }
72827}
72828#[doc = "Table look-up"]
72829#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
72830#[inline]
72831#[cfg(target_endian = "big")]
72832#[target_feature(enable = "neon")]
72833#[cfg(target_arch = "arm")]
72834#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72835#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72836#[cfg_attr(test, assert_instr(vtbl))]
72837pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
72838    let mut a: uint8x8x4_t = a;
72839    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72840    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72841    a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
72842    a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
72843    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72844    unsafe {
72845        let ret_val: uint8x8_t = transmute(vtbl4(
72846            transmute(a.0),
72847            transmute(a.1),
72848            transmute(a.2),
72849            transmute(a.3),
72850            transmute(b),
72851        ));
72852        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72853    }
72854}
72855#[doc = "Table look-up"]
72856#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
72857#[inline]
72858#[cfg(target_endian = "little")]
72859#[target_feature(enable = "neon")]
72860#[cfg(target_arch = "arm")]
72861#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72862#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72863#[cfg_attr(test, assert_instr(vtbl))]
72864pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
72865    unsafe {
72866        transmute(vtbl4(
72867            transmute(a.0),
72868            transmute(a.1),
72869            transmute(a.2),
72870            transmute(a.3),
72871            transmute(b),
72872        ))
72873    }
72874}
72875#[doc = "Table look-up"]
72876#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
72877#[inline]
72878#[cfg(target_endian = "big")]
72879#[target_feature(enable = "neon")]
72880#[cfg(target_arch = "arm")]
72881#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72882#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72883#[cfg_attr(test, assert_instr(vtbl))]
72884pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
72885    let mut a: poly8x8x4_t = a;
72886    a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72887    a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72888    a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
72889    a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
72890    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72891    unsafe {
72892        let ret_val: poly8x8_t = transmute(vtbl4(
72893            transmute(a.0),
72894            transmute(a.1),
72895            transmute(a.2),
72896            transmute(a.3),
72897            transmute(b),
72898        ));
72899        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72900    }
72901}
72902#[doc = "Extended table look-up"]
72903#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1)"]
72904#[inline]
72905#[target_feature(enable = "neon,v7")]
72906#[cfg(target_arch = "arm")]
72907#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72908#[cfg_attr(test, assert_instr(vtbx))]
72909fn vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
72910    unsafe extern "unadjusted" {
72911        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx1")]
72912        fn _vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t;
72913    }
72914    unsafe { _vtbx1(a, b, c) }
72915}
72916#[doc = "Extended table look-up"]
72917#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"]
72918#[inline]
72919#[target_feature(enable = "neon,v7")]
72920#[cfg(target_arch = "arm")]
72921#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72922#[cfg_attr(test, assert_instr(vtbx))]
72923pub fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
72924    vtbx1(a, b, c)
72925}
72926#[doc = "Extended table look-up"]
72927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"]
72928#[inline]
72929#[cfg(target_endian = "little")]
72930#[target_feature(enable = "neon,v7")]
72931#[cfg(target_arch = "arm")]
72932#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72933#[cfg_attr(test, assert_instr(vtbx))]
72934pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
72935    unsafe { transmute(vtbx1(transmute(a), transmute(b), transmute(c))) }
72936}
72937#[doc = "Extended table look-up"]
72938#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"]
72939#[inline]
72940#[cfg(target_endian = "big")]
72941#[target_feature(enable = "neon,v7")]
72942#[cfg(target_arch = "arm")]
72943#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72944#[cfg_attr(test, assert_instr(vtbx))]
72945pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
72946    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
72947    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72948    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
72949    unsafe {
72950        let ret_val: uint8x8_t = transmute(vtbx1(transmute(a), transmute(b), transmute(c)));
72951        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72952    }
72953}
72954#[doc = "Extended table look-up"]
72955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"]
72956#[inline]
72957#[cfg(target_endian = "little")]
72958#[target_feature(enable = "neon,v7")]
72959#[cfg(target_arch = "arm")]
72960#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72961#[cfg_attr(test, assert_instr(vtbx))]
72962pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
72963    unsafe { transmute(vtbx1(transmute(a), transmute(b), transmute(c))) }
72964}
72965#[doc = "Extended table look-up"]
72966#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"]
72967#[inline]
72968#[cfg(target_endian = "big")]
72969#[target_feature(enable = "neon,v7")]
72970#[cfg(target_arch = "arm")]
72971#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72972#[cfg_attr(test, assert_instr(vtbx))]
72973pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
72974    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
72975    let b: poly8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72976    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
72977    unsafe {
72978        let ret_val: poly8x8_t = transmute(vtbx1(transmute(a), transmute(b), transmute(c)));
72979        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72980    }
72981}
72982#[doc = "Extended table look-up"]
72983#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2)"]
72984#[inline]
72985#[target_feature(enable = "neon,v7")]
72986#[cfg(target_arch = "arm")]
72987#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72988#[cfg_attr(test, assert_instr(vtbx))]
72989fn vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t {
72990    unsafe extern "unadjusted" {
72991        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx2")]
72992        fn _vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t;
72993    }
72994    unsafe { _vtbx2(a, b, c, d) }
72995}
72996#[doc = "Extended table look-up"]
72997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_s8)"]
72998#[inline]
72999#[target_feature(enable = "neon,v7")]
73000#[cfg(target_arch = "arm")]
73001#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73002#[cfg_attr(test, assert_instr(vtbx))]
73003pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t {
73004    vtbx2(a, b.0, b.1, c)
73005}
73006#[doc = "Extended table look-up"]
73007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
73008#[inline]
73009#[cfg(target_endian = "little")]
73010#[target_feature(enable = "neon,v7")]
73011#[cfg(target_arch = "arm")]
73012#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73013#[cfg_attr(test, assert_instr(vtbx))]
73014pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
73015    unsafe {
73016        transmute(vtbx2(
73017            transmute(a),
73018            transmute(b.0),
73019            transmute(b.1),
73020            transmute(c),
73021        ))
73022    }
73023}
73024#[doc = "Extended table look-up"]
73025#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
73026#[inline]
73027#[cfg(target_endian = "big")]
73028#[target_feature(enable = "neon,v7")]
73029#[cfg(target_arch = "arm")]
73030#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73031#[cfg_attr(test, assert_instr(vtbx))]
73032pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
73033    let mut b: uint8x8x2_t = b;
73034    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73035    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
73036    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
73037    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73038    unsafe {
73039        let ret_val: uint8x8_t = transmute(vtbx2(
73040            transmute(a),
73041            transmute(b.0),
73042            transmute(b.1),
73043            transmute(c),
73044        ));
73045        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73046    }
73047}
73048#[doc = "Extended table look-up"]
73049#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
73050#[inline]
73051#[cfg(target_endian = "little")]
73052#[target_feature(enable = "neon,v7")]
73053#[cfg(target_arch = "arm")]
73054#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73055#[cfg_attr(test, assert_instr(vtbx))]
73056pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
73057    unsafe {
73058        transmute(vtbx2(
73059            transmute(a),
73060            transmute(b.0),
73061            transmute(b.1),
73062            transmute(c),
73063        ))
73064    }
73065}
73066#[doc = "Extended table look-up"]
73067#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
73068#[inline]
73069#[cfg(target_endian = "big")]
73070#[target_feature(enable = "neon,v7")]
73071#[cfg(target_arch = "arm")]
73072#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73073#[cfg_attr(test, assert_instr(vtbx))]
73074pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
73075    let mut b: poly8x8x2_t = b;
73076    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73077    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
73078    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
73079    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73080    unsafe {
73081        let ret_val: poly8x8_t = transmute(vtbx2(
73082            transmute(a),
73083            transmute(b.0),
73084            transmute(b.1),
73085            transmute(c),
73086        ));
73087        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73088    }
73089}
73090#[doc = "Extended table look-up"]
73091#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3)"]
73092#[inline]
73093#[target_feature(enable = "neon,v7")]
73094#[cfg(target_arch = "arm")]
73095#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73096#[cfg_attr(test, assert_instr(vtbx))]
73097fn vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t {
73098    unsafe extern "unadjusted" {
73099        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx3")]
73100        fn _vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t;
73101    }
73102    unsafe { _vtbx3(a, b, c, d, e) }
73103}
73104#[doc = "Extended table look-up"]
73105#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"]
73106#[inline]
73107#[target_feature(enable = "neon,v7")]
73108#[cfg(target_arch = "arm")]
73109#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73110#[cfg_attr(test, assert_instr(vtbx))]
73111pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t {
73112    vtbx3(a, b.0, b.1, b.2, c)
73113}
73114#[doc = "Extended table look-up"]
73115#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
73116#[inline]
73117#[cfg(target_endian = "little")]
73118#[target_feature(enable = "neon,v7")]
73119#[cfg(target_arch = "arm")]
73120#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73121#[cfg_attr(test, assert_instr(vtbx))]
73122pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
73123    unsafe {
73124        transmute(vtbx3(
73125            transmute(a),
73126            transmute(b.0),
73127            transmute(b.1),
73128            transmute(b.2),
73129            transmute(c),
73130        ))
73131    }
73132}
73133#[doc = "Extended table look-up"]
73134#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
73135#[inline]
73136#[cfg(target_endian = "big")]
73137#[target_feature(enable = "neon,v7")]
73138#[cfg(target_arch = "arm")]
73139#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73140#[cfg_attr(test, assert_instr(vtbx))]
73141pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
73142    let mut b: uint8x8x3_t = b;
73143    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73144    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
73145    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
73146    b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
73147    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73148    unsafe {
73149        let ret_val: uint8x8_t = transmute(vtbx3(
73150            transmute(a),
73151            transmute(b.0),
73152            transmute(b.1),
73153            transmute(b.2),
73154            transmute(c),
73155        ));
73156        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73157    }
73158}
73159#[doc = "Extended table look-up"]
73160#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
73161#[inline]
73162#[cfg(target_endian = "little")]
73163#[target_feature(enable = "neon,v7")]
73164#[cfg(target_arch = "arm")]
73165#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73166#[cfg_attr(test, assert_instr(vtbx))]
73167pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
73168    unsafe {
73169        transmute(vtbx3(
73170            transmute(a),
73171            transmute(b.0),
73172            transmute(b.1),
73173            transmute(b.2),
73174            transmute(c),
73175        ))
73176    }
73177}
73178#[doc = "Extended table look-up"]
73179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
73180#[inline]
73181#[cfg(target_endian = "big")]
73182#[target_feature(enable = "neon,v7")]
73183#[cfg(target_arch = "arm")]
73184#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73185#[cfg_attr(test, assert_instr(vtbx))]
73186pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
73187    let mut b: poly8x8x3_t = b;
73188    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73189    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
73190    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
73191    b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
73192    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73193    unsafe {
73194        let ret_val: poly8x8_t = transmute(vtbx3(
73195            transmute(a),
73196            transmute(b.0),
73197            transmute(b.1),
73198            transmute(b.2),
73199            transmute(c),
73200        ));
73201        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73202    }
73203}
73204#[doc = "Extended table look-up"]
73205#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4)"]
73206#[inline]
73207#[target_feature(enable = "neon,v7")]
73208#[cfg(target_arch = "arm")]
73209#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73210#[cfg_attr(test, assert_instr(vtbx))]
73211fn vtbx4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t, f: int8x8_t) -> int8x8_t {
73212    unsafe extern "unadjusted" {
73213        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx4")]
73214        fn _vtbx4(
73215            a: int8x8_t,
73216            b: int8x8_t,
73217            c: int8x8_t,
73218            d: int8x8_t,
73219            e: int8x8_t,
73220            f: int8x8_t,
73221        ) -> int8x8_t;
73222    }
73223    unsafe { _vtbx4(a, b, c, d, e, f) }
73224}
73225#[doc = "Extended table look-up"]
73226#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"]
73227#[inline]
73228#[cfg(target_endian = "little")]
73229#[target_feature(enable = "neon,v7")]
73230#[cfg(target_arch = "arm")]
73231#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73232#[cfg_attr(test, assert_instr(vtbx))]
73233pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
73234    unsafe {
73235        vtbx4(
73236            a,
73237            transmute(b.0),
73238            transmute(b.1),
73239            transmute(b.2),
73240            transmute(b.3),
73241            c,
73242        )
73243    }
73244}
73245#[doc = "Extended table look-up"]
73246#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"]
73247#[inline]
73248#[cfg(target_endian = "big")]
73249#[target_feature(enable = "neon,v7")]
73250#[cfg(target_arch = "arm")]
73251#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73252#[cfg_attr(test, assert_instr(vtbx))]
73253pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
73254    let mut b: int8x8x4_t = b;
73255    let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73256    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
73257    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
73258    b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
73259    b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
73260    let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73261    unsafe {
73262        let ret_val: int8x8_t = vtbx4(
73263            a,
73264            transmute(b.0),
73265            transmute(b.1),
73266            transmute(b.2),
73267            transmute(b.3),
73268            c,
73269        );
73270        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73271    }
73272}
73273#[doc = "Extended table look-up"]
73274#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
73275#[inline]
73276#[cfg(target_endian = "little")]
73277#[target_feature(enable = "neon,v7")]
73278#[cfg(target_arch = "arm")]
73279#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73280#[cfg_attr(test, assert_instr(vtbx))]
73281pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
73282    unsafe {
73283        transmute(vtbx4(
73284            transmute(a),
73285            transmute(b.0),
73286            transmute(b.1),
73287            transmute(b.2),
73288            transmute(b.3),
73289            transmute(c),
73290        ))
73291    }
73292}
73293#[doc = "Extended table look-up"]
73294#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
73295#[inline]
73296#[cfg(target_endian = "big")]
73297#[target_feature(enable = "neon,v7")]
73298#[cfg(target_arch = "arm")]
73299#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73300#[cfg_attr(test, assert_instr(vtbx))]
73301pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
73302    let mut b: uint8x8x4_t = b;
73303    let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73304    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
73305    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
73306    b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
73307    b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
73308    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73309    unsafe {
73310        let ret_val: uint8x8_t = transmute(vtbx4(
73311            transmute(a),
73312            transmute(b.0),
73313            transmute(b.1),
73314            transmute(b.2),
73315            transmute(b.3),
73316            transmute(c),
73317        ));
73318        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73319    }
73320}
73321#[doc = "Extended table look-up"]
73322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
73323#[inline]
73324#[cfg(target_endian = "little")]
73325#[target_feature(enable = "neon,v7")]
73326#[cfg(target_arch = "arm")]
73327#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73328#[cfg_attr(test, assert_instr(vtbx))]
73329pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
73330    unsafe {
73331        transmute(vtbx4(
73332            transmute(a),
73333            transmute(b.0),
73334            transmute(b.1),
73335            transmute(b.2),
73336            transmute(b.3),
73337            transmute(c),
73338        ))
73339    }
73340}
73341#[doc = "Extended table look-up"]
73342#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
73343#[inline]
73344#[cfg(target_endian = "big")]
73345#[target_feature(enable = "neon,v7")]
73346#[cfg(target_arch = "arm")]
73347#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73348#[cfg_attr(test, assert_instr(vtbx))]
73349pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
73350    let mut b: poly8x8x4_t = b;
73351    let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73352    b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
73353    b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
73354    b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
73355    b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
73356    let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73357    unsafe {
73358        let ret_val: poly8x8_t = transmute(vtbx4(
73359            transmute(a),
73360            transmute(b.0),
73361            transmute(b.1),
73362            transmute(b.2),
73363            transmute(b.3),
73364            transmute(c),
73365        ));
73366        simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73367    }
73368}
73369#[doc = "Transpose elements"]
73370#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f16)"]
73371#[inline]
73372#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73373#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73374#[cfg_attr(
73375    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73376    assert_instr(trn)
73377)]
73378#[target_feature(enable = "neon,fp16")]
73379#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
73380pub fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
73381    unsafe {
73382        let a1: float16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73383        let b1: float16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73384        transmute((a1, b1))
73385    }
73386}
73387#[doc = "Transpose elements"]
73388#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f16)"]
73389#[inline]
73390#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73391#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73392#[cfg_attr(
73393    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73394    assert_instr(trn)
73395)]
73396#[target_feature(enable = "neon,fp16")]
73397#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
73398pub fn vtrnq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
73399    unsafe {
73400        let a1: float16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73401        let b1: float16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73402        transmute((a1, b1))
73403    }
73404}
73405#[doc = "Transpose elements"]
73406#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f32)"]
73407#[inline]
73408#[target_feature(enable = "neon")]
73409#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73410#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73411#[cfg_attr(
73412    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73413    assert_instr(zip)
73414)]
73415#[cfg_attr(
73416    not(target_arch = "arm"),
73417    stable(feature = "neon_intrinsics", since = "1.59.0")
73418)]
73419#[cfg_attr(
73420    target_arch = "arm",
73421    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73422)]
73423pub fn vtrn_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
73424    unsafe {
73425        let a1: float32x2_t = simd_shuffle!(a, b, [0, 2]);
73426        let b1: float32x2_t = simd_shuffle!(a, b, [1, 3]);
73427        transmute((a1, b1))
73428    }
73429}
73430#[doc = "Transpose elements"]
73431#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s32)"]
73432#[inline]
73433#[target_feature(enable = "neon")]
73434#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73435#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73436#[cfg_attr(
73437    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73438    assert_instr(zip)
73439)]
73440#[cfg_attr(
73441    not(target_arch = "arm"),
73442    stable(feature = "neon_intrinsics", since = "1.59.0")
73443)]
73444#[cfg_attr(
73445    target_arch = "arm",
73446    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73447)]
73448pub fn vtrn_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
73449    unsafe {
73450        let a1: int32x2_t = simd_shuffle!(a, b, [0, 2]);
73451        let b1: int32x2_t = simd_shuffle!(a, b, [1, 3]);
73452        transmute((a1, b1))
73453    }
73454}
73455#[doc = "Transpose elements"]
73456#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u32)"]
73457#[inline]
73458#[target_feature(enable = "neon")]
73459#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73460#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73461#[cfg_attr(
73462    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73463    assert_instr(zip)
73464)]
73465#[cfg_attr(
73466    not(target_arch = "arm"),
73467    stable(feature = "neon_intrinsics", since = "1.59.0")
73468)]
73469#[cfg_attr(
73470    target_arch = "arm",
73471    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73472)]
73473pub fn vtrn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
73474    unsafe {
73475        let a1: uint32x2_t = simd_shuffle!(a, b, [0, 2]);
73476        let b1: uint32x2_t = simd_shuffle!(a, b, [1, 3]);
73477        transmute((a1, b1))
73478    }
73479}
73480#[doc = "Transpose elements"]
73481#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f32)"]
73482#[inline]
73483#[target_feature(enable = "neon")]
73484#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73485#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73486#[cfg_attr(
73487    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73488    assert_instr(trn)
73489)]
73490#[cfg_attr(
73491    not(target_arch = "arm"),
73492    stable(feature = "neon_intrinsics", since = "1.59.0")
73493)]
73494#[cfg_attr(
73495    target_arch = "arm",
73496    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73497)]
73498pub fn vtrnq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
73499    unsafe {
73500        let a1: float32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73501        let b1: float32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73502        transmute((a1, b1))
73503    }
73504}
73505#[doc = "Transpose elements"]
73506#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s8)"]
73507#[inline]
73508#[target_feature(enable = "neon")]
73509#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73510#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73511#[cfg_attr(
73512    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73513    assert_instr(trn)
73514)]
73515#[cfg_attr(
73516    not(target_arch = "arm"),
73517    stable(feature = "neon_intrinsics", since = "1.59.0")
73518)]
73519#[cfg_attr(
73520    target_arch = "arm",
73521    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73522)]
73523pub fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
73524    unsafe {
73525        let a1: int8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73526        let b1: int8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73527        transmute((a1, b1))
73528    }
73529}
73530#[doc = "Transpose elements"]
73531#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s8)"]
73532#[inline]
73533#[target_feature(enable = "neon")]
73534#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73535#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73536#[cfg_attr(
73537    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73538    assert_instr(trn)
73539)]
73540#[cfg_attr(
73541    not(target_arch = "arm"),
73542    stable(feature = "neon_intrinsics", since = "1.59.0")
73543)]
73544#[cfg_attr(
73545    target_arch = "arm",
73546    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73547)]
73548pub fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
73549    unsafe {
73550        let a1: int8x16_t = simd_shuffle!(
73551            a,
73552            b,
73553            [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]
73554        );
73555        let b1: int8x16_t = simd_shuffle!(
73556            a,
73557            b,
73558            [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]
73559        );
73560        transmute((a1, b1))
73561    }
73562}
73563#[doc = "Transpose elements"]
73564#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s16)"]
73565#[inline]
73566#[target_feature(enable = "neon")]
73567#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73568#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73569#[cfg_attr(
73570    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73571    assert_instr(trn)
73572)]
73573#[cfg_attr(
73574    not(target_arch = "arm"),
73575    stable(feature = "neon_intrinsics", since = "1.59.0")
73576)]
73577#[cfg_attr(
73578    target_arch = "arm",
73579    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73580)]
73581pub fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
73582    unsafe {
73583        let a1: int16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73584        let b1: int16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73585        transmute((a1, b1))
73586    }
73587}
73588#[doc = "Transpose elements"]
73589#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s16)"]
73590#[inline]
73591#[target_feature(enable = "neon")]
73592#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73593#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73594#[cfg_attr(
73595    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73596    assert_instr(trn)
73597)]
73598#[cfg_attr(
73599    not(target_arch = "arm"),
73600    stable(feature = "neon_intrinsics", since = "1.59.0")
73601)]
73602#[cfg_attr(
73603    target_arch = "arm",
73604    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73605)]
73606pub fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
73607    unsafe {
73608        let a1: int16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73609        let b1: int16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73610        transmute((a1, b1))
73611    }
73612}
73613#[doc = "Transpose elements"]
73614#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s32)"]
73615#[inline]
73616#[target_feature(enable = "neon")]
73617#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73618#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73619#[cfg_attr(
73620    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73621    assert_instr(trn)
73622)]
73623#[cfg_attr(
73624    not(target_arch = "arm"),
73625    stable(feature = "neon_intrinsics", since = "1.59.0")
73626)]
73627#[cfg_attr(
73628    target_arch = "arm",
73629    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73630)]
73631pub fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
73632    unsafe {
73633        let a1: int32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73634        let b1: int32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73635        transmute((a1, b1))
73636    }
73637}
73638#[doc = "Transpose elements"]
73639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u8)"]
73640#[inline]
73641#[target_feature(enable = "neon")]
73642#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73643#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73644#[cfg_attr(
73645    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73646    assert_instr(trn)
73647)]
73648#[cfg_attr(
73649    not(target_arch = "arm"),
73650    stable(feature = "neon_intrinsics", since = "1.59.0")
73651)]
73652#[cfg_attr(
73653    target_arch = "arm",
73654    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73655)]
73656pub fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
73657    unsafe {
73658        let a1: uint8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73659        let b1: uint8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73660        transmute((a1, b1))
73661    }
73662}
73663#[doc = "Transpose elements"]
73664#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u8)"]
73665#[inline]
73666#[target_feature(enable = "neon")]
73667#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73668#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73669#[cfg_attr(
73670    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73671    assert_instr(trn)
73672)]
73673#[cfg_attr(
73674    not(target_arch = "arm"),
73675    stable(feature = "neon_intrinsics", since = "1.59.0")
73676)]
73677#[cfg_attr(
73678    target_arch = "arm",
73679    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73680)]
73681pub fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
73682    unsafe {
73683        let a1: uint8x16_t = simd_shuffle!(
73684            a,
73685            b,
73686            [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]
73687        );
73688        let b1: uint8x16_t = simd_shuffle!(
73689            a,
73690            b,
73691            [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]
73692        );
73693        transmute((a1, b1))
73694    }
73695}
73696#[doc = "Transpose elements"]
73697#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u16)"]
73698#[inline]
73699#[target_feature(enable = "neon")]
73700#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73701#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73702#[cfg_attr(
73703    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73704    assert_instr(trn)
73705)]
73706#[cfg_attr(
73707    not(target_arch = "arm"),
73708    stable(feature = "neon_intrinsics", since = "1.59.0")
73709)]
73710#[cfg_attr(
73711    target_arch = "arm",
73712    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73713)]
73714pub fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
73715    unsafe {
73716        let a1: uint16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73717        let b1: uint16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73718        transmute((a1, b1))
73719    }
73720}
73721#[doc = "Transpose elements"]
73722#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u16)"]
73723#[inline]
73724#[target_feature(enable = "neon")]
73725#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73726#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73727#[cfg_attr(
73728    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73729    assert_instr(trn)
73730)]
73731#[cfg_attr(
73732    not(target_arch = "arm"),
73733    stable(feature = "neon_intrinsics", since = "1.59.0")
73734)]
73735#[cfg_attr(
73736    target_arch = "arm",
73737    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73738)]
73739pub fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
73740    unsafe {
73741        let a1: uint16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73742        let b1: uint16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73743        transmute((a1, b1))
73744    }
73745}
73746#[doc = "Transpose elements"]
73747#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u32)"]
73748#[inline]
73749#[target_feature(enable = "neon")]
73750#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73751#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73752#[cfg_attr(
73753    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73754    assert_instr(trn)
73755)]
73756#[cfg_attr(
73757    not(target_arch = "arm"),
73758    stable(feature = "neon_intrinsics", since = "1.59.0")
73759)]
73760#[cfg_attr(
73761    target_arch = "arm",
73762    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73763)]
73764pub fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
73765    unsafe {
73766        let a1: uint32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73767        let b1: uint32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73768        transmute((a1, b1))
73769    }
73770}
73771#[doc = "Transpose elements"]
73772#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p8)"]
73773#[inline]
73774#[target_feature(enable = "neon")]
73775#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73776#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73777#[cfg_attr(
73778    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73779    assert_instr(trn)
73780)]
73781#[cfg_attr(
73782    not(target_arch = "arm"),
73783    stable(feature = "neon_intrinsics", since = "1.59.0")
73784)]
73785#[cfg_attr(
73786    target_arch = "arm",
73787    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73788)]
73789pub fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
73790    unsafe {
73791        let a1: poly8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73792        let b1: poly8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73793        transmute((a1, b1))
73794    }
73795}
73796#[doc = "Transpose elements"]
73797#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p8)"]
73798#[inline]
73799#[target_feature(enable = "neon")]
73800#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73801#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73802#[cfg_attr(
73803    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73804    assert_instr(trn)
73805)]
73806#[cfg_attr(
73807    not(target_arch = "arm"),
73808    stable(feature = "neon_intrinsics", since = "1.59.0")
73809)]
73810#[cfg_attr(
73811    target_arch = "arm",
73812    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73813)]
73814pub fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
73815    unsafe {
73816        let a1: poly8x16_t = simd_shuffle!(
73817            a,
73818            b,
73819            [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]
73820        );
73821        let b1: poly8x16_t = simd_shuffle!(
73822            a,
73823            b,
73824            [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]
73825        );
73826        transmute((a1, b1))
73827    }
73828}
73829#[doc = "Transpose elements"]
73830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p16)"]
73831#[inline]
73832#[target_feature(enable = "neon")]
73833#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73834#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73835#[cfg_attr(
73836    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73837    assert_instr(trn)
73838)]
73839#[cfg_attr(
73840    not(target_arch = "arm"),
73841    stable(feature = "neon_intrinsics", since = "1.59.0")
73842)]
73843#[cfg_attr(
73844    target_arch = "arm",
73845    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73846)]
73847pub fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
73848    unsafe {
73849        let a1: poly16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73850        let b1: poly16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73851        transmute((a1, b1))
73852    }
73853}
73854#[doc = "Transpose elements"]
73855#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p16)"]
73856#[inline]
73857#[target_feature(enable = "neon")]
73858#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73859#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73860#[cfg_attr(
73861    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73862    assert_instr(trn)
73863)]
73864#[cfg_attr(
73865    not(target_arch = "arm"),
73866    stable(feature = "neon_intrinsics", since = "1.59.0")
73867)]
73868#[cfg_attr(
73869    target_arch = "arm",
73870    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73871)]
73872pub fn vtrnq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
73873    unsafe {
73874        let a1: poly16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73875        let b1: poly16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73876        transmute((a1, b1))
73877    }
73878}
73879#[doc = "Signed compare bitwise Test bits nonzero"]
73880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s8)"]
73881#[inline]
73882#[target_feature(enable = "neon")]
73883#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73884#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73885#[cfg_attr(
73886    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73887    assert_instr(cmtst)
73888)]
73889#[cfg_attr(
73890    not(target_arch = "arm"),
73891    stable(feature = "neon_intrinsics", since = "1.59.0")
73892)]
73893#[cfg_attr(
73894    target_arch = "arm",
73895    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73896)]
73897pub fn vtst_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
73898    unsafe {
73899        let c: int8x8_t = simd_and(a, b);
73900        let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
73901        simd_ne(c, transmute(d))
73902    }
73903}
73904#[doc = "Signed compare bitwise Test bits nonzero"]
73905#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s8)"]
73906#[inline]
73907#[target_feature(enable = "neon")]
73908#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73909#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73910#[cfg_attr(
73911    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73912    assert_instr(cmtst)
73913)]
73914#[cfg_attr(
73915    not(target_arch = "arm"),
73916    stable(feature = "neon_intrinsics", since = "1.59.0")
73917)]
73918#[cfg_attr(
73919    target_arch = "arm",
73920    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73921)]
73922pub fn vtstq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
73923    unsafe {
73924        let c: int8x16_t = simd_and(a, b);
73925        let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
73926        simd_ne(c, transmute(d))
73927    }
73928}
73929#[doc = "Signed compare bitwise Test bits nonzero"]
73930#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s16)"]
73931#[inline]
73932#[target_feature(enable = "neon")]
73933#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73934#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73935#[cfg_attr(
73936    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73937    assert_instr(cmtst)
73938)]
73939#[cfg_attr(
73940    not(target_arch = "arm"),
73941    stable(feature = "neon_intrinsics", since = "1.59.0")
73942)]
73943#[cfg_attr(
73944    target_arch = "arm",
73945    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73946)]
73947pub fn vtst_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
73948    unsafe {
73949        let c: int16x4_t = simd_and(a, b);
73950        let d: i16x4 = i16x4::new(0, 0, 0, 0);
73951        simd_ne(c, transmute(d))
73952    }
73953}
73954#[doc = "Signed compare bitwise Test bits nonzero"]
73955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s16)"]
73956#[inline]
73957#[target_feature(enable = "neon")]
73958#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73959#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73960#[cfg_attr(
73961    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73962    assert_instr(cmtst)
73963)]
73964#[cfg_attr(
73965    not(target_arch = "arm"),
73966    stable(feature = "neon_intrinsics", since = "1.59.0")
73967)]
73968#[cfg_attr(
73969    target_arch = "arm",
73970    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73971)]
73972pub fn vtstq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
73973    unsafe {
73974        let c: int16x8_t = simd_and(a, b);
73975        let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
73976        simd_ne(c, transmute(d))
73977    }
73978}
73979#[doc = "Signed compare bitwise Test bits nonzero"]
73980#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s32)"]
73981#[inline]
73982#[target_feature(enable = "neon")]
73983#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73984#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73985#[cfg_attr(
73986    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73987    assert_instr(cmtst)
73988)]
73989#[cfg_attr(
73990    not(target_arch = "arm"),
73991    stable(feature = "neon_intrinsics", since = "1.59.0")
73992)]
73993#[cfg_attr(
73994    target_arch = "arm",
73995    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73996)]
73997pub fn vtst_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
73998    unsafe {
73999        let c: int32x2_t = simd_and(a, b);
74000        let d: i32x2 = i32x2::new(0, 0);
74001        simd_ne(c, transmute(d))
74002    }
74003}
74004#[doc = "Signed compare bitwise Test bits nonzero"]
74005#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s32)"]
74006#[inline]
74007#[target_feature(enable = "neon")]
74008#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74009#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74010#[cfg_attr(
74011    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74012    assert_instr(cmtst)
74013)]
74014#[cfg_attr(
74015    not(target_arch = "arm"),
74016    stable(feature = "neon_intrinsics", since = "1.59.0")
74017)]
74018#[cfg_attr(
74019    target_arch = "arm",
74020    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74021)]
74022pub fn vtstq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
74023    unsafe {
74024        let c: int32x4_t = simd_and(a, b);
74025        let d: i32x4 = i32x4::new(0, 0, 0, 0);
74026        simd_ne(c, transmute(d))
74027    }
74028}
74029#[doc = "Signed compare bitwise Test bits nonzero"]
74030#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p8)"]
74031#[inline]
74032#[target_feature(enable = "neon")]
74033#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74034#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74035#[cfg_attr(
74036    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74037    assert_instr(cmtst)
74038)]
74039#[cfg_attr(
74040    not(target_arch = "arm"),
74041    stable(feature = "neon_intrinsics", since = "1.59.0")
74042)]
74043#[cfg_attr(
74044    target_arch = "arm",
74045    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74046)]
74047pub fn vtst_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t {
74048    unsafe {
74049        let c: poly8x8_t = simd_and(a, b);
74050        let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
74051        simd_ne(c, transmute(d))
74052    }
74053}
74054#[doc = "Signed compare bitwise Test bits nonzero"]
74055#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p8)"]
74056#[inline]
74057#[target_feature(enable = "neon")]
74058#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74059#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74060#[cfg_attr(
74061    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74062    assert_instr(cmtst)
74063)]
74064#[cfg_attr(
74065    not(target_arch = "arm"),
74066    stable(feature = "neon_intrinsics", since = "1.59.0")
74067)]
74068#[cfg_attr(
74069    target_arch = "arm",
74070    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74071)]
74072pub fn vtstq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t {
74073    unsafe {
74074        let c: poly8x16_t = simd_and(a, b);
74075        let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
74076        simd_ne(c, transmute(d))
74077    }
74078}
74079#[doc = "Signed compare bitwise Test bits nonzero"]
74080#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p16)"]
74081#[inline]
74082#[target_feature(enable = "neon")]
74083#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74084#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74085#[cfg_attr(
74086    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74087    assert_instr(cmtst)
74088)]
74089#[cfg_attr(
74090    not(target_arch = "arm"),
74091    stable(feature = "neon_intrinsics", since = "1.59.0")
74092)]
74093#[cfg_attr(
74094    target_arch = "arm",
74095    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74096)]
74097pub fn vtst_p16(a: poly16x4_t, b: poly16x4_t) -> uint16x4_t {
74098    unsafe {
74099        let c: poly16x4_t = simd_and(a, b);
74100        let d: i16x4 = i16x4::new(0, 0, 0, 0);
74101        simd_ne(c, transmute(d))
74102    }
74103}
74104#[doc = "Signed compare bitwise Test bits nonzero"]
74105#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p16)"]
74106#[inline]
74107#[target_feature(enable = "neon")]
74108#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74109#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74110#[cfg_attr(
74111    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74112    assert_instr(cmtst)
74113)]
74114#[cfg_attr(
74115    not(target_arch = "arm"),
74116    stable(feature = "neon_intrinsics", since = "1.59.0")
74117)]
74118#[cfg_attr(
74119    target_arch = "arm",
74120    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74121)]
74122pub fn vtstq_p16(a: poly16x8_t, b: poly16x8_t) -> uint16x8_t {
74123    unsafe {
74124        let c: poly16x8_t = simd_and(a, b);
74125        let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
74126        simd_ne(c, transmute(d))
74127    }
74128}
74129#[doc = "Unsigned compare bitwise Test bits nonzero"]
74130#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u8)"]
74131#[inline]
74132#[target_feature(enable = "neon")]
74133#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74134#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74135#[cfg_attr(
74136    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74137    assert_instr(cmtst)
74138)]
74139#[cfg_attr(
74140    not(target_arch = "arm"),
74141    stable(feature = "neon_intrinsics", since = "1.59.0")
74142)]
74143#[cfg_attr(
74144    target_arch = "arm",
74145    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74146)]
74147pub fn vtst_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
74148    unsafe {
74149        let c: uint8x8_t = simd_and(a, b);
74150        let d: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
74151        simd_ne(c, transmute(d))
74152    }
74153}
74154#[doc = "Unsigned compare bitwise Test bits nonzero"]
74155#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u8)"]
74156#[inline]
74157#[target_feature(enable = "neon")]
74158#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74159#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74160#[cfg_attr(
74161    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74162    assert_instr(cmtst)
74163)]
74164#[cfg_attr(
74165    not(target_arch = "arm"),
74166    stable(feature = "neon_intrinsics", since = "1.59.0")
74167)]
74168#[cfg_attr(
74169    target_arch = "arm",
74170    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74171)]
74172pub fn vtstq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
74173    unsafe {
74174        let c: uint8x16_t = simd_and(a, b);
74175        let d: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
74176        simd_ne(c, transmute(d))
74177    }
74178}
74179#[doc = "Unsigned compare bitwise Test bits nonzero"]
74180#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u16)"]
74181#[inline]
74182#[target_feature(enable = "neon")]
74183#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74184#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74185#[cfg_attr(
74186    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74187    assert_instr(cmtst)
74188)]
74189#[cfg_attr(
74190    not(target_arch = "arm"),
74191    stable(feature = "neon_intrinsics", since = "1.59.0")
74192)]
74193#[cfg_attr(
74194    target_arch = "arm",
74195    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74196)]
74197pub fn vtst_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
74198    unsafe {
74199        let c: uint16x4_t = simd_and(a, b);
74200        let d: u16x4 = u16x4::new(0, 0, 0, 0);
74201        simd_ne(c, transmute(d))
74202    }
74203}
74204#[doc = "Unsigned compare bitwise Test bits nonzero"]
74205#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u16)"]
74206#[inline]
74207#[target_feature(enable = "neon")]
74208#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74209#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74210#[cfg_attr(
74211    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74212    assert_instr(cmtst)
74213)]
74214#[cfg_attr(
74215    not(target_arch = "arm"),
74216    stable(feature = "neon_intrinsics", since = "1.59.0")
74217)]
74218#[cfg_attr(
74219    target_arch = "arm",
74220    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74221)]
74222pub fn vtstq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
74223    unsafe {
74224        let c: uint16x8_t = simd_and(a, b);
74225        let d: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
74226        simd_ne(c, transmute(d))
74227    }
74228}
74229#[doc = "Unsigned compare bitwise Test bits nonzero"]
74230#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u32)"]
74231#[inline]
74232#[target_feature(enable = "neon")]
74233#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74234#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74235#[cfg_attr(
74236    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74237    assert_instr(cmtst)
74238)]
74239#[cfg_attr(
74240    not(target_arch = "arm"),
74241    stable(feature = "neon_intrinsics", since = "1.59.0")
74242)]
74243#[cfg_attr(
74244    target_arch = "arm",
74245    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74246)]
74247pub fn vtst_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
74248    unsafe {
74249        let c: uint32x2_t = simd_and(a, b);
74250        let d: u32x2 = u32x2::new(0, 0);
74251        simd_ne(c, transmute(d))
74252    }
74253}
74254#[doc = "Unsigned compare bitwise Test bits nonzero"]
74255#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u32)"]
74256#[inline]
74257#[target_feature(enable = "neon")]
74258#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74259#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74260#[cfg_attr(
74261    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74262    assert_instr(cmtst)
74263)]
74264#[cfg_attr(
74265    not(target_arch = "arm"),
74266    stable(feature = "neon_intrinsics", since = "1.59.0")
74267)]
74268#[cfg_attr(
74269    target_arch = "arm",
74270    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74271)]
74272pub fn vtstq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
74273    unsafe {
74274        let c: uint32x4_t = simd_and(a, b);
74275        let d: u32x4 = u32x4::new(0, 0, 0, 0);
74276        simd_ne(c, transmute(d))
74277    }
74278}
74279#[doc = "Dot product index form with unsigned and signed integers"]
74280#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"]
74281#[inline]
74282#[target_feature(enable = "neon,i8mm")]
74283#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
74284#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))]
74285#[cfg_attr(
74286    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74287    assert_instr(usdot, LANE = 0)
74288)]
74289#[rustc_legacy_const_generics(3)]
74290#[cfg_attr(
74291    not(target_arch = "arm"),
74292    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
74293)]
74294#[cfg_attr(
74295    target_arch = "arm",
74296    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74297)]
74298pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t {
74299    static_assert_uimm_bits!(LANE, 1);
74300    unsafe {
74301        let c: int32x2_t = transmute(c);
74302        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
74303        vusdot_s32(a, b, transmute(c))
74304    }
74305}
74306#[doc = "Dot product index form with unsigned and signed integers"]
74307#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"]
74308#[inline]
74309#[target_feature(enable = "neon,i8mm")]
74310#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
74311#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))]
74312#[cfg_attr(
74313    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74314    assert_instr(usdot, LANE = 0)
74315)]
74316#[rustc_legacy_const_generics(3)]
74317#[cfg_attr(
74318    not(target_arch = "arm"),
74319    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
74320)]
74321#[cfg_attr(
74322    target_arch = "arm",
74323    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74324)]
74325pub fn vusdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x8_t) -> int32x4_t {
74326    static_assert_uimm_bits!(LANE, 1);
74327    unsafe {
74328        let c: int32x2_t = transmute(c);
74329        let c: int32x4_t =
74330            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
74331        vusdotq_s32(a, b, transmute(c))
74332    }
74333}
74334#[doc = "Dot product vector form with unsigned and signed integers"]
74335#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_s32)"]
74336#[inline]
74337#[target_feature(enable = "neon,i8mm")]
74338#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
74339#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))]
74340#[cfg_attr(
74341    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74342    assert_instr(usdot)
74343)]
74344#[cfg_attr(
74345    not(target_arch = "arm"),
74346    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
74347)]
74348#[cfg_attr(
74349    target_arch = "arm",
74350    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74351)]
74352pub fn vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t {
74353    unsafe extern "unadjusted" {
74354        #[cfg_attr(
74355            any(target_arch = "aarch64", target_arch = "arm64ec"),
74356            link_name = "llvm.aarch64.neon.usdot.v2i32.v8i8"
74357        )]
74358        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v2i32.v8i8")]
74359        fn _vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t;
74360    }
74361    unsafe { _vusdot_s32(a, b, c) }
74362}
74363#[doc = "Dot product vector form with unsigned and signed integers"]
74364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_s32)"]
74365#[inline]
74366#[target_feature(enable = "neon,i8mm")]
74367#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
74368#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))]
74369#[cfg_attr(
74370    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74371    assert_instr(usdot)
74372)]
74373#[cfg_attr(
74374    not(target_arch = "arm"),
74375    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
74376)]
74377#[cfg_attr(
74378    target_arch = "arm",
74379    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74380)]
74381pub fn vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
74382    unsafe extern "unadjusted" {
74383        #[cfg_attr(
74384            any(target_arch = "aarch64", target_arch = "arm64ec"),
74385            link_name = "llvm.aarch64.neon.usdot.v4i32.v16i8"
74386        )]
74387        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v4i32.v16i8")]
74388        fn _vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t;
74389    }
74390    unsafe { _vusdotq_s32(a, b, c) }
74391}
74392#[doc = "Unsigned and signed 8-bit integer matrix multiply-accumulate"]
74393#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusmmlaq_s32)"]
74394#[inline]
74395#[target_feature(enable = "neon,i8mm")]
74396#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
74397#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
74398#[cfg_attr(
74399    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74400    assert_instr(usmmla)
74401)]
74402#[cfg_attr(
74403    not(target_arch = "arm"),
74404    unstable(feature = "stdarch_neon_i8mm", issue = "117223")
74405)]
74406#[cfg_attr(
74407    target_arch = "arm",
74408    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74409)]
74410pub fn vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
74411    unsafe extern "unadjusted" {
74412        #[cfg_attr(
74413            any(target_arch = "aarch64", target_arch = "arm64ec"),
74414            link_name = "llvm.aarch64.neon.usmmla.v4i32.v16i8"
74415        )]
74416        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usmmla.v4i32.v16i8")]
74417        fn _vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t;
74418    }
74419    unsafe { _vusmmlaq_s32(a, b, c) }
74420}
74421#[doc = "Unzip vectors"]
74422#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f16)"]
74423#[inline]
74424#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74425#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74426#[cfg_attr(
74427    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74428    assert_instr(uzp)
74429)]
74430#[target_feature(enable = "neon,fp16")]
74431#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
74432pub fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
74433    unsafe {
74434        let a0: float16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74435        let b0: float16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74436        transmute((a0, b0))
74437    }
74438}
74439#[doc = "Unzip vectors"]
74440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f16)"]
74441#[inline]
74442#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74443#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74444#[cfg_attr(
74445    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74446    assert_instr(uzp)
74447)]
74448#[target_feature(enable = "neon,fp16")]
74449#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
74450pub fn vuzpq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
74451    unsafe {
74452        let a0: float16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74453        let b0: float16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74454        transmute((a0, b0))
74455    }
74456}
74457#[doc = "Unzip vectors"]
74458#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f32)"]
74459#[inline]
74460#[target_feature(enable = "neon")]
74461#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74462#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
74463#[cfg_attr(
74464    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74465    assert_instr(zip)
74466)]
74467#[cfg_attr(
74468    not(target_arch = "arm"),
74469    stable(feature = "neon_intrinsics", since = "1.59.0")
74470)]
74471#[cfg_attr(
74472    target_arch = "arm",
74473    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74474)]
74475pub fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
74476    unsafe {
74477        let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]);
74478        let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]);
74479        transmute((a0, b0))
74480    }
74481}
74482#[doc = "Unzip vectors"]
74483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s32)"]
74484#[inline]
74485#[target_feature(enable = "neon")]
74486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74487#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
74488#[cfg_attr(
74489    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74490    assert_instr(zip)
74491)]
74492#[cfg_attr(
74493    not(target_arch = "arm"),
74494    stable(feature = "neon_intrinsics", since = "1.59.0")
74495)]
74496#[cfg_attr(
74497    target_arch = "arm",
74498    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74499)]
74500pub fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
74501    unsafe {
74502        let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]);
74503        let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]);
74504        transmute((a0, b0))
74505    }
74506}
74507#[doc = "Unzip vectors"]
74508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u32)"]
74509#[inline]
74510#[target_feature(enable = "neon")]
74511#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74512#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
74513#[cfg_attr(
74514    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74515    assert_instr(zip)
74516)]
74517#[cfg_attr(
74518    not(target_arch = "arm"),
74519    stable(feature = "neon_intrinsics", since = "1.59.0")
74520)]
74521#[cfg_attr(
74522    target_arch = "arm",
74523    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74524)]
74525pub fn vuzp_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
74526    unsafe {
74527        let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]);
74528        let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]);
74529        transmute((a0, b0))
74530    }
74531}
74532#[doc = "Unzip vectors"]
74533#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f32)"]
74534#[inline]
74535#[target_feature(enable = "neon")]
74536#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74537#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74538#[cfg_attr(
74539    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74540    assert_instr(uzp)
74541)]
74542#[cfg_attr(
74543    not(target_arch = "arm"),
74544    stable(feature = "neon_intrinsics", since = "1.59.0")
74545)]
74546#[cfg_attr(
74547    target_arch = "arm",
74548    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74549)]
74550pub fn vuzpq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
74551    unsafe {
74552        let a0: float32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74553        let b0: float32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74554        transmute((a0, b0))
74555    }
74556}
74557#[doc = "Unzip vectors"]
74558#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s8)"]
74559#[inline]
74560#[target_feature(enable = "neon")]
74561#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74562#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74563#[cfg_attr(
74564    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74565    assert_instr(uzp)
74566)]
74567#[cfg_attr(
74568    not(target_arch = "arm"),
74569    stable(feature = "neon_intrinsics", since = "1.59.0")
74570)]
74571#[cfg_attr(
74572    target_arch = "arm",
74573    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74574)]
74575pub fn vuzp_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
74576    unsafe {
74577        let a0: int8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74578        let b0: int8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74579        transmute((a0, b0))
74580    }
74581}
74582#[doc = "Unzip vectors"]
74583#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s8)"]
74584#[inline]
74585#[target_feature(enable = "neon")]
74586#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74587#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74588#[cfg_attr(
74589    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74590    assert_instr(uzp)
74591)]
74592#[cfg_attr(
74593    not(target_arch = "arm"),
74594    stable(feature = "neon_intrinsics", since = "1.59.0")
74595)]
74596#[cfg_attr(
74597    target_arch = "arm",
74598    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74599)]
74600pub fn vuzpq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
74601    unsafe {
74602        let a0: int8x16_t = simd_shuffle!(
74603            a,
74604            b,
74605            [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
74606        );
74607        let b0: int8x16_t = simd_shuffle!(
74608            a,
74609            b,
74610            [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
74611        );
74612        transmute((a0, b0))
74613    }
74614}
74615#[doc = "Unzip vectors"]
74616#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s16)"]
74617#[inline]
74618#[target_feature(enable = "neon")]
74619#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74620#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74621#[cfg_attr(
74622    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74623    assert_instr(uzp)
74624)]
74625#[cfg_attr(
74626    not(target_arch = "arm"),
74627    stable(feature = "neon_intrinsics", since = "1.59.0")
74628)]
74629#[cfg_attr(
74630    target_arch = "arm",
74631    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74632)]
74633pub fn vuzp_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
74634    unsafe {
74635        let a0: int16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74636        let b0: int16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74637        transmute((a0, b0))
74638    }
74639}
74640#[doc = "Unzip vectors"]
74641#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s16)"]
74642#[inline]
74643#[target_feature(enable = "neon")]
74644#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74645#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74646#[cfg_attr(
74647    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74648    assert_instr(uzp)
74649)]
74650#[cfg_attr(
74651    not(target_arch = "arm"),
74652    stable(feature = "neon_intrinsics", since = "1.59.0")
74653)]
74654#[cfg_attr(
74655    target_arch = "arm",
74656    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74657)]
74658pub fn vuzpq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
74659    unsafe {
74660        let a0: int16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74661        let b0: int16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74662        transmute((a0, b0))
74663    }
74664}
74665#[doc = "Unzip vectors"]
74666#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s32)"]
74667#[inline]
74668#[target_feature(enable = "neon")]
74669#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74670#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74671#[cfg_attr(
74672    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74673    assert_instr(uzp)
74674)]
74675#[cfg_attr(
74676    not(target_arch = "arm"),
74677    stable(feature = "neon_intrinsics", since = "1.59.0")
74678)]
74679#[cfg_attr(
74680    target_arch = "arm",
74681    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74682)]
74683pub fn vuzpq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
74684    unsafe {
74685        let a0: int32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74686        let b0: int32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74687        transmute((a0, b0))
74688    }
74689}
74690#[doc = "Unzip vectors"]
74691#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u8)"]
74692#[inline]
74693#[target_feature(enable = "neon")]
74694#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74695#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74696#[cfg_attr(
74697    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74698    assert_instr(uzp)
74699)]
74700#[cfg_attr(
74701    not(target_arch = "arm"),
74702    stable(feature = "neon_intrinsics", since = "1.59.0")
74703)]
74704#[cfg_attr(
74705    target_arch = "arm",
74706    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74707)]
74708pub fn vuzp_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
74709    unsafe {
74710        let a0: uint8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74711        let b0: uint8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74712        transmute((a0, b0))
74713    }
74714}
74715#[doc = "Unzip vectors"]
74716#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u8)"]
74717#[inline]
74718#[target_feature(enable = "neon")]
74719#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74720#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74721#[cfg_attr(
74722    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74723    assert_instr(uzp)
74724)]
74725#[cfg_attr(
74726    not(target_arch = "arm"),
74727    stable(feature = "neon_intrinsics", since = "1.59.0")
74728)]
74729#[cfg_attr(
74730    target_arch = "arm",
74731    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74732)]
74733pub fn vuzpq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
74734    unsafe {
74735        let a0: uint8x16_t = simd_shuffle!(
74736            a,
74737            b,
74738            [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
74739        );
74740        let b0: uint8x16_t = simd_shuffle!(
74741            a,
74742            b,
74743            [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
74744        );
74745        transmute((a0, b0))
74746    }
74747}
74748#[doc = "Unzip vectors"]
74749#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u16)"]
74750#[inline]
74751#[target_feature(enable = "neon")]
74752#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74753#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74754#[cfg_attr(
74755    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74756    assert_instr(uzp)
74757)]
74758#[cfg_attr(
74759    not(target_arch = "arm"),
74760    stable(feature = "neon_intrinsics", since = "1.59.0")
74761)]
74762#[cfg_attr(
74763    target_arch = "arm",
74764    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74765)]
74766pub fn vuzp_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
74767    unsafe {
74768        let a0: uint16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74769        let b0: uint16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74770        transmute((a0, b0))
74771    }
74772}
74773#[doc = "Unzip vectors"]
74774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u16)"]
74775#[inline]
74776#[target_feature(enable = "neon")]
74777#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74778#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74779#[cfg_attr(
74780    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74781    assert_instr(uzp)
74782)]
74783#[cfg_attr(
74784    not(target_arch = "arm"),
74785    stable(feature = "neon_intrinsics", since = "1.59.0")
74786)]
74787#[cfg_attr(
74788    target_arch = "arm",
74789    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74790)]
74791pub fn vuzpq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
74792    unsafe {
74793        let a0: uint16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74794        let b0: uint16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74795        transmute((a0, b0))
74796    }
74797}
74798#[doc = "Unzip vectors"]
74799#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u32)"]
74800#[inline]
74801#[target_feature(enable = "neon")]
74802#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74803#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74804#[cfg_attr(
74805    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74806    assert_instr(uzp)
74807)]
74808#[cfg_attr(
74809    not(target_arch = "arm"),
74810    stable(feature = "neon_intrinsics", since = "1.59.0")
74811)]
74812#[cfg_attr(
74813    target_arch = "arm",
74814    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74815)]
74816pub fn vuzpq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
74817    unsafe {
74818        let a0: uint32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74819        let b0: uint32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74820        transmute((a0, b0))
74821    }
74822}
74823#[doc = "Unzip vectors"]
74824#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p8)"]
74825#[inline]
74826#[target_feature(enable = "neon")]
74827#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74828#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74829#[cfg_attr(
74830    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74831    assert_instr(uzp)
74832)]
74833#[cfg_attr(
74834    not(target_arch = "arm"),
74835    stable(feature = "neon_intrinsics", since = "1.59.0")
74836)]
74837#[cfg_attr(
74838    target_arch = "arm",
74839    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74840)]
74841pub fn vuzp_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
74842    unsafe {
74843        let a0: poly8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74844        let b0: poly8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74845        transmute((a0, b0))
74846    }
74847}
74848#[doc = "Unzip vectors"]
74849#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p8)"]
74850#[inline]
74851#[target_feature(enable = "neon")]
74852#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74853#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74854#[cfg_attr(
74855    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74856    assert_instr(uzp)
74857)]
74858#[cfg_attr(
74859    not(target_arch = "arm"),
74860    stable(feature = "neon_intrinsics", since = "1.59.0")
74861)]
74862#[cfg_attr(
74863    target_arch = "arm",
74864    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74865)]
74866pub fn vuzpq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
74867    unsafe {
74868        let a0: poly8x16_t = simd_shuffle!(
74869            a,
74870            b,
74871            [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
74872        );
74873        let b0: poly8x16_t = simd_shuffle!(
74874            a,
74875            b,
74876            [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
74877        );
74878        transmute((a0, b0))
74879    }
74880}
74881#[doc = "Unzip vectors"]
74882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p16)"]
74883#[inline]
74884#[target_feature(enable = "neon")]
74885#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74886#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74887#[cfg_attr(
74888    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74889    assert_instr(uzp)
74890)]
74891#[cfg_attr(
74892    not(target_arch = "arm"),
74893    stable(feature = "neon_intrinsics", since = "1.59.0")
74894)]
74895#[cfg_attr(
74896    target_arch = "arm",
74897    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74898)]
74899pub fn vuzp_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
74900    unsafe {
74901        let a0: poly16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74902        let b0: poly16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74903        transmute((a0, b0))
74904    }
74905}
74906#[doc = "Unzip vectors"]
74907#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p16)"]
74908#[inline]
74909#[target_feature(enable = "neon")]
74910#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74911#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74912#[cfg_attr(
74913    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74914    assert_instr(uzp)
74915)]
74916#[cfg_attr(
74917    not(target_arch = "arm"),
74918    stable(feature = "neon_intrinsics", since = "1.59.0")
74919)]
74920#[cfg_attr(
74921    target_arch = "arm",
74922    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74923)]
74924pub fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
74925    unsafe {
74926        let a0: poly16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74927        let b0: poly16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74928        transmute((a0, b0))
74929    }
74930}
74931#[doc = "Zip vectors"]
74932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f16)"]
74933#[inline]
74934#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74935#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))]
74936#[cfg_attr(
74937    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74938    assert_instr(zip)
74939)]
74940#[target_feature(enable = "neon,fp16")]
74941#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
74942pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
74943    unsafe {
74944        let a0: float16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
74945        let b0: float16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
74946        transmute((a0, b0))
74947    }
74948}
74949#[doc = "Zip vectors"]
74950#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f16)"]
74951#[inline]
74952#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74953#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))]
74954#[cfg_attr(
74955    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74956    assert_instr(zip)
74957)]
74958#[target_feature(enable = "neon,fp16")]
74959#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
74960pub fn vzipq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
74961    unsafe {
74962        let a0: float16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
74963        let b0: float16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
74964        transmute((a0, b0))
74965    }
74966}
74967#[doc = "Zip vectors"]
74968#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f32)"]
74969#[inline]
74970#[target_feature(enable = "neon")]
74971#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74972#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
74973#[cfg_attr(
74974    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74975    assert_instr(zip)
74976)]
74977#[cfg_attr(
74978    not(target_arch = "arm"),
74979    stable(feature = "neon_intrinsics", since = "1.59.0")
74980)]
74981#[cfg_attr(
74982    target_arch = "arm",
74983    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74984)]
74985pub fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
74986    unsafe {
74987        let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]);
74988        let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]);
74989        transmute((a0, b0))
74990    }
74991}
74992#[doc = "Zip vectors"]
74993#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s32)"]
74994#[inline]
74995#[target_feature(enable = "neon")]
74996#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74997#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
74998#[cfg_attr(
74999    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75000    assert_instr(zip)
75001)]
75002#[cfg_attr(
75003    not(target_arch = "arm"),
75004    stable(feature = "neon_intrinsics", since = "1.59.0")
75005)]
75006#[cfg_attr(
75007    target_arch = "arm",
75008    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75009)]
75010pub fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
75011    unsafe {
75012        let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]);
75013        let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]);
75014        transmute((a0, b0))
75015    }
75016}
75017#[doc = "Zip vectors"]
75018#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u32)"]
75019#[inline]
75020#[target_feature(enable = "neon")]
75021#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75022#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
75023#[cfg_attr(
75024    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75025    assert_instr(zip)
75026)]
75027#[cfg_attr(
75028    not(target_arch = "arm"),
75029    stable(feature = "neon_intrinsics", since = "1.59.0")
75030)]
75031#[cfg_attr(
75032    target_arch = "arm",
75033    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75034)]
75035pub fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
75036    unsafe {
75037        let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]);
75038        let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]);
75039        transmute((a0, b0))
75040    }
75041}
75042#[doc = "Zip vectors"]
75043#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s8)"]
75044#[inline]
75045#[target_feature(enable = "neon")]
75046#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75047#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
75048#[cfg_attr(
75049    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75050    assert_instr(zip)
75051)]
75052#[cfg_attr(
75053    not(target_arch = "arm"),
75054    stable(feature = "neon_intrinsics", since = "1.59.0")
75055)]
75056#[cfg_attr(
75057    target_arch = "arm",
75058    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75059)]
75060pub fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
75061    unsafe {
75062        let a0: int8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
75063        let b0: int8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
75064        transmute((a0, b0))
75065    }
75066}
75067#[doc = "Zip vectors"]
75068#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s16)"]
75069#[inline]
75070#[target_feature(enable = "neon")]
75071#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75072#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
75073#[cfg_attr(
75074    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75075    assert_instr(zip)
75076)]
75077#[cfg_attr(
75078    not(target_arch = "arm"),
75079    stable(feature = "neon_intrinsics", since = "1.59.0")
75080)]
75081#[cfg_attr(
75082    target_arch = "arm",
75083    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75084)]
75085pub fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
75086    unsafe {
75087        let a0: int16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75088        let b0: int16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75089        transmute((a0, b0))
75090    }
75091}
75092#[doc = "Zip vectors"]
75093#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u8)"]
75094#[inline]
75095#[target_feature(enable = "neon")]
75096#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75097#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
75098#[cfg_attr(
75099    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75100    assert_instr(zip)
75101)]
75102#[cfg_attr(
75103    not(target_arch = "arm"),
75104    stable(feature = "neon_intrinsics", since = "1.59.0")
75105)]
75106#[cfg_attr(
75107    target_arch = "arm",
75108    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75109)]
75110pub fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
75111    unsafe {
75112        let a0: uint8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
75113        let b0: uint8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
75114        transmute((a0, b0))
75115    }
75116}
75117#[doc = "Zip vectors"]
75118#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u16)"]
75119#[inline]
75120#[target_feature(enable = "neon")]
75121#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75122#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
75123#[cfg_attr(
75124    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75125    assert_instr(zip)
75126)]
75127#[cfg_attr(
75128    not(target_arch = "arm"),
75129    stable(feature = "neon_intrinsics", since = "1.59.0")
75130)]
75131#[cfg_attr(
75132    target_arch = "arm",
75133    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75134)]
75135pub fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
75136    unsafe {
75137        let a0: uint16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75138        let b0: uint16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75139        transmute((a0, b0))
75140    }
75141}
75142#[doc = "Zip vectors"]
75143#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p8)"]
75144#[inline]
75145#[target_feature(enable = "neon")]
75146#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75147#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
75148#[cfg_attr(
75149    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75150    assert_instr(zip)
75151)]
75152#[cfg_attr(
75153    not(target_arch = "arm"),
75154    stable(feature = "neon_intrinsics", since = "1.59.0")
75155)]
75156#[cfg_attr(
75157    target_arch = "arm",
75158    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75159)]
75160pub fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
75161    unsafe {
75162        let a0: poly8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
75163        let b0: poly8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
75164        transmute((a0, b0))
75165    }
75166}
75167#[doc = "Zip vectors"]
75168#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p16)"]
75169#[inline]
75170#[target_feature(enable = "neon")]
75171#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75172#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
75173#[cfg_attr(
75174    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75175    assert_instr(zip)
75176)]
75177#[cfg_attr(
75178    not(target_arch = "arm"),
75179    stable(feature = "neon_intrinsics", since = "1.59.0")
75180)]
75181#[cfg_attr(
75182    target_arch = "arm",
75183    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75184)]
75185pub fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
75186    unsafe {
75187        let a0: poly16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75188        let b0: poly16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75189        transmute((a0, b0))
75190    }
75191}
75192#[doc = "Zip vectors"]
75193#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f32)"]
75194#[inline]
75195#[target_feature(enable = "neon")]
75196#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75197#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75198#[cfg_attr(
75199    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75200    assert_instr(zip)
75201)]
75202#[cfg_attr(
75203    not(target_arch = "arm"),
75204    stable(feature = "neon_intrinsics", since = "1.59.0")
75205)]
75206#[cfg_attr(
75207    target_arch = "arm",
75208    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75209)]
75210pub fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
75211    unsafe {
75212        let a0: float32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75213        let b0: float32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75214        transmute((a0, b0))
75215    }
75216}
75217#[doc = "Zip vectors"]
75218#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s8)"]
75219#[inline]
75220#[target_feature(enable = "neon")]
75221#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75222#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75223#[cfg_attr(
75224    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75225    assert_instr(zip)
75226)]
75227#[cfg_attr(
75228    not(target_arch = "arm"),
75229    stable(feature = "neon_intrinsics", since = "1.59.0")
75230)]
75231#[cfg_attr(
75232    target_arch = "arm",
75233    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75234)]
75235pub fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
75236    unsafe {
75237        let a0: int8x16_t = simd_shuffle!(
75238            a,
75239            b,
75240            [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]
75241        );
75242        let b0: int8x16_t = simd_shuffle!(
75243            a,
75244            b,
75245            [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]
75246        );
75247        transmute((a0, b0))
75248    }
75249}
75250#[doc = "Zip vectors"]
75251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s16)"]
75252#[inline]
75253#[target_feature(enable = "neon")]
75254#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75255#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75256#[cfg_attr(
75257    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75258    assert_instr(zip)
75259)]
75260#[cfg_attr(
75261    not(target_arch = "arm"),
75262    stable(feature = "neon_intrinsics", since = "1.59.0")
75263)]
75264#[cfg_attr(
75265    target_arch = "arm",
75266    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75267)]
75268pub fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
75269    unsafe {
75270        let a0: int16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
75271        let b0: int16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
75272        transmute((a0, b0))
75273    }
75274}
75275#[doc = "Zip vectors"]
75276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s32)"]
75277#[inline]
75278#[target_feature(enable = "neon")]
75279#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75280#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75281#[cfg_attr(
75282    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75283    assert_instr(zip)
75284)]
75285#[cfg_attr(
75286    not(target_arch = "arm"),
75287    stable(feature = "neon_intrinsics", since = "1.59.0")
75288)]
75289#[cfg_attr(
75290    target_arch = "arm",
75291    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75292)]
75293pub fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
75294    unsafe {
75295        let a0: int32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75296        let b0: int32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75297        transmute((a0, b0))
75298    }
75299}
75300#[doc = "Zip vectors"]
75301#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u8)"]
75302#[inline]
75303#[target_feature(enable = "neon")]
75304#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75305#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75306#[cfg_attr(
75307    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75308    assert_instr(zip)
75309)]
75310#[cfg_attr(
75311    not(target_arch = "arm"),
75312    stable(feature = "neon_intrinsics", since = "1.59.0")
75313)]
75314#[cfg_attr(
75315    target_arch = "arm",
75316    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75317)]
75318pub fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
75319    unsafe {
75320        let a0: uint8x16_t = simd_shuffle!(
75321            a,
75322            b,
75323            [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]
75324        );
75325        let b0: uint8x16_t = simd_shuffle!(
75326            a,
75327            b,
75328            [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]
75329        );
75330        transmute((a0, b0))
75331    }
75332}
75333#[doc = "Zip vectors"]
75334#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u16)"]
75335#[inline]
75336#[target_feature(enable = "neon")]
75337#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75338#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75339#[cfg_attr(
75340    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75341    assert_instr(zip)
75342)]
75343#[cfg_attr(
75344    not(target_arch = "arm"),
75345    stable(feature = "neon_intrinsics", since = "1.59.0")
75346)]
75347#[cfg_attr(
75348    target_arch = "arm",
75349    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75350)]
75351pub fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
75352    unsafe {
75353        let a0: uint16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
75354        let b0: uint16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
75355        transmute((a0, b0))
75356    }
75357}
75358#[doc = "Zip vectors"]
75359#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u32)"]
75360#[inline]
75361#[target_feature(enable = "neon")]
75362#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75363#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75364#[cfg_attr(
75365    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75366    assert_instr(zip)
75367)]
75368#[cfg_attr(
75369    not(target_arch = "arm"),
75370    stable(feature = "neon_intrinsics", since = "1.59.0")
75371)]
75372#[cfg_attr(
75373    target_arch = "arm",
75374    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75375)]
75376pub fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
75377    unsafe {
75378        let a0: uint32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75379        let b0: uint32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75380        transmute((a0, b0))
75381    }
75382}
75383#[doc = "Zip vectors"]
75384#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p8)"]
75385#[inline]
75386#[target_feature(enable = "neon")]
75387#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75388#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75389#[cfg_attr(
75390    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75391    assert_instr(zip)
75392)]
75393#[cfg_attr(
75394    not(target_arch = "arm"),
75395    stable(feature = "neon_intrinsics", since = "1.59.0")
75396)]
75397#[cfg_attr(
75398    target_arch = "arm",
75399    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75400)]
75401pub fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
75402    unsafe {
75403        let a0: poly8x16_t = simd_shuffle!(
75404            a,
75405            b,
75406            [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]
75407        );
75408        let b0: poly8x16_t = simd_shuffle!(
75409            a,
75410            b,
75411            [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]
75412        );
75413        transmute((a0, b0))
75414    }
75415}
75416#[doc = "Zip vectors"]
75417#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p16)"]
75418#[inline]
75419#[target_feature(enable = "neon")]
75420#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75421#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75422#[cfg_attr(
75423    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75424    assert_instr(zip)
75425)]
75426#[cfg_attr(
75427    not(target_arch = "arm"),
75428    stable(feature = "neon_intrinsics", since = "1.59.0")
75429)]
75430#[cfg_attr(
75431    target_arch = "arm",
75432    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75433)]
75434pub fn vzipq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
75435    unsafe {
75436        let a0: poly16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
75437        let b0: poly16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
75438        transmute((a0, b0))
75439    }
75440}